diff options
Diffstat (limited to 'target/linux/ath79/dts/ar7161_trendnet_tew-673gru.dts')
| -rw-r--r-- | target/linux/ath79/dts/ar7161_trendnet_tew-673gru.dts | 180 |
1 files changed, 180 insertions, 0 deletions
diff --git a/target/linux/ath79/dts/ar7161_trendnet_tew-673gru.dts b/target/linux/ath79/dts/ar7161_trendnet_tew-673gru.dts new file mode 100644 index 0000000000..8657e291bd --- /dev/null +++ b/target/linux/ath79/dts/ar7161_trendnet_tew-673gru.dts @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "ar7100.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + compatible = "trendnet,tew-673gru", "qca,ar7161"; + model = "TRENDNET TEW-673GRU"; + + aliases { + led-boot = &led_wps; + led-failsafe = &led_wps; + led-running = &led_wps; + led-upgrade = &led_wps; + }; + + extosc: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "ref"; + clock-frequency = <40000000>; + }; + + leds { + compatible = "gpio-leds"; + + led_wps: wps { + label = "blue:wps"; + gpios = <&gpio 9 GPIO_ACTIVE_LOW>; + }; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&gpio 3 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&gpio 8 GPIO_ACTIVE_LOW>; + }; + }; + + rtl8366s { + compatible = "realtek,rtl8366s"; + gpio-sda = <&gpio 5 GPIO_ACTIVE_HIGH>; + gpio-sck = <&gpio 7 GPIO_ACTIVE_HIGH>; + realtek,initvals = <0x06 0x0108>; + + mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + phy4: ethernet-phy@4 { + reg = <4>; + phy-mode = "rgmii"; + }; + }; + }; + + virtual_flash { + compatible = "mtd-concat"; + devices = <&fwconcat0 &fwconcat1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x0 0x0>; + }; + }; + }; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + wifi@0,11 { + compatible = "pci168c,0029"; + reg = <0x8800 0 0 0 0>; + qca,no-eeprom; + }; + + wifi@0,12 { + compatible = "pci168c,0029"; + reg = <0x9000 0 0 0 0>; + qca,no-eeprom; + }; +}; + +&pll { + clocks = <&extosc>; +}; + +&spi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x000000 0x040000>; + read-only; + }; + + partition@40000 { + label = "config"; + reg = <0x040000 0x010000>; + read-only; + }; + + fwconcat0: partition@50000 { + label = "fwconcat0"; + reg = <0x050000 0x610000>; + }; + + partition@660000 { + label = "caldata"; + reg = <0x660000 0x010000>; + read-only; + }; + + fwconcat1: partition@670000 { + label = "fwconcat1"; + reg = <0x670000 0x190000>; + }; + }; + }; +}; + +ð0 { + status = "okay"; + + pll-data = <0x11110000 0x00001099 0x00991099>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +ð1 { + status = "okay"; + + pll-data = <0x11110000 0x00001099 0x00991099>; + + phy-handle = <&phy4>; +}; |