diff options
Diffstat (limited to 'target/linux/at91/patches-5.15/182-media-atmel-atmel-isc-regs-add-additional-fields-for.patch')
| -rw-r--r-- | target/linux/at91/patches-5.15/182-media-atmel-atmel-isc-regs-add-additional-fields-for.patch | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/target/linux/at91/patches-5.15/182-media-atmel-atmel-isc-regs-add-additional-fields-for.patch b/target/linux/at91/patches-5.15/182-media-atmel-atmel-isc-regs-add-additional-fields-for.patch new file mode 100644 index 0000000000..00849c7d12 --- /dev/null +++ b/target/linux/at91/patches-5.15/182-media-atmel-atmel-isc-regs-add-additional-fields-for.patch @@ -0,0 +1,55 @@ +From bf032d1a0105939b90072914d88181fbe6187f43 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev <eugen.hristev@microchip.com> +Date: Tue, 13 Apr 2021 12:57:24 +0200 +Subject: [PATCH 182/247] media: atmel: atmel-isc-regs: add additional fields + for sama7g5 type pipeline + +Add additional fields for registers present in sama7g5 type pipeline. +Extend register masks for additional bits in sama7g5 type pipeline registers. + +Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> +Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> +Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> +--- + drivers/media/platform/atmel/atmel-isc-regs.h | 16 ++++++++++++++-- + 1 file changed, 14 insertions(+), 2 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-isc-regs.h ++++ b/drivers/media/platform/atmel/atmel-isc-regs.h +@@ -289,8 +289,18 @@ + #define ISC_RLP_CFG_MODE_ARGB32 0xa + #define ISC_RLP_CFG_MODE_YYCC 0xb + #define ISC_RLP_CFG_MODE_YYCC_LIMITED 0xc ++#define ISC_RLP_CFG_MODE_YCYC 0xd + #define ISC_RLP_CFG_MODE_MASK GENMASK(3, 0) + ++#define ISC_RLP_CFG_LSH BIT(5) ++ ++#define ISC_RLP_CFG_YMODE_YUYV (3 << 6) ++#define ISC_RLP_CFG_YMODE_YVYU (2 << 6) ++#define ISC_RLP_CFG_YMODE_VYUY (0 << 6) ++#define ISC_RLP_CFG_YMODE_UYVY (1 << 6) ++ ++#define ISC_RLP_CFG_YMODE_MASK GENMASK(7, 6) ++ + /* Offset for HIS register specific to sama5d2 product */ + #define ISC_SAMA5D2_HIS_OFFSET 0 + /* Histogram Control Register */ +@@ -332,13 +342,15 @@ + #define ISC_DCFG_YMBSIZE_BEATS4 (0x1 << 4) + #define ISC_DCFG_YMBSIZE_BEATS8 (0x2 << 4) + #define ISC_DCFG_YMBSIZE_BEATS16 (0x3 << 4) +-#define ISC_DCFG_YMBSIZE_MASK GENMASK(5, 4) ++#define ISC_DCFG_YMBSIZE_BEATS32 (0x4 << 4) ++#define ISC_DCFG_YMBSIZE_MASK GENMASK(6, 4) + + #define ISC_DCFG_CMBSIZE_SINGLE (0x0 << 8) + #define ISC_DCFG_CMBSIZE_BEATS4 (0x1 << 8) + #define ISC_DCFG_CMBSIZE_BEATS8 (0x2 << 8) + #define ISC_DCFG_CMBSIZE_BEATS16 (0x3 << 8) +-#define ISC_DCFG_CMBSIZE_MASK GENMASK(9, 8) ++#define ISC_DCFG_CMBSIZE_BEATS32 (0x4 << 8) ++#define ISC_DCFG_CMBSIZE_MASK GENMASK(10, 8) + + /* DMA Control Register */ + #define ISC_DCTRL 0x000003e4 |