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| author | Sebastian Schaper <openwrt@sebastianschaper.net> | 2020-05-19 12:40:17 +0200 |
|---|---|---|
| committer | Adrian Schmutzler <freifunk@adrianschmutzler.de> | 2020-05-26 22:49:18 +0200 |
| commit | 64d088d8f9f2fbca75f3240ced5cf40b721dc3f2 (patch) | |
| tree | 94090b2006257351d11f9f85ec6895feb82d2936 /target | |
| parent | 8643c0b53d74aeb535c6700c115d323cb55ec7fb (diff) | |
| download | upstream-64d088d8f9f2fbca75f3240ced5cf40b721dc3f2.tar.gz upstream-64d088d8f9f2fbca75f3240ced5cf40b721dc3f2.tar.bz2 upstream-64d088d8f9f2fbca75f3240ced5cf40b721dc3f2.zip | |
ath79: increase spi clock for D-Link DIR-842
AHB is 258 MHz for this device (CPU_PLL / 3), but there is no difference
between 64 MHz and 50 MHz for spi-max-frequency, thus increase to 50 MHz.
Tested on revisions C1 and C3.
Signed-off-by: Sebastian Schaper <openwrt@sebastianschaper.net>
Diffstat (limited to 'target')
| -rw-r--r-- | target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi b/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi index 8071332451..6b2fb1c4a0 100644 --- a/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi +++ b/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi @@ -37,12 +37,13 @@ &spi { status = "okay"; + num-cs = <1>; flash@0 { compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <30000000>; + spi-max-frequency = <50000000>; partitions { compatible = "fixed-partitions"; |