diff options
| author | Chuanhong Guo <gch981213@gmail.com> | 2019-11-01 11:11:32 +0800 |
|---|---|---|
| committer | Chuanhong Guo <gch981213@gmail.com> | 2019-11-04 20:51:19 +0800 |
| commit | 109e614d906995cc7d9ec1233a13eb8be1823ba3 (patch) | |
| tree | a9974a4ea1426f7a61a7ee3051007ded651b4163 /target/linux | |
| parent | 46a97fe316e47f6287579ff15e047f4b63576965 (diff) | |
| download | upstream-109e614d906995cc7d9ec1233a13eb8be1823ba3.tar.gz upstream-109e614d906995cc7d9ec1233a13eb8be1823ba3.tar.bz2 upstream-109e614d906995cc7d9ec1233a13eb8be1823ba3.zip | |
mediatek: backport upstream patches related to mt7629 support
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Diffstat (limited to 'target/linux')
5 files changed, 17403 insertions, 0 deletions
diff --git a/target/linux/mediatek/patches-4.19/0002-Revert-ARM-mediatek-add-MT7623a-smp-bringup-code.patch b/target/linux/mediatek/patches-4.19/0002-Revert-ARM-mediatek-add-MT7623a-smp-bringup-code.patch new file mode 100644 index 0000000000..5c48ae19fc --- /dev/null +++ b/target/linux/mediatek/patches-4.19/0002-Revert-ARM-mediatek-add-MT7623a-smp-bringup-code.patch @@ -0,0 +1,51 @@ +From 2663146427cedb9d7582cfa481d5d5611fb3138a Mon Sep 17 00:00:00 2001 +From: Ryder Lee <ryder.lee@mediatek.com> +Date: Tue, 29 Jan 2019 12:28:48 +0800 +Subject: [PATCH] Revert "ARM: mediatek: add MT7623a smp bringup code" + +This reverts commit 3b99ab7deca1e5f4229b4bdecd005d71e22cfc60. + +The compatible "mediatek,mt7623a" is useless, so remove it. + +Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> +Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> +--- + arch/arm/mach-mediatek/mediatek.c | 2 -- + arch/arm/mach-mediatek/platsmp.c | 1 - + 2 files changed, 3 deletions(-) + +diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c +index 6910b4e0d913..c3cf215773b2 100644 +--- a/arch/arm/mach-mediatek/mediatek.c ++++ b/arch/arm/mach-mediatek/mediatek.c +@@ -30,7 +30,6 @@ static void __init mediatek_timer_init(void) + + if (of_machine_is_compatible("mediatek,mt6589") || + of_machine_is_compatible("mediatek,mt7623") || +- of_machine_is_compatible("mediatek,mt7623a") || + of_machine_is_compatible("mediatek,mt8135") || + of_machine_is_compatible("mediatek,mt8127")) { + /* turn on GPT6 which ungates arch timer clocks */ +@@ -50,7 +49,6 @@ static const char * const mediatek_board_dt_compat[] = { + "mediatek,mt6589", + "mediatek,mt6592", + "mediatek,mt7623", +- "mediatek,mt7623a", + "mediatek,mt8127", + "mediatek,mt8135", + NULL, +diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c +index 6882ff07aaa6..51e85562098c 100644 +--- a/arch/arm/mach-mediatek/platsmp.c ++++ b/arch/arm/mach-mediatek/platsmp.c +@@ -60,7 +60,6 @@ static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = { + static const struct of_device_id mtk_smp_boot_infos[] __initconst = { + { .compatible = "mediatek,mt6589", .data = &mtk_mt6589_boot }, + { .compatible = "mediatek,mt7623", .data = &mtk_mt7623_boot }, +- { .compatible = "mediatek,mt7623a", .data = &mtk_mt7623_boot }, + {}, + }; + +-- +2.21.0 + diff --git a/target/linux/mediatek/patches-4.19/0003-arm-mediatek-add-MT7629-smp-bring-up-code.patch b/target/linux/mediatek/patches-4.19/0003-arm-mediatek-add-MT7629-smp-bring-up-code.patch new file mode 100644 index 0000000000..898488ef1e --- /dev/null +++ b/target/linux/mediatek/patches-4.19/0003-arm-mediatek-add-MT7629-smp-bring-up-code.patch @@ -0,0 +1,57 @@ +From a43379dddf1ba14b6a9d50d95175117bbdf52ed2 Mon Sep 17 00:00:00 2001 +From: Ryder Lee <ryder.lee@mediatek.com> +Date: Tue, 29 Jan 2019 12:31:18 +0800 +Subject: [PATCH] arm: mediatek: add MT7629 smp bring up code + +Add support for booting secondary CPUs on MT7629. + +Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> +Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> +--- + arch/arm/mach-mediatek/Kconfig | 4 ++++ + arch/arm/mach-mediatek/mediatek.c | 1 + + arch/arm/mach-mediatek/platsmp.c | 1 + + 3 files changed, 6 insertions(+) + +diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig +index 91cc461f7b04..11ed264f0731 100644 +--- a/arch/arm/mach-mediatek/Kconfig ++++ b/arch/arm/mach-mediatek/Kconfig +@@ -26,6 +26,10 @@ config MACH_MT7623 + bool "MediaTek MT7623 SoCs support" + default ARCH_MEDIATEK + ++config MACH_MT7629 ++ bool "MediaTek MT7629 SoCs support" ++ default ARCH_MEDIATEK ++ + config MACH_MT8127 + bool "MediaTek MT8127 SoCs support" + default ARCH_MEDIATEK +diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c +index c3cf215773b2..b6a81ba1ce32 100644 +--- a/arch/arm/mach-mediatek/mediatek.c ++++ b/arch/arm/mach-mediatek/mediatek.c +@@ -49,6 +49,7 @@ static const char * const mediatek_board_dt_compat[] = { + "mediatek,mt6589", + "mediatek,mt6592", + "mediatek,mt7623", ++ "mediatek,mt7629", + "mediatek,mt8127", + "mediatek,mt8135", + NULL, +diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c +index 51e85562098c..c9d7c0458452 100644 +--- a/arch/arm/mach-mediatek/platsmp.c ++++ b/arch/arm/mach-mediatek/platsmp.c +@@ -60,6 +60,7 @@ static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = { + static const struct of_device_id mtk_smp_boot_infos[] __initconst = { + { .compatible = "mediatek,mt6589", .data = &mtk_mt6589_boot }, + { .compatible = "mediatek,mt7623", .data = &mtk_mt7623_boot }, ++ { .compatible = "mediatek,mt7629", .data = &mtk_mt7623_boot }, + {}, + }; + +-- +2.21.0 + diff --git a/target/linux/mediatek/patches-4.19/0004-clk-mediatek-add-clock-support-for-MT7629-SoC.patch b/target/linux/mediatek/patches-4.19/0004-clk-mediatek-add-clock-support-for-MT7629-SoC.patch new file mode 100644 index 0000000000..87aa5a82ef --- /dev/null +++ b/target/linux/mediatek/patches-4.19/0004-clk-mediatek-add-clock-support-for-MT7629-SoC.patch @@ -0,0 +1,1339 @@ +From 3b5e748615e714711220b2a95d19bd25a037db09 Mon Sep 17 00:00:00 2001 +From: Ryder Lee <ryder.lee@mediatek.com> +Date: Mon, 5 Nov 2018 16:43:55 +0800 +Subject: [PATCH] clk: mediatek: add clock support for MT7629 SoC + +Add all supported clocks exported from every susbystem found on MT7629 SoC. + +Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com> +Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> +Acked-by: Rob Herring <robh@kernel.org> +Signed-off-by: Stephen Boyd <sboyd@kernel.org> +--- + drivers/clk/mediatek/Kconfig | 23 + + drivers/clk/mediatek/Makefile | 3 + + drivers/clk/mediatek/clk-mt7629-eth.c | 159 ++++++ + drivers/clk/mediatek/clk-mt7629-hif.c | 156 ++++++ + drivers/clk/mediatek/clk-mt7629.c | 723 +++++++++++++++++++++++++ + include/dt-bindings/clock/mt7629-clk.h | 203 +++++++ + 6 files changed, 1267 insertions(+) + create mode 100644 drivers/clk/mediatek/clk-mt7629-eth.c + create mode 100644 drivers/clk/mediatek/clk-mt7629-hif.c + create mode 100644 drivers/clk/mediatek/clk-mt7629.c + create mode 100644 include/dt-bindings/clock/mt7629-clk.h + +diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig +index 3dd1dab92223..53edade25a1d 100644 +--- a/drivers/clk/mediatek/Kconfig ++++ b/drivers/clk/mediatek/Kconfig +@@ -178,6 +178,29 @@ config COMMON_CLK_MT7622_AUDSYS + This driver supports MediaTek MT7622 AUDSYS clocks providing + to audio consumers such as I2S and TDM. + ++config COMMON_CLK_MT7629 ++ bool "Clock driver for MediaTek MT7629" ++ depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST ++ select COMMON_CLK_MEDIATEK ++ default ARCH_MEDIATEK && ARM ++ ---help--- ++ This driver supports MediaTek MT7629 basic clocks and clocks ++ required for various periperals found on MediaTek. ++ ++config COMMON_CLK_MT7629_ETHSYS ++ bool "Clock driver for MediaTek MT7629 ETHSYS" ++ depends on COMMON_CLK_MT7629 ++ ---help--- ++ This driver add support for clocks for Ethernet and SGMII ++ required on MediaTek MT7629 SoC. ++ ++config COMMON_CLK_MT7629_HIFSYS ++ bool "Clock driver for MediaTek MT7629 HIFSYS" ++ depends on COMMON_CLK_MT7629 ++ ---help--- ++ This driver supports MediaTek MT7629 HIFSYS clocks providing ++ to PCI-E and USB. ++ + config COMMON_CLK_MT8135 + bool "Clock driver for MediaTek MT8135" + depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST +diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile +index 844b55d2770d..ee4410ff43ab 100644 +--- a/drivers/clk/mediatek/Makefile ++++ b/drivers/clk/mediatek/Makefile +@@ -26,5 +26,8 @@ obj-$(CONFIG_COMMON_CLK_MT7622) += clk-mt7622.o + obj-$(CONFIG_COMMON_CLK_MT7622_ETHSYS) += clk-mt7622-eth.o + obj-$(CONFIG_COMMON_CLK_MT7622_HIFSYS) += clk-mt7622-hif.o + obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) += clk-mt7622-aud.o ++obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o ++obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o ++obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o + obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o + obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o +diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c +new file mode 100644 +index 000000000000..88279d0ea1a7 +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt7629-eth.c +@@ -0,0 +1,159 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2018 MediaTek Inc. ++ * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com> ++ * Ryder Lee <ryder.lee@mediatek.com> ++ */ ++ ++#include <linux/clk-provider.h> ++#include <linux/of.h> ++#include <linux/of_address.h> ++#include <linux/of_device.h> ++#include <linux/platform_device.h> ++ ++#include "clk-mtk.h" ++#include "clk-gate.h" ++ ++#include <dt-bindings/clock/mt7629-clk.h> ++ ++#define GATE_ETH(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = ð_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ ++ } ++ ++static const struct mtk_gate_regs eth_cg_regs = { ++ .set_ofs = 0x30, ++ .clr_ofs = 0x30, ++ .sta_ofs = 0x30, ++}; ++ ++static const struct mtk_gate eth_clks[] = { ++ GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "eth2pll", 6), ++ GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7), ++ GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8), ++ GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9), ++ GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 16), ++}; ++ ++static const struct mtk_gate_regs sgmii_cg_regs = { ++ .set_ofs = 0xE4, ++ .clr_ofs = 0xE4, ++ .sta_ofs = 0xE4, ++}; ++ ++#define GATE_SGMII(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &sgmii_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ ++ } ++ ++static const struct mtk_gate sgmii_clks[2][4] = { ++ { ++ GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en", ++ "ssusb_tx250m", 2), ++ GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en", ++ "ssusb_eq_rx250m", 3), ++ GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref", ++ "ssusb_cdr_ref", 4), ++ GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb", ++ "ssusb_cdr_fb", 5), ++ }, { ++ GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en1", ++ "ssusb_tx250m", 2), ++ GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en1", ++ "ssusb_eq_rx250m", 3), ++ GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref1", ++ "ssusb_cdr_ref", 4), ++ GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb1", ++ "ssusb_cdr_fb", 5), ++ } ++}; ++ ++static int clk_mt7629_ethsys_init(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ struct device_node *node = pdev->dev.of_node; ++ int r; ++ ++ clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK); ++ ++ mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ if (r) ++ dev_err(&pdev->dev, ++ "could not register clock provider: %s: %d\n", ++ pdev->name, r); ++ ++ mtk_register_reset_controller(node, 1, 0x34); ++ ++ return r; ++} ++ ++static int clk_mt7629_sgmiisys_init(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ struct device_node *node = pdev->dev.of_node; ++ static int id; ++ int r; ++ ++ clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK); ++ ++ mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK, ++ clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ if (r) ++ dev_err(&pdev->dev, ++ "could not register clock provider: %s: %d\n", ++ pdev->name, r); ++ ++ return r; ++} ++ ++static const struct of_device_id of_match_clk_mt7629_eth[] = { ++ { ++ .compatible = "mediatek,mt7629-ethsys", ++ .data = clk_mt7629_ethsys_init, ++ }, { ++ .compatible = "mediatek,mt7629-sgmiisys", ++ .data = clk_mt7629_sgmiisys_init, ++ }, { ++ /* sentinel */ ++ } ++}; ++ ++static int clk_mt7629_eth_probe(struct platform_device *pdev) ++{ ++ int (*clk_init)(struct platform_device *); ++ int r; ++ ++ clk_init = of_device_get_match_data(&pdev->dev); ++ if (!clk_init) ++ return -EINVAL; ++ ++ r = clk_init(pdev); ++ if (r) ++ dev_err(&pdev->dev, ++ "could not register clock provider: %s: %d\n", ++ pdev->name, r); ++ ++ return r; ++} ++ ++static struct platform_driver clk_mt7629_eth_drv = { ++ .probe = clk_mt7629_eth_probe, ++ .driver = { ++ .name = "clk-mt7629-eth", ++ .of_match_table = of_match_clk_mt7629_eth, ++ }, ++}; ++ ++builtin_platform_driver(clk_mt7629_eth_drv); +diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c +new file mode 100644 +index 000000000000..5c5b37207afb +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt7629-hif.c +@@ -0,0 +1,156 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2018 MediaTek Inc. ++ * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com> ++ * Ryder Lee <ryder.lee@mediatek.com> ++ */ ++ ++#include <linux/clk-provider.h> ++#include <linux/of.h> ++#include <linux/of_address.h> ++#include <linux/of_device.h> ++#include <linux/platform_device.h> ++ ++#include "clk-mtk.h" ++#include "clk-gate.h" ++ ++#include <dt-bindings/clock/mt7629-clk.h> ++ ++#define GATE_PCIE(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &pcie_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ ++ } ++ ++#define GATE_SSUSB(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &ssusb_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ ++ } ++ ++static const struct mtk_gate_regs pcie_cg_regs = { ++ .set_ofs = 0x30, ++ .clr_ofs = 0x30, ++ .sta_ofs = 0x30, ++}; ++ ++static const struct mtk_gate_regs ssusb_cg_regs = { ++ .set_ofs = 0x30, ++ .clr_ofs = 0x30, ++ .sta_ofs = 0x30, ++}; ++ ++static const struct mtk_gate ssusb_clks[] = { ++ GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p", ++ "to_u2_phy_1p", 0), ++ GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1), ++ GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5), ++ GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6), ++ GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "to_usb3_mcu", 7), ++ GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "to_usb3_dma", 8), ++}; ++ ++static const struct mtk_gate pcie_clks[] = { ++ GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12), ++ GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13), ++ GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "from_top_ahb", 14), ++ GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "from_top_axi", 15), ++ GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16), ++ GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17), ++ GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18), ++ GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19), ++ GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "from_top_ahb", 20), ++ GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "from_top_axi", 21), ++ GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22), ++ GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23), ++}; ++ ++static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ struct device_node *node = pdev->dev.of_node; ++ int r; ++ ++ clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); ++ ++ mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), ++ clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ if (r) ++ dev_err(&pdev->dev, ++ "could not register clock provider: %s: %d\n", ++ pdev->name, r); ++ ++ mtk_register_reset_controller(node, 1, 0x34); ++ ++ return r; ++} ++ ++static int clk_mt7629_pciesys_init(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ struct device_node *node = pdev->dev.of_node; ++ int r; ++ ++ clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); ++ ++ mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), ++ clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ if (r) ++ dev_err(&pdev->dev, ++ "could not register clock provider: %s: %d\n", ++ pdev->name, r); ++ ++ mtk_register_reset_controller(node, 1, 0x34); ++ ++ return r; ++} ++ ++static const struct of_device_id of_match_clk_mt7629_hif[] = { ++ { ++ .compatible = "mediatek,mt7629-pciesys", ++ .data = clk_mt7629_pciesys_init, ++ }, { ++ .compatible = "mediatek,mt7629-ssusbsys", ++ .data = clk_mt7629_ssusbsys_init, ++ }, { ++ /* sentinel */ ++ } ++}; ++ ++static int clk_mt7629_hif_probe(struct platform_device *pdev) ++{ ++ int (*clk_init)(struct platform_device *); ++ int r; ++ ++ clk_init = of_device_get_match_data(&pdev->dev); ++ if (!clk_init) ++ return -EINVAL; ++ ++ r = clk_init(pdev); ++ if (r) ++ dev_err(&pdev->dev, ++ "could not register clock provider: %s: %d\n", ++ pdev->name, r); ++ ++ return r; ++} ++ ++static struct platform_driver clk_mt7629_hif_drv = { ++ .probe = clk_mt7629_hif_probe, ++ .driver = { ++ .name = "clk-mt7629-hif", ++ .of_match_table = of_match_clk_mt7629_hif, ++ }, ++}; ++ ++builtin_platform_driver(clk_mt7629_hif_drv); +diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c +new file mode 100644 +index 000000000000..200ba147bbc6 +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt7629.c +@@ -0,0 +1,723 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2018 MediaTek Inc. ++ * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com> ++ * Ryder Lee <ryder.lee@mediatek.com> ++ */ ++ ++#include <linux/clk.h> ++#include <linux/clk-provider.h> ++#include <linux/of.h> ++#include <linux/of_address.h> ++#include <linux/of_device.h> ++#include <linux/platform_device.h> ++ ++#include "clk-mtk.h" ++#include "clk-gate.h" ++#include "clk-cpumux.h" ++ ++#include <dt-bindings/clock/mt7629-clk.h> ++ ++#define MT7629_PLL_FMAX (2500UL * MHZ) ++#define CON0_MT7629_RST_BAR BIT(24) ++ ++#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ ++ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ ++ _pcw_shift, _div_table, _parent_name) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .reg = _reg, \ ++ .pwr_reg = _pwr_reg, \ ++ .en_mask = _en_mask, \ ++ .flags = _flags, \ ++ .rst_bar_mask = CON0_MT7629_RST_BAR, \ ++ .fmax = MT7629_PLL_FMAX, \ ++ .pcwbits = _pcwbits, \ ++ .pd_reg = _pd_reg, \ ++ .pd_shift = _pd_shift, \ ++ .tuner_reg = _tuner_reg, \ ++ .pcw_reg = _pcw_reg, \ ++ .pcw_shift = _pcw_shift, \ ++ .div_table = _div_table, \ ++ .parent_name = _parent_name, \ ++ } ++ ++#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ ++ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ ++ _pcw_shift) \ ++ PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ ++ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ ++ NULL, "clk20m") ++ ++#define GATE_APMIXED(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &apmixed_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ ++ } ++ ++#define GATE_INFRA(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &infra_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++#define GATE_PERI0(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &peri0_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++#define GATE_PERI1(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &peri1_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++static DEFINE_SPINLOCK(mt7629_clk_lock); ++ ++static const char * const axi_parents[] = { ++ "clkxtal", ++ "syspll1_d2", ++ "syspll_d5", ++ "syspll1_d4", ++ "univpll_d5", ++ "univpll2_d2", ++ "univpll_d7", ++ "dmpll_ck" ++}; ++ ++static const char * const mem_parents[] = { ++ "clkxtal", ++ "dmpll_ck" ++}; ++ ++static const char * const ddrphycfg_parents[] = { ++ "clkxtal", ++ "syspll1_d8" ++}; ++ ++static const char * const eth_parents[] = { ++ "clkxtal", ++ "syspll1_d2", ++ "univpll1_d2", ++ "syspll1_d4", ++ "univpll_d5", ++ "sgmiipll_d2", ++ "univpll_d7", ++ "dmpll_ck" ++}; ++ ++static const char * const pwm_parents[] = { ++ "clkxtal", ++ "univpll2_d4" ++}; ++ ++static const char * const f10m_ref_parents[] = { ++ "clkxtal", ++ "sgmiipll_d2" ++}; ++ ++static const char * const nfi_infra_parents[] = { ++ "clkxtal", ++ "clkxtal", ++ "clkxtal", ++ "clkxtal", ++ "clkxtal", ++ "clkxtal", ++ "univpll2_d8", ++ "univpll3_d4", ++ "syspll1_d8", ++ "univpll1_d8", ++ "syspll4_d2", ++ "syspll2_d4", ++ "univpll2_d4", ++ "univpll3_d2", ++ "syspll1_d4", ++ "syspll_d7" ++}; ++ ++static const char * const flash_parents[] = { ++ "clkxtal", ++ "univpll_d80_d4", ++ "syspll2_d8", ++ "syspll3_d4", ++ "univpll3_d4", ++ "univpll1_d8", ++ "syspll2_d4", ++ "univpll2_d4" ++}; ++ ++static const char * const uart_parents[] = { ++ "clkxtal", ++ "univpll2_d8" ++}; ++ ++static const char * const spi0_parents[] = { ++ "clkxtal", ++ "syspll3_d2", ++ "clkxtal", ++ "syspll2_d4", ++ "syspll4_d2", ++ "univpll2_d4", ++ "univpll1_d8", ++ "clkxtal" ++}; ++ ++static const char * const spi1_parents[] = { ++ "clkxtal", ++ "syspll3_d2", ++ "clkxtal", ++ "syspll4_d4", ++ "syspll4_d2", ++ "univpll2_d4", ++ "univpll1_d8", ++ "clkxtal" ++}; ++ ++static const char * const msdc30_0_parents[] = { ++ "clkxtal", ++ "univpll2_d16", ++ "univ48m" ++}; ++ ++static const char * const msdc30_1_parents[] = { ++ "clkxtal", ++ "univpll2_d16", ++ "univ48m", ++ "syspll2_d4", ++ "univpll2_d4", ++ "syspll_d7", ++ "syspll2_d2", ++ "univpll2_d2" ++}; ++ ++static const char * const ap2wbmcu_parents[] = { ++ "clkxtal", ++ "syspll1_d2", ++ "univ48m", ++ "syspll1_d8", ++ "univpll2_d4", ++ "syspll_d7", ++ "syspll2_d2", ++ "univpll2_d2" ++}; ++ ++static const char * const audio_parents[] = { ++ "clkxtal", ++ "syspll3_d4", ++ "syspll4_d4", ++ "syspll1_d16" ++}; ++ ++static const char * const aud_intbus_parents[] = { ++ "clkxtal", ++ "syspll1_d4", ++ "syspll4_d2", ++ "dmpll_d4" ++}; ++ ++static const char * const pmicspi_parents[] = { ++ "clkxtal", ++ "syspll1_d8", ++ "syspll3_d4", ++ "syspll1_d16", ++ "univpll3_d4", ++ "clkxtal", ++ "univpll2_d4", ++ "dmpll_d8" ++}; ++ ++static const char * const scp_parents[] = { ++ "clkxtal", ++ "syspll1_d8", ++ "univpll2_d2", ++ "univpll2_d4" ++}; ++ ++static const char * const atb_parents[] = { ++ "clkxtal", ++ "syspll1_d2", ++ "syspll_d5" ++}; ++ ++static const char * const hif_parents[] = { ++ "clkxtal", ++ "syspll1_d2", ++ "univpll1_d2", ++ "syspll1_d4", ++ "univpll_d5", ++ "clk_null", ++ "univpll_d7" ++}; ++ ++static const char * const sata_parents[] = { ++ "clkxtal", ++ "univpll2_d4" ++}; ++ ++static const char * const usb20_parents[] = { ++ "clkxtal", ++ "univpll3_d4", ++ "syspll1_d8" ++}; ++ ++static const char * const aud1_parents[] = { ++ "clkxtal" ++}; ++ ++static const char * const irrx_parents[] = { ++ "clkxtal", ++ "syspll4_d16" ++}; ++ ++static const char * const crypto_parents[] = { ++ "clkxtal", ++ "univpll_d3", ++ "univpll1_d2", ++ "syspll1_d2", ++ "univpll_d5", ++ "syspll_d5", ++ "univpll2_d2", ++ "syspll_d2" ++}; ++ ++static const char * const gpt10m_parents[] = { ++ "clkxtal", ++ "clkxtal_d4" ++}; ++ ++static const char * const peribus_ck_parents[] = { ++ "syspll1_d8", ++ "syspll1_d4" ++}; ++ ++static const char * const infra_mux1_parents[] = { ++ "clkxtal", ++ "armpll", ++ "main_core_en", ++ "armpll" ++}; ++ ++static const struct mtk_gate_regs apmixed_cg_regs = { ++ .set_ofs = 0x8, ++ .clr_ofs = 0x8, ++ .sta_ofs = 0x8, ++}; ++ ++static const struct mtk_gate_regs infra_cg_regs = { ++ .set_ofs = 0x40, ++ .clr_ofs = 0x44, ++ .sta_ofs = 0x48, ++}; ++ ++static const struct mtk_gate_regs peri0_cg_regs = { ++ .set_ofs = 0x8, ++ .clr_ofs = 0x10, ++ .sta_ofs = 0x18, ++}; ++ ++static const struct mtk_gate_regs peri1_cg_regs = { ++ .set_ofs = 0xC, ++ .clr_ofs = 0x14, ++ .sta_ofs = 0x1C, ++}; ++ ++static const struct mtk_pll_data plls[] = { ++ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, ++ 0, 21, 0x0204, 24, 0, 0x0204, 0), ++ PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001, ++ HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0), ++ PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001, ++ HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14), ++ PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001, ++ 0, 21, 0x0300, 1, 0, 0x0304, 0), ++ PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001, ++ 0, 21, 0x0314, 1, 0, 0x0318, 0), ++ PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001, ++ 0, 21, 0x0358, 1, 0, 0x035C, 0), ++}; ++ ++static const struct mtk_gate apmixed_clks[] = { ++ GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5), ++}; ++ ++static const struct mtk_gate infra_clks[] = { ++ GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "hd_faxi", 0), ++ GATE_INFRA(CLK_INFRA_TRNG_PD, "infra_trng_pd", "hd_faxi", 2), ++ GATE_INFRA(CLK_INFRA_DEVAPC_PD, "infra_devapc_pd", "hd_faxi", 4), ++ GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "infrao_10m", 18), ++ GATE_INFRA(CLK_INFRA_SEJ_PD, "infra_sej_pd", "infrao_10m", 19), ++}; ++ ++static const struct mtk_fixed_clk top_fixed_clks[] = { ++ FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal", ++ 31250000), ++ FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal", ++ 31250000), ++ FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal", ++ 125000000), ++ FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal", ++ 125000000), ++ FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal", ++ 250000000), ++ FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal", ++ 250000000), ++ FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal", ++ 33333333), ++ FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal", ++ 50000000), ++ FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal", ++ 50000000), ++ FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal", ++ 50000000), ++}; ++ ++static const struct mtk_fixed_factor top_divs[] = { ++ FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4), ++ FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500), ++ FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125), ++ FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500), ++ FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1), ++ FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1), ++ FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024), ++ FACTOR(CLK_TOP_PWM_QTR_26M, "pwm_qtr_26m", "clkxtal", 1, 1), ++ FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "cpum_tck", 1, 1), ++ FACTOR(CLK_TOP_TO_USB3_DA_TOP, "to_usb3_da_top", "clkxtal", 1, 1), ++ FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1), ++ FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1), ++ FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "mempll", 1, 4), ++ FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "mempll", 1, 8), ++ FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2), ++ FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4), ++ FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8), ++ FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16), ++ FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32), ++ FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll", 1, 6), ++ FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12), ++ FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24), ++ FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5), ++ FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10), ++ FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20), ++ FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7), ++ FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14), ++ FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28), ++ FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112), ++ FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2), ++ FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4), ++ FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8), ++ FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16), ++ FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), ++ FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6), ++ FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12), ++ FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24), ++ FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48), ++ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), ++ FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10), ++ FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20), ++ FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80), ++ FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), ++ FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320), ++ FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25), ++ FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2), ++ FACTOR(CLK_TOP_CLKXTAL_D4, "clkxtal_d4", "clkxtal", 1, 4), ++ FACTOR(CLK_TOP_HD_FAXI, "hd_faxi", "axi_sel", 1, 1), ++ FACTOR(CLK_TOP_FAXI, "faxi", "axi_sel", 1, 1), ++ FACTOR(CLK_TOP_F_FAUD_INTBUS, "f_faud_intbus", "aud_intbus_sel", 1, 1), ++ FACTOR(CLK_TOP_AP2WBHIF_HCLK, "ap2wbhif_hclk", "syspll1_d8", 1, 1), ++ FACTOR(CLK_TOP_10M_INFRAO, "infrao_10m", "gpt10m_sel", 1, 1), ++ FACTOR(CLK_TOP_MSDC30_1, "msdc30_1", "msdc30_1_sel", 1, 1), ++ FACTOR(CLK_TOP_SPI, "spi", "spi0_sel", 1, 1), ++ FACTOR(CLK_TOP_SF, "sf", "nfi_infra_sel", 1, 1), ++ FACTOR(CLK_TOP_FLASH, "flash", "flash_sel", 1, 1), ++ FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "sata_sel", 1, 4), ++ FACTOR(CLK_TOP_TO_USB3_MCU, "to_usb3_mcu", "axi_sel", 1, 1), ++ FACTOR(CLK_TOP_TO_USB3_DMA, "to_usb3_dma", "hif_sel", 1, 1), ++ FACTOR(CLK_TOP_FROM_TOP_AHB, "from_top_ahb", "axi_sel", 1, 1), ++ FACTOR(CLK_TOP_FROM_TOP_AXI, "from_top_axi", "hif_sel", 1, 1), ++ FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1), ++ FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1), ++}; ++ ++static const struct mtk_gate peri_clks[] = { ++ /* PERI0 */ ++ GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "pwm_qtr_26m", 2), ++ GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "pwm_qtr_26m", 3), ++ GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "pwm_qtr_26m", 4), ++ GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "pwm_qtr_26m", 5), ++ GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "pwm_qtr_26m", 6), ++ GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "pwm_qtr_26m", 7), ++ GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "pwm_qtr_26m", 8), ++ GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "pwm_qtr_26m", 9), ++ GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "faxi", 12), ++ GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1", 14), ++ GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "faxi", 17), ++ GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "faxi", 18), ++ GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "faxi", 19), ++ GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "faxi", 20), ++ GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "faxi", 22), ++ GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "faxi", 23), ++ GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi", 28), ++ GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "sf", 29), ++ GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "faxi", 30), ++ GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "faxi", 31), ++ /* PERI1 */ ++ GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash", 1), ++}; ++ ++static struct mtk_composite infra_muxes[] = { ++ /* INFRA_TOPCKGEN_CKMUXSEL */ ++ MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 0x000, ++ 2, 2), ++}; ++ ++static struct mtk_composite top_muxes[] = { ++ /* CLK_CFG_0 */ ++ MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, ++ 0x040, 0, 3, 7), ++ MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, ++ 0x040, 8, 1, 15), ++ MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, ++ 0x040, 16, 1, 23), ++ MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, ++ 0x040, 24, 3, 31), ++ /* CLK_CFG_1 */ ++ MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, ++ 0x050, 0, 2, 7), ++ MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents, ++ 0x050, 8, 1, 15), ++ MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents, ++ 0x050, 16, 4, 23), ++ MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents, ++ 0x050, 24, 3, 31), ++ /* CLK_CFG_2 */ ++ MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, ++ 0x060, 0, 1, 7), ++ MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents, ++ 0x060, 8, 3, 15), ++ MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents, ++ 0x060, 16, 3, 23), ++ MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents, ++ 0x060, 24, 3, 31), ++ /* CLK_CFG_3 */ ++ MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents, ++ 0x070, 0, 3, 7), ++ MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, ++ 0x070, 8, 3, 15), ++ MUX_GATE(CLK_TOP_AP2WBMCU_SEL, "ap2wbmcu_sel", ap2wbmcu_parents, ++ 0x070, 16, 3, 23), ++ MUX_GATE(CLK_TOP_AP2WBHIF_SEL, "ap2wbhif_sel", ap2wbmcu_parents, ++ 0x070, 24, 3, 31), ++ /* CLK_CFG_4 */ ++ MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, ++ 0x080, 0, 2, 7), ++ MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, ++ 0x080, 8, 2, 15), ++ MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, ++ 0x080, 16, 3, 23), ++ MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, ++ 0x080, 24, 2, 31), ++ /* CLK_CFG_5 */ ++ MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, ++ 0x090, 0, 2, 7), ++ MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", hif_parents, ++ 0x090, 8, 3, 15), ++ MUX_GATE(CLK_TOP_SATA_SEL, "sata_sel", sata_parents, ++ 0x090, 16, 1, 23), ++ MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents, ++ 0x090, 24, 2, 31), ++ /* CLK_CFG_6 */ ++ MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents, ++ 0x0A0, 0, 1, 7), ++ MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud1_parents, ++ 0x0A0, 8, 1, 15), ++ MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", irrx_parents, ++ 0x0A0, 16, 1, 23), ++ MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", irrx_parents, ++ 0x0A0, 24, 1, 31), ++ /* CLK_CFG_7 */ ++ MUX_GATE(CLK_TOP_SATA_MCU_SEL, "sata_mcu_sel", scp_parents, ++ 0x0B0, 0, 2, 7), ++ MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, "pcie0_mcu_sel", scp_parents, ++ 0x0B0, 8, 2, 15), ++ MUX_GATE(CLK_TOP_PCIE1_MCU_SEL, "pcie1_mcu_sel", scp_parents, ++ 0x0B0, 16, 2, 23), ++ MUX_GATE(CLK_TOP_SSUSB_MCU_SEL, "ssusb_mcu_sel", scp_parents, ++ 0x0B0, 24, 2, 31), ++ /* CLK_CFG_8 */ ++ MUX_GATE(CLK_TOP_CRYPTO_SEL, "crypto_sel", crypto_parents, ++ 0x0C0, 0, 3, 7), ++ MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, "sgmii_ref_1_sel", f10m_ref_parents, ++ 0x0C0, 8, 1, 15), ++ MUX_GATE(CLK_TOP_10M_SEL, "gpt10m_sel", gpt10m_parents, ++ 0x0C0, 16, 1, 23), ++}; ++ ++static struct mtk_composite peri_muxes[] = { ++ /* PERI_GLOBALCON_CKSEL */ ++ MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1), ++}; ++ ++static int mtk_topckgen_init(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ void __iomem *base; ++ struct device_node *node = pdev->dev.of_node; ++ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ++ base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); ++ ++ mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), ++ clk_data); ++ ++ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), ++ clk_data); ++ ++ mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), ++ base, &mt7629_clk_lock, clk_data); ++ ++ clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]); ++ clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]); ++ clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); ++ ++ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++} ++ ++static int mtk_infrasys_init(struct platform_device *pdev) ++{ ++ struct device_node *node = pdev->dev.of_node; ++ struct clk_onecell_data *clk_data; ++ int r; ++ ++ clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); ++ ++ mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), ++ clk_data); ++ ++ mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), ++ clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, ++ clk_data); ++ if (r) ++ return r; ++ ++ return 0; ++} ++ ++static int mtk_pericfg_init(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ void __iomem *base; ++ int r; ++ struct device_node *node = pdev->dev.of_node; ++ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ++ base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); ++ ++ mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), ++ clk_data); ++ ++ mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, ++ &mt7629_clk_lock, clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ if (r) ++ return r; ++ ++ clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]); ++ ++ return 0; ++} ++ ++static int mtk_apmixedsys_init(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ struct device_node *node = pdev->dev.of_node; ++ ++ clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); ++ if (!clk_data) ++ return -ENOMEM; ++ ++ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), ++ clk_data); ++ ++ mtk_clk_register_gates(node, apmixed_clks, ++ ARRAY_SIZE(apmixed_clks), clk_data); ++ ++ clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]); ++ clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]); ++ ++ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++} ++ ++ ++static const struct of_device_id of_match_clk_mt7629[] = { ++ { ++ .compatible = "mediatek,mt7629-apmixedsys", ++ .data = mtk_apmixedsys_init, ++ }, { ++ .compatible = "mediatek,mt7629-infracfg", ++ .data = mtk_infrasys_init, ++ }, { ++ .compatible = "mediatek,mt7629-topckgen", ++ .data = mtk_topckgen_init, ++ }, { ++ .compatible = "mediatek,mt7629-pericfg", ++ .data = mtk_pericfg_init, ++ }, { ++ /* sentinel */ ++ } ++}; ++ ++static int clk_mt7629_probe(struct platform_device *pdev) ++{ ++ int (*clk_init)(struct platform_device *); ++ int r; ++ ++ clk_init = of_device_get_match_data(&pdev->dev); ++ if (!clk_init) ++ return -EINVAL; ++ ++ r = clk_init(pdev); ++ if (r) ++ dev_err(&pdev->dev, ++ "could not register clock provider: %s: %d\n", ++ pdev->name, r); ++ ++ return r; ++} ++ ++static struct platform_driver clk_mt7629_drv = { ++ .probe = clk_mt7629_probe, ++ .driver = { ++ .name = "clk-mt7629", ++ .of_match_table = of_match_clk_mt7629, ++ }, ++}; ++ ++static int clk_mt7629_init(void) ++{ ++ return platform_driver_register(&clk_mt7629_drv); ++} ++ ++arch_initcall(clk_mt7629_init); +diff --git a/include/dt-bindings/clock/mt7629-clk.h b/include/dt-bindings/clock/mt7629-clk.h +new file mode 100644 +index 000000000000..ad8e6d7f0154 +--- /dev/null ++++ b/include/dt-bindings/clock/mt7629-clk.h +@@ -0,0 +1,203 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2018 MediaTek Inc. ++ */ ++ ++#ifndef _DT_BINDINGS_CLK_MT7629_H ++#define _DT_BINDINGS_CLK_MT7629_H ++ ++/* TOPCKGEN */ ++#define CLK_TOP_TO_U2_PHY 0 ++#define CLK_TOP_TO_U2_PHY_1P 1 ++#define CLK_TOP_PCIE0_PIPE_EN 2 ++#define CLK_TOP_PCIE1_PIPE_EN 3 ++#define CLK_TOP_SSUSB_TX250M 4 ++#define CLK_TOP_SSUSB_EQ_RX250M 5 ++#define CLK_TOP_SSUSB_CDR_REF 6 ++#define CLK_TOP_SSUSB_CDR_FB 7 ++#define CLK_TOP_SATA_ASIC 8 ++#define CLK_TOP_SATA_RBC 9 ++#define CLK_TOP_TO_USB3_SYS 10 ++#define CLK_TOP_P1_1MHZ 11 ++#define CLK_TOP_4MHZ 12 ++#define CLK_TOP_P0_1MHZ 13 ++#define CLK_TOP_ETH_500M 14 ++#define CLK_TOP_TXCLK_SRC_PRE 15 ++#define CLK_TOP_RTC 16 ++#define CLK_TOP_PWM_QTR_26M 17 ++#define CLK_TOP_CPUM_TCK_IN 18 ++#define CLK_TOP_TO_USB3_DA_TOP 19 ++#define CLK_TOP_MEMPLL 20 ++#define CLK_TOP_DMPLL 21 ++#define CLK_TOP_DMPLL_D4 22 ++#define CLK_TOP_DMPLL_D8 23 ++#define CLK_TOP_SYSPLL_D2 24 ++#define CLK_TOP_SYSPLL1_D2 25 ++#define CLK_TOP_SYSPLL1_D4 26 ++#define CLK_TOP_SYSPLL1_D8 27 ++#define CLK_TOP_SYSPLL1_D16 28 ++#define CLK_TOP_SYSPLL2_D2 29 ++#define CLK_TOP_SYSPLL2_D4 30 ++#define CLK_TOP_SYSPLL2_D8 31 ++#define CLK_TOP_SYSPLL_D5 32 ++#define CLK_TOP_SYSPLL3_D2 33 ++#define CLK_TOP_SYSPLL3_D4 34 ++#define CLK_TOP_SYSPLL_D7 35 ++#define CLK_TOP_SYSPLL4_D2 36 ++#define CLK_TOP_SYSPLL4_D4 37 ++#define CLK_TOP_SYSPLL4_D16 38 ++#define CLK_TOP_UNIVPLL 39 ++#define CLK_TOP_UNIVPLL1_D2 40 ++#define CLK_TOP_UNIVPLL1_D4 41 ++#define CLK_TOP_UNIVPLL1_D8 42 ++#define CLK_TOP_UNIVPLL_D3 43 ++#define CLK_TOP_UNIVPLL2_D2 44 ++#define CLK_TOP_UNIVPLL2_D4 45 ++#define CLK_TOP_UNIVPLL2_D8 46 ++#define CLK_TOP_UNIVPLL2_D16 47 ++#define CLK_TOP_UNIVPLL_D5 48 ++#define CLK_TOP_UNIVPLL3_D2 49 ++#define CLK_TOP_UNIVPLL3_D4 50 ++#define CLK_TOP_UNIVPLL3_D16 51 ++#define CLK_TOP_UNIVPLL_D7 52 ++#define CLK_TOP_UNIVPLL_D80_D4 53 ++#define CLK_TOP_UNIV48M 54 ++#define CLK_TOP_SGMIIPLL_D2 55 ++#define CLK_TOP_CLKXTAL_D4 56 ++#define CLK_TOP_HD_FAXI 57 ++#define CLK_TOP_FAXI 58 ++#define CLK_TOP_F_FAUD_INTBUS 59 ++#define CLK_TOP_AP2WBHIF_HCLK 60 ++#define CLK_TOP_10M_INFRAO 61 ++#define CLK_TOP_MSDC30_1 62 ++#define CLK_TOP_SPI 63 ++#define CLK_TOP_SF 64 ++#define CLK_TOP_FLASH 65 ++#define CLK_TOP_TO_USB3_REF 66 ++#define CLK_TOP_TO_USB3_MCU 67 ++#define CLK_TOP_TO_USB3_DMA 68 ++#define CLK_TOP_FROM_TOP_AHB 69 ++#define CLK_TOP_FROM_TOP_AXI 70 ++#define CLK_TOP_PCIE1_MAC_EN 71 ++#define CLK_TOP_PCIE0_MAC_EN 72 ++#define CLK_TOP_AXI_SEL 73 ++#define CLK_TOP_MEM_SEL 74 ++#define CLK_TOP_DDRPHYCFG_SEL 75 ++#define CLK_TOP_ETH_SEL 76 ++#define CLK_TOP_PWM_SEL 77 ++#define CLK_TOP_F10M_REF_SEL 78 ++#define CLK_TOP_NFI_INFRA_SEL 79 ++#define CLK_TOP_FLASH_SEL 80 ++#define CLK_TOP_UART_SEL 81 ++#define CLK_TOP_SPI0_SEL 82 ++#define CLK_TOP_SPI1_SEL 83 ++#define CLK_TOP_MSDC50_0_SEL 84 ++#define CLK_TOP_MSDC30_0_SEL 85 ++#define CLK_TOP_MSDC30_1_SEL 86 ++#define CLK_TOP_AP2WBMCU_SEL 87 ++#define CLK_TOP_AP2WBHIF_SEL 88 ++#define CLK_TOP_AUDIO_SEL 89 ++#define CLK_TOP_AUD_INTBUS_SEL 90 ++#define CLK_TOP_PMICSPI_SEL 91 ++#define CLK_TOP_SCP_SEL 92 ++#define CLK_TOP_ATB_SEL 93 ++#define CLK_TOP_HIF_SEL 94 ++#define CLK_TOP_SATA_SEL 95 ++#define CLK_TOP_U2_SEL 96 ++#define CLK_TOP_AUD1_SEL 97 ++#define CLK_TOP_AUD2_SEL 98 ++#define CLK_TOP_IRRX_SEL 99 ++#define CLK_TOP_IRTX_SEL 100 ++#define CLK_TOP_SATA_MCU_SEL 101 ++#define CLK_TOP_PCIE0_MCU_SEL 102 ++#define CLK_TOP_PCIE1_MCU_SEL 103 ++#define CLK_TOP_SSUSB_MCU_SEL 104 ++#define CLK_TOP_CRYPTO_SEL 105 ++#define CLK_TOP_SGMII_REF_1_SEL 106 ++#define CLK_TOP_10M_SEL 107 ++#define CLK_TOP_NR_CLK 108 ++ ++/* INFRACFG */ ++#define CLK_INFRA_MUX1_SEL 0 ++#define CLK_INFRA_DBGCLK_PD 1 ++#define CLK_INFRA_TRNG_PD 2 ++#define CLK_INFRA_DEVAPC_PD 3 ++#define CLK_INFRA_APXGPT_PD 4 ++#define CLK_INFRA_SEJ_PD 5 ++#define CLK_INFRA_NR_CLK 6 ++ ++/* PERICFG */ ++#define CLK_PERIBUS_SEL 0 ++#define CLK_PERI_PWM1_PD 1 ++#define CLK_PERI_PWM2_PD 2 ++#define CLK_PERI_PWM3_PD 3 ++#define CLK_PERI_PWM4_PD 4 ++#define CLK_PERI_PWM5_PD 5 ++#define CLK_PERI_PWM6_PD 6 ++#define CLK_PERI_PWM7_PD 7 ++#define CLK_PERI_PWM_PD 8 ++#define CLK_PERI_AP_DMA_PD 9 ++#define CLK_PERI_MSDC30_1_PD 10 ++#define CLK_PERI_UART0_PD 11 ++#define CLK_PERI_UART1_PD 12 ++#define CLK_PERI_UART2_PD 13 ++#define CLK_PERI_UART3_PD 14 ++#define CLK_PERI_BTIF_PD 15 ++#define CLK_PERI_I2C0_PD 16 ++#define CLK_PERI_SPI0_PD 17 ++#define CLK_PERI_SNFI_PD 18 ++#define CLK_PERI_NFI_PD 19 ++#define CLK_PERI_NFIECC_PD 20 ++#define CLK_PERI_FLASH_PD 21 ++#define CLK_PERI_NR_CLK 22 ++ ++/* APMIXEDSYS */ ++#define CLK_APMIXED_ARMPLL 0 ++#define CLK_APMIXED_MAINPLL 1 ++#define CLK_APMIXED_UNIV2PLL 2 ++#define CLK_APMIXED_ETH1PLL 3 ++#define CLK_APMIXED_ETH2PLL 4 ++#define CLK_APMIXED_SGMIPLL 5 ++#define CLK_APMIXED_MAIN_CORE_EN 6 ++#define CLK_APMIXED_NR_CLK 7 ++ ++/* SSUSBSYS */ ++#define CLK_SSUSB_U2_PHY_1P_EN 0 ++#define CLK_SSUSB_U2_PHY_EN 1 ++#define CLK_SSUSB_REF_EN 2 ++#define CLK_SSUSB_SYS_EN 3 ++#define CLK_SSUSB_MCU_EN 4 ++#define CLK_SSUSB_DMA_EN 5 ++#define CLK_SSUSB_NR_CLK 6 ++ ++/* PCIESYS */ ++#define CLK_PCIE_P1_AUX_EN 0 ++#define CLK_PCIE_P1_OBFF_EN 1 ++#define CLK_PCIE_P1_AHB_EN 2 ++#define CLK_PCIE_P1_AXI_EN 3 ++#define CLK_PCIE_P1_MAC_EN 4 ++#define CLK_PCIE_P1_PIPE_EN 5 ++#define CLK_PCIE_P0_AUX_EN 6 ++#define CLK_PCIE_P0_OBFF_EN 7 ++#define CLK_PCIE_P0_AHB_EN 8 ++#define CLK_PCIE_P0_AXI_EN 9 ++#define CLK_PCIE_P0_MAC_EN 10 ++#define CLK_PCIE_P0_PIPE_EN 11 ++#define CLK_PCIE_NR_CLK 12 ++ ++/* ETHSYS */ ++#define CLK_ETH_FE_EN 0 ++#define CLK_ETH_GP2_EN 1 ++#define CLK_ETH_GP1_EN 2 ++#define CLK_ETH_GP0_EN 3 ++#define CLK_ETH_ESW_EN 4 ++#define CLK_ETH_NR_CLK 5 ++ ++/* SGMIISYS */ ++#define CLK_SGMII_TX_EN 0 ++#define CLK_SGMII_RX_EN 1 ++#define CLK_SGMII_CDR_REF 2 ++#define CLK_SGMII_CDR_FB 3 ++#define CLK_SGMII_NR_CLK 4 ++ ++#endif /* _DT_BINDINGS_CLK_MT7629_H */ +-- +2.21.0 + diff --git a/target/linux/mediatek/patches-4.19/0005-pinctrl-mediatek-sync-with-5.3.patch b/target/linux/mediatek/patches-4.19/0005-pinctrl-mediatek-sync-with-5.3.patch new file mode 100644 index 0000000000..129b48dfce --- /dev/null +++ b/target/linux/mediatek/patches-4.19/0005-pinctrl-mediatek-sync-with-5.3.patch @@ -0,0 +1,15922 @@ +This patch squashes the following upstream commits: + +5ca1b1c5cd98 pinctrl: mediatek: mt8183: Add pm_ops +5c0904488a20 pinctrl: mediatek: Add pm_ops to pinctrl-paris +1802d0beecaf treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 +ec8f24b7faaf treewide: Add SPDX license identifier - Makefile/Kconfig +264667112ef0 pinctrl: mediatek: Add MT8516 Pinctrl driver +5e73de3413c5 pinctrl: add drive for I2C related pins on MT8183 +e65372124cd7 Merge tag 'v5.0-rc6' into devel +2d2d478576d7 pinctrl: mediatek: fix Kconfig build errors for moore core +6e737a4e921e pinctrl: mediatek: add EINT support to virtual GPIOs +b5af33df50e9 pinctrl: mediatek: improve Kconfig dependencies +9ede2a76f66e pinctrl: mediatek: Convert to using %pOFn instead of device_node.name +b44677375fee pinctrl: mediatek: add pinctrl support for MT7629 SoC +f969b7aac980 pinctrl: mediatek: Add initial pinctrl driver for MT6797 SoC +7c68024a82a2 pinctrl: mediatek: Fix dependencies for EINT_MTK +78bf386daf8a pinctrl: mediatek: clean up indentation issues, add missing tab +28e0603c4df4 pinctrl: mediatek: Make eint_m u16 +71a9d395aa12 pinctrl: mediatek: select GPIOLIB +ad335bee6ced pinctrl: mediatek: mark dummy helpers as 'static inline' +7a52127e3cf1 pinctrl: mediatek: fix check on EINT_NA comparison +bb8d8466ca25 pinctrl: mediatek: add eint support to MT6765 pinctrl driver +477fecee7ca9 pinctrl: mediatek: add MT6765 pinctrl driver +ecfcfb498860 pinctrl: mediatek: add no eint function for pin define +7f2e29e133ea pinctrl: mediatek: fix static checker warning caused by EINT_NA +068cfb9a0fd9 pinctrl: mediatek: moore: fix return value check in mtk_moore_pinctrl_probe() +07c6b037c2ba pinctrl: mediatek: make symbol 'mtk_drive' static +184744e9a014 pinctrl: mediatek: paris: fix return value check in mtk_paris_pinctrl_probe() +22d7fe4984a2 pinctrl: mtk: Fix up GPIO includes +55818b90233b Merge branch 'ib-mtk' into devel +6561859b067f pinctrl: mediatek: add eint support to MT8183 pinctrl driver +89132dd8ffd2 pinctrl: mediatek: extend eint build to pinctrl-mtk-common-v2.c +29686f0151df pintcrl: mediatek: add pull tweaks for I2C related pins on MT8183 +79348f6fb713 pinctrl: mediatek: extend advanced pull support in pinctrl-mtk-common-v2.c +750cd15d9081 pinctrl: mediatek: add MT8183 pinctrl driver +805250982bb5 pinctrl: mediatek: add pinctrl-paris that implements the vendor dt-bindings +b7d7f9eeca55 pinctrl: mediatek: extend struct mtk_pin_desc which per-pin driver depends on +9d9b171c6897 pinctrl: mediatek: adjust error code and message when some register not supported is found +2bc47dfe4f8b pinctrl: mediatek: add multiple register bases support to pinctrl-mtk-common-v2.c +ea051eb38413 pinctrl: mediatek: use pin descriptor all in pinctrl-mtk-common-v2.c +e7507f57a93a pinctrl: mediatek: add MT7623 pinctrl driver based on generic pinctrl binding +9afc305bfad7 pinctrl: mediatek: add pullen, pullsel register support to pinctrl-mtk-common-v2.c +182c842fd5e6 pinctrl: mediatek: add ies register support to pinctrl-mtk-common-v2.c +0d7ca772148f pinctrl: mediatek: add advanced pull related support to pinctrl-mtk-common-v2.c +85430152ba46 pinctrl: mediatek: add pull related support to pinctrl-mtk-common-v2.c +3ad38a14e13c pinctrl: mediatek: add drv register support to pinctrl-mtk-common-v2.c +c28321979ba8 pinctrl: mediatek: add driving strength related support to pinctrl-mtk-common-v2.c +1dc5e5369159 pinctrl: mediatek: extend struct mtk_pin_soc to pinctrl-mtk-common-v2.c +fb5fa8dc151b pinctrl: mediatek: extend struct mtk_pin_desc to pinctrl-mtk-common-v2.c +b906faf7b61d pinctrl: mediatek: extend struct mtk_pin_field_calc to pinctrl-mtk-common-v2.c +e78d57b2f87c pinctrl: mediatek: add pinctrl-moore that implements the generic pinctrl dt-bindings +a1a503a8c332 pinctrl: mediatek: add pinctrl-mtk-common-v2 for all MediaTek pinctrls +1c5fb66afa2a pinctrl: Include <linux/gpio/driver.h> nothing else +94f4e54cecaf pinctrl: Convert to using %pOFn instead of device_node.name + +diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig +index 9905dc672f6b..26ed5dca1460 100644 +--- a/drivers/pinctrl/mediatek/Kconfig ++++ b/drivers/pinctrl/mediatek/Kconfig +@@ -3,7 +3,8 @@ menu "MediaTek pinctrl drivers" + + config EINT_MTK + bool "MediaTek External Interrupt Support" +- depends on PINCTRL_MTK || PINCTRL_MT7622 || COMPILE_TEST ++ depends on PINCTRL_MTK || PINCTRL_MTK_MOORE || PINCTRL_MTK_PARIS || COMPILE_TEST ++ select GPIOLIB + select IRQ_DOMAIN + + config PINCTRL_MTK +@@ -15,6 +16,24 @@ config PINCTRL_MTK + select EINT_MTK + select OF_GPIO + ++config PINCTRL_MTK_MOORE ++ bool ++ depends on OF ++ select GENERIC_PINCONF ++ select GENERIC_PINCTRL_GROUPS ++ select GENERIC_PINMUX_FUNCTIONS ++ select GPIOLIB ++ select OF_GPIO ++ ++config PINCTRL_MTK_PARIS ++ bool ++ depends on OF ++ select PINMUX ++ select GENERIC_PINCONF ++ select GPIOLIB ++ select EINT_MTK ++ select OF_GPIO ++ + # For ARMv7 SoCs + config PINCTRL_MT2701 + bool "Mediatek MT2701 pin control" +@@ -23,6 +42,20 @@ config PINCTRL_MT2701 + default MACH_MT2701 + select PINCTRL_MTK + ++config PINCTRL_MT7623 ++ bool "Mediatek MT7623 pin control with generic binding" ++ depends on MACH_MT7623 || COMPILE_TEST ++ depends on OF ++ default MACH_MT7623 ++ select PINCTRL_MTK_MOORE ++ ++config PINCTRL_MT7629 ++ bool "Mediatek MT7629 pin control" ++ depends on MACH_MT7629 || COMPILE_TEST ++ depends on OF ++ default MACH_MT7629 ++ select PINCTRL_MTK_MOORE ++ + config PINCTRL_MT8135 + bool "Mediatek MT8135 pin control" + depends on MACH_MT8135 || COMPILE_TEST +@@ -45,15 +78,26 @@ config PINCTRL_MT2712 + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK + ++config PINCTRL_MT6765 ++ bool "Mediatek MT6765 pin control" ++ depends on OF ++ depends on ARM64 || COMPILE_TEST ++ default ARM64 && ARCH_MEDIATEK ++ select PINCTRL_MTK_PARIS ++ ++config PINCTRL_MT6797 ++ bool "Mediatek MT6797 pin control" ++ depends on OF ++ depends on ARM64 || COMPILE_TEST ++ default ARM64 && ARCH_MEDIATEK ++ select PINCTRL_MTK_PARIS ++ + config PINCTRL_MT7622 + bool "MediaTek MT7622 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST +- select GENERIC_PINCONF +- select GENERIC_PINCTRL_GROUPS +- select GENERIC_PINMUX_FUNCTIONS +- select GPIOLIB +- select OF_GPIO ++ default ARM64 && ARCH_MEDIATEK ++ select PINCTRL_MTK_MOORE + + config PINCTRL_MT8173 + bool "Mediatek MT8173 pin control" +@@ -62,6 +106,20 @@ config PINCTRL_MT8173 + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK + ++config PINCTRL_MT8183 ++ bool "Mediatek MT8183 pin control" ++ depends on OF ++ depends on ARM64 || COMPILE_TEST ++ default ARM64 && ARCH_MEDIATEK ++ select PINCTRL_MTK_PARIS ++ ++config PINCTRL_MT8516 ++ bool "Mediatek MT8516 pin control" ++ depends on OF ++ depends on ARM64 || COMPILE_TEST ++ default ARM64 && ARCH_MEDIATEK ++ select PINCTRL_MTK ++ + # For PMIC + config PINCTRL_MT6397 + bool "Mediatek MT6397 pin control" +diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile +index 3de7156df345..a74325abd877 100644 +--- a/drivers/pinctrl/mediatek/Makefile ++++ b/drivers/pinctrl/mediatek/Makefile +@@ -2,12 +2,20 @@ + # Core + obj-$(CONFIG_EINT_MTK) += mtk-eint.o + obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o ++obj-$(CONFIG_PINCTRL_MTK_MOORE) += pinctrl-moore.o pinctrl-mtk-common-v2.o ++obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o pinctrl-mtk-common-v2.o + + # SoC Drivers + obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o + obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o + obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o + obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o ++obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o ++obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o + obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o ++obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o ++obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o + obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o ++obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o ++obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o + obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o +diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c +index a613e546717a..f464f8cd274b 100644 +--- a/drivers/pinctrl/mediatek/mtk-eint.c ++++ b/drivers/pinctrl/mediatek/mtk-eint.c +@@ -11,7 +11,7 @@ + + #include <linux/delay.h> + #include <linux/err.h> +-#include <linux/gpio.h> ++#include <linux/gpio/driver.h> + #include <linux/io.h> + #include <linux/irqchip/chained_irq.h> + #include <linux/irqdomain.h> +diff --git a/drivers/pinctrl/mediatek/mtk-eint.h b/drivers/pinctrl/mediatek/mtk-eint.h +index c286a9b940f2..48468d0fae68 100644 +--- a/drivers/pinctrl/mediatek/mtk-eint.h ++++ b/drivers/pinctrl/mediatek/mtk-eint.h +@@ -92,13 +92,13 @@ static inline int mtk_eint_do_resume(struct mtk_eint *eint) + return -EOPNOTSUPP; + } + +-int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_n, ++static inline int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_n, + unsigned int debounce) + { + return -EOPNOTSUPP; + } + +-int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n) ++static inline int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n) + { + return -EOPNOTSUPP; + } +diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c +new file mode 100644 +index 000000000000..aa1068d2867f +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-moore.c +@@ -0,0 +1,690 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * MediaTek Pinctrl Moore Driver, which implement the generic dt-binding ++ * pinctrl-bindings.txt for MediaTek SoC. ++ * ++ * Copyright (C) 2017-2018 MediaTek Inc. ++ * Author: Sean Wang <sean.wang@mediatek.com> ++ * ++ */ ++ ++#include <linux/gpio/driver.h> ++#include "pinctrl-moore.h" ++ ++#define PINCTRL_PINCTRL_DEV KBUILD_MODNAME ++ ++/* Custom pinconf parameters */ ++#define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1) ++#define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2) ++#define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3) ++#define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4) ++ ++static const struct pinconf_generic_params mtk_custom_bindings[] = { ++ {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0}, ++ {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0}, ++ {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1}, ++ {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1}, ++}; ++ ++#ifdef CONFIG_DEBUG_FS ++static const struct pin_config_item mtk_conf_items[] = { ++ PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true), ++ PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true), ++ PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true), ++ PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true), ++}; ++#endif ++ ++static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev, ++ unsigned int selector, unsigned int group) ++{ ++ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); ++ struct function_desc *func; ++ struct group_desc *grp; ++ int i; ++ ++ func = pinmux_generic_get_function(pctldev, selector); ++ if (!func) ++ return -EINVAL; ++ ++ grp = pinctrl_generic_get_group(pctldev, group); ++ if (!grp) ++ return -EINVAL; ++ ++ dev_dbg(pctldev->dev, "enable function %s group %s\n", ++ func->name, grp->name); ++ ++ for (i = 0; i < grp->num_pins; i++) { ++ const struct mtk_pin_desc *desc; ++ int *pin_modes = grp->data; ++ int pin = grp->pins[i]; ++ ++ desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; ++ ++ mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, ++ pin_modes[i]); ++ } ++ ++ return 0; ++} ++ ++static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, ++ struct pinctrl_gpio_range *range, ++ unsigned int pin) ++{ ++ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); ++ const struct mtk_pin_desc *desc; ++ ++ desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; ++ ++ return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, ++ hw->soc->gpio_m); ++} ++ ++static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, ++ struct pinctrl_gpio_range *range, ++ unsigned int pin, bool input) ++{ ++ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); ++ const struct mtk_pin_desc *desc; ++ ++ desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; ++ ++ /* hardware would take 0 as input direction */ ++ return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input); ++} ++ ++static int mtk_pinconf_get(struct pinctrl_dev *pctldev, ++ unsigned int pin, unsigned long *config) ++{ ++ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); ++ u32 param = pinconf_to_config_param(*config); ++ int val, val2, err, reg, ret = 1; ++ const struct mtk_pin_desc *desc; ++ ++ desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; ++ ++ switch (param) { ++ case PIN_CONFIG_BIAS_DISABLE: ++ if (hw->soc->bias_disable_get) { ++ err = hw->soc->bias_disable_get(hw, desc, &ret); ++ if (err) ++ return err; ++ } else { ++ return -ENOTSUPP; ++ } ++ break; ++ case PIN_CONFIG_BIAS_PULL_UP: ++ if (hw->soc->bias_get) { ++ err = hw->soc->bias_get(hw, desc, 1, &ret); ++ if (err) ++ return err; ++ } else { ++ return -ENOTSUPP; ++ } ++ break; ++ case PIN_CONFIG_BIAS_PULL_DOWN: ++ if (hw->soc->bias_get) { ++ err = hw->soc->bias_get(hw, desc, 0, &ret); ++ if (err) ++ return err; ++ } else { ++ return -ENOTSUPP; ++ } ++ break; ++ case PIN_CONFIG_SLEW_RATE: ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &val); ++ if (err) ++ return err; ++ ++ if (!val) ++ return -EINVAL; ++ ++ break; ++ case PIN_CONFIG_INPUT_ENABLE: ++ case PIN_CONFIG_OUTPUT_ENABLE: ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val); ++ if (err) ++ return err; ++ ++ /* HW takes input mode as zero; output mode as non-zero */ ++ if ((val && param == PIN_CONFIG_INPUT_ENABLE) || ++ (!val && param == PIN_CONFIG_OUTPUT_ENABLE)) ++ return -EINVAL; ++ ++ break; ++ case PIN_CONFIG_INPUT_SCHMITT_ENABLE: ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val); ++ if (err) ++ return err; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &val2); ++ if (err) ++ return err; ++ ++ if (val || !val2) ++ return -EINVAL; ++ ++ break; ++ case PIN_CONFIG_DRIVE_STRENGTH: ++ if (hw->soc->drive_get) { ++ err = hw->soc->drive_get(hw, desc, &ret); ++ if (err) ++ return err; ++ } else { ++ err = -ENOTSUPP; ++ } ++ break; ++ case MTK_PIN_CONFIG_TDSEL: ++ case MTK_PIN_CONFIG_RDSEL: ++ reg = (param == MTK_PIN_CONFIG_TDSEL) ? ++ PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL; ++ ++ err = mtk_hw_get_value(hw, desc, reg, &val); ++ if (err) ++ return err; ++ ++ ret = val; ++ ++ break; ++ case MTK_PIN_CONFIG_PU_ADV: ++ case MTK_PIN_CONFIG_PD_ADV: ++ if (hw->soc->adv_pull_get) { ++ bool pullup; ++ ++ pullup = param == MTK_PIN_CONFIG_PU_ADV; ++ err = hw->soc->adv_pull_get(hw, desc, pullup, &ret); ++ if (err) ++ return err; ++ } else { ++ return -ENOTSUPP; ++ } ++ break; ++ default: ++ return -ENOTSUPP; ++ } ++ ++ *config = pinconf_to_config_packed(param, ret); ++ ++ return 0; ++} ++ ++static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, ++ unsigned long *configs, unsigned int num_configs) ++{ ++ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); ++ const struct mtk_pin_desc *desc; ++ u32 reg, param, arg; ++ int cfg, err = 0; ++ ++ desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; ++ ++ for (cfg = 0; cfg < num_configs; cfg++) { ++ param = pinconf_to_config_param(configs[cfg]); ++ arg = pinconf_to_config_argument(configs[cfg]); ++ ++ switch (param) { ++ case PIN_CONFIG_BIAS_DISABLE: ++ if (hw->soc->bias_disable_set) { ++ err = hw->soc->bias_disable_set(hw, desc); ++ if (err) ++ return err; ++ } else { ++ return -ENOTSUPP; ++ } ++ break; ++ case PIN_CONFIG_BIAS_PULL_UP: ++ if (hw->soc->bias_set) { ++ err = hw->soc->bias_set(hw, desc, 1); ++ if (err) ++ return err; ++ } else { ++ return -ENOTSUPP; ++ } ++ break; ++ case PIN_CONFIG_BIAS_PULL_DOWN: ++ if (hw->soc->bias_set) { ++ err = hw->soc->bias_set(hw, desc, 0); ++ if (err) ++ return err; ++ } else { ++ return -ENOTSUPP; ++ } ++ break; ++ case PIN_CONFIG_OUTPUT_ENABLE: ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, ++ MTK_DISABLE); ++ if (err) ++ goto err; ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, ++ MTK_OUTPUT); ++ if (err) ++ goto err; ++ break; ++ case PIN_CONFIG_INPUT_ENABLE: ++ ++ if (hw->soc->ies_present) { ++ mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, ++ MTK_ENABLE); ++ } ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, ++ MTK_INPUT); ++ if (err) ++ goto err; ++ break; ++ case PIN_CONFIG_SLEW_RATE: ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR, ++ arg); ++ if (err) ++ goto err; ++ ++ break; ++ case PIN_CONFIG_OUTPUT: ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, ++ MTK_OUTPUT); ++ if (err) ++ goto err; ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, ++ arg); ++ if (err) ++ goto err; ++ break; ++ case PIN_CONFIG_INPUT_SCHMITT_ENABLE: ++ /* arg = 1: Input mode & SMT enable ; ++ * arg = 0: Output mode & SMT disable ++ */ ++ arg = arg ? 2 : 1; ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, ++ arg & 1); ++ if (err) ++ goto err; ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, ++ !!(arg & 2)); ++ if (err) ++ goto err; ++ break; ++ case PIN_CONFIG_DRIVE_STRENGTH: ++ if (hw->soc->drive_set) { ++ err = hw->soc->drive_set(hw, desc, arg); ++ if (err) ++ return err; ++ } else { ++ err = -ENOTSUPP; ++ } ++ break; ++ case MTK_PIN_CONFIG_TDSEL: ++ case MTK_PIN_CONFIG_RDSEL: ++ reg = (param == MTK_PIN_CONFIG_TDSEL) ? ++ PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL; ++ ++ err = mtk_hw_set_value(hw, desc, reg, arg); ++ if (err) ++ goto err; ++ break; ++ case MTK_PIN_CONFIG_PU_ADV: ++ case MTK_PIN_CONFIG_PD_ADV: ++ if (hw->soc->adv_pull_set) { ++ bool pullup; ++ ++ pullup = param == MTK_PIN_CONFIG_PU_ADV; ++ err = hw->soc->adv_pull_set(hw, desc, pullup, ++ arg); ++ if (err) ++ return err; ++ } else { ++ return -ENOTSUPP; ++ } ++ break; ++ default: ++ err = -ENOTSUPP; ++ } ++ } ++err: ++ return err; ++} ++ ++static int mtk_pinconf_group_get(struct pinctrl_dev *pctldev, ++ unsigned int group, unsigned long *config) ++{ ++ const unsigned int *pins; ++ unsigned int i, npins, old = 0; ++ int ret; ++ ++ ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); ++ if (ret) ++ return ret; ++ ++ for (i = 0; i < npins; i++) { ++ if (mtk_pinconf_get(pctldev, pins[i], config)) ++ return -ENOTSUPP; ++ ++ /* configs do not match between two pins */ ++ if (i && old != *config) ++ return -ENOTSUPP; ++ ++ old = *config; ++ } ++ ++ return 0; ++} ++ ++static int mtk_pinconf_group_set(struct pinctrl_dev *pctldev, ++ unsigned int group, unsigned long *configs, ++ unsigned int num_configs) ++{ ++ const unsigned int *pins; ++ unsigned int i, npins; ++ int ret; ++ ++ ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); ++ if (ret) ++ return ret; ++ ++ for (i = 0; i < npins; i++) { ++ ret = mtk_pinconf_set(pctldev, pins[i], configs, num_configs); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static const struct pinctrl_ops mtk_pctlops = { ++ .get_groups_count = pinctrl_generic_get_group_count, ++ .get_group_name = pinctrl_generic_get_group_name, ++ .get_group_pins = pinctrl_generic_get_group_pins, ++ .dt_node_to_map = pinconf_generic_dt_node_to_map_all, ++ .dt_free_map = pinconf_generic_dt_free_map, ++}; ++ ++static const struct pinmux_ops mtk_pmxops = { ++ .get_functions_count = pinmux_generic_get_function_count, ++ .get_function_name = pinmux_generic_get_function_name, ++ .get_function_groups = pinmux_generic_get_function_groups, ++ .set_mux = mtk_pinmux_set_mux, ++ .gpio_request_enable = mtk_pinmux_gpio_request_enable, ++ .gpio_set_direction = mtk_pinmux_gpio_set_direction, ++ .strict = true, ++}; ++ ++static const struct pinconf_ops mtk_confops = { ++ .is_generic = true, ++ .pin_config_get = mtk_pinconf_get, ++ .pin_config_set = mtk_pinconf_set, ++ .pin_config_group_get = mtk_pinconf_group_get, ++ .pin_config_group_set = mtk_pinconf_group_set, ++ .pin_config_config_dbg_show = pinconf_generic_dump_config, ++}; ++ ++static struct pinctrl_desc mtk_desc = { ++ .name = PINCTRL_PINCTRL_DEV, ++ .pctlops = &mtk_pctlops, ++ .pmxops = &mtk_pmxops, ++ .confops = &mtk_confops, ++ .owner = THIS_MODULE, ++}; ++ ++static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio) ++{ ++ struct mtk_pinctrl *hw = gpiochip_get_data(chip); ++ const struct mtk_pin_desc *desc; ++ int value, err; ++ ++ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value); ++ if (err) ++ return err; ++ ++ return !!value; ++} ++ ++static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) ++{ ++ struct mtk_pinctrl *hw = gpiochip_get_data(chip); ++ const struct mtk_pin_desc *desc; ++ ++ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; ++ ++ mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value); ++} ++ ++static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio) ++{ ++ return pinctrl_gpio_direction_input(chip->base + gpio); ++} ++ ++static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, ++ int value) ++{ ++ mtk_gpio_set(chip, gpio, value); ++ ++ return pinctrl_gpio_direction_output(chip->base + gpio); ++} ++ ++static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) ++{ ++ struct mtk_pinctrl *hw = gpiochip_get_data(chip); ++ const struct mtk_pin_desc *desc; ++ ++ if (!hw->eint) ++ return -ENOTSUPP; ++ ++ desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset]; ++ ++ if (desc->eint.eint_n == (u16)EINT_NA) ++ return -ENOTSUPP; ++ ++ return mtk_eint_find_irq(hw->eint, desc->eint.eint_n); ++} ++ ++static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset, ++ unsigned long config) ++{ ++ struct mtk_pinctrl *hw = gpiochip_get_data(chip); ++ const struct mtk_pin_desc *desc; ++ u32 debounce; ++ ++ desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset]; ++ ++ if (!hw->eint || ++ pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE || ++ desc->eint.eint_n == (u16)EINT_NA) ++ return -ENOTSUPP; ++ ++ debounce = pinconf_to_config_argument(config); ++ ++ return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce); ++} ++ ++static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np) ++{ ++ struct gpio_chip *chip = &hw->chip; ++ int ret; ++ ++ chip->label = PINCTRL_PINCTRL_DEV; ++ chip->parent = hw->dev; ++ chip->request = gpiochip_generic_request; ++ chip->free = gpiochip_generic_free; ++ chip->direction_input = mtk_gpio_direction_input; ++ chip->direction_output = mtk_gpio_direction_output; ++ chip->get = mtk_gpio_get; ++ chip->set = mtk_gpio_set; ++ chip->to_irq = mtk_gpio_to_irq, ++ chip->set_config = mtk_gpio_set_config, ++ chip->base = -1; ++ chip->ngpio = hw->soc->npins; ++ chip->of_node = np; ++ chip->of_gpio_n_cells = 2; ++ ++ ret = gpiochip_add_data(chip, hw); ++ if (ret < 0) ++ return ret; ++ ++ /* Just for backward compatible for these old pinctrl nodes without ++ * "gpio-ranges" property. Otherwise, called directly from a ++ * DeviceTree-supported pinctrl driver is DEPRECATED. ++ * Please see Section 2.1 of ++ * Documentation/devicetree/bindings/gpio/gpio.txt on how to ++ * bind pinctrl and gpio drivers via the "gpio-ranges" property. ++ */ ++ if (!of_find_property(np, "gpio-ranges", NULL)) { ++ ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0, ++ chip->ngpio); ++ if (ret < 0) { ++ gpiochip_remove(chip); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static int mtk_build_groups(struct mtk_pinctrl *hw) ++{ ++ int err, i; ++ ++ for (i = 0; i < hw->soc->ngrps; i++) { ++ const struct group_desc *group = hw->soc->grps + i; ++ ++ err = pinctrl_generic_add_group(hw->pctrl, group->name, ++ group->pins, group->num_pins, ++ group->data); ++ if (err < 0) { ++ dev_err(hw->dev, "Failed to register group %s\n", ++ group->name); ++ return err; ++ } ++ } ++ ++ return 0; ++} ++ ++static int mtk_build_functions(struct mtk_pinctrl *hw) ++{ ++ int i, err; ++ ++ for (i = 0; i < hw->soc->nfuncs ; i++) { ++ const struct function_desc *func = hw->soc->funcs + i; ++ ++ err = pinmux_generic_add_function(hw->pctrl, func->name, ++ func->group_names, ++ func->num_group_names, ++ func->data); ++ if (err < 0) { ++ dev_err(hw->dev, "Failed to register function %s\n", ++ func->name); ++ return err; ++ } ++ } ++ ++ return 0; ++} ++ ++int mtk_moore_pinctrl_probe(struct platform_device *pdev, ++ const struct mtk_pin_soc *soc) ++{ ++ struct pinctrl_pin_desc *pins; ++ struct resource *res; ++ struct mtk_pinctrl *hw; ++ int err, i; ++ ++ hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL); ++ if (!hw) ++ return -ENOMEM; ++ ++ hw->soc = soc; ++ hw->dev = &pdev->dev; ++ ++ if (!hw->soc->nbase_names) { ++ dev_err(&pdev->dev, ++ "SoC should be assigned at least one register base\n"); ++ return -EINVAL; ++ } ++ ++ hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names, ++ sizeof(*hw->base), GFP_KERNEL); ++ if (!hw->base) ++ return -ENOMEM; ++ ++ for (i = 0; i < hw->soc->nbase_names; i++) { ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, ++ hw->soc->base_names[i]); ++ if (!res) { ++ dev_err(&pdev->dev, "missing IO resource\n"); ++ return -ENXIO; ++ } ++ ++ hw->base[i] = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(hw->base[i])) ++ return PTR_ERR(hw->base[i]); ++ } ++ ++ hw->nbase = hw->soc->nbase_names; ++ ++ /* Copy from internal struct mtk_pin_desc to register to the core */ ++ pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins), ++ GFP_KERNEL); ++ if (!pins) ++ return -ENOMEM; ++ ++ for (i = 0; i < hw->soc->npins; i++) { ++ pins[i].number = hw->soc->pins[i].number; ++ pins[i].name = hw->soc->pins[i].name; ++ } ++ ++ /* Setup pins descriptions per SoC types */ ++ mtk_desc.pins = (const struct pinctrl_pin_desc *)pins; ++ mtk_desc.npins = hw->soc->npins; ++ mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings); ++ mtk_desc.custom_params = mtk_custom_bindings; ++#ifdef CONFIG_DEBUG_FS ++ mtk_desc.custom_conf_items = mtk_conf_items; ++#endif ++ ++ err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw, ++ &hw->pctrl); ++ if (err) ++ return err; ++ ++ /* Setup groups descriptions per SoC types */ ++ err = mtk_build_groups(hw); ++ if (err) { ++ dev_err(&pdev->dev, "Failed to build groups\n"); ++ return err; ++ } ++ ++ /* Setup functions descriptions per SoC types */ ++ err = mtk_build_functions(hw); ++ if (err) { ++ dev_err(&pdev->dev, "Failed to build functions\n"); ++ return err; ++ } ++ ++ /* For able to make pinctrl_claim_hogs, we must not enable pinctrl ++ * until all groups and functions are being added one. ++ */ ++ err = pinctrl_enable(hw->pctrl); ++ if (err) ++ return err; ++ ++ err = mtk_build_eint(hw, pdev); ++ if (err) ++ dev_warn(&pdev->dev, ++ "Failed to add EINT, but pinctrl still can work\n"); ++ ++ /* Build gpiochip should be after pinctrl_enable is done */ ++ err = mtk_build_gpiochip(hw, pdev->dev.of_node); ++ if (err) { ++ dev_err(&pdev->dev, "Failed to add gpio_chip\n"); ++ return err; ++ } ++ ++ platform_set_drvdata(pdev, hw); ++ ++ return 0; ++} +diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.h b/drivers/pinctrl/mediatek/pinctrl-moore.h +new file mode 100644 +index 000000000000..e1b4b82b9d3d +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-moore.h +@@ -0,0 +1,51 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2017-2018 MediaTek Inc. ++ * ++ * Author: Sean Wang <sean.wang@mediatek.com> ++ * ++ */ ++#ifndef __PINCTRL_MOORE_H ++#define __PINCTRL_MOORE_H ++ ++#include <linux/io.h> ++#include <linux/init.h> ++#include <linux/of.h> ++#include <linux/of_platform.h> ++#include <linux/platform_device.h> ++#include <linux/pinctrl/pinctrl.h> ++#include <linux/pinctrl/pinmux.h> ++#include <linux/pinctrl/pinconf.h> ++#include <linux/pinctrl/pinconf-generic.h> ++ ++#include "../core.h" ++#include "../pinconf.h" ++#include "../pinmux.h" ++#include "mtk-eint.h" ++#include "pinctrl-mtk-common-v2.h" ++ ++#define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), } ++ ++#define MTK_PIN(_number, _name, _eint_m, _eint_n, _drv_n) { \ ++ .number = _number, \ ++ .name = _name, \ ++ .eint = { \ ++ .eint_m = _eint_m, \ ++ .eint_n = _eint_n, \ ++ }, \ ++ .drv_n = _drv_n, \ ++ .funcs = NULL, \ ++ } ++ ++#define PINCTRL_PIN_GROUP(name, id) \ ++ { \ ++ name, \ ++ id##_pins, \ ++ ARRAY_SIZE(id##_pins), \ ++ id##_funcs, \ ++ } ++ ++int mtk_moore_pinctrl_probe(struct platform_device *pdev, ++ const struct mtk_pin_soc *soc); ++ ++#endif /* __PINCTRL_MOORE_H */ +diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6765.c b/drivers/pinctrl/mediatek/pinctrl-mt6765.c +new file mode 100644 +index 000000000000..32451e8693be +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mt6765.c +@@ -0,0 +1,1108 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2018 MediaTek Inc. ++ * ++ * Author: ZH Chen <zh.chen@mediatek.com> ++ * ++ */ ++ ++#include "pinctrl-mtk-mt6765.h" ++#include "pinctrl-paris.h" ++ ++/* MT6765 have multiple bases to program pin configuration listed as the below: ++ * iocfg[0]:0x10005000, iocfg[1]:0x10002C00, iocfg[2]:0x10002800, ++ * iocfg[3]:0x10002A00, iocfg[4]:0x10002000, iocfg[5]:0x10002200, ++ * iocfg[6]:0x10002500, iocfg[7]:0x10002600. ++ * _i_base could be used to indicate what base the pin should be mapped into. ++ */ ++ ++#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ ++ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ ++ _x_bits, 32, 0) ++ ++#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ ++ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ ++ _x_bits, 32, 1) ++ ++static const struct mtk_pin_field_calc mt6765_pin_mode_range[] = { ++ PIN_FIELD(0, 202, 0x300, 0x10, 0, 4), ++}; ++ ++static const struct mtk_pin_field_calc mt6765_pin_dir_range[] = { ++ PIN_FIELD(0, 202, 0x0, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt6765_pin_di_range[] = { ++ PIN_FIELD(0, 202, 0x200, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt6765_pin_do_range[] = { ++ PIN_FIELD(0, 202, 0x100, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt6765_pin_smt_range[] = { ++ PINS_FIELD_BASE(0, 3, 2, 0x00b0, 0x10, 4, 1), ++ PINS_FIELD_BASE(4, 7, 2, 0x00b0, 0x10, 5, 1), ++ PIN_FIELD_BASE(8, 8, 3, 0x0080, 0x10, 3, 1), ++ PINS_FIELD_BASE(9, 11, 2, 0x00b0, 0x10, 6, 1), ++ PIN_FIELD_BASE(12, 12, 5, 0x0060, 0x10, 9, 1), ++ PINS_FIELD_BASE(13, 16, 6, 0x00b0, 0x10, 10, 1), ++ PINS_FIELD_BASE(17, 20, 6, 0x00b0, 0x10, 8, 1), ++ PINS_FIELD_BASE(21, 24, 6, 0x00b0, 0x10, 9, 1), ++ PINS_FIELD_BASE(25, 28, 6, 0x00b0, 0x10, 7, 1), ++ PIN_FIELD_BASE(29, 29, 6, 0x00b0, 0x10, 0, 1), ++ PIN_FIELD_BASE(30, 30, 6, 0x00b0, 0x10, 1, 1), ++ PINS_FIELD_BASE(31, 34, 6, 0x00b0, 0x10, 2, 1), ++ PINS_FIELD_BASE(35, 36, 6, 0x00b0, 0x10, 5, 1), ++ PIN_FIELD_BASE(37, 37, 6, 0x00b0, 0x10, 6, 1), ++ PIN_FIELD_BASE(38, 38, 6, 0x00b0, 0x10, 4, 1), ++ PINS_FIELD_BASE(39, 40, 6, 0x00b0, 0x10, 3, 1), ++ PINS_FIELD_BASE(41, 42, 7, 0x00c0, 0x10, 6, 1), ++ PIN_FIELD_BASE(43, 43, 7, 0x00c0, 0x10, 3, 1), ++ PIN_FIELD_BASE(44, 44, 7, 0x00c0, 0x10, 4, 1), ++ PIN_FIELD_BASE(45, 45, 7, 0x00c0, 0x10, 8, 1), ++ PINS_FIELD_BASE(46, 47, 7, 0x00c0, 0x10, 7, 1), ++ PIN_FIELD_BASE(48, 48, 7, 0x00c0, 0x10, 15, 1), ++ PIN_FIELD_BASE(49, 49, 7, 0x00c0, 0x10, 17, 1), ++ PIN_FIELD_BASE(50, 50, 7, 0x00c0, 0x10, 14, 1), ++ PIN_FIELD_BASE(51, 51, 7, 0x00c0, 0x10, 16, 1), ++ PINS_FIELD_BASE(52, 57, 7, 0x00c0, 0x10, 0, 1), ++ PINS_FIELD_BASE(58, 60, 7, 0x00c0, 0x10, 12, 1), ++ PINS_FIELD_BASE(61, 62, 3, 0x0080, 0x10, 5, 1), ++ PINS_FIELD_BASE(63, 64, 3, 0x0080, 0x10, 4, 1), ++ PINS_FIELD_BASE(65, 66, 3, 0x0080, 0x10, 7, 1), ++ PINS_FIELD_BASE(67, 68, 3, 0x0080, 0x10, 6, 1), ++ PINS_FIELD_BASE(69, 73, 3, 0x0080, 0x10, 1, 1), ++ PINS_FIELD_BASE(74, 78, 3, 0x0080, 0x10, 2, 1), ++ PINS_FIELD_BASE(79, 80, 3, 0x0080, 0x10, 0, 1), ++ PIN_FIELD_BASE(81, 81, 3, 0x0080, 0x10, 12, 1), ++ PIN_FIELD_BASE(82, 82, 3, 0x0080, 0x10, 11, 1), ++ PIN_FIELD_BASE(83, 83, 3, 0x0080, 0x10, 9, 1), ++ PIN_FIELD_BASE(84, 84, 3, 0x0080, 0x10, 10, 1), ++ PIN_FIELD_BASE(85, 85, 7, 0x00c0, 0x10, 12, 1), ++ PIN_FIELD_BASE(86, 86, 7, 0x00c0, 0x10, 13, 1), ++ PIN_FIELD_BASE(87, 87, 7, 0x00c0, 0x10, 2, 1), ++ PIN_FIELD_BASE(88, 88, 7, 0x00c0, 0x10, 1, 1), ++ PIN_FIELD_BASE(89, 89, 2, 0x00b0, 0x10, 13, 1), ++ PIN_FIELD_BASE(90, 90, 3, 0x0080, 0x10, 8, 1), ++ PINS_FIELD_BASE(91, 92, 2, 0x00b0, 0x10, 8, 1), ++ PINS_FIELD_BASE(93, 94, 2, 0x00b0, 0x10, 7, 1), ++ PINS_FIELD_BASE(95, 96, 2, 0x00b0, 0x10, 14, 1), ++ PINS_FIELD_BASE(97, 98, 2, 0x00b0, 0x10, 2, 1), ++ PIN_FIELD_BASE(99, 99, 2, 0x00b0, 0x10, 0, 1), ++ PIN_FIELD_BASE(100, 100, 2, 0x00b0, 0x10, 1, 1), ++ PINS_FIELD_BASE(101, 102, 2, 0x00b0, 0x10, 3, 1), ++ PIN_FIELD_BASE(103, 103, 2, 0x00b0, 0x10, 9, 1), ++ PIN_FIELD_BASE(104, 104, 2, 0x00b0, 0x10, 11, 1), ++ PIN_FIELD_BASE(105, 105, 2, 0x00b0, 0x10, 10, 1), ++ PIN_FIELD_BASE(106, 106, 2, 0x00b0, 0x10, 12, 1), ++ PIN_FIELD_BASE(107, 107, 1, 0x0080, 0x10, 4, 1), ++ PIN_FIELD_BASE(108, 108, 1, 0x0080, 0x10, 3, 1), ++ PIN_FIELD_BASE(109, 109, 1, 0x0080, 0x10, 5, 1), ++ PIN_FIELD_BASE(110, 110, 1, 0x0080, 0x10, 0, 1), ++ PIN_FIELD_BASE(111, 111, 1, 0x0080, 0x10, 1, 1), ++ PIN_FIELD_BASE(112, 112, 1, 0x0080, 0x10, 2, 1), ++ PIN_FIELD_BASE(113, 113, 1, 0x0080, 0x10, 9, 1), ++ PIN_FIELD_BASE(114, 114, 1, 0x0080, 0x10, 10, 1), ++ PIN_FIELD_BASE(115, 115, 1, 0x0080, 0x10, 6, 1), ++ PIN_FIELD_BASE(116, 116, 1, 0x0080, 0x10, 7, 1), ++ PIN_FIELD_BASE(117, 117, 1, 0x0080, 0x10, 12, 1), ++ PIN_FIELD_BASE(118, 118, 1, 0x0080, 0x10, 13, 1), ++ PIN_FIELD_BASE(119, 119, 1, 0x0080, 0x10, 14, 1), ++ PIN_FIELD_BASE(120, 120, 1, 0x0080, 0x10, 11, 1), ++ PIN_FIELD_BASE(121, 121, 1, 0x0080, 0x10, 8, 1), ++ PIN_FIELD_BASE(122, 122, 4, 0x0080, 0x10, 2, 1), ++ PIN_FIELD_BASE(123, 123, 4, 0x0080, 0x10, 3, 1), ++ PIN_FIELD_BASE(124, 124, 4, 0x0080, 0x10, 1, 1), ++ PIN_FIELD_BASE(125, 125, 4, 0x0080, 0x10, 5, 1), ++ PIN_FIELD_BASE(126, 126, 4, 0x0080, 0x10, 7, 1), ++ PIN_FIELD_BASE(127, 127, 4, 0x0080, 0x10, 9, 1), ++ PIN_FIELD_BASE(128, 128, 4, 0x0080, 0x10, 4, 1), ++ PIN_FIELD_BASE(129, 129, 4, 0x0080, 0x10, 8, 1), ++ PIN_FIELD_BASE(130, 130, 4, 0x0080, 0x10, 10, 1), ++ PIN_FIELD_BASE(131, 131, 4, 0x0080, 0x10, 11, 1), ++ PIN_FIELD_BASE(132, 132, 4, 0x0080, 0x10, 6, 1), ++ PIN_FIELD_BASE(133, 133, 4, 0x0080, 0x10, 12, 1), ++ PIN_FIELD_BASE(134, 134, 5, 0x0060, 0x10, 11, 1), ++ PIN_FIELD_BASE(135, 135, 5, 0x0060, 0x10, 13, 1), ++ PIN_FIELD_BASE(136, 136, 5, 0x0060, 0x10, 1, 1), ++ PIN_FIELD_BASE(137, 137, 5, 0x0060, 0x10, 7, 1), ++ PIN_FIELD_BASE(138, 138, 5, 0x0060, 0x10, 4, 1), ++ PIN_FIELD_BASE(139, 139, 5, 0x0060, 0x10, 5, 1), ++ PIN_FIELD_BASE(140, 140, 5, 0x0060, 0x10, 0, 1), ++ PIN_FIELD_BASE(141, 141, 5, 0x0060, 0x10, 6, 1), ++ PIN_FIELD_BASE(142, 142, 5, 0x0060, 0x10, 2, 1), ++ PIN_FIELD_BASE(143, 143, 5, 0x0060, 0x10, 3, 1), ++ PINS_FIELD_BASE(144, 147, 5, 0x0060, 0x10, 10, 1), ++ PINS_FIELD_BASE(148, 149, 5, 0x0060, 0x10, 12, 1), ++ PINS_FIELD_BASE(150, 151, 7, 0x00c0, 0x10, 9, 1), ++ PINS_FIELD_BASE(152, 153, 7, 0x00c0, 0x10, 10, 1), ++ PIN_FIELD_BASE(154, 154, 7, 0x00c0, 0x10, 11, 1), ++ PINS_FIELD_BASE(155, 158, 3, 0x0080, 0x10, 13, 1), ++ PIN_FIELD_BASE(159, 159, 7, 0x00c0, 0x10, 11, 1), ++ PIN_FIELD_BASE(160, 160, 5, 0x0060, 0x10, 8, 1), ++ PIN_FIELD_BASE(161, 161, 1, 0x0080, 0x10, 15, 1), ++ PIN_FIELD_BASE(162, 162, 1, 0x0080, 0x10, 16, 1), ++ PINS_FIELD_BASE(163, 170, 4, 0x0080, 0x10, 0, 1), ++ PINS_FIELD_BASE(171, 179, 7, 0x00c0, 0x10, 5, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt6765_pin_pd_range[] = { ++ PIN_FIELD_BASE(0, 0, 2, 0x0040, 0x10, 6, 1), ++ PIN_FIELD_BASE(1, 1, 2, 0x0040, 0x10, 7, 1), ++ PIN_FIELD_BASE(2, 2, 2, 0x0040, 0x10, 10, 1), ++ PIN_FIELD_BASE(3, 3, 2, 0x0040, 0x10, 11, 1), ++ PIN_FIELD_BASE(4, 4, 2, 0x0040, 0x10, 12, 1), ++ PIN_FIELD_BASE(5, 5, 2, 0x0040, 0x10, 13, 1), ++ PIN_FIELD_BASE(6, 6, 2, 0x0040, 0x10, 14, 1), ++ PIN_FIELD_BASE(7, 7, 2, 0x0040, 0x10, 15, 1), ++ PIN_FIELD_BASE(8, 8, 3, 0x0040, 0x10, 12, 1), ++ PIN_FIELD_BASE(9, 9, 2, 0x0040, 0x10, 16, 1), ++ PIN_FIELD_BASE(10, 10, 2, 0x0040, 0x10, 8, 1), ++ PIN_FIELD_BASE(11, 11, 2, 0x0040, 0x10, 9, 1), ++ PIN_FIELD_BASE(12, 12, 5, 0x0030, 0x10, 9, 1), ++ PIN_FIELD_BASE(13, 13, 6, 0x0040, 0x10, 14, 1), ++ PIN_FIELD_BASE(14, 14, 6, 0x0040, 0x10, 13, 1), ++ PIN_FIELD_BASE(15, 15, 6, 0x0040, 0x10, 15, 1), ++ PIN_FIELD_BASE(16, 16, 6, 0x0040, 0x10, 12, 1), ++ PIN_FIELD_BASE(17, 17, 6, 0x0040, 0x10, 7, 1), ++ PIN_FIELD_BASE(18, 18, 6, 0x0040, 0x10, 4, 1), ++ PIN_FIELD_BASE(19, 19, 6, 0x0040, 0x10, 6, 1), ++ PIN_FIELD_BASE(20, 20, 6, 0x0040, 0x10, 5, 1), ++ PIN_FIELD_BASE(21, 21, 6, 0x0040, 0x10, 10, 1), ++ PIN_FIELD_BASE(22, 22, 6, 0x0040, 0x10, 9, 1), ++ PIN_FIELD_BASE(23, 23, 6, 0x0040, 0x10, 11, 1), ++ PIN_FIELD_BASE(24, 24, 6, 0x0040, 0x10, 8, 1), ++ PIN_FIELD_BASE(25, 25, 6, 0x0040, 0x10, 2, 1), ++ PIN_FIELD_BASE(26, 26, 6, 0x0040, 0x10, 1, 1), ++ PIN_FIELD_BASE(27, 27, 6, 0x0040, 0x10, 3, 1), ++ PINS_FIELD_BASE(28, 40, 6, 0x0040, 0x10, 0, 1), ++ PIN_FIELD_BASE(41, 41, 7, 0x0060, 0x10, 19, 1), ++ PIN_FIELD_BASE(42, 42, 7, 0x0060, 0x10, 9, 1), ++ PIN_FIELD_BASE(43, 43, 7, 0x0060, 0x10, 8, 1), ++ PIN_FIELD_BASE(44, 44, 7, 0x0060, 0x10, 10, 1), ++ PIN_FIELD_BASE(45, 45, 7, 0x0060, 0x10, 22, 1), ++ PIN_FIELD_BASE(46, 46, 7, 0x0060, 0x10, 21, 1), ++ PIN_FIELD_BASE(47, 47, 7, 0x0060, 0x10, 20, 1), ++ PIN_FIELD_BASE(48, 48, 7, 0x0070, 0x10, 3, 1), ++ PIN_FIELD_BASE(49, 49, 7, 0x0070, 0x10, 5, 1), ++ PIN_FIELD_BASE(50, 50, 7, 0x0070, 0x10, 2, 1), ++ PIN_FIELD_BASE(51, 51, 7, 0x0070, 0x10, 4, 1), ++ PIN_FIELD_BASE(52, 52, 7, 0x0060, 0x10, 1, 1), ++ PIN_FIELD_BASE(53, 53, 7, 0x0060, 0x10, 0, 1), ++ PIN_FIELD_BASE(54, 54, 7, 0x0060, 0x10, 5, 1), ++ PIN_FIELD_BASE(55, 55, 7, 0x0060, 0x10, 3, 1), ++ PIN_FIELD_BASE(56, 56, 7, 0x0060, 0x10, 4, 1), ++ PIN_FIELD_BASE(57, 57, 7, 0x0060, 0x10, 2, 1), ++ PIN_FIELD_BASE(58, 58, 7, 0x0070, 0x10, 0, 1), ++ PIN_FIELD_BASE(59, 59, 7, 0x0060, 0x10, 31, 1), ++ PIN_FIELD_BASE(60, 60, 7, 0x0060, 0x10, 30, 1), ++ PIN_FIELD_BASE(61, 61, 3, 0x0040, 0x10, 18, 1), ++ PIN_FIELD_BASE(62, 62, 3, 0x0040, 0x10, 14, 1), ++ PIN_FIELD_BASE(63, 63, 3, 0x0040, 0x10, 17, 1), ++ PIN_FIELD_BASE(64, 64, 3, 0x0040, 0x10, 13, 1), ++ PIN_FIELD_BASE(65, 65, 3, 0x0040, 0x10, 20, 1), ++ PIN_FIELD_BASE(66, 66, 3, 0x0040, 0x10, 16, 1), ++ PIN_FIELD_BASE(67, 67, 3, 0x0040, 0x10, 19, 1), ++ PIN_FIELD_BASE(68, 68, 3, 0x0040, 0x10, 15, 1), ++ PIN_FIELD_BASE(69, 69, 3, 0x0040, 0x10, 8, 1), ++ PIN_FIELD_BASE(70, 70, 3, 0x0040, 0x10, 7, 1), ++ PIN_FIELD_BASE(71, 71, 3, 0x0040, 0x10, 6, 1), ++ PIN_FIELD_BASE(72, 72, 3, 0x0040, 0x10, 5, 1), ++ PIN_FIELD_BASE(73, 73, 3, 0x0040, 0x10, 4, 1), ++ PIN_FIELD_BASE(74, 74, 3, 0x0040, 0x10, 3, 1), ++ PIN_FIELD_BASE(75, 75, 3, 0x0040, 0x10, 2, 1), ++ PIN_FIELD_BASE(76, 76, 3, 0x0040, 0x10, 1, 1), ++ PIN_FIELD_BASE(77, 77, 3, 0x0040, 0x10, 0, 1), ++ PIN_FIELD_BASE(78, 78, 3, 0x0040, 0x10, 9, 1), ++ PIN_FIELD_BASE(79, 79, 3, 0x0040, 0x10, 11, 1), ++ PIN_FIELD_BASE(80, 80, 3, 0x0040, 0x10, 10, 1), ++ PIN_FIELD_BASE(81, 81, 3, 0x0040, 0x10, 25, 1), ++ PIN_FIELD_BASE(82, 82, 3, 0x0040, 0x10, 24, 1), ++ PIN_FIELD_BASE(83, 83, 3, 0x0040, 0x10, 22, 1), ++ PIN_FIELD_BASE(84, 84, 3, 0x0040, 0x10, 23, 1), ++ PIN_FIELD_BASE(85, 85, 7, 0x0070, 0x10, 1, 1), ++ PIN_FIELD_BASE(86, 86, 7, 0x0060, 0x10, 29, 1), ++ PIN_FIELD_BASE(87, 87, 7, 0x0060, 0x10, 7, 1), ++ PIN_FIELD_BASE(88, 88, 7, 0x0060, 0x10, 6, 1), ++ PIN_FIELD_BASE(89, 89, 2, 0x0040, 0x10, 21, 1), ++ PINS_FIELD_BASE(90, 94, 3, 0x0040, 0x10, 21, 1), ++ PIN_FIELD_BASE(95, 95, 2, 0x0040, 0x10, 22, 1), ++ PIN_FIELD_BASE(96, 96, 2, 0x0040, 0x10, 23, 1), ++ PIN_FIELD_BASE(97, 97, 2, 0x0040, 0x10, 2, 1), ++ PIN_FIELD_BASE(98, 98, 2, 0x0040, 0x10, 3, 1), ++ PIN_FIELD_BASE(99, 99, 2, 0x0040, 0x10, 0, 1), ++ PIN_FIELD_BASE(100, 100, 2, 0x0040, 0x10, 1, 1), ++ PIN_FIELD_BASE(101, 101, 2, 0x0040, 0x10, 4, 1), ++ PIN_FIELD_BASE(102, 102, 2, 0x0040, 0x10, 5, 1), ++ PIN_FIELD_BASE(103, 103, 2, 0x0040, 0x10, 17, 1), ++ PIN_FIELD_BASE(104, 104, 2, 0x0040, 0x10, 19, 1), ++ PIN_FIELD_BASE(105, 105, 2, 0x0040, 0x10, 18, 1), ++ PIN_FIELD_BASE(106, 106, 2, 0x0040, 0x10, 20, 1), ++ PIN_FIELD_BASE(107, 107, 1, 0x0040, 0x10, 4, 1), ++ PIN_FIELD_BASE(108, 108, 1, 0x0040, 0x10, 3, 1), ++ PIN_FIELD_BASE(109, 109, 1, 0x0040, 0x10, 5, 1), ++ PIN_FIELD_BASE(110, 110, 1, 0x0040, 0x10, 0, 1), ++ PIN_FIELD_BASE(111, 111, 1, 0x0040, 0x10, 1, 1), ++ PIN_FIELD_BASE(112, 112, 1, 0x0040, 0x10, 2, 1), ++ PIN_FIELD_BASE(113, 113, 1, 0x0040, 0x10, 9, 1), ++ PIN_FIELD_BASE(114, 114, 1, 0x0040, 0x10, 10, 1), ++ PIN_FIELD_BASE(115, 115, 1, 0x0040, 0x10, 6, 1), ++ PIN_FIELD_BASE(116, 116, 1, 0x0040, 0x10, 7, 1), ++ PIN_FIELD_BASE(117, 117, 1, 0x0040, 0x10, 12, 1), ++ PIN_FIELD_BASE(118, 118, 1, 0x0040, 0x10, 13, 1), ++ PIN_FIELD_BASE(119, 119, 1, 0x0040, 0x10, 14, 1), ++ PIN_FIELD_BASE(120, 120, 1, 0x0040, 0x10, 11, 1), ++ PINS_FIELD_BASE(121, 133, 1, 0x0040, 0x10, 8, 1), ++ PIN_FIELD_BASE(134, 134, 5, 0x0030, 0x10, 14, 1), ++ PIN_FIELD_BASE(135, 135, 5, 0x0030, 0x10, 19, 1), ++ PIN_FIELD_BASE(136, 136, 5, 0x0030, 0x10, 1, 1), ++ PIN_FIELD_BASE(137, 137, 5, 0x0030, 0x10, 7, 1), ++ PIN_FIELD_BASE(138, 138, 5, 0x0030, 0x10, 4, 1), ++ PIN_FIELD_BASE(139, 139, 5, 0x0030, 0x10, 5, 1), ++ PIN_FIELD_BASE(140, 140, 5, 0x0030, 0x10, 0, 1), ++ PIN_FIELD_BASE(141, 141, 5, 0x0030, 0x10, 6, 1), ++ PIN_FIELD_BASE(142, 142, 5, 0x0030, 0x10, 2, 1), ++ PIN_FIELD_BASE(143, 143, 5, 0x0030, 0x10, 3, 1), ++ PIN_FIELD_BASE(144, 144, 5, 0x0030, 0x10, 12, 1), ++ PIN_FIELD_BASE(145, 145, 5, 0x0030, 0x10, 11, 1), ++ PIN_FIELD_BASE(146, 146, 5, 0x0030, 0x10, 13, 1), ++ PIN_FIELD_BASE(147, 147, 5, 0x0030, 0x10, 10, 1), ++ PIN_FIELD_BASE(148, 148, 5, 0x0030, 0x10, 15, 1), ++ PIN_FIELD_BASE(149, 149, 5, 0x0030, 0x10, 16, 1), ++ PIN_FIELD_BASE(150, 150, 7, 0x0060, 0x10, 23, 1), ++ PIN_FIELD_BASE(151, 151, 7, 0x0060, 0x10, 24, 1), ++ PIN_FIELD_BASE(152, 152, 7, 0x0060, 0x10, 25, 1), ++ PIN_FIELD_BASE(153, 153, 7, 0x0060, 0x10, 26, 1), ++ PIN_FIELD_BASE(154, 154, 7, 0x0060, 0x10, 28, 1), ++ PIN_FIELD_BASE(155, 155, 3, 0x0040, 0x10, 28, 1), ++ PIN_FIELD_BASE(156, 156, 3, 0x0040, 0x10, 27, 1), ++ PIN_FIELD_BASE(157, 157, 3, 0x0040, 0x10, 29, 1), ++ PIN_FIELD_BASE(158, 158, 3, 0x0040, 0x10, 26, 1), ++ PIN_FIELD_BASE(159, 159, 7, 0x0060, 0x10, 27, 1), ++ PIN_FIELD_BASE(160, 160, 5, 0x0030, 0x10, 8, 1), ++ PIN_FIELD_BASE(161, 161, 1, 0x0040, 0x10, 15, 1), ++ PIN_FIELD_BASE(162, 162, 1, 0x0040, 0x10, 16, 1), ++ PIN_FIELD_BASE(163, 163, 4, 0x0020, 0x10, 0, 1), ++ PIN_FIELD_BASE(164, 164, 4, 0x0020, 0x10, 1, 1), ++ PIN_FIELD_BASE(165, 165, 4, 0x0020, 0x10, 2, 1), ++ PIN_FIELD_BASE(166, 166, 4, 0x0020, 0x10, 3, 1), ++ PIN_FIELD_BASE(167, 167, 4, 0x0020, 0x10, 4, 1), ++ PIN_FIELD_BASE(168, 168, 4, 0x0020, 0x10, 5, 1), ++ PIN_FIELD_BASE(169, 169, 4, 0x0020, 0x10, 6, 1), ++ PIN_FIELD_BASE(170, 170, 4, 0x0020, 0x10, 7, 1), ++ PIN_FIELD_BASE(171, 171, 7, 0x0060, 0x10, 17, 1), ++ PIN_FIELD_BASE(172, 172, 7, 0x0060, 0x10, 18, 1), ++ PIN_FIELD_BASE(173, 173, 7, 0x0060, 0x10, 11, 1), ++ PIN_FIELD_BASE(174, 174, 7, 0x0060, 0x10, 12, 1), ++ PIN_FIELD_BASE(175, 175, 7, 0x0060, 0x10, 13, 1), ++ PIN_FIELD_BASE(176, 176, 7, 0x0060, 0x10, 14, 1), ++ PIN_FIELD_BASE(177, 177, 7, 0x0060, 0x10, 15, 1), ++ PINS_FIELD_BASE(178, 179, 7, 0x0060, 0x10, 16, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt6765_pin_pu_range[] = { ++ PIN_FIELD_BASE(0, 0, 2, 0x0060, 0x10, 6, 1), ++ PIN_FIELD_BASE(1, 1, 2, 0x0060, 0x10, 7, 1), ++ PIN_FIELD_BASE(2, 2, 2, 0x0060, 0x10, 10, 1), ++ PIN_FIELD_BASE(3, 3, 2, 0x0060, 0x10, 11, 1), ++ PIN_FIELD_BASE(4, 4, 2, 0x0060, 0x10, 12, 1), ++ PIN_FIELD_BASE(5, 5, 2, 0x0060, 0x10, 13, 1), ++ PIN_FIELD_BASE(6, 6, 2, 0x0060, 0x10, 14, 1), ++ PIN_FIELD_BASE(7, 7, 2, 0x0060, 0x10, 15, 1), ++ PIN_FIELD_BASE(8, 8, 3, 0x0050, 0x10, 12, 1), ++ PIN_FIELD_BASE(9, 9, 2, 0x0060, 0x10, 16, 1), ++ PIN_FIELD_BASE(10, 10, 2, 0x0060, 0x10, 8, 1), ++ PIN_FIELD_BASE(11, 11, 2, 0x0060, 0x10, 9, 1), ++ PIN_FIELD_BASE(12, 12, 5, 0x0040, 0x10, 9, 1), ++ PIN_FIELD_BASE(13, 13, 6, 0x0060, 0x10, 14, 1), ++ PIN_FIELD_BASE(14, 14, 6, 0x0060, 0x10, 13, 1), ++ PIN_FIELD_BASE(15, 15, 6, 0x0060, 0x10, 15, 1), ++ PIN_FIELD_BASE(16, 16, 6, 0x0060, 0x10, 12, 1), ++ PIN_FIELD_BASE(17, 17, 6, 0x0060, 0x10, 7, 1), ++ PIN_FIELD_BASE(18, 18, 6, 0x0060, 0x10, 4, 1), ++ PIN_FIELD_BASE(19, 19, 6, 0x0060, 0x10, 6, 1), ++ PIN_FIELD_BASE(20, 20, 6, 0x0060, 0x10, 5, 1), ++ PIN_FIELD_BASE(21, 21, 6, 0x0060, 0x10, 10, 1), ++ PIN_FIELD_BASE(22, 22, 6, 0x0060, 0x10, 9, 1), ++ PIN_FIELD_BASE(23, 23, 6, 0x0060, 0x10, 11, 1), ++ PIN_FIELD_BASE(24, 24, 6, 0x0060, 0x10, 8, 1), ++ PIN_FIELD_BASE(25, 25, 6, 0x0060, 0x10, 2, 1), ++ PIN_FIELD_BASE(26, 26, 6, 0x0060, 0x10, 1, 1), ++ PIN_FIELD_BASE(27, 27, 6, 0x0060, 0x10, 3, 1), ++ PINS_FIELD_BASE(28, 40, 6, 0x0060, 0x10, 0, 1), ++ PIN_FIELD_BASE(41, 41, 7, 0x0080, 0x10, 19, 1), ++ PIN_FIELD_BASE(42, 42, 7, 0x0080, 0x10, 9, 1), ++ PIN_FIELD_BASE(43, 43, 7, 0x0080, 0x10, 8, 1), ++ PIN_FIELD_BASE(44, 44, 7, 0x0080, 0x10, 10, 1), ++ PIN_FIELD_BASE(45, 45, 7, 0x0080, 0x10, 22, 1), ++ PIN_FIELD_BASE(46, 46, 7, 0x0080, 0x10, 21, 1), ++ PIN_FIELD_BASE(47, 47, 7, 0x0080, 0x10, 20, 1), ++ PIN_FIELD_BASE(48, 48, 7, 0x0090, 0x10, 3, 1), ++ PIN_FIELD_BASE(49, 49, 7, 0x0090, 0x10, 5, 1), ++ PIN_FIELD_BASE(50, 50, 7, 0x0090, 0x10, 2, 1), ++ PIN_FIELD_BASE(51, 51, 7, 0x0090, 0x10, 4, 1), ++ PIN_FIELD_BASE(52, 52, 7, 0x0080, 0x10, 1, 1), ++ PIN_FIELD_BASE(53, 53, 7, 0x0080, 0x10, 0, 1), ++ PIN_FIELD_BASE(54, 54, 7, 0x0080, 0x10, 5, 1), ++ PIN_FIELD_BASE(55, 55, 7, 0x0080, 0x10, 3, 1), ++ PIN_FIELD_BASE(56, 56, 7, 0x0080, 0x10, 4, 1), ++ PIN_FIELD_BASE(57, 57, 7, 0x0080, 0x10, 2, 1), ++ PIN_FIELD_BASE(58, 58, 7, 0x0090, 0x10, 0, 1), ++ PIN_FIELD_BASE(59, 59, 7, 0x0080, 0x10, 31, 1), ++ PIN_FIELD_BASE(60, 60, 7, 0x0080, 0x10, 30, 1), ++ PIN_FIELD_BASE(61, 61, 3, 0x0050, 0x10, 18, 1), ++ PIN_FIELD_BASE(62, 62, 3, 0x0050, 0x10, 14, 1), ++ PIN_FIELD_BASE(63, 63, 3, 0x0050, 0x10, 17, 1), ++ PIN_FIELD_BASE(64, 64, 3, 0x0050, 0x10, 13, 1), ++ PIN_FIELD_BASE(65, 65, 3, 0x0050, 0x10, 20, 1), ++ PIN_FIELD_BASE(66, 66, 3, 0x0050, 0x10, 16, 1), ++ PIN_FIELD_BASE(67, 67, 3, 0x0050, 0x10, 19, 1), ++ PIN_FIELD_BASE(68, 68, 3, 0x0050, 0x10, 15, 1), ++ PIN_FIELD_BASE(69, 69, 3, 0x0050, 0x10, 8, 1), ++ PIN_FIELD_BASE(70, 70, 3, 0x0050, 0x10, 7, 1), ++ PIN_FIELD_BASE(71, 71, 3, 0x0050, 0x10, 6, 1), ++ PIN_FIELD_BASE(72, 72, 3, 0x0050, 0x10, 5, 1), ++ PIN_FIELD_BASE(73, 73, 3, 0x0050, 0x10, 4, 1), ++ PIN_FIELD_BASE(74, 74, 3, 0x0050, 0x10, 3, 1), ++ PIN_FIELD_BASE(75, 75, 3, 0x0050, 0x10, 2, 1), ++ PIN_FIELD_BASE(76, 76, 3, 0x0050, 0x10, 1, 1), ++ PIN_FIELD_BASE(77, 77, 3, 0x0050, 0x10, 0, 1), ++ PIN_FIELD_BASE(78, 78, 3, 0x0050, 0x10, 9, 1), ++ PIN_FIELD_BASE(79, 79, 3, 0x0050, 0x10, 11, 1), ++ PIN_FIELD_BASE(80, 80, 3, 0x0050, 0x10, 10, 1), ++ PIN_FIELD_BASE(81, 81, 3, 0x0050, 0x10, 25, 1), ++ PIN_FIELD_BASE(82, 82, 3, 0x0050, 0x10, 24, 1), ++ PIN_FIELD_BASE(83, 83, 3, 0x0050, 0x10, 22, 1), ++ PIN_FIELD_BASE(84, 84, 3, 0x0050, 0x10, 23, 1), ++ PIN_FIELD_BASE(85, 85, 7, 0x0090, 0x10, 1, 1), ++ PIN_FIELD_BASE(86, 86, 7, 0x0080, 0x10, 29, 1), ++ PIN_FIELD_BASE(87, 87, 7, 0x0080, 0x10, 7, 1), ++ PIN_FIELD_BASE(88, 88, 7, 0x0080, 0x10, 6, 1), ++ PIN_FIELD_BASE(89, 89, 2, 0x0060, 0x10, 21, 1), ++ PINS_FIELD_BASE(90, 94, 3, 0x0050, 0x10, 21, 1), ++ PIN_FIELD_BASE(95, 95, 2, 0x0060, 0x10, 22, 1), ++ PIN_FIELD_BASE(96, 96, 2, 0x0060, 0x10, 23, 1), ++ PIN_FIELD_BASE(97, 97, 2, 0x0060, 0x10, 2, 1), ++ PIN_FIELD_BASE(98, 98, 2, 0x0060, 0x10, 3, 1), ++ PIN_FIELD_BASE(99, 99, 2, 0x0060, 0x10, 0, 1), ++ PIN_FIELD_BASE(100, 100, 2, 0x0060, 0x10, 1, 1), ++ PIN_FIELD_BASE(101, 101, 2, 0x0060, 0x10, 4, 1), ++ PIN_FIELD_BASE(102, 102, 2, 0x0060, 0x10, 5, 1), ++ PIN_FIELD_BASE(103, 103, 2, 0x0060, 0x10, 17, 1), ++ PIN_FIELD_BASE(104, 104, 2, 0x0060, 0x10, 19, 1), ++ PIN_FIELD_BASE(105, 105, 2, 0x0060, 0x10, 18, 1), ++ PIN_FIELD_BASE(106, 106, 2, 0x0060, 0x10, 20, 1), ++ PIN_FIELD_BASE(107, 107, 1, 0x0050, 0x10, 4, 1), ++ PIN_FIELD_BASE(108, 108, 1, 0x0050, 0x10, 3, 1), ++ PIN_FIELD_BASE(109, 109, 1, 0x0050, 0x10, 5, 1), ++ PIN_FIELD_BASE(110, 110, 1, 0x0050, 0x10, 0, 1), ++ PIN_FIELD_BASE(111, 111, 1, 0x0050, 0x10, 1, 1), ++ PIN_FIELD_BASE(112, 112, 1, 0x0050, 0x10, 2, 1), ++ PIN_FIELD_BASE(113, 113, 1, 0x0050, 0x10, 9, 1), ++ PIN_FIELD_BASE(114, 114, 1, 0x0050, 0x10, 10, 1), ++ PIN_FIELD_BASE(115, 115, 1, 0x0050, 0x10, 6, 1), ++ PIN_FIELD_BASE(116, 116, 1, 0x0050, 0x10, 7, 1), ++ PIN_FIELD_BASE(117, 117, 1, 0x0050, 0x10, 12, 1), ++ PIN_FIELD_BASE(118, 118, 1, 0x0050, 0x10, 13, 1), ++ PIN_FIELD_BASE(119, 119, 1, 0x0050, 0x10, 14, 1), ++ PIN_FIELD_BASE(120, 120, 1, 0x0050, 0x10, 11, 1), ++ PINS_FIELD_BASE(121, 133, 1, 0x0050, 0x10, 8, 1), ++ PIN_FIELD_BASE(134, 134, 5, 0x0040, 0x10, 14, 1), ++ PIN_FIELD_BASE(135, 135, 5, 0x0040, 0x10, 19, 1), ++ PIN_FIELD_BASE(136, 136, 5, 0x0040, 0x10, 1, 1), ++ PIN_FIELD_BASE(137, 137, 5, 0x0040, 0x10, 7, 1), ++ PIN_FIELD_BASE(138, 138, 5, 0x0040, 0x10, 4, 1), ++ PIN_FIELD_BASE(139, 139, 5, 0x0040, 0x10, 5, 1), ++ PIN_FIELD_BASE(140, 140, 5, 0x0040, 0x10, 0, 1), ++ PIN_FIELD_BASE(141, 141, 5, 0x0040, 0x10, 6, 1), ++ PIN_FIELD_BASE(142, 142, 5, 0x0040, 0x10, 2, 1), ++ PIN_FIELD_BASE(143, 143, 5, 0x0040, 0x10, 3, 1), ++ PIN_FIELD_BASE(144, 144, 5, 0x0040, 0x10, 12, 1), ++ PIN_FIELD_BASE(145, 145, 5, 0x0040, 0x10, 11, 1), ++ PIN_FIELD_BASE(146, 146, 5, 0x0040, 0x10, 13, 1), ++ PIN_FIELD_BASE(147, 147, 5, 0x0040, 0x10, 10, 1), ++ PIN_FIELD_BASE(148, 148, 5, 0x0040, 0x10, 15, 1), ++ PIN_FIELD_BASE(149, 149, 5, 0x0040, 0x10, 16, 1), ++ PIN_FIELD_BASE(150, 150, 7, 0x0080, 0x10, 23, 1), ++ PIN_FIELD_BASE(151, 151, 7, 0x0080, 0x10, 24, 1), ++ PIN_FIELD_BASE(152, 152, 7, 0x0080, 0x10, 25, 1), ++ PIN_FIELD_BASE(153, 153, 7, 0x0080, 0x10, 26, 1), ++ PIN_FIELD_BASE(154, 154, 7, 0x0080, 0x10, 28, 1), ++ PIN_FIELD_BASE(155, 155, 3, 0x0050, 0x10, 28, 1), ++ PIN_FIELD_BASE(156, 156, 3, 0x0050, 0x10, 27, 1), ++ PIN_FIELD_BASE(157, 157, 3, 0x0050, 0x10, 29, 1), ++ PIN_FIELD_BASE(158, 158, 3, 0x0050, 0x10, 26, 1), ++ PIN_FIELD_BASE(159, 159, 7, 0x0080, 0x10, 27, 1), ++ PIN_FIELD_BASE(160, 160, 5, 0x0040, 0x10, 8, 1), ++ PIN_FIELD_BASE(161, 161, 1, 0x0050, 0x10, 15, 1), ++ PIN_FIELD_BASE(162, 162, 1, 0x0050, 0x10, 16, 1), ++ PIN_FIELD_BASE(163, 163, 4, 0x0040, 0x10, 0, 1), ++ PIN_FIELD_BASE(164, 164, 4, 0x0040, 0x10, 1, 1), ++ PIN_FIELD_BASE(165, 165, 4, 0x0040, 0x10, 2, 1), ++ PIN_FIELD_BASE(166, 166, 4, 0x0040, 0x10, 3, 1), ++ PIN_FIELD_BASE(167, 167, 4, 0x0040, 0x10, 4, 1), ++ PIN_FIELD_BASE(168, 168, 4, 0x0040, 0x10, 5, 1), ++ PIN_FIELD_BASE(169, 169, 4, 0x0040, 0x10, 6, 1), ++ PIN_FIELD_BASE(170, 170, 4, 0x0040, 0x10, 7, 1), ++ PIN_FIELD_BASE(171, 171, 7, 0x0080, 0x10, 17, 1), ++ PIN_FIELD_BASE(172, 172, 7, 0x0080, 0x10, 18, 1), ++ PIN_FIELD_BASE(173, 173, 7, 0x0080, 0x10, 11, 1), ++ PIN_FIELD_BASE(174, 174, 7, 0x0080, 0x10, 12, 1), ++ PIN_FIELD_BASE(175, 175, 7, 0x0080, 0x10, 13, 1), ++ PIN_FIELD_BASE(176, 176, 7, 0x0080, 0x10, 14, 1), ++ PIN_FIELD_BASE(177, 177, 7, 0x0080, 0x10, 15, 1), ++ PINS_FIELD_BASE(178, 179, 7, 0x0080, 0x10, 16, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt6765_pin_tdsel_range[] = { ++ PINS_FIELD_BASE(0, 3, 2, 0x00c0, 0x10, 16, 4), ++ PINS_FIELD_BASE(4, 7, 2, 0x00c0, 0x10, 20, 4), ++ PIN_FIELD_BASE(8, 8, 3, 0x0090, 0x10, 12, 4), ++ PINS_FIELD_BASE(9, 11, 2, 0x00c0, 0x10, 24, 4), ++ PIN_FIELD_BASE(12, 12, 5, 0x0080, 0x10, 4, 4), ++ PINS_FIELD_BASE(13, 16, 6, 0x00e0, 0x10, 8, 4), ++ PINS_FIELD_BASE(17, 20, 6, 0x00e0, 0x10, 0, 4), ++ PINS_FIELD_BASE(21, 24, 6, 0x00e0, 0x10, 4, 4), ++ PINS_FIELD_BASE(25, 28, 6, 0x00d0, 0x10, 28, 4), ++ PIN_FIELD_BASE(29, 29, 6, 0x00d0, 0x10, 0, 4), ++ PIN_FIELD_BASE(30, 30, 6, 0x00d0, 0x10, 4, 4), ++ PINS_FIELD_BASE(31, 34, 6, 0x00d0, 0x10, 8, 4), ++ PINS_FIELD_BASE(35, 36, 6, 0x00d0, 0x10, 20, 4), ++ PIN_FIELD_BASE(37, 37, 6, 0x00d0, 0x10, 24, 4), ++ PIN_FIELD_BASE(38, 38, 6, 0x00d0, 0x10, 16, 4), ++ PINS_FIELD_BASE(39, 40, 6, 0x00d0, 0x10, 12, 4), ++ PINS_FIELD_BASE(41, 42, 7, 0x00d0, 0x10, 24, 4), ++ PIN_FIELD_BASE(43, 43, 7, 0x00d0, 0x10, 12, 4), ++ PIN_FIELD_BASE(44, 44, 7, 0x00d0, 0x10, 16, 4), ++ PIN_FIELD_BASE(45, 45, 7, 0x00e0, 0x10, 0, 4), ++ PINS_FIELD_BASE(46, 47, 7, 0x00d0, 0x10, 28, 4), ++ PINS_FIELD_BASE(48, 49, 7, 0x00e0, 0x10, 28, 4), ++ PINS_FIELD_BASE(50, 51, 7, 0x00e0, 0x10, 24, 4), ++ PINS_FIELD_BASE(52, 57, 7, 0x00d0, 0x10, 0, 4), ++ PINS_FIELD_BASE(58, 60, 7, 0x00e0, 0x10, 16, 4), ++ PINS_FIELD_BASE(61, 62, 3, 0x0090, 0x10, 20, 4), ++ PINS_FIELD_BASE(63, 64, 3, 0x0090, 0x10, 16, 4), ++ PINS_FIELD_BASE(65, 66, 3, 0x0090, 0x10, 28, 4), ++ PINS_FIELD_BASE(67, 68, 3, 0x0090, 0x10, 24, 4), ++ PINS_FIELD_BASE(69, 73, 3, 0x0090, 0x10, 4, 4), ++ PINS_FIELD_BASE(74, 78, 3, 0x0090, 0x10, 8, 4), ++ PINS_FIELD_BASE(79, 80, 3, 0x0090, 0x10, 0, 4), ++ PIN_FIELD_BASE(81, 81, 3, 0x00a0, 0x10, 8, 4), ++ PINS_FIELD_BASE(82, 83, 3, 0x00a0, 0x10, 4, 4), ++ PIN_FIELD_BASE(84, 84, 3, 0x00a0, 0x10, 8, 4), ++ PIN_FIELD_BASE(85, 85, 7, 0x00e0, 0x10, 16, 4), ++ PIN_FIELD_BASE(86, 86, 7, 0x00e0, 0x10, 20, 4), ++ PIN_FIELD_BASE(87, 87, 7, 0x00d0, 0x10, 8, 4), ++ PIN_FIELD_BASE(88, 88, 7, 0x00d0, 0x10, 4, 4), ++ PIN_FIELD_BASE(89, 89, 2, 0x00d0, 0x10, 12, 4), ++ PIN_FIELD_BASE(90, 90, 3, 0x00a0, 0x10, 0, 4), ++ PINS_FIELD_BASE(91, 92, 2, 0x00d0, 0x10, 0, 4), ++ PINS_FIELD_BASE(93, 94, 2, 0x00c0, 0x10, 28, 4), ++ PINS_FIELD_BASE(95, 96, 2, 0x00d0, 0x10, 16, 4), ++ PINS_FIELD_BASE(97, 98, 2, 0x00c0, 0x10, 8, 4), ++ PIN_FIELD_BASE(99, 99, 2, 0x00c0, 0x10, 0, 4), ++ PIN_FIELD_BASE(100, 100, 2, 0x00c0, 0x10, 4, 4), ++ PINS_FIELD_BASE(101, 102, 2, 0x00c0, 0x10, 12, 4), ++ PINS_FIELD_BASE(103, 104, 2, 0x00d0, 0x10, 4, 4), ++ PINS_FIELD_BASE(105, 106, 2, 0x00d0, 0x10, 8, 4), ++ PIN_FIELD_BASE(107, 107, 1, 0x0090, 0x10, 16, 4), ++ PIN_FIELD_BASE(108, 108, 1, 0x0090, 0x10, 12, 4), ++ PIN_FIELD_BASE(109, 109, 1, 0x0090, 0x10, 20, 4), ++ PIN_FIELD_BASE(110, 110, 1, 0x0090, 0x10, 0, 4), ++ PIN_FIELD_BASE(111, 111, 1, 0x0090, 0x10, 4, 4), ++ PIN_FIELD_BASE(112, 112, 1, 0x0090, 0x10, 8, 4), ++ PIN_FIELD_BASE(113, 113, 1, 0x00a0, 0x10, 4, 4), ++ PIN_FIELD_BASE(114, 114, 1, 0x00a0, 0x10, 8, 4), ++ PIN_FIELD_BASE(115, 115, 1, 0x0090, 0x10, 24, 4), ++ PIN_FIELD_BASE(116, 116, 1, 0x0090, 0x10, 28, 4), ++ PIN_FIELD_BASE(117, 117, 1, 0x00a0, 0x10, 16, 4), ++ PIN_FIELD_BASE(118, 118, 1, 0x00a0, 0x10, 20, 4), ++ PIN_FIELD_BASE(119, 119, 1, 0x00a0, 0x10, 24, 4), ++ PIN_FIELD_BASE(120, 120, 1, 0x00a0, 0x10, 12, 4), ++ PIN_FIELD_BASE(121, 121, 1, 0x00a0, 0x10, 0, 4), ++ PIN_FIELD_BASE(122, 122, 4, 0x0090, 0x10, 8, 4), ++ PIN_FIELD_BASE(123, 123, 4, 0x0090, 0x10, 12, 4), ++ PIN_FIELD_BASE(124, 124, 4, 0x0090, 0x10, 4, 4), ++ PINS_FIELD_BASE(125, 130, 4, 0x0090, 0x10, 12, 4), ++ PIN_FIELD_BASE(131, 131, 4, 0x0090, 0x10, 16, 4), ++ PIN_FIELD_BASE(132, 132, 4, 0x0090, 0x10, 12, 4), ++ PIN_FIELD_BASE(133, 133, 4, 0x0090, 0x10, 20, 4), ++ PIN_FIELD_BASE(134, 134, 5, 0x0080, 0x10, 12, 4), ++ PIN_FIELD_BASE(135, 135, 5, 0x0080, 0x10, 20, 4), ++ PIN_FIELD_BASE(136, 136, 5, 0x0070, 0x10, 4, 4), ++ PIN_FIELD_BASE(137, 137, 5, 0x0070, 0x10, 28, 4), ++ PIN_FIELD_BASE(138, 138, 5, 0x0070, 0x10, 16, 4), ++ PIN_FIELD_BASE(139, 139, 5, 0x0070, 0x10, 20, 4), ++ PIN_FIELD_BASE(140, 140, 5, 0x0070, 0x10, 0, 4), ++ PIN_FIELD_BASE(141, 141, 5, 0x0070, 0x10, 24, 4), ++ PIN_FIELD_BASE(142, 142, 5, 0x0070, 0x10, 8, 4), ++ PIN_FIELD_BASE(143, 143, 5, 0x0070, 0x10, 12, 4), ++ PINS_FIELD_BASE(144, 147, 5, 0x0080, 0x10, 8, 4), ++ PINS_FIELD_BASE(148, 149, 5, 0x0080, 0x10, 16, 4), ++ PINS_FIELD_BASE(150, 151, 7, 0x00e0, 0x10, 4, 4), ++ PINS_FIELD_BASE(152, 153, 7, 0x00e0, 0x10, 8, 4), ++ PIN_FIELD_BASE(154, 154, 7, 0x00e0, 0x10, 12, 4), ++ PINS_FIELD_BASE(155, 158, 3, 0x00a0, 0x10, 12, 4), ++ PIN_FIELD_BASE(159, 159, 7, 0x00e0, 0x10, 12, 4), ++ PIN_FIELD_BASE(160, 160, 5, 0x0080, 0x10, 0, 4), ++ PINS_FIELD_BASE(161, 162, 1, 0x00a0, 0x10, 28, 4), ++ PINS_FIELD_BASE(163, 170, 4, 0x0090, 0x10, 0, 4), ++ PINS_FIELD_BASE(171, 179, 7, 0x00d0, 0x10, 20, 4), ++}; ++ ++static const struct mtk_pin_field_calc mt6765_pin_rdsel_range[] = { ++ PINS_FIELD_BASE(0, 3, 2, 0x0090, 0x10, 8, 2), ++ PINS_FIELD_BASE(4, 7, 2, 0x0090, 0x10, 10, 2), ++ PIN_FIELD_BASE(8, 8, 3, 0x0060, 0x10, 6, 2), ++ PINS_FIELD_BASE(9, 11, 2, 0x0090, 0x10, 12, 2), ++ PIN_FIELD_BASE(12, 12, 5, 0x0050, 0x10, 18, 2), ++ PINS_FIELD_BASE(13, 16, 6, 0x00a0, 0x10, 18, 2), ++ PINS_FIELD_BASE(17, 20, 6, 0x00a0, 0x10, 14, 2), ++ PINS_FIELD_BASE(21, 24, 6, 0x00a0, 0x10, 16, 2), ++ PINS_FIELD_BASE(25, 28, 6, 0x00a0, 0x10, 12, 2), ++ PIN_FIELD_BASE(29, 29, 6, 0x0090, 0x10, 0, 6), ++ PIN_FIELD_BASE(30, 30, 6, 0x0090, 0x10, 6, 6), ++ PINS_FIELD_BASE(31, 34, 6, 0x0090, 0x10, 12, 6), ++ PINS_FIELD_BASE(35, 36, 6, 0x00a0, 0x10, 0, 6), ++ PIN_FIELD_BASE(37, 37, 6, 0x00a0, 0x10, 6, 6), ++ PIN_FIELD_BASE(38, 38, 6, 0x0090, 0x10, 24, 6), ++ PINS_FIELD_BASE(39, 40, 6, 0x0090, 0x10, 18, 6), ++ PINS_FIELD_BASE(41, 42, 7, 0x00a0, 0x10, 12, 2), ++ PIN_FIELD_BASE(43, 43, 7, 0x00a0, 0x10, 6, 2), ++ PIN_FIELD_BASE(44, 44, 7, 0x00a0, 0x10, 8, 2), ++ PIN_FIELD_BASE(45, 45, 7, 0x00a0, 0x10, 16, 2), ++ PINS_FIELD_BASE(46, 47, 7, 0x00a0, 0x10, 14, 2), ++ PINS_FIELD_BASE(48, 49, 7, 0x00a0, 0x10, 30, 2), ++ PINS_FIELD_BASE(50, 51, 7, 0x00a0, 0x10, 28, 2), ++ PINS_FIELD_BASE(52, 57, 7, 0x00a0, 0x10, 0, 2), ++ PINS_FIELD_BASE(58, 60, 7, 0x00a0, 0x10, 24, 2), ++ PINS_FIELD_BASE(61, 62, 3, 0x0060, 0x10, 10, 2), ++ PINS_FIELD_BASE(63, 64, 3, 0x0060, 0x10, 8, 2), ++ PINS_FIELD_BASE(65, 66, 3, 0x0060, 0x10, 14, 2), ++ PINS_FIELD_BASE(67, 68, 3, 0x0060, 0x10, 12, 2), ++ PINS_FIELD_BASE(69, 73, 3, 0x0060, 0x10, 2, 2), ++ PINS_FIELD_BASE(74, 78, 3, 0x0060, 0x10, 4, 2), ++ PINS_FIELD_BASE(79, 80, 3, 0x0060, 0x10, 0, 2), ++ PIN_FIELD_BASE(81, 81, 3, 0x0060, 0x10, 20, 2), ++ PINS_FIELD_BASE(82, 83, 3, 0x0060, 0x10, 18, 2), ++ PIN_FIELD_BASE(84, 84, 3, 0x0060, 0x10, 20, 2), ++ PIN_FIELD_BASE(85, 85, 7, 0x00a0, 0x10, 24, 2), ++ PIN_FIELD_BASE(86, 86, 7, 0x00a0, 0x10, 26, 2), ++ PIN_FIELD_BASE(87, 87, 7, 0x00a0, 0x10, 4, 2), ++ PIN_FIELD_BASE(88, 88, 7, 0x00a0, 0x10, 2, 2), ++ PIN_FIELD_BASE(89, 89, 2, 0x0090, 0x10, 22, 2), ++ PIN_FIELD_BASE(90, 90, 3, 0x0060, 0x10, 16, 2), ++ PINS_FIELD_BASE(91, 92, 2, 0x0090, 0x10, 16, 2), ++ PINS_FIELD_BASE(93, 94, 2, 0x0090, 0x10, 14, 2), ++ PINS_FIELD_BASE(95, 96, 2, 0x0090, 0x10, 24, 2), ++ PINS_FIELD_BASE(97, 98, 2, 0x0090, 0x10, 4, 2), ++ PIN_FIELD_BASE(99, 99, 2, 0x0090, 0x10, 0, 2), ++ PIN_FIELD_BASE(100, 100, 2, 0x0090, 0x10, 2, 2), ++ PINS_FIELD_BASE(101, 102, 2, 0x0090, 0x10, 6, 2), ++ PINS_FIELD_BASE(103, 104, 2, 0x0090, 0x10, 18, 2), ++ PINS_FIELD_BASE(105, 106, 2, 0x0090, 0x10, 20, 2), ++ PIN_FIELD_BASE(107, 107, 1, 0x0060, 0x10, 8, 2), ++ PIN_FIELD_BASE(108, 108, 1, 0x0060, 0x10, 6, 2), ++ PIN_FIELD_BASE(109, 109, 1, 0x0060, 0x10, 10, 2), ++ PIN_FIELD_BASE(110, 110, 1, 0x0060, 0x10, 0, 2), ++ PIN_FIELD_BASE(111, 111, 1, 0x0060, 0x10, 2, 2), ++ PIN_FIELD_BASE(112, 112, 1, 0x0060, 0x10, 4, 2), ++ PIN_FIELD_BASE(113, 113, 1, 0x0060, 0x10, 18, 2), ++ PIN_FIELD_BASE(114, 114, 1, 0x0060, 0x10, 20, 2), ++ PIN_FIELD_BASE(115, 115, 1, 0x0060, 0x10, 12, 2), ++ PIN_FIELD_BASE(116, 116, 1, 0x0060, 0x10, 14, 2), ++ PIN_FIELD_BASE(117, 117, 1, 0x0060, 0x10, 24, 2), ++ PIN_FIELD_BASE(118, 118, 1, 0x0060, 0x10, 26, 2), ++ PIN_FIELD_BASE(119, 119, 1, 0x0060, 0x10, 28, 2), ++ PIN_FIELD_BASE(120, 120, 1, 0x0060, 0x10, 22, 2), ++ PIN_FIELD_BASE(121, 121, 1, 0x0060, 0x10, 16, 2), ++ PIN_FIELD_BASE(122, 122, 4, 0x0070, 0x10, 8, 6), ++ PIN_FIELD_BASE(123, 123, 4, 0x0070, 0x10, 14, 6), ++ PIN_FIELD_BASE(124, 124, 4, 0x0070, 0x10, 2, 6), ++ PINS_FIELD_BASE(125, 130, 4, 0x0070, 0x10, 14, 6), ++ PIN_FIELD_BASE(131, 131, 4, 0x0070, 0x10, 20, 6), ++ PIN_FIELD_BASE(132, 132, 4, 0x0070, 0x10, 14, 6), ++ PIN_FIELD_BASE(133, 133, 4, 0x0070, 0x10, 26, 6), ++ PIN_FIELD_BASE(134, 134, 5, 0x0050, 0x10, 22, 2), ++ PIN_FIELD_BASE(135, 135, 5, 0x0050, 0x10, 30, 2), ++ PIN_FIELD_BASE(136, 136, 5, 0x0050, 0x10, 2, 2), ++ PIN_FIELD_BASE(137, 137, 5, 0x0050, 0x10, 14, 2), ++ PIN_FIELD_BASE(138, 138, 5, 0x0050, 0x10, 8, 2), ++ PIN_FIELD_BASE(139, 139, 5, 0x0050, 0x10, 10, 2), ++ PIN_FIELD_BASE(140, 140, 5, 0x0050, 0x10, 0, 2), ++ PIN_FIELD_BASE(141, 141, 5, 0x0050, 0x10, 12, 2), ++ PIN_FIELD_BASE(142, 142, 5, 0x0050, 0x10, 4, 2), ++ PIN_FIELD_BASE(143, 143, 5, 0x0050, 0x10, 6, 2), ++ PINS_FIELD_BASE(144, 147, 5, 0x0050, 0x10, 20, 2), ++ PINS_FIELD_BASE(148, 149, 5, 0x0050, 0x10, 24, 2), ++ PINS_FIELD_BASE(150, 151, 7, 0x00a0, 0x10, 18, 2), ++ PINS_FIELD_BASE(152, 153, 7, 0x00a0, 0x10, 20, 2), ++ PIN_FIELD_BASE(154, 154, 7, 0x00a0, 0x10, 22, 2), ++ PINS_FIELD_BASE(155, 158, 3, 0x0060, 0x10, 22, 2), ++ PIN_FIELD_BASE(159, 159, 7, 0x00a0, 0x10, 22, 2), ++ PIN_FIELD_BASE(160, 160, 5, 0x0050, 0x10, 16, 2), ++ PINS_FIELD_BASE(161, 162, 1, 0x0060, 0x10, 30, 2), ++ PINS_FIELD_BASE(163, 170, 4, 0x0070, 0x10, 0, 2), ++ PINS_FIELD_BASE(171, 179, 7, 0x00a0, 0x10, 10, 2), ++}; ++ ++static const struct mtk_pin_field_calc mt6765_pin_drv_range[] = { ++ PINS_FIELD_BASE(0, 2, 2, 0x0000, 0x10, 12, 3), ++ PIN_FIELD_BASE(3, 3, 2, 0x0000, 0x10, 15, 3), ++ PINS_FIELD_BASE(4, 6, 2, 0x0000, 0x10, 18, 3), ++ PIN_FIELD_BASE(7, 7, 2, 0x0000, 0x10, 21, 3), ++ PIN_FIELD_BASE(8, 8, 3, 0x0000, 0x10, 9, 3), ++ PINS_FIELD_BASE(9, 11, 2, 0x0000, 0x10, 24, 3), ++ PIN_FIELD_BASE(12, 12, 5, 0x0000, 0x10, 27, 3), ++ PINS_FIELD_BASE(13, 15, 6, 0x0010, 0x10, 3, 3), ++ PIN_FIELD_BASE(16, 16, 6, 0x0010, 0x10, 6, 3), ++ PIN_FIELD_BASE(17, 17, 6, 0x0000, 0x10, 23, 3), ++ PIN_FIELD_BASE(18, 18, 6, 0x0000, 0x10, 26, 3), ++ PINS_FIELD_BASE(19, 20, 6, 0x0000, 0x10, 23, 3), ++ PINS_FIELD_BASE(21, 23, 6, 0x0000, 0x10, 29, 3), ++ PIN_FIELD_BASE(24, 24, 6, 0x0010, 0x10, 0, 3), ++ PINS_FIELD_BASE(25, 27, 6, 0x0000, 0x10, 17, 3), ++ PIN_FIELD_BASE(28, 28, 6, 0x0000, 0x10, 20, 3), ++ PIN_FIELD_BASE(29, 29, 6, 0x0000, 0x10, 0, 3), ++ PIN_FIELD_BASE(30, 30, 6, 0x0000, 0x10, 3, 3), ++ PINS_FIELD_BASE(31, 34, 6, 0x0000, 0x10, 6, 3), ++ PINS_FIELD_BASE(35, 36, 6, 0x0000, 0x10, 13, 2), ++ PIN_FIELD_BASE(37, 37, 6, 0x0000, 0x10, 15, 2), ++ PIN_FIELD_BASE(38, 38, 6, 0x0000, 0x10, 11, 2), ++ PINS_FIELD_BASE(39, 40, 6, 0x0000, 0x10, 9, 2), ++ PINS_FIELD_BASE(41, 42, 7, 0x0000, 0x10, 21, 3), ++ PIN_FIELD_BASE(43, 43, 7, 0x0000, 0x10, 9, 3), ++ PIN_FIELD_BASE(44, 44, 7, 0x0000, 0x10, 12, 3), ++ PIN_FIELD_BASE(45, 45, 7, 0x0000, 0x10, 27, 3), ++ PINS_FIELD_BASE(46, 47, 7, 0x0000, 0x10, 24, 3), ++ PINS_FIELD_BASE(48, 49, 7, 0x0010, 0x10, 18, 3), ++ PINS_FIELD_BASE(50, 51, 7, 0x0010, 0x10, 15, 3), ++ PINS_FIELD_BASE(52, 57, 7, 0x0000, 0x10, 0, 3), ++ PINS_FIELD_BASE(58, 60, 7, 0x0010, 0x10, 9, 3), ++ PINS_FIELD_BASE(61, 62, 3, 0x0000, 0x10, 15, 3), ++ PINS_FIELD_BASE(63, 64, 3, 0x0000, 0x10, 12, 3), ++ PINS_FIELD_BASE(65, 66, 3, 0x0000, 0x10, 21, 3), ++ PINS_FIELD_BASE(67, 68, 3, 0x0000, 0x10, 18, 3), ++ PINS_FIELD_BASE(69, 73, 3, 0x0000, 0x10, 3, 3), ++ PINS_FIELD_BASE(74, 78, 3, 0x0000, 0x10, 6, 3), ++ PINS_FIELD_BASE(79, 80, 3, 0x0000, 0x10, 0, 3), ++ PIN_FIELD_BASE(81, 81, 3, 0x0010, 0x10, 0, 3), ++ PINS_FIELD_BASE(82, 83, 3, 0x0000, 0x10, 27, 3), ++ PIN_FIELD_BASE(84, 84, 3, 0x0010, 0x10, 0, 3), ++ PIN_FIELD_BASE(85, 85, 7, 0x0010, 0x10, 9, 3), ++ PIN_FIELD_BASE(86, 86, 7, 0x0010, 0x10, 12, 3), ++ PIN_FIELD_BASE(87, 87, 7, 0x0000, 0x10, 6, 3), ++ PIN_FIELD_BASE(88, 88, 7, 0x0000, 0x10, 3, 3), ++ PIN_FIELD_BASE(89, 89, 2, 0x0010, 0x10, 15, 3), ++ PIN_FIELD_BASE(90, 90, 3, 0x0000, 0x10, 24, 3), ++ PIN_FIELD_BASE(91, 91, 2, 0x0010, 0x10, 6, 3), ++ PIN_FIELD_BASE(92, 92, 2, 0x0010, 0x10, 3, 3), ++ PIN_FIELD_BASE(93, 93, 2, 0x0000, 0x10, 27, 3), ++ PIN_FIELD_BASE(94, 94, 2, 0x0010, 0x10, 0, 3), ++ PINS_FIELD_BASE(95, 96, 2, 0x0010, 0x10, 18, 3), ++ PINS_FIELD_BASE(97, 98, 2, 0x0000, 0x10, 6, 3), ++ PIN_FIELD_BASE(99, 99, 2, 0x0000, 0x10, 0, 3), ++ PIN_FIELD_BASE(100, 100, 2, 0x0000, 0x10, 3, 3), ++ PINS_FIELD_BASE(101, 102, 2, 0x0000, 0x10, 9, 3), ++ PINS_FIELD_BASE(103, 104, 2, 0x0010, 0x10, 9, 3), ++ PINS_FIELD_BASE(105, 106, 2, 0x0010, 0x10, 12, 3), ++ PIN_FIELD_BASE(107, 107, 1, 0x0000, 0x10, 12, 3), ++ PIN_FIELD_BASE(108, 108, 1, 0x0000, 0x10, 9, 3), ++ PIN_FIELD_BASE(109, 109, 1, 0x0000, 0x10, 15, 3), ++ PIN_FIELD_BASE(110, 110, 1, 0x0000, 0x10, 0, 3), ++ PIN_FIELD_BASE(111, 111, 1, 0x0000, 0x10, 3, 3), ++ PIN_FIELD_BASE(112, 112, 1, 0x0000, 0x10, 6, 3), ++ PIN_FIELD_BASE(113, 113, 1, 0x0000, 0x10, 27, 3), ++ PIN_FIELD_BASE(114, 114, 1, 0x0010, 0x10, 0, 3), ++ PIN_FIELD_BASE(115, 115, 1, 0x0000, 0x10, 18, 3), ++ PIN_FIELD_BASE(116, 116, 1, 0x0000, 0x10, 21, 3), ++ PIN_FIELD_BASE(117, 117, 1, 0x0010, 0x10, 6, 3), ++ PIN_FIELD_BASE(118, 118, 1, 0x0010, 0x10, 9, 3), ++ PIN_FIELD_BASE(119, 119, 1, 0x0010, 0x10, 12, 3), ++ PIN_FIELD_BASE(120, 120, 1, 0x0010, 0x10, 3, 3), ++ PIN_FIELD_BASE(121, 121, 1, 0x0000, 0x10, 24, 3), ++ PIN_FIELD_BASE(122, 122, 4, 0x0000, 0x10, 9, 3), ++ PIN_FIELD_BASE(123, 123, 4, 0x0000, 0x10, 12, 3), ++ PIN_FIELD_BASE(124, 124, 4, 0x0000, 0x10, 6, 3), ++ PINS_FIELD_BASE(125, 130, 4, 0x0000, 0x10, 12, 3), ++ PIN_FIELD_BASE(131, 131, 4, 0x0000, 0x10, 15, 3), ++ PIN_FIELD_BASE(132, 132, 4, 0x0000, 0x10, 12, 3), ++ PIN_FIELD_BASE(133, 133, 4, 0x0000, 0x10, 18, 3), ++ PIN_FIELD_BASE(134, 134, 5, 0x0010, 0x10, 6, 3), ++ PIN_FIELD_BASE(135, 135, 5, 0x0010, 0x10, 12, 3), ++ PIN_FIELD_BASE(136, 136, 5, 0x0000, 0x10, 3, 3), ++ PIN_FIELD_BASE(137, 137, 5, 0x0000, 0x10, 21, 3), ++ PIN_FIELD_BASE(138, 138, 5, 0x0000, 0x10, 12, 3), ++ PIN_FIELD_BASE(139, 139, 5, 0x0000, 0x10, 15, 3), ++ PIN_FIELD_BASE(140, 140, 5, 0x0000, 0x10, 0, 3), ++ PIN_FIELD_BASE(141, 141, 5, 0x0000, 0x10, 18, 3), ++ PIN_FIELD_BASE(142, 142, 5, 0x0000, 0x10, 6, 3), ++ PIN_FIELD_BASE(143, 143, 5, 0x0000, 0x10, 9, 3), ++ PINS_FIELD_BASE(144, 146, 5, 0x0010, 0x10, 0, 3), ++ PIN_FIELD_BASE(147, 147, 5, 0x0010, 0x10, 3, 3), ++ PINS_FIELD_BASE(148, 149, 5, 0x0010, 0x10, 9, 3), ++ PINS_FIELD_BASE(150, 151, 7, 0x0010, 0x10, 0, 3), ++ PINS_FIELD_BASE(152, 153, 7, 0x0010, 0x10, 3, 3), ++ PIN_FIELD_BASE(154, 154, 7, 0x0010, 0x10, 6, 3), ++ PINS_FIELD_BASE(155, 157, 3, 0x0010, 0x10, 3, 3), ++ PIN_FIELD_BASE(158, 158, 3, 0x0010, 0x10, 6, 3), ++ PIN_FIELD_BASE(159, 159, 7, 0x0010, 0x10, 6, 3), ++ PIN_FIELD_BASE(160, 160, 5, 0x0000, 0x10, 24, 3), ++ PINS_FIELD_BASE(161, 162, 1, 0x0010, 0x10, 15, 3), ++ PINS_FIELD_BASE(163, 166, 4, 0x0000, 0x10, 0, 3), ++ PINS_FIELD_BASE(167, 170, 4, 0x0000, 0x10, 3, 3), ++ PINS_FIELD_BASE(171, 174, 7, 0x0000, 0x10, 18, 3), ++ PINS_FIELD_BASE(175, 179, 7, 0x0000, 0x10, 15, 3), ++}; ++ ++static const struct mtk_pin_field_calc mt6765_pin_pupd_range[] = { ++ PINS_FIELD_BASE(0, 28, 0, 0x0050, 0x10, 18, 1), ++ PIN_FIELD_BASE(29, 29, 6, 0x0050, 0x10, 0, 1), ++ PIN_FIELD_BASE(30, 30, 6, 0x0050, 0x10, 1, 1), ++ PIN_FIELD_BASE(31, 31, 6, 0x0050, 0x10, 5, 1), ++ PIN_FIELD_BASE(32, 32, 6, 0x0050, 0x10, 2, 1), ++ PIN_FIELD_BASE(33, 33, 6, 0x0050, 0x10, 4, 1), ++ PIN_FIELD_BASE(34, 34, 6, 0x0050, 0x10, 3, 1), ++ PIN_FIELD_BASE(35, 35, 6, 0x0050, 0x10, 10, 1), ++ PIN_FIELD_BASE(36, 36, 6, 0x0050, 0x10, 11, 1), ++ PIN_FIELD_BASE(37, 37, 6, 0x0050, 0x10, 9, 1), ++ PIN_FIELD_BASE(38, 38, 6, 0x0050, 0x10, 6, 1), ++ PIN_FIELD_BASE(39, 39, 6, 0x0050, 0x10, 8, 1), ++ PINS_FIELD_BASE(40, 90, 6, 0x0050, 0x10, 7, 1), ++ PIN_FIELD_BASE(91, 91, 2, 0x0050, 0x10, 3, 1), ++ PIN_FIELD_BASE(92, 92, 2, 0x0050, 0x10, 2, 1), ++ PIN_FIELD_BASE(93, 93, 2, 0x0050, 0x10, 0, 1), ++ PINS_FIELD_BASE(94, 121, 2, 0x0050, 0x10, 1, 1), ++ PIN_FIELD_BASE(122, 122, 4, 0x0030, 0x10, 1, 1), ++ PIN_FIELD_BASE(123, 123, 4, 0x0030, 0x10, 2, 1), ++ PIN_FIELD_BASE(124, 124, 4, 0x0030, 0x10, 0, 1), ++ PIN_FIELD_BASE(125, 125, 4, 0x0030, 0x10, 4, 1), ++ PIN_FIELD_BASE(126, 126, 4, 0x0030, 0x10, 6, 1), ++ PIN_FIELD_BASE(127, 127, 4, 0x0030, 0x10, 8, 1), ++ PIN_FIELD_BASE(128, 128, 4, 0x0030, 0x10, 3, 1), ++ PIN_FIELD_BASE(129, 129, 4, 0x0030, 0x10, 7, 1), ++ PIN_FIELD_BASE(130, 130, 4, 0x0030, 0x10, 9, 1), ++ PIN_FIELD_BASE(131, 131, 4, 0x0030, 0x10, 10, 1), ++ PIN_FIELD_BASE(132, 132, 4, 0x0030, 0x10, 5, 1), ++ PINS_FIELD_BASE(133, 179, 4, 0x0030, 0x10, 11, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt6765_pin_r0_range[] = { ++ PINS_FIELD_BASE(0, 28, 4, 0x0030, 0x10, 11, 1), ++ PIN_FIELD_BASE(29, 29, 6, 0x0070, 0x10, 0, 1), ++ PIN_FIELD_BASE(30, 30, 6, 0x0070, 0x10, 1, 1), ++ PIN_FIELD_BASE(31, 31, 6, 0x0070, 0x10, 5, 1), ++ PIN_FIELD_BASE(32, 32, 6, 0x0070, 0x10, 2, 1), ++ PIN_FIELD_BASE(33, 33, 6, 0x0070, 0x10, 4, 1), ++ PIN_FIELD_BASE(34, 34, 6, 0x0070, 0x10, 3, 1), ++ PIN_FIELD_BASE(35, 35, 6, 0x0070, 0x10, 10, 1), ++ PIN_FIELD_BASE(36, 36, 6, 0x0070, 0x10, 11, 1), ++ PIN_FIELD_BASE(37, 37, 6, 0x0070, 0x10, 9, 1), ++ PIN_FIELD_BASE(38, 38, 6, 0x0070, 0x10, 6, 1), ++ PIN_FIELD_BASE(39, 39, 6, 0x0070, 0x10, 8, 1), ++ PINS_FIELD_BASE(40, 90, 6, 0x0070, 0x10, 7, 1), ++ PIN_FIELD_BASE(91, 91, 2, 0x0070, 0x10, 3, 1), ++ PIN_FIELD_BASE(92, 92, 2, 0x0070, 0x10, 2, 1), ++ PIN_FIELD_BASE(93, 93, 2, 0x0070, 0x10, 0, 1), ++ PINS_FIELD_BASE(94, 121, 2, 0x0070, 0x10, 1, 1), ++ PIN_FIELD_BASE(122, 122, 4, 0x0050, 0x10, 1, 1), ++ PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 2, 1), ++ PIN_FIELD_BASE(124, 124, 4, 0x0050, 0x10, 0, 1), ++ PIN_FIELD_BASE(125, 125, 4, 0x0050, 0x10, 4, 1), ++ PIN_FIELD_BASE(126, 126, 4, 0x0050, 0x10, 6, 1), ++ PIN_FIELD_BASE(127, 127, 4, 0x0050, 0x10, 8, 1), ++ PIN_FIELD_BASE(128, 128, 4, 0x0050, 0x10, 3, 1), ++ PIN_FIELD_BASE(129, 129, 4, 0x0050, 0x10, 7, 1), ++ PIN_FIELD_BASE(130, 130, 4, 0x0050, 0x10, 9, 1), ++ PIN_FIELD_BASE(131, 131, 4, 0x0050, 0x10, 10, 1), ++ PIN_FIELD_BASE(132, 132, 4, 0x0050, 0x10, 5, 1), ++ PINS_FIELD_BASE(133, 179, 4, 0x0050, 0x10, 11, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt6765_pin_r1_range[] = { ++ PINS_FIELD_BASE(0, 28, 4, 0x0050, 0x10, 11, 1), ++ PIN_FIELD_BASE(29, 29, 6, 0x0080, 0x10, 0, 1), ++ PIN_FIELD_BASE(30, 30, 6, 0x0080, 0x10, 1, 1), ++ PIN_FIELD_BASE(31, 31, 6, 0x0080, 0x10, 5, 1), ++ PIN_FIELD_BASE(32, 32, 6, 0x0080, 0x10, 2, 1), ++ PIN_FIELD_BASE(33, 33, 6, 0x0080, 0x10, 4, 1), ++ PIN_FIELD_BASE(34, 34, 6, 0x0080, 0x10, 3, 1), ++ PIN_FIELD_BASE(35, 35, 6, 0x0080, 0x10, 10, 1), ++ PIN_FIELD_BASE(36, 36, 6, 0x0080, 0x10, 11, 1), ++ PIN_FIELD_BASE(37, 37, 6, 0x0080, 0x10, 9, 1), ++ PIN_FIELD_BASE(38, 38, 6, 0x0080, 0x10, 6, 1), ++ PIN_FIELD_BASE(39, 39, 6, 0x0080, 0x10, 8, 1), ++ PINS_FIELD_BASE(40, 90, 6, 0x0080, 0x10, 7, 1), ++ PIN_FIELD_BASE(91, 91, 2, 0x0080, 0x10, 3, 1), ++ PIN_FIELD_BASE(92, 92, 2, 0x0080, 0x10, 2, 1), ++ PIN_FIELD_BASE(93, 93, 2, 0x0080, 0x10, 0, 1), ++ PINS_FIELD_BASE(94, 121, 2, 0x0080, 0x10, 1, 1), ++ PIN_FIELD_BASE(122, 122, 4, 0x0060, 0x10, 1, 1), ++ PIN_FIELD_BASE(123, 123, 4, 0x0060, 0x10, 2, 1), ++ PIN_FIELD_BASE(124, 124, 4, 0x0060, 0x10, 0, 1), ++ PIN_FIELD_BASE(125, 125, 4, 0x0060, 0x10, 4, 1), ++ PIN_FIELD_BASE(126, 126, 4, 0x0060, 0x10, 6, 1), ++ PIN_FIELD_BASE(127, 127, 4, 0x0060, 0x10, 8, 1), ++ PIN_FIELD_BASE(128, 128, 4, 0x0060, 0x10, 3, 1), ++ PIN_FIELD_BASE(129, 129, 4, 0x0060, 0x10, 7, 1), ++ PIN_FIELD_BASE(130, 130, 4, 0x0060, 0x10, 9, 1), ++ PIN_FIELD_BASE(131, 131, 4, 0x0060, 0x10, 10, 1), ++ PIN_FIELD_BASE(132, 132, 4, 0x0060, 0x10, 5, 1), ++ PINS_FIELD_BASE(133, 179, 4, 0x0060, 0x10, 11, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt6765_pin_ies_range[] = { ++ PIN_FIELD_BASE(0, 0, 2, 0x0030, 0x10, 6, 1), ++ PIN_FIELD_BASE(1, 1, 2, 0x0030, 0x10, 7, 1), ++ PIN_FIELD_BASE(2, 2, 2, 0x0030, 0x10, 10, 1), ++ PIN_FIELD_BASE(3, 3, 2, 0x0030, 0x10, 11, 1), ++ PIN_FIELD_BASE(4, 4, 2, 0x0030, 0x10, 12, 1), ++ PIN_FIELD_BASE(5, 5, 2, 0x0030, 0x10, 13, 1), ++ PIN_FIELD_BASE(6, 6, 2, 0x0030, 0x10, 14, 1), ++ PIN_FIELD_BASE(7, 7, 2, 0x0030, 0x10, 15, 1), ++ PIN_FIELD_BASE(8, 8, 3, 0x0030, 0x10, 12, 1), ++ PIN_FIELD_BASE(9, 9, 2, 0x0030, 0x10, 16, 1), ++ PIN_FIELD_BASE(10, 10, 2, 0x0030, 0x10, 8, 1), ++ PIN_FIELD_BASE(11, 11, 2, 0x0030, 0x10, 9, 1), ++ PIN_FIELD_BASE(12, 12, 5, 0x0020, 0x10, 9, 1), ++ PIN_FIELD_BASE(13, 13, 6, 0x0020, 0x10, 26, 1), ++ PIN_FIELD_BASE(14, 14, 6, 0x0020, 0x10, 25, 1), ++ PIN_FIELD_BASE(15, 15, 6, 0x0020, 0x10, 27, 1), ++ PIN_FIELD_BASE(16, 16, 6, 0x0020, 0x10, 24, 1), ++ PIN_FIELD_BASE(17, 17, 6, 0x0020, 0x10, 19, 1), ++ PIN_FIELD_BASE(18, 18, 6, 0x0020, 0x10, 16, 1), ++ PIN_FIELD_BASE(19, 19, 6, 0x0020, 0x10, 18, 1), ++ PIN_FIELD_BASE(20, 20, 6, 0x0020, 0x10, 17, 1), ++ PIN_FIELD_BASE(21, 21, 6, 0x0020, 0x10, 22, 1), ++ PIN_FIELD_BASE(22, 22, 6, 0x0020, 0x10, 21, 1), ++ PIN_FIELD_BASE(23, 23, 6, 0x0020, 0x10, 23, 1), ++ PIN_FIELD_BASE(24, 24, 6, 0x0020, 0x10, 20, 1), ++ PIN_FIELD_BASE(25, 25, 6, 0x0020, 0x10, 14, 1), ++ PIN_FIELD_BASE(26, 26, 6, 0x0020, 0x10, 13, 1), ++ PIN_FIELD_BASE(27, 27, 6, 0x0020, 0x10, 15, 1), ++ PIN_FIELD_BASE(28, 28, 6, 0x0020, 0x10, 12, 1), ++ PIN_FIELD_BASE(29, 29, 6, 0x0020, 0x10, 0, 1), ++ PIN_FIELD_BASE(30, 30, 6, 0x0020, 0x10, 1, 1), ++ PIN_FIELD_BASE(31, 31, 6, 0x0020, 0x10, 5, 1), ++ PIN_FIELD_BASE(32, 32, 6, 0x0020, 0x10, 2, 1), ++ PIN_FIELD_BASE(33, 33, 6, 0x0020, 0x10, 4, 1), ++ PIN_FIELD_BASE(34, 34, 6, 0x0020, 0x10, 3, 1), ++ PIN_FIELD_BASE(35, 35, 6, 0x0020, 0x10, 10, 1), ++ PIN_FIELD_BASE(36, 36, 6, 0x0020, 0x10, 11, 1), ++ PIN_FIELD_BASE(37, 37, 6, 0x0020, 0x10, 9, 1), ++ PIN_FIELD_BASE(38, 38, 6, 0x0020, 0x10, 6, 1), ++ PIN_FIELD_BASE(39, 39, 6, 0x0020, 0x10, 8, 1), ++ PIN_FIELD_BASE(40, 40, 6, 0x0020, 0x10, 7, 1), ++ PIN_FIELD_BASE(41, 41, 7, 0x0040, 0x10, 19, 1), ++ PIN_FIELD_BASE(42, 42, 7, 0x0040, 0x10, 9, 1), ++ PIN_FIELD_BASE(43, 43, 7, 0x0040, 0x10, 8, 1), ++ PIN_FIELD_BASE(44, 44, 7, 0x0040, 0x10, 10, 1), ++ PIN_FIELD_BASE(45, 45, 7, 0x0040, 0x10, 22, 1), ++ PIN_FIELD_BASE(46, 46, 7, 0x0040, 0x10, 21, 1), ++ PIN_FIELD_BASE(47, 47, 7, 0x0040, 0x10, 20, 1), ++ PIN_FIELD_BASE(48, 48, 7, 0x0050, 0x10, 3, 1), ++ PIN_FIELD_BASE(49, 49, 7, 0x0050, 0x10, 5, 1), ++ PIN_FIELD_BASE(50, 50, 7, 0x0050, 0x10, 2, 1), ++ PIN_FIELD_BASE(51, 51, 7, 0x0050, 0x10, 4, 1), ++ PIN_FIELD_BASE(52, 52, 7, 0x0040, 0x10, 1, 1), ++ PIN_FIELD_BASE(53, 53, 7, 0x0040, 0x10, 0, 1), ++ PIN_FIELD_BASE(54, 54, 7, 0x0040, 0x10, 5, 1), ++ PIN_FIELD_BASE(55, 55, 7, 0x0040, 0x10, 3, 1), ++ PIN_FIELD_BASE(56, 56, 7, 0x0040, 0x10, 4, 1), ++ PIN_FIELD_BASE(57, 57, 7, 0x0040, 0x10, 2, 1), ++ PIN_FIELD_BASE(58, 58, 7, 0x0050, 0x10, 0, 1), ++ PIN_FIELD_BASE(59, 59, 7, 0x0040, 0x10, 31, 1), ++ PIN_FIELD_BASE(60, 60, 7, 0x0040, 0x10, 30, 1), ++ PIN_FIELD_BASE(61, 61, 3, 0x0030, 0x10, 18, 1), ++ PIN_FIELD_BASE(62, 62, 3, 0x0030, 0x10, 14, 1), ++ PIN_FIELD_BASE(63, 63, 3, 0x0030, 0x10, 17, 1), ++ PIN_FIELD_BASE(64, 64, 3, 0x0030, 0x10, 13, 1), ++ PIN_FIELD_BASE(65, 65, 3, 0x0030, 0x10, 20, 1), ++ PIN_FIELD_BASE(66, 66, 3, 0x0030, 0x10, 16, 1), ++ PIN_FIELD_BASE(67, 67, 3, 0x0030, 0x10, 19, 1), ++ PIN_FIELD_BASE(68, 68, 3, 0x0030, 0x10, 15, 1), ++ PIN_FIELD_BASE(69, 69, 3, 0x0030, 0x10, 8, 1), ++ PIN_FIELD_BASE(70, 70, 3, 0x0030, 0x10, 7, 1), ++ PIN_FIELD_BASE(71, 71, 3, 0x0030, 0x10, 6, 1), ++ PIN_FIELD_BASE(72, 72, 3, 0x0030, 0x10, 5, 1), ++ PIN_FIELD_BASE(73, 73, 3, 0x0030, 0x10, 4, 1), ++ PIN_FIELD_BASE(74, 74, 3, 0x0030, 0x10, 3, 1), ++ PIN_FIELD_BASE(75, 75, 3, 0x0030, 0x10, 2, 1), ++ PIN_FIELD_BASE(76, 76, 3, 0x0030, 0x10, 1, 1), ++ PIN_FIELD_BASE(77, 77, 3, 0x0030, 0x10, 0, 1), ++ PIN_FIELD_BASE(78, 78, 3, 0x0030, 0x10, 9, 1), ++ PIN_FIELD_BASE(79, 79, 3, 0x0030, 0x10, 11, 1), ++ PIN_FIELD_BASE(80, 80, 3, 0x0030, 0x10, 10, 1), ++ PIN_FIELD_BASE(81, 81, 3, 0x0030, 0x10, 25, 1), ++ PIN_FIELD_BASE(82, 82, 3, 0x0030, 0x10, 24, 1), ++ PIN_FIELD_BASE(83, 83, 3, 0x0030, 0x10, 22, 1), ++ PIN_FIELD_BASE(84, 84, 3, 0x0030, 0x10, 23, 1), ++ PIN_FIELD_BASE(85, 85, 7, 0x0050, 0x10, 1, 1), ++ PIN_FIELD_BASE(86, 86, 7, 0x0040, 0x10, 29, 1), ++ PIN_FIELD_BASE(87, 87, 7, 0x0040, 0x10, 7, 1), ++ PIN_FIELD_BASE(88, 88, 7, 0x0040, 0x10, 6, 1), ++ PIN_FIELD_BASE(89, 89, 2, 0x0030, 0x10, 25, 1), ++ PIN_FIELD_BASE(90, 90, 3, 0x0030, 0x10, 21, 1), ++ PIN_FIELD_BASE(91, 91, 2, 0x0030, 0x10, 20, 1), ++ PIN_FIELD_BASE(92, 92, 2, 0x0030, 0x10, 19, 1), ++ PIN_FIELD_BASE(93, 93, 2, 0x0030, 0x10, 17, 1), ++ PIN_FIELD_BASE(94, 94, 2, 0x0030, 0x10, 18, 1), ++ PIN_FIELD_BASE(95, 95, 2, 0x0030, 0x10, 26, 1), ++ PIN_FIELD_BASE(96, 96, 2, 0x0030, 0x10, 27, 1), ++ PIN_FIELD_BASE(97, 97, 2, 0x0030, 0x10, 2, 1), ++ PIN_FIELD_BASE(98, 98, 2, 0x0030, 0x10, 3, 1), ++ PIN_FIELD_BASE(99, 99, 2, 0x0030, 0x10, 0, 1), ++ PIN_FIELD_BASE(100, 100, 2, 0x0030, 0x10, 1, 1), ++ PIN_FIELD_BASE(101, 101, 2, 0x0030, 0x10, 4, 1), ++ PIN_FIELD_BASE(102, 102, 2, 0x0030, 0x10, 5, 1), ++ PIN_FIELD_BASE(103, 103, 2, 0x0030, 0x10, 21, 1), ++ PIN_FIELD_BASE(104, 104, 2, 0x0030, 0x10, 23, 1), ++ PIN_FIELD_BASE(105, 105, 2, 0x0030, 0x10, 22, 1), ++ PIN_FIELD_BASE(106, 106, 2, 0x0030, 0x10, 24, 1), ++ PIN_FIELD_BASE(107, 107, 1, 0x0030, 0x10, 4, 1), ++ PIN_FIELD_BASE(108, 108, 1, 0x0030, 0x10, 3, 1), ++ PIN_FIELD_BASE(109, 109, 1, 0x0030, 0x10, 5, 1), ++ PIN_FIELD_BASE(110, 110, 1, 0x0030, 0x10, 0, 1), ++ PIN_FIELD_BASE(111, 111, 1, 0x0030, 0x10, 1, 1), ++ PIN_FIELD_BASE(112, 112, 1, 0x0030, 0x10, 2, 1), ++ PIN_FIELD_BASE(113, 113, 1, 0x0030, 0x10, 9, 1), ++ PIN_FIELD_BASE(114, 114, 1, 0x0030, 0x10, 10, 1), ++ PIN_FIELD_BASE(115, 115, 1, 0x0030, 0x10, 6, 1), ++ PIN_FIELD_BASE(116, 116, 1, 0x0030, 0x10, 7, 1), ++ PIN_FIELD_BASE(117, 117, 1, 0x0030, 0x10, 12, 1), ++ PIN_FIELD_BASE(118, 118, 1, 0x0030, 0x10, 13, 1), ++ PIN_FIELD_BASE(119, 119, 1, 0x0030, 0x10, 14, 1), ++ PIN_FIELD_BASE(120, 120, 1, 0x0030, 0x10, 11, 1), ++ PIN_FIELD_BASE(121, 121, 1, 0x0030, 0x10, 8, 1), ++ PIN_FIELD_BASE(122, 122, 4, 0x0010, 0x10, 9, 1), ++ PIN_FIELD_BASE(123, 123, 4, 0x0010, 0x10, 10, 1), ++ PIN_FIELD_BASE(124, 124, 4, 0x0010, 0x10, 8, 1), ++ PIN_FIELD_BASE(125, 125, 4, 0x0010, 0x10, 12, 1), ++ PIN_FIELD_BASE(126, 126, 4, 0x0010, 0x10, 14, 1), ++ PIN_FIELD_BASE(127, 127, 4, 0x0010, 0x10, 16, 1), ++ PIN_FIELD_BASE(128, 128, 4, 0x0010, 0x10, 11, 1), ++ PIN_FIELD_BASE(129, 129, 4, 0x0010, 0x10, 15, 1), ++ PIN_FIELD_BASE(130, 130, 4, 0x0010, 0x10, 17, 1), ++ PIN_FIELD_BASE(131, 131, 4, 0x0010, 0x10, 18, 1), ++ PIN_FIELD_BASE(132, 132, 4, 0x0010, 0x10, 13, 1), ++ PIN_FIELD_BASE(133, 133, 4, 0x0010, 0x10, 19, 1), ++ PIN_FIELD_BASE(134, 134, 5, 0x0020, 0x10, 14, 1), ++ PIN_FIELD_BASE(135, 135, 5, 0x0020, 0x10, 17, 1), ++ PIN_FIELD_BASE(136, 136, 5, 0x0020, 0x10, 1, 1), ++ PIN_FIELD_BASE(137, 137, 5, 0x0020, 0x10, 7, 1), ++ PIN_FIELD_BASE(138, 138, 5, 0x0020, 0x10, 4, 1), ++ PIN_FIELD_BASE(139, 139, 5, 0x0020, 0x10, 5, 1), ++ PIN_FIELD_BASE(140, 140, 5, 0x0020, 0x10, 0, 1), ++ PIN_FIELD_BASE(141, 141, 5, 0x0020, 0x10, 6, 1), ++ PIN_FIELD_BASE(142, 142, 5, 0x0020, 0x10, 2, 1), ++ PIN_FIELD_BASE(143, 143, 5, 0x0020, 0x10, 3, 1), ++ PIN_FIELD_BASE(144, 144, 5, 0x0020, 0x10, 12, 1), ++ PIN_FIELD_BASE(145, 145, 5, 0x0020, 0x10, 11, 1), ++ PIN_FIELD_BASE(146, 146, 5, 0x0020, 0x10, 13, 1), ++ PIN_FIELD_BASE(147, 147, 5, 0x0020, 0x10, 10, 1), ++ PIN_FIELD_BASE(148, 148, 5, 0x0020, 0x10, 15, 1), ++ PIN_FIELD_BASE(149, 149, 5, 0x0020, 0x10, 16, 1), ++ PIN_FIELD_BASE(150, 150, 7, 0x0040, 0x10, 23, 1), ++ PIN_FIELD_BASE(151, 151, 7, 0x0040, 0x10, 24, 1), ++ PIN_FIELD_BASE(152, 152, 7, 0x0040, 0x10, 25, 1), ++ PIN_FIELD_BASE(153, 153, 7, 0x0040, 0x10, 26, 1), ++ PIN_FIELD_BASE(154, 154, 7, 0x0040, 0x10, 28, 1), ++ PIN_FIELD_BASE(155, 155, 3, 0x0030, 0x10, 28, 1), ++ PIN_FIELD_BASE(156, 156, 3, 0x0030, 0x10, 27, 1), ++ PIN_FIELD_BASE(157, 157, 3, 0x0030, 0x10, 29, 1), ++ PIN_FIELD_BASE(158, 158, 3, 0x0030, 0x10, 26, 1), ++ PIN_FIELD_BASE(159, 159, 7, 0x0040, 0x10, 27, 1), ++ PIN_FIELD_BASE(160, 160, 5, 0x0020, 0x10, 8, 1), ++ PIN_FIELD_BASE(161, 161, 1, 0x0030, 0x10, 15, 1), ++ PIN_FIELD_BASE(162, 162, 1, 0x0030, 0x10, 16, 1), ++ PIN_FIELD_BASE(163, 163, 4, 0x0010, 0x10, 0, 1), ++ PIN_FIELD_BASE(164, 164, 4, 0x0010, 0x10, 1, 1), ++ PIN_FIELD_BASE(165, 165, 4, 0x0010, 0x10, 2, 1), ++ PIN_FIELD_BASE(166, 166, 4, 0x0010, 0x10, 3, 1), ++ PIN_FIELD_BASE(167, 167, 4, 0x0010, 0x10, 4, 1), ++ PIN_FIELD_BASE(168, 168, 4, 0x0010, 0x10, 5, 1), ++ PIN_FIELD_BASE(169, 169, 4, 0x0010, 0x10, 6, 1), ++ PIN_FIELD_BASE(170, 170, 4, 0x0010, 0x10, 7, 1), ++ PIN_FIELD_BASE(171, 171, 7, 0x0040, 0x10, 17, 1), ++ PIN_FIELD_BASE(172, 172, 7, 0x0040, 0x10, 18, 1), ++ PIN_FIELD_BASE(173, 173, 7, 0x0040, 0x10, 11, 1), ++ PIN_FIELD_BASE(174, 174, 7, 0x0040, 0x10, 12, 1), ++ PIN_FIELD_BASE(175, 175, 7, 0x0040, 0x10, 13, 1), ++ PIN_FIELD_BASE(176, 176, 7, 0x0040, 0x10, 14, 1), ++ PIN_FIELD_BASE(177, 177, 7, 0x0040, 0x10, 15, 1), ++ PINS_FIELD_BASE(178, 179, 7, 0x0040, 0x10, 16, 1), ++}; ++ ++static const struct mtk_pin_reg_calc mt6765_reg_cals[PINCTRL_PIN_REG_MAX] = { ++ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6765_pin_mode_range), ++ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6765_pin_dir_range), ++ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6765_pin_di_range), ++ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6765_pin_do_range), ++ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6765_pin_smt_range), ++ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt6765_pin_pd_range), ++ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt6765_pin_pu_range), ++ [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt6765_pin_tdsel_range), ++ [PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt6765_pin_rdsel_range), ++ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6765_pin_drv_range), ++ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt6765_pin_pupd_range), ++ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6765_pin_r0_range), ++ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6765_pin_r1_range), ++ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6765_pin_ies_range), ++}; ++ ++static const char * const mt6765_pinctrl_register_base_names[] = { ++ "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4", "iocfg5", ++ "iocfg6", "iocfg7", ++}; ++ ++static const struct mtk_eint_hw mt6765_eint_hw = { ++ .port_mask = 7, ++ .ports = 6, ++ .ap_num = 160, ++ .db_cnt = 13, ++}; ++ ++static const struct mtk_pin_soc mt6765_data = { ++ .reg_cal = mt6765_reg_cals, ++ .pins = mtk_pins_mt6765, ++ .npins = ARRAY_SIZE(mtk_pins_mt6765), ++ .ngrps = ARRAY_SIZE(mtk_pins_mt6765), ++ .eint_hw = &mt6765_eint_hw, ++ .gpio_m = 0, ++ .ies_present = true, ++ .base_names = mt6765_pinctrl_register_base_names, ++ .nbase_names = ARRAY_SIZE(mt6765_pinctrl_register_base_names), ++ .bias_disable_set = mtk_pinconf_bias_disable_set, ++ .bias_disable_get = mtk_pinconf_bias_disable_get, ++ .bias_set = mtk_pinconf_bias_set, ++ .bias_get = mtk_pinconf_bias_get, ++ .drive_set = mtk_pinconf_drive_set_rev1, ++ .drive_get = mtk_pinconf_drive_get_rev1, ++ .adv_pull_get = mtk_pinconf_adv_pull_get, ++ .adv_pull_set = mtk_pinconf_adv_pull_set, ++}; ++ ++static const struct of_device_id mt6765_pinctrl_of_match[] = { ++ { .compatible = "mediatek,mt6765-pinctrl", }, ++ { } ++}; ++ ++static int mt6765_pinctrl_probe(struct platform_device *pdev) ++{ ++ return mtk_paris_pinctrl_probe(pdev, &mt6765_data); ++} ++ ++static struct platform_driver mt6765_pinctrl_driver = { ++ .driver = { ++ .name = "mt6765-pinctrl", ++ .of_match_table = mt6765_pinctrl_of_match, ++ }, ++ .probe = mt6765_pinctrl_probe, ++}; ++ ++static int __init mt6765_pinctrl_init(void) ++{ ++ return platform_driver_register(&mt6765_pinctrl_driver); ++} ++arch_initcall(mt6765_pinctrl_init); +diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6797.c b/drivers/pinctrl/mediatek/pinctrl-mt6797.c +new file mode 100644 +index 000000000000..adebe4333ed9 +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mt6797.c +@@ -0,0 +1,82 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Based on pinctrl-mt6765.c ++ * ++ * Copyright (C) 2018 MediaTek Inc. ++ * ++ * Author: ZH Chen <zh.chen@mediatek.com> ++ * ++ * Copyright (C) Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> ++ * ++ */ ++ ++#include "pinctrl-mtk-mt6797.h" ++#include "pinctrl-paris.h" ++ ++/* ++ * MT6797 have multiple bases to program pin configuration listed as the below: ++ * gpio:0x10005000, iocfg[l]:0x10002000, iocfg[b]:0x10002400, ++ * iocfg[r]:0x10002800, iocfg[t]:0x10002C00. ++ * _i_base could be used to indicate what base the pin should be mapped into. ++ */ ++ ++static const struct mtk_pin_field_calc mt6797_pin_mode_range[] = { ++ PIN_FIELD(0, 261, 0x300, 0x10, 0, 4), ++}; ++ ++static const struct mtk_pin_field_calc mt6797_pin_dir_range[] = { ++ PIN_FIELD(0, 261, 0x0, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt6797_pin_di_range[] = { ++ PIN_FIELD(0, 261, 0x200, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt6797_pin_do_range[] = { ++ PIN_FIELD(0, 261, 0x100, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_reg_calc mt6797_reg_cals[PINCTRL_PIN_REG_MAX] = { ++ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6797_pin_mode_range), ++ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6797_pin_dir_range), ++ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6797_pin_di_range), ++ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6797_pin_do_range), ++}; ++ ++static const char * const mt6797_pinctrl_register_base_names[] = { ++ "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt", ++}; ++ ++static const struct mtk_pin_soc mt6797_data = { ++ .reg_cal = mt6797_reg_cals, ++ .pins = mtk_pins_mt6797, ++ .npins = ARRAY_SIZE(mtk_pins_mt6797), ++ .ngrps = ARRAY_SIZE(mtk_pins_mt6797), ++ .gpio_m = 0, ++ .base_names = mt6797_pinctrl_register_base_names, ++ .nbase_names = ARRAY_SIZE(mt6797_pinctrl_register_base_names), ++}; ++ ++static const struct of_device_id mt6797_pinctrl_of_match[] = { ++ { .compatible = "mediatek,mt6797-pinctrl", }, ++ { } ++}; ++ ++static int mt6797_pinctrl_probe(struct platform_device *pdev) ++{ ++ return mtk_paris_pinctrl_probe(pdev, &mt6797_data); ++} ++ ++static struct platform_driver mt6797_pinctrl_driver = { ++ .driver = { ++ .name = "mt6797-pinctrl", ++ .of_match_table = mt6797_pinctrl_of_match, ++ }, ++ .probe = mt6797_pinctrl_probe, ++}; ++ ++static int __init mt6797_pinctrl_init(void) ++{ ++ return platform_driver_register(&mt6797_pinctrl_driver); ++} ++arch_initcall(mt6797_pinctrl_init); +diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c b/drivers/pinctrl/mediatek/pinctrl-mt7622.c +index 6f931b85701b..ce4a8a0cc19c 100644 +--- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c +@@ -1,297 +1,140 @@ ++// SPDX-License-Identifier: GPL-2.0 + /* +- * MediaTek MT7622 Pinctrl Driver ++ * Copyright (C) 2017-2018 MediaTek Inc. + * +- * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> ++ * Author: Sean Wang <sean.wang@mediatek.com> + * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License version 2 as +- * published by the Free Software Foundation. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#include <linux/gpio.h> +-#include <linux/gpio/driver.h> +-#include <linux/io.h> +-#include <linux/init.h> +-#include <linux/mfd/syscon.h> +-#include <linux/of.h> +-#include <linux/of_irq.h> +-#include <linux/of_platform.h> +-#include <linux/platform_device.h> +-#include <linux/pinctrl/pinctrl.h> +-#include <linux/pinctrl/pinmux.h> +-#include <linux/pinctrl/pinconf.h> +-#include <linux/pinctrl/pinconf-generic.h> +-#include <linux/regmap.h> +- +-#include "../core.h" +-#include "../pinconf.h" +-#include "../pinmux.h" +-#include "mtk-eint.h" +- +-#define PINCTRL_PINCTRL_DEV KBUILD_MODNAME +-#define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), } +-#define PINCTRL_PIN_GROUP(name, id) \ +- { \ +- name, \ +- id##_pins, \ +- ARRAY_SIZE(id##_pins), \ +- id##_funcs, \ +- } +- +-#define MTK_GPIO_MODE 1 +-#define MTK_INPUT 0 +-#define MTK_OUTPUT 1 +-#define MTK_DISABLE 0 +-#define MTK_ENABLE 1 +- +-/* Custom pinconf parameters */ +-#define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1) +-#define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2) +- +-/* List these attributes which could be modified for the pin */ +-enum { +- PINCTRL_PIN_REG_MODE, +- PINCTRL_PIN_REG_DIR, +- PINCTRL_PIN_REG_DI, +- PINCTRL_PIN_REG_DO, +- PINCTRL_PIN_REG_SR, +- PINCTRL_PIN_REG_SMT, +- PINCTRL_PIN_REG_PD, +- PINCTRL_PIN_REG_PU, +- PINCTRL_PIN_REG_E4, +- PINCTRL_PIN_REG_E8, +- PINCTRL_PIN_REG_TDSEL, +- PINCTRL_PIN_REG_RDSEL, +- PINCTRL_PIN_REG_MAX, +-}; +- +-/* struct mtk_pin_field - the structure that holds the information of the field +- * used to describe the attribute for the pin +- * @offset: the register offset relative to the base address +- * @mask: the mask used to filter out the field from the register +- * @bitpos: the start bit relative to the register +- * @next: the indication that the field would be extended to the +- next register + */ +-struct mtk_pin_field { +- u32 offset; +- u32 mask; +- u8 bitpos; +- u8 next; +-}; + +-/* struct mtk_pin_field_calc - the structure that holds the range providing +- * the guide used to look up the relevant field +- * @s_pin: the start pin within the range +- * @e_pin: the end pin within the range +- * @s_addr: the start address for the range +- * @x_addrs: the address distance between two consecutive registers +- * within the range +- * @s_bit: the start bit for the first register within the range +- * @x_bits: the bit distance between two consecutive pins within +- * the range +- */ +-struct mtk_pin_field_calc { +- u16 s_pin; +- u16 e_pin; +- u32 s_addr; +- u8 x_addrs; +- u8 s_bit; +- u8 x_bits; +-}; ++#include "pinctrl-moore.h" + +-/* struct mtk_pin_reg_calc - the structure that holds all ranges used to +- * determine which register the pin would make use of +- * for certain pin attribute. +- * @range: the start address for the range +- * @nranges: the number of items in the range +- */ +-struct mtk_pin_reg_calc { +- const struct mtk_pin_field_calc *range; +- unsigned int nranges; +-}; +- +-/* struct mtk_pin_soc - the structure that holds SoC-specific data */ +-struct mtk_pin_soc { +- const struct mtk_pin_reg_calc *reg_cal; +- const struct pinctrl_pin_desc *pins; +- unsigned int npins; +- const struct group_desc *grps; +- unsigned int ngrps; +- const struct function_desc *funcs; +- unsigned int nfuncs; +- const struct mtk_eint_regs *eint_regs; +- const struct mtk_eint_hw *eint_hw; +-}; +- +-struct mtk_pinctrl { +- struct pinctrl_dev *pctrl; +- void __iomem *base; +- struct device *dev; +- struct gpio_chip chip; +- const struct mtk_pin_soc *soc; +- struct mtk_eint *eint; +-}; ++#define MT7622_PIN(_number, _name) \ ++ MTK_PIN(_number, _name, 1, _number, DRV_GRP0) + + static const struct mtk_pin_field_calc mt7622_pin_mode_range[] = { +- {0, 0, 0x320, 0x10, 16, 4}, +- {1, 4, 0x3a0, 0x10, 16, 4}, +- {5, 5, 0x320, 0x10, 0, 4}, +- {6, 6, 0x300, 0x10, 4, 4}, +- {7, 7, 0x300, 0x10, 4, 4}, +- {8, 9, 0x350, 0x10, 20, 4}, +- {10, 10, 0x300, 0x10, 8, 4}, +- {11, 11, 0x300, 0x10, 8, 4}, +- {12, 12, 0x300, 0x10, 8, 4}, +- {13, 13, 0x300, 0x10, 8, 4}, +- {14, 15, 0x320, 0x10, 4, 4}, +- {16, 17, 0x320, 0x10, 20, 4}, +- {18, 21, 0x310, 0x10, 16, 4}, +- {22, 22, 0x380, 0x10, 16, 4}, +- {23, 23, 0x300, 0x10, 24, 4}, +- {24, 24, 0x300, 0x10, 24, 4}, +- {25, 25, 0x300, 0x10, 12, 4}, +- {25, 25, 0x300, 0x10, 12, 4}, +- {26, 26, 0x300, 0x10, 12, 4}, +- {27, 27, 0x300, 0x10, 12, 4}, +- {28, 28, 0x300, 0x10, 12, 4}, +- {29, 29, 0x300, 0x10, 12, 4}, +- {30, 30, 0x300, 0x10, 12, 4}, +- {31, 31, 0x300, 0x10, 12, 4}, +- {32, 32, 0x300, 0x10, 12, 4}, +- {33, 33, 0x300, 0x10, 12, 4}, +- {34, 34, 0x300, 0x10, 12, 4}, +- {35, 35, 0x300, 0x10, 12, 4}, +- {36, 36, 0x300, 0x10, 12, 4}, +- {37, 37, 0x300, 0x10, 20, 4}, +- {38, 38, 0x300, 0x10, 20, 4}, +- {39, 39, 0x300, 0x10, 20, 4}, +- {40, 40, 0x300, 0x10, 20, 4}, +- {41, 41, 0x300, 0x10, 20, 4}, +- {42, 42, 0x300, 0x10, 20, 4}, +- {43, 43, 0x300, 0x10, 20, 4}, +- {44, 44, 0x300, 0x10, 20, 4}, +- {45, 46, 0x300, 0x10, 20, 4}, +- {47, 47, 0x300, 0x10, 20, 4}, +- {48, 48, 0x300, 0x10, 20, 4}, +- {49, 49, 0x300, 0x10, 20, 4}, +- {50, 50, 0x300, 0x10, 20, 4}, +- {51, 70, 0x330, 0x10, 4, 4}, +- {71, 71, 0x300, 0x10, 16, 4}, +- {72, 72, 0x300, 0x10, 16, 4}, +- {73, 76, 0x310, 0x10, 0, 4}, +- {77, 77, 0x320, 0x10, 28, 4}, +- {78, 78, 0x320, 0x10, 12, 4}, +- {79, 82, 0x3a0, 0x10, 0, 4}, +- {83, 83, 0x350, 0x10, 28, 4}, +- {84, 84, 0x330, 0x10, 0, 4}, +- {85, 90, 0x360, 0x10, 4, 4}, +- {91, 94, 0x390, 0x10, 16, 4}, +- {95, 97, 0x380, 0x10, 20, 4}, +- {98, 101, 0x390, 0x10, 0, 4}, +- {102, 102, 0x360, 0x10, 0, 4}, ++ PIN_FIELD(0, 0, 0x320, 0x10, 16, 4), ++ PIN_FIELD(1, 4, 0x3a0, 0x10, 16, 4), ++ PIN_FIELD(5, 5, 0x320, 0x10, 0, 4), ++ PINS_FIELD(6, 7, 0x300, 0x10, 4, 4), ++ PIN_FIELD(8, 9, 0x350, 0x10, 20, 4), ++ PINS_FIELD(10, 13, 0x300, 0x10, 8, 4), ++ PIN_FIELD(14, 15, 0x320, 0x10, 4, 4), ++ PIN_FIELD(16, 17, 0x320, 0x10, 20, 4), ++ PIN_FIELD(18, 21, 0x310, 0x10, 16, 4), ++ PIN_FIELD(22, 22, 0x380, 0x10, 16, 4), ++ PINS_FIELD(23, 24, 0x300, 0x10, 24, 4), ++ PINS_FIELD(25, 36, 0x300, 0x10, 12, 4), ++ PINS_FIELD(37, 50, 0x300, 0x10, 20, 4), ++ PIN_FIELD(51, 70, 0x330, 0x10, 4, 4), ++ PINS_FIELD(71, 72, 0x300, 0x10, 16, 4), ++ PIN_FIELD(73, 76, 0x310, 0x10, 0, 4), ++ PIN_FIELD(77, 77, 0x320, 0x10, 28, 4), ++ PIN_FIELD(78, 78, 0x320, 0x10, 12, 4), ++ PIN_FIELD(79, 82, 0x3a0, 0x10, 0, 4), ++ PIN_FIELD(83, 83, 0x350, 0x10, 28, 4), ++ PIN_FIELD(84, 84, 0x330, 0x10, 0, 4), ++ PIN_FIELD(85, 90, 0x360, 0x10, 4, 4), ++ PIN_FIELD(91, 94, 0x390, 0x10, 16, 4), ++ PIN_FIELD(95, 97, 0x380, 0x10, 20, 4), ++ PIN_FIELD(98, 101, 0x390, 0x10, 0, 4), ++ PIN_FIELD(102, 102, 0x360, 0x10, 0, 4), + }; + + static const struct mtk_pin_field_calc mt7622_pin_dir_range[] = { +- {0, 102, 0x0, 0x10, 0, 1}, ++ PIN_FIELD(0, 102, 0x0, 0x10, 0, 1), + }; + + static const struct mtk_pin_field_calc mt7622_pin_di_range[] = { +- {0, 102, 0x200, 0x10, 0, 1}, ++ PIN_FIELD(0, 102, 0x200, 0x10, 0, 1), + }; + + static const struct mtk_pin_field_calc mt7622_pin_do_range[] = { +- {0, 102, 0x100, 0x10, 0, 1}, ++ PIN_FIELD(0, 102, 0x100, 0x10, 0, 1), + }; + + static const struct mtk_pin_field_calc mt7622_pin_sr_range[] = { +- {0, 31, 0x910, 0x10, 0, 1}, +- {32, 50, 0xa10, 0x10, 0, 1}, +- {51, 70, 0x810, 0x10, 0, 1}, +- {71, 72, 0xb10, 0x10, 0, 1}, +- {73, 86, 0xb10, 0x10, 4, 1}, +- {87, 90, 0xc10, 0x10, 0, 1}, +- {91, 102, 0xb10, 0x10, 18, 1}, ++ PIN_FIELD(0, 31, 0x910, 0x10, 0, 1), ++ PIN_FIELD(32, 50, 0xa10, 0x10, 0, 1), ++ PIN_FIELD(51, 70, 0x810, 0x10, 0, 1), ++ PIN_FIELD(71, 72, 0xb10, 0x10, 0, 1), ++ PIN_FIELD(73, 86, 0xb10, 0x10, 4, 1), ++ PIN_FIELD(87, 90, 0xc10, 0x10, 0, 1), ++ PIN_FIELD(91, 102, 0xb10, 0x10, 18, 1), + }; + + static const struct mtk_pin_field_calc mt7622_pin_smt_range[] = { +- {0, 31, 0x920, 0x10, 0, 1}, +- {32, 50, 0xa20, 0x10, 0, 1}, +- {51, 70, 0x820, 0x10, 0, 1}, +- {71, 72, 0xb20, 0x10, 0, 1}, +- {73, 86, 0xb20, 0x10, 4, 1}, +- {87, 90, 0xc20, 0x10, 0, 1}, +- {91, 102, 0xb20, 0x10, 18, 1}, ++ PIN_FIELD(0, 31, 0x920, 0x10, 0, 1), ++ PIN_FIELD(32, 50, 0xa20, 0x10, 0, 1), ++ PIN_FIELD(51, 70, 0x820, 0x10, 0, 1), ++ PIN_FIELD(71, 72, 0xb20, 0x10, 0, 1), ++ PIN_FIELD(73, 86, 0xb20, 0x10, 4, 1), ++ PIN_FIELD(87, 90, 0xc20, 0x10, 0, 1), ++ PIN_FIELD(91, 102, 0xb20, 0x10, 18, 1), + }; + + static const struct mtk_pin_field_calc mt7622_pin_pu_range[] = { +- {0, 31, 0x930, 0x10, 0, 1}, +- {32, 50, 0xa30, 0x10, 0, 1}, +- {51, 70, 0x830, 0x10, 0, 1}, +- {71, 72, 0xb30, 0x10, 0, 1}, +- {73, 86, 0xb30, 0x10, 4, 1}, +- {87, 90, 0xc30, 0x10, 0, 1}, +- {91, 102, 0xb30, 0x10, 18, 1}, ++ PIN_FIELD(0, 31, 0x930, 0x10, 0, 1), ++ PIN_FIELD(32, 50, 0xa30, 0x10, 0, 1), ++ PIN_FIELD(51, 70, 0x830, 0x10, 0, 1), ++ PIN_FIELD(71, 72, 0xb30, 0x10, 0, 1), ++ PIN_FIELD(73, 86, 0xb30, 0x10, 4, 1), ++ PIN_FIELD(87, 90, 0xc30, 0x10, 0, 1), ++ PIN_FIELD(91, 102, 0xb30, 0x10, 18, 1), + }; + + static const struct mtk_pin_field_calc mt7622_pin_pd_range[] = { +- {0, 31, 0x940, 0x10, 0, 1}, +- {32, 50, 0xa40, 0x10, 0, 1}, +- {51, 70, 0x840, 0x10, 0, 1}, +- {71, 72, 0xb40, 0x10, 0, 1}, +- {73, 86, 0xb40, 0x10, 4, 1}, +- {87, 90, 0xc40, 0x10, 0, 1}, +- {91, 102, 0xb40, 0x10, 18, 1}, ++ PIN_FIELD(0, 31, 0x940, 0x10, 0, 1), ++ PIN_FIELD(32, 50, 0xa40, 0x10, 0, 1), ++ PIN_FIELD(51, 70, 0x840, 0x10, 0, 1), ++ PIN_FIELD(71, 72, 0xb40, 0x10, 0, 1), ++ PIN_FIELD(73, 86, 0xb40, 0x10, 4, 1), ++ PIN_FIELD(87, 90, 0xc40, 0x10, 0, 1), ++ PIN_FIELD(91, 102, 0xb40, 0x10, 18, 1), + }; + + static const struct mtk_pin_field_calc mt7622_pin_e4_range[] = { +- {0, 31, 0x960, 0x10, 0, 1}, +- {32, 50, 0xa60, 0x10, 0, 1}, +- {51, 70, 0x860, 0x10, 0, 1}, +- {71, 72, 0xb60, 0x10, 0, 1}, +- {73, 86, 0xb60, 0x10, 4, 1}, +- {87, 90, 0xc60, 0x10, 0, 1}, +- {91, 102, 0xb60, 0x10, 18, 1}, ++ PIN_FIELD(0, 31, 0x960, 0x10, 0, 1), ++ PIN_FIELD(32, 50, 0xa60, 0x10, 0, 1), ++ PIN_FIELD(51, 70, 0x860, 0x10, 0, 1), ++ PIN_FIELD(71, 72, 0xb60, 0x10, 0, 1), ++ PIN_FIELD(73, 86, 0xb60, 0x10, 4, 1), ++ PIN_FIELD(87, 90, 0xc60, 0x10, 0, 1), ++ PIN_FIELD(91, 102, 0xb60, 0x10, 18, 1), + }; + + static const struct mtk_pin_field_calc mt7622_pin_e8_range[] = { +- {0, 31, 0x970, 0x10, 0, 1}, +- {32, 50, 0xa70, 0x10, 0, 1}, +- {51, 70, 0x870, 0x10, 0, 1}, +- {71, 72, 0xb70, 0x10, 0, 1}, +- {73, 86, 0xb70, 0x10, 4, 1}, +- {87, 90, 0xc70, 0x10, 0, 1}, +- {91, 102, 0xb70, 0x10, 18, 1}, ++ PIN_FIELD(0, 31, 0x970, 0x10, 0, 1), ++ PIN_FIELD(32, 50, 0xa70, 0x10, 0, 1), ++ PIN_FIELD(51, 70, 0x870, 0x10, 0, 1), ++ PIN_FIELD(71, 72, 0xb70, 0x10, 0, 1), ++ PIN_FIELD(73, 86, 0xb70, 0x10, 4, 1), ++ PIN_FIELD(87, 90, 0xc70, 0x10, 0, 1), ++ PIN_FIELD(91, 102, 0xb70, 0x10, 18, 1), + }; + + static const struct mtk_pin_field_calc mt7622_pin_tdsel_range[] = { +- {0, 31, 0x980, 0x4, 0, 4}, +- {32, 50, 0xa80, 0x4, 0, 4}, +- {51, 70, 0x880, 0x4, 0, 4}, +- {71, 72, 0xb80, 0x4, 0, 4}, +- {73, 86, 0xb80, 0x4, 16, 4}, +- {87, 90, 0xc80, 0x4, 0, 4}, +- {91, 102, 0xb88, 0x4, 8, 4}, ++ PIN_FIELD(0, 31, 0x980, 0x4, 0, 4), ++ PIN_FIELD(32, 50, 0xa80, 0x4, 0, 4), ++ PIN_FIELD(51, 70, 0x880, 0x4, 0, 4), ++ PIN_FIELD(71, 72, 0xb80, 0x4, 0, 4), ++ PIN_FIELD(73, 86, 0xb80, 0x4, 16, 4), ++ PIN_FIELD(87, 90, 0xc80, 0x4, 0, 4), ++ PIN_FIELD(91, 102, 0xb88, 0x4, 8, 4), + }; + + static const struct mtk_pin_field_calc mt7622_pin_rdsel_range[] = { +- {0, 31, 0x990, 0x4, 0, 6}, +- {32, 50, 0xa90, 0x4, 0, 6}, +- {51, 58, 0x890, 0x4, 0, 6}, +- {59, 60, 0x894, 0x4, 28, 6}, +- {61, 62, 0x894, 0x4, 16, 6}, +- {63, 66, 0x898, 0x4, 8, 6}, +- {67, 68, 0x89c, 0x4, 12, 6}, +- {69, 70, 0x89c, 0x4, 0, 6}, +- {71, 72, 0xb90, 0x4, 0, 6}, +- {73, 86, 0xb90, 0x4, 24, 6}, +- {87, 90, 0xc90, 0x4, 0, 6}, +- {91, 102, 0xb9c, 0x4, 12, 6}, ++ PIN_FIELD(0, 31, 0x990, 0x4, 0, 6), ++ PIN_FIELD(32, 50, 0xa90, 0x4, 0, 6), ++ PIN_FIELD(51, 58, 0x890, 0x4, 0, 6), ++ PIN_FIELD(59, 60, 0x894, 0x4, 28, 6), ++ PIN_FIELD(61, 62, 0x894, 0x4, 16, 6), ++ PIN_FIELD(63, 66, 0x898, 0x4, 8, 6), ++ PIN_FIELD(67, 68, 0x89c, 0x4, 12, 6), ++ PIN_FIELD(69, 70, 0x89c, 0x4, 0, 6), ++ PIN_FIELD(71, 72, 0xb90, 0x4, 0, 6), ++ PIN_FIELD(73, 86, 0xb90, 0x4, 24, 6), ++ PIN_FIELD(87, 90, 0xc90, 0x4, 0, 6), ++ PIN_FIELD(91, 102, 0xb9c, 0x4, 12, 6), + }; + + static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = { +@@ -309,110 +152,110 @@ static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt7622_pin_rdsel_range), + }; + +-static const struct pinctrl_pin_desc mt7622_pins[] = { +- PINCTRL_PIN(0, "GPIO_A"), +- PINCTRL_PIN(1, "I2S1_IN"), +- PINCTRL_PIN(2, "I2S1_OUT"), +- PINCTRL_PIN(3, "I2S_BCLK"), +- PINCTRL_PIN(4, "I2S_WS"), +- PINCTRL_PIN(5, "I2S_MCLK"), +- PINCTRL_PIN(6, "TXD0"), +- PINCTRL_PIN(7, "RXD0"), +- PINCTRL_PIN(8, "SPI_WP"), +- PINCTRL_PIN(9, "SPI_HOLD"), +- PINCTRL_PIN(10, "SPI_CLK"), +- PINCTRL_PIN(11, "SPI_MOSI"), +- PINCTRL_PIN(12, "SPI_MISO"), +- PINCTRL_PIN(13, "SPI_CS"), +- PINCTRL_PIN(14, "I2C_SDA"), +- PINCTRL_PIN(15, "I2C_SCL"), +- PINCTRL_PIN(16, "I2S2_IN"), +- PINCTRL_PIN(17, "I2S3_IN"), +- PINCTRL_PIN(18, "I2S4_IN"), +- PINCTRL_PIN(19, "I2S2_OUT"), +- PINCTRL_PIN(20, "I2S3_OUT"), +- PINCTRL_PIN(21, "I2S4_OUT"), +- PINCTRL_PIN(22, "GPIO_B"), +- PINCTRL_PIN(23, "MDC"), +- PINCTRL_PIN(24, "MDIO"), +- PINCTRL_PIN(25, "G2_TXD0"), +- PINCTRL_PIN(26, "G2_TXD1"), +- PINCTRL_PIN(27, "G2_TXD2"), +- PINCTRL_PIN(28, "G2_TXD3"), +- PINCTRL_PIN(29, "G2_TXEN"), +- PINCTRL_PIN(30, "G2_TXC"), +- PINCTRL_PIN(31, "G2_RXD0"), +- PINCTRL_PIN(32, "G2_RXD1"), +- PINCTRL_PIN(33, "G2_RXD2"), +- PINCTRL_PIN(34, "G2_RXD3"), +- PINCTRL_PIN(35, "G2_RXDV"), +- PINCTRL_PIN(36, "G2_RXC"), +- PINCTRL_PIN(37, "NCEB"), +- PINCTRL_PIN(38, "NWEB"), +- PINCTRL_PIN(39, "NREB"), +- PINCTRL_PIN(40, "NDL4"), +- PINCTRL_PIN(41, "NDL5"), +- PINCTRL_PIN(42, "NDL6"), +- PINCTRL_PIN(43, "NDL7"), +- PINCTRL_PIN(44, "NRB"), +- PINCTRL_PIN(45, "NCLE"), +- PINCTRL_PIN(46, "NALE"), +- PINCTRL_PIN(47, "NDL0"), +- PINCTRL_PIN(48, "NDL1"), +- PINCTRL_PIN(49, "NDL2"), +- PINCTRL_PIN(50, "NDL3"), +- PINCTRL_PIN(51, "MDI_TP_P0"), +- PINCTRL_PIN(52, "MDI_TN_P0"), +- PINCTRL_PIN(53, "MDI_RP_P0"), +- PINCTRL_PIN(54, "MDI_RN_P0"), +- PINCTRL_PIN(55, "MDI_TP_P1"), +- PINCTRL_PIN(56, "MDI_TN_P1"), +- PINCTRL_PIN(57, "MDI_RP_P1"), +- PINCTRL_PIN(58, "MDI_RN_P1"), +- PINCTRL_PIN(59, "MDI_RP_P2"), +- PINCTRL_PIN(60, "MDI_RN_P2"), +- PINCTRL_PIN(61, "MDI_TP_P2"), +- PINCTRL_PIN(62, "MDI_TN_P2"), +- PINCTRL_PIN(63, "MDI_TP_P3"), +- PINCTRL_PIN(64, "MDI_TN_P3"), +- PINCTRL_PIN(65, "MDI_RP_P3"), +- PINCTRL_PIN(66, "MDI_RN_P3"), +- PINCTRL_PIN(67, "MDI_RP_P4"), +- PINCTRL_PIN(68, "MDI_RN_P4"), +- PINCTRL_PIN(69, "MDI_TP_P4"), +- PINCTRL_PIN(70, "MDI_TN_P4"), +- PINCTRL_PIN(71, "PMIC_SCL"), +- PINCTRL_PIN(72, "PMIC_SDA"), +- PINCTRL_PIN(73, "SPIC1_CLK"), +- PINCTRL_PIN(74, "SPIC1_MOSI"), +- PINCTRL_PIN(75, "SPIC1_MISO"), +- PINCTRL_PIN(76, "SPIC1_CS"), +- PINCTRL_PIN(77, "GPIO_D"), +- PINCTRL_PIN(78, "WATCHDOG"), +- PINCTRL_PIN(79, "RTS3_N"), +- PINCTRL_PIN(80, "CTS3_N"), +- PINCTRL_PIN(81, "TXD3"), +- PINCTRL_PIN(82, "RXD3"), +- PINCTRL_PIN(83, "PERST0_N"), +- PINCTRL_PIN(84, "PERST1_N"), +- PINCTRL_PIN(85, "WLED_N"), +- PINCTRL_PIN(86, "EPHY_LED0_N"), +- PINCTRL_PIN(87, "AUXIN0"), +- PINCTRL_PIN(88, "AUXIN1"), +- PINCTRL_PIN(89, "AUXIN2"), +- PINCTRL_PIN(90, "AUXIN3"), +- PINCTRL_PIN(91, "TXD4"), +- PINCTRL_PIN(92, "RXD4"), +- PINCTRL_PIN(93, "RTS4_N"), +- PINCTRL_PIN(94, "CTS4_N"), +- PINCTRL_PIN(95, "PWM1"), +- PINCTRL_PIN(96, "PWM2"), +- PINCTRL_PIN(97, "PWM3"), +- PINCTRL_PIN(98, "PWM4"), +- PINCTRL_PIN(99, "PWM5"), +- PINCTRL_PIN(100, "PWM6"), +- PINCTRL_PIN(101, "PWM7"), +- PINCTRL_PIN(102, "GPIO_E"), ++static const struct mtk_pin_desc mt7622_pins[] = { ++ MT7622_PIN(0, "GPIO_A"), ++ MT7622_PIN(1, "I2S1_IN"), ++ MT7622_PIN(2, "I2S1_OUT"), ++ MT7622_PIN(3, "I2S_BCLK"), ++ MT7622_PIN(4, "I2S_WS"), ++ MT7622_PIN(5, "I2S_MCLK"), ++ MT7622_PIN(6, "TXD0"), ++ MT7622_PIN(7, "RXD0"), ++ MT7622_PIN(8, "SPI_WP"), ++ MT7622_PIN(9, "SPI_HOLD"), ++ MT7622_PIN(10, "SPI_CLK"), ++ MT7622_PIN(11, "SPI_MOSI"), ++ MT7622_PIN(12, "SPI_MISO"), ++ MT7622_PIN(13, "SPI_CS"), ++ MT7622_PIN(14, "I2C_SDA"), ++ MT7622_PIN(15, "I2C_SCL"), ++ MT7622_PIN(16, "I2S2_IN"), ++ MT7622_PIN(17, "I2S3_IN"), ++ MT7622_PIN(18, "I2S4_IN"), ++ MT7622_PIN(19, "I2S2_OUT"), ++ MT7622_PIN(20, "I2S3_OUT"), ++ MT7622_PIN(21, "I2S4_OUT"), ++ MT7622_PIN(22, "GPIO_B"), ++ MT7622_PIN(23, "MDC"), ++ MT7622_PIN(24, "MDIO"), ++ MT7622_PIN(25, "G2_TXD0"), ++ MT7622_PIN(26, "G2_TXD1"), ++ MT7622_PIN(27, "G2_TXD2"), ++ MT7622_PIN(28, "G2_TXD3"), ++ MT7622_PIN(29, "G2_TXEN"), ++ MT7622_PIN(30, "G2_TXC"), ++ MT7622_PIN(31, "G2_RXD0"), ++ MT7622_PIN(32, "G2_RXD1"), ++ MT7622_PIN(33, "G2_RXD2"), ++ MT7622_PIN(34, "G2_RXD3"), ++ MT7622_PIN(35, "G2_RXDV"), ++ MT7622_PIN(36, "G2_RXC"), ++ MT7622_PIN(37, "NCEB"), ++ MT7622_PIN(38, "NWEB"), ++ MT7622_PIN(39, "NREB"), ++ MT7622_PIN(40, "NDL4"), ++ MT7622_PIN(41, "NDL5"), ++ MT7622_PIN(42, "NDL6"), ++ MT7622_PIN(43, "NDL7"), ++ MT7622_PIN(44, "NRB"), ++ MT7622_PIN(45, "NCLE"), ++ MT7622_PIN(46, "NALE"), ++ MT7622_PIN(47, "NDL0"), ++ MT7622_PIN(48, "NDL1"), ++ MT7622_PIN(49, "NDL2"), ++ MT7622_PIN(50, "NDL3"), ++ MT7622_PIN(51, "MDI_TP_P0"), ++ MT7622_PIN(52, "MDI_TN_P0"), ++ MT7622_PIN(53, "MDI_RP_P0"), ++ MT7622_PIN(54, "MDI_RN_P0"), ++ MT7622_PIN(55, "MDI_TP_P1"), ++ MT7622_PIN(56, "MDI_TN_P1"), ++ MT7622_PIN(57, "MDI_RP_P1"), ++ MT7622_PIN(58, "MDI_RN_P1"), ++ MT7622_PIN(59, "MDI_RP_P2"), ++ MT7622_PIN(60, "MDI_RN_P2"), ++ MT7622_PIN(61, "MDI_TP_P2"), ++ MT7622_PIN(62, "MDI_TN_P2"), ++ MT7622_PIN(63, "MDI_TP_P3"), ++ MT7622_PIN(64, "MDI_TN_P3"), ++ MT7622_PIN(65, "MDI_RP_P3"), ++ MT7622_PIN(66, "MDI_RN_P3"), ++ MT7622_PIN(67, "MDI_RP_P4"), ++ MT7622_PIN(68, "MDI_RN_P4"), ++ MT7622_PIN(69, "MDI_TP_P4"), ++ MT7622_PIN(70, "MDI_TN_P4"), ++ MT7622_PIN(71, "PMIC_SCL"), ++ MT7622_PIN(72, "PMIC_SDA"), ++ MT7622_PIN(73, "SPIC1_CLK"), ++ MT7622_PIN(74, "SPIC1_MOSI"), ++ MT7622_PIN(75, "SPIC1_MISO"), ++ MT7622_PIN(76, "SPIC1_CS"), ++ MT7622_PIN(77, "GPIO_D"), ++ MT7622_PIN(78, "WATCHDOG"), ++ MT7622_PIN(79, "RTS3_N"), ++ MT7622_PIN(80, "CTS3_N"), ++ MT7622_PIN(81, "TXD3"), ++ MT7622_PIN(82, "RXD3"), ++ MT7622_PIN(83, "PERST0_N"), ++ MT7622_PIN(84, "PERST1_N"), ++ MT7622_PIN(85, "WLED_N"), ++ MT7622_PIN(86, "EPHY_LED0_N"), ++ MT7622_PIN(87, "AUXIN0"), ++ MT7622_PIN(88, "AUXIN1"), ++ MT7622_PIN(89, "AUXIN2"), ++ MT7622_PIN(90, "AUXIN3"), ++ MT7622_PIN(91, "TXD4"), ++ MT7622_PIN(92, "RXD4"), ++ MT7622_PIN(93, "RTS4_N"), ++ MT7622_PIN(94, "CTS4_N"), ++ MT7622_PIN(95, "PWM1"), ++ MT7622_PIN(96, "PWM2"), ++ MT7622_PIN(97, "PWM3"), ++ MT7622_PIN(98, "PWM4"), ++ MT7622_PIN(99, "PWM5"), ++ MT7622_PIN(100, "PWM6"), ++ MT7622_PIN(101, "PWM7"), ++ MT7622_PIN(102, "GPIO_E"), + }; + + /* List all groups consisting of these pins dedicated to the enablement of +@@ -906,18 +749,6 @@ static const struct function_desc mt7622_functions[] = { + {"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)}, + }; + +-static const struct pinconf_generic_params mtk_custom_bindings[] = { +- {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0}, +- {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0}, +-}; +- +-#ifdef CONFIG_DEBUG_FS +-static const struct pin_config_item mtk_conf_items[] = { +- PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true), +- PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true), +-}; +-#endif +- + static const struct mtk_eint_hw mt7622_eint_hw = { + .port_mask = 7, + .ports = 7, +@@ -934,830 +765,38 @@ static const struct mtk_pin_soc mt7622_data = { + .funcs = mt7622_functions, + .nfuncs = ARRAY_SIZE(mt7622_functions), + .eint_hw = &mt7622_eint_hw, +-}; +- +-static void mtk_w32(struct mtk_pinctrl *pctl, u32 reg, u32 val) +-{ +- writel_relaxed(val, pctl->base + reg); +-} +- +-static u32 mtk_r32(struct mtk_pinctrl *pctl, u32 reg) +-{ +- return readl_relaxed(pctl->base + reg); +-} +- +-static void mtk_rmw(struct mtk_pinctrl *pctl, u32 reg, u32 mask, u32 set) +-{ +- u32 val; +- +- val = mtk_r32(pctl, reg); +- val &= ~mask; +- val |= set; +- mtk_w32(pctl, reg, val); +-} +- +-static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, int pin, +- const struct mtk_pin_reg_calc *rc, +- struct mtk_pin_field *pfd) +-{ +- const struct mtk_pin_field_calc *c, *e; +- u32 bits; +- +- c = rc->range; +- e = c + rc->nranges; +- +- while (c < e) { +- if (pin >= c->s_pin && pin <= c->e_pin) +- break; +- c++; +- } +- +- if (c >= e) { +- dev_err(hw->dev, "Out of range for pin = %d\n", pin); +- return -EINVAL; +- } +- +- /* Caculated bits as the overall offset the pin is located at */ +- bits = c->s_bit + (pin - c->s_pin) * (c->x_bits); +- +- /* Fill pfd from bits and 32-bit register applied is assumed */ +- pfd->offset = c->s_addr + c->x_addrs * (bits / 32); +- pfd->bitpos = bits % 32; +- pfd->mask = (1 << c->x_bits) - 1; +- +- /* pfd->next is used for indicating that bit wrapping-around happens +- * which requires the manipulation for bit 0 starting in the next +- * register to form the complete field read/write. +- */ +- pfd->next = pfd->bitpos + c->x_bits - 1 > 31 ? c->x_addrs : 0; +- +- return 0; +-} +- +-static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw, int pin, +- int field, struct mtk_pin_field *pfd) +-{ +- const struct mtk_pin_reg_calc *rc; +- +- if (field < 0 || field >= PINCTRL_PIN_REG_MAX) { +- dev_err(hw->dev, "Invalid Field %d\n", field); +- return -EINVAL; +- } +- +- if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) { +- rc = &hw->soc->reg_cal[field]; +- } else { +- dev_err(hw->dev, "Undefined range for field %d\n", field); +- return -EINVAL; +- } +- +- return mtk_hw_pin_field_lookup(hw, pin, rc, pfd); +-} +- +-static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l) +-{ +- *l = 32 - pf->bitpos; +- *h = get_count_order(pf->mask) - *l; +-} +- +-static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw, +- struct mtk_pin_field *pf, int value) +-{ +- int nbits_l, nbits_h; +- +- mtk_hw_bits_part(pf, &nbits_h, &nbits_l); +- +- mtk_rmw(hw, pf->offset, pf->mask << pf->bitpos, +- (value & pf->mask) << pf->bitpos); +- +- mtk_rmw(hw, pf->offset + pf->next, BIT(nbits_h) - 1, +- (value & pf->mask) >> nbits_l); +-} +- +-static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw, +- struct mtk_pin_field *pf, int *value) +-{ +- int nbits_l, nbits_h, h, l; +- +- mtk_hw_bits_part(pf, &nbits_h, &nbits_l); +- +- l = (mtk_r32(hw, pf->offset) >> pf->bitpos) & (BIT(nbits_l) - 1); +- h = (mtk_r32(hw, pf->offset + pf->next)) & (BIT(nbits_h) - 1); +- +- *value = (h << nbits_l) | l; +-} +- +-static int mtk_hw_set_value(struct mtk_pinctrl *hw, int pin, int field, +- int value) +-{ +- struct mtk_pin_field pf; +- int err; +- +- err = mtk_hw_pin_field_get(hw, pin, field, &pf); +- if (err) +- return err; +- +- if (!pf.next) +- mtk_rmw(hw, pf.offset, pf.mask << pf.bitpos, +- (value & pf.mask) << pf.bitpos); +- else +- mtk_hw_write_cross_field(hw, &pf, value); +- +- return 0; +-} +- +-static int mtk_hw_get_value(struct mtk_pinctrl *hw, int pin, int field, +- int *value) +-{ +- struct mtk_pin_field pf; +- int err; +- +- err = mtk_hw_pin_field_get(hw, pin, field, &pf); +- if (err) +- return err; +- +- if (!pf.next) +- *value = (mtk_r32(hw, pf.offset) >> pf.bitpos) & pf.mask; +- else +- mtk_hw_read_cross_field(hw, &pf, value); +- +- return 0; +-} +- +-static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev, +- unsigned int selector, unsigned int group) +-{ +- struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); +- struct function_desc *func; +- struct group_desc *grp; +- int i; +- +- func = pinmux_generic_get_function(pctldev, selector); +- if (!func) +- return -EINVAL; +- +- grp = pinctrl_generic_get_group(pctldev, group); +- if (!grp) +- return -EINVAL; +- +- dev_dbg(pctldev->dev, "enable function %s group %s\n", +- func->name, grp->name); +- +- for (i = 0; i < grp->num_pins; i++) { +- int *pin_modes = grp->data; +- +- mtk_hw_set_value(hw, grp->pins[i], PINCTRL_PIN_REG_MODE, +- pin_modes[i]); +- } +- +- return 0; +-} +- +-static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, +- struct pinctrl_gpio_range *range, +- unsigned int pin) +-{ +- struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); +- +- return mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_MODE, MTK_GPIO_MODE); +-} +- +-static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, +- struct pinctrl_gpio_range *range, +- unsigned int pin, bool input) +-{ +- struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); +- +- /* hardware would take 0 as input direction */ +- return mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR, !input); +-} +- +-static int mtk_pinconf_get(struct pinctrl_dev *pctldev, +- unsigned int pin, unsigned long *config) +-{ +- struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); +- u32 param = pinconf_to_config_param(*config); +- int val, val2, err, reg, ret = 1; +- +- switch (param) { +- case PIN_CONFIG_BIAS_DISABLE: +- err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_PU, &val); +- if (err) +- return err; +- +- err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_PD, &val2); +- if (err) +- return err; +- +- if (val || val2) +- return -EINVAL; +- +- break; +- case PIN_CONFIG_BIAS_PULL_UP: +- case PIN_CONFIG_BIAS_PULL_DOWN: +- case PIN_CONFIG_SLEW_RATE: +- reg = (param == PIN_CONFIG_BIAS_PULL_UP) ? +- PINCTRL_PIN_REG_PU : +- (param == PIN_CONFIG_BIAS_PULL_DOWN) ? +- PINCTRL_PIN_REG_PD : PINCTRL_PIN_REG_SR; +- +- err = mtk_hw_get_value(hw, pin, reg, &val); +- if (err) +- return err; +- +- if (!val) +- return -EINVAL; +- +- break; +- case PIN_CONFIG_INPUT_ENABLE: +- case PIN_CONFIG_OUTPUT_ENABLE: +- err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_DIR, &val); +- if (err) +- return err; +- +- /* HW takes input mode as zero; output mode as non-zero */ +- if ((val && param == PIN_CONFIG_INPUT_ENABLE) || +- (!val && param == PIN_CONFIG_OUTPUT_ENABLE)) +- return -EINVAL; +- +- break; +- case PIN_CONFIG_INPUT_SCHMITT_ENABLE: +- err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_DIR, &val); +- if (err) +- return err; +- +- err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_SMT, &val2); +- if (err) +- return err; +- +- if (val || !val2) +- return -EINVAL; +- +- break; +- case PIN_CONFIG_DRIVE_STRENGTH: +- err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_E4, &val); +- if (err) +- return err; +- +- err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_E8, &val2); +- if (err) +- return err; +- +- /* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1) +- * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1) +- */ +- ret = ((val2 << 1) + val + 1) * 4; +- +- break; +- case MTK_PIN_CONFIG_TDSEL: +- case MTK_PIN_CONFIG_RDSEL: +- reg = (param == MTK_PIN_CONFIG_TDSEL) ? +- PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL; +- +- err = mtk_hw_get_value(hw, pin, reg, &val); +- if (err) +- return err; +- +- ret = val; +- +- break; +- default: +- return -ENOTSUPP; +- } +- +- *config = pinconf_to_config_packed(param, ret); +- +- return 0; +-} +- +-static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, +- unsigned long *configs, unsigned int num_configs) +-{ +- struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); +- u32 reg, param, arg; +- int cfg, err = 0; +- +- for (cfg = 0; cfg < num_configs; cfg++) { +- param = pinconf_to_config_param(configs[cfg]); +- arg = pinconf_to_config_argument(configs[cfg]); +- +- switch (param) { +- case PIN_CONFIG_BIAS_DISABLE: +- case PIN_CONFIG_BIAS_PULL_UP: +- case PIN_CONFIG_BIAS_PULL_DOWN: +- arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : +- (param == PIN_CONFIG_BIAS_PULL_UP) ? 1 : 2; +- +- err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_PU, +- arg & 1); +- if (err) +- goto err; +- +- err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_PD, +- !!(arg & 2)); +- if (err) +- goto err; +- break; +- case PIN_CONFIG_OUTPUT_ENABLE: +- err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_SMT, +- MTK_DISABLE); +- if (err) +- goto err; +- /* else: fall through */ +- case PIN_CONFIG_INPUT_ENABLE: +- case PIN_CONFIG_SLEW_RATE: +- reg = (param == PIN_CONFIG_SLEW_RATE) ? +- PINCTRL_PIN_REG_SR : PINCTRL_PIN_REG_DIR; +- +- arg = (param == PIN_CONFIG_INPUT_ENABLE) ? 0 : +- (param == PIN_CONFIG_OUTPUT_ENABLE) ? 1 : arg; +- err = mtk_hw_set_value(hw, pin, reg, arg); +- if (err) +- goto err; +- +- break; +- case PIN_CONFIG_OUTPUT: +- err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR, +- MTK_OUTPUT); +- if (err) +- goto err; +- +- err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DO, +- arg); +- if (err) +- goto err; +- break; +- case PIN_CONFIG_INPUT_SCHMITT_ENABLE: +- /* arg = 1: Input mode & SMT enable ; +- * arg = 0: Output mode & SMT disable +- */ +- arg = arg ? 2 : 1; +- err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR, +- arg & 1); +- if (err) +- goto err; +- +- err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_SMT, +- !!(arg & 2)); +- if (err) +- goto err; +- break; +- case PIN_CONFIG_DRIVE_STRENGTH: +- /* 4mA when (e8, e4) = (0, 0); +- * 8mA when (e8, e4) = (0, 1); +- * 12mA when (e8, e4) = (1, 0); +- * 16mA when (e8, e4) = (1, 1) +- */ +- if (!(arg % 4) && (arg >= 4 && arg <= 16)) { +- arg = arg / 4 - 1; +- err = mtk_hw_set_value(hw, pin, +- PINCTRL_PIN_REG_E4, +- arg & 0x1); +- if (err) +- goto err; +- +- err = mtk_hw_set_value(hw, pin, +- PINCTRL_PIN_REG_E8, +- (arg & 0x2) >> 1); +- if (err) +- goto err; +- } else { +- err = -ENOTSUPP; +- } +- break; +- case MTK_PIN_CONFIG_TDSEL: +- case MTK_PIN_CONFIG_RDSEL: +- reg = (param == MTK_PIN_CONFIG_TDSEL) ? +- PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL; +- +- err = mtk_hw_set_value(hw, pin, reg, arg); +- if (err) +- goto err; +- break; +- default: +- err = -ENOTSUPP; +- } +- } +-err: +- return err; +-} +- +-static int mtk_pinconf_group_get(struct pinctrl_dev *pctldev, +- unsigned int group, unsigned long *config) +-{ +- const unsigned int *pins; +- unsigned int i, npins, old = 0; +- int ret; +- +- ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); +- if (ret) +- return ret; +- +- for (i = 0; i < npins; i++) { +- if (mtk_pinconf_get(pctldev, pins[i], config)) +- return -ENOTSUPP; +- +- /* configs do not match between two pins */ +- if (i && old != *config) +- return -ENOTSUPP; +- +- old = *config; +- } +- +- return 0; +-} +- +-static int mtk_pinconf_group_set(struct pinctrl_dev *pctldev, +- unsigned int group, unsigned long *configs, +- unsigned int num_configs) +-{ +- const unsigned int *pins; +- unsigned int i, npins; +- int ret; +- +- ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); +- if (ret) +- return ret; +- +- for (i = 0; i < npins; i++) { +- ret = mtk_pinconf_set(pctldev, pins[i], configs, num_configs); +- if (ret) +- return ret; +- } +- +- return 0; +-} +- +-static const struct pinctrl_ops mtk_pctlops = { +- .get_groups_count = pinctrl_generic_get_group_count, +- .get_group_name = pinctrl_generic_get_group_name, +- .get_group_pins = pinctrl_generic_get_group_pins, +- .dt_node_to_map = pinconf_generic_dt_node_to_map_all, +- .dt_free_map = pinconf_generic_dt_free_map, +-}; +- +-static const struct pinmux_ops mtk_pmxops = { +- .get_functions_count = pinmux_generic_get_function_count, +- .get_function_name = pinmux_generic_get_function_name, +- .get_function_groups = pinmux_generic_get_function_groups, +- .set_mux = mtk_pinmux_set_mux, +- .gpio_request_enable = mtk_pinmux_gpio_request_enable, +- .gpio_set_direction = mtk_pinmux_gpio_set_direction, +- .strict = true, +-}; +- +-static const struct pinconf_ops mtk_confops = { +- .is_generic = true, +- .pin_config_get = mtk_pinconf_get, +- .pin_config_set = mtk_pinconf_set, +- .pin_config_group_get = mtk_pinconf_group_get, +- .pin_config_group_set = mtk_pinconf_group_set, +- .pin_config_config_dbg_show = pinconf_generic_dump_config, +-}; +- +-static struct pinctrl_desc mtk_desc = { +- .name = PINCTRL_PINCTRL_DEV, +- .pctlops = &mtk_pctlops, +- .pmxops = &mtk_pmxops, +- .confops = &mtk_confops, +- .owner = THIS_MODULE, +-}; +- +-static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio) +-{ +- struct mtk_pinctrl *hw = gpiochip_get_data(chip); +- int value, err; +- +- err = mtk_hw_get_value(hw, gpio, PINCTRL_PIN_REG_DI, &value); +- if (err) +- return err; +- +- return !!value; +-} +- +-static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) +-{ +- struct mtk_pinctrl *hw = gpiochip_get_data(chip); +- +- mtk_hw_set_value(hw, gpio, PINCTRL_PIN_REG_DO, !!value); +-} +- +-static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio) +-{ +- return pinctrl_gpio_direction_input(chip->base + gpio); +-} +- +-static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, +- int value) +-{ +- mtk_gpio_set(chip, gpio, value); +- +- return pinctrl_gpio_direction_output(chip->base + gpio); +-} +- +-static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) +-{ +- struct mtk_pinctrl *hw = gpiochip_get_data(chip); +- unsigned long eint_n; +- +- if (!hw->eint) +- return -ENOTSUPP; +- +- eint_n = offset; +- +- return mtk_eint_find_irq(hw->eint, eint_n); +-} +- +-static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset, +- unsigned long config) +-{ +- struct mtk_pinctrl *hw = gpiochip_get_data(chip); +- unsigned long eint_n; +- u32 debounce; +- +- if (!hw->eint || +- pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) +- return -ENOTSUPP; +- +- debounce = pinconf_to_config_argument(config); +- eint_n = offset; +- +- return mtk_eint_set_debounce(hw->eint, eint_n, debounce); +-} +- +-static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np) +-{ +- struct gpio_chip *chip = &hw->chip; +- int ret; +- +- chip->label = PINCTRL_PINCTRL_DEV; +- chip->parent = hw->dev; +- chip->request = gpiochip_generic_request; +- chip->free = gpiochip_generic_free; +- chip->direction_input = mtk_gpio_direction_input; +- chip->direction_output = mtk_gpio_direction_output; +- chip->get = mtk_gpio_get; +- chip->set = mtk_gpio_set; +- chip->to_irq = mtk_gpio_to_irq, +- chip->set_config = mtk_gpio_set_config, +- chip->base = -1; +- chip->ngpio = hw->soc->npins; +- chip->of_node = np; +- chip->of_gpio_n_cells = 2; +- +- ret = gpiochip_add_data(chip, hw); +- if (ret < 0) +- return ret; +- +- /* Just for backward compatible for these old pinctrl nodes without +- * "gpio-ranges" property. Otherwise, called directly from a +- * DeviceTree-supported pinctrl driver is DEPRECATED. +- * Please see Section 2.1 of +- * Documentation/devicetree/bindings/gpio/gpio.txt on how to +- * bind pinctrl and gpio drivers via the "gpio-ranges" property. +- */ +- if (!of_find_property(np, "gpio-ranges", NULL)) { +- ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0, +- chip->ngpio); +- if (ret < 0) { +- gpiochip_remove(chip); +- return ret; +- } +- } +- +- return 0; +-} +- +-static int mtk_build_groups(struct mtk_pinctrl *hw) +-{ +- int err, i; +- +- for (i = 0; i < hw->soc->ngrps; i++) { +- const struct group_desc *group = hw->soc->grps + i; +- +- err = pinctrl_generic_add_group(hw->pctrl, group->name, +- group->pins, group->num_pins, +- group->data); +- if (err < 0) { +- dev_err(hw->dev, "Failed to register group %s\n", +- group->name); +- return err; +- } +- } +- +- return 0; +-} +- +-static int mtk_build_functions(struct mtk_pinctrl *hw) +-{ +- int i, err; +- +- for (i = 0; i < hw->soc->nfuncs ; i++) { +- const struct function_desc *func = hw->soc->funcs + i; +- +- err = pinmux_generic_add_function(hw->pctrl, func->name, +- func->group_names, +- func->num_group_names, +- func->data); +- if (err < 0) { +- dev_err(hw->dev, "Failed to register function %s\n", +- func->name); +- return err; +- } +- } +- +- return 0; +-} +- +-static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n, +- unsigned int *gpio_n, +- struct gpio_chip **gpio_chip) +-{ +- struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data; +- +- *gpio_chip = &hw->chip; +- *gpio_n = eint_n; +- +- return 0; +-} +- +-static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n) +-{ +- struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data; +- struct gpio_chip *gpio_chip; +- unsigned int gpio_n; +- int err; +- +- err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip); +- if (err) +- return err; +- +- return mtk_gpio_get(gpio_chip, gpio_n); +-} +- +-static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n) +-{ +- struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data; +- struct gpio_chip *gpio_chip; +- unsigned int gpio_n; +- int err; +- +- err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip); +- if (err) +- return err; +- +- err = mtk_hw_set_value(hw, gpio_n, PINCTRL_PIN_REG_MODE, +- MTK_GPIO_MODE); +- if (err) +- return err; +- +- err = mtk_hw_set_value(hw, gpio_n, PINCTRL_PIN_REG_DIR, MTK_INPUT); +- if (err) +- return err; +- +- err = mtk_hw_set_value(hw, gpio_n, PINCTRL_PIN_REG_SMT, MTK_ENABLE); +- if (err) +- return err; +- +- return 0; +-} +- +-static const struct mtk_eint_xt mtk_eint_xt = { +- .get_gpio_n = mtk_xt_get_gpio_n, +- .get_gpio_state = mtk_xt_get_gpio_state, +- .set_gpio_as_eint = mtk_xt_set_gpio_as_eint, +-}; +- +-static int +-mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev) +-{ +- struct device_node *np = pdev->dev.of_node; +- struct resource *res; +- +- if (!IS_ENABLED(CONFIG_EINT_MTK)) +- return 0; +- +- if (!of_property_read_bool(np, "interrupt-controller")) +- return -ENODEV; +- +- hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL); +- if (!hw->eint) +- return -ENOMEM; +- +- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eint"); +- if (!res) { +- dev_err(&pdev->dev, "Unable to get eint resource\n"); +- return -ENODEV; +- } +- +- hw->eint->base = devm_ioremap_resource(&pdev->dev, res); +- if (IS_ERR(hw->eint->base)) +- return PTR_ERR(hw->eint->base); +- +- hw->eint->irq = irq_of_parse_and_map(np, 0); +- if (!hw->eint->irq) +- return -EINVAL; +- +- hw->eint->dev = &pdev->dev; +- hw->eint->hw = hw->soc->eint_hw; +- hw->eint->pctl = hw; +- hw->eint->gpio_xlate = &mtk_eint_xt; +- +- return mtk_eint_do_init(hw->eint); +-} +- +-static const struct of_device_id mtk_pinctrl_of_match[] = { +- { .compatible = "mediatek,mt7622-pinctrl", .data = &mt7622_data}, ++ .gpio_m = 1, ++ .ies_present = false, ++ .base_names = mtk_default_register_base_names, ++ .nbase_names = ARRAY_SIZE(mtk_default_register_base_names), ++ .bias_disable_set = mtk_pinconf_bias_disable_set, ++ .bias_disable_get = mtk_pinconf_bias_disable_get, ++ .bias_set = mtk_pinconf_bias_set, ++ .bias_get = mtk_pinconf_bias_get, ++ .drive_set = mtk_pinconf_drive_set, ++ .drive_get = mtk_pinconf_drive_get, ++}; ++ ++static const struct of_device_id mt7622_pinctrl_of_match[] = { ++ { .compatible = "mediatek,mt7622-pinctrl", }, + { } + }; + +-static int mtk_pinctrl_probe(struct platform_device *pdev) ++static int mt7622_pinctrl_probe(struct platform_device *pdev) + { +- struct resource *res; +- struct mtk_pinctrl *hw; +- const struct of_device_id *of_id = +- of_match_device(mtk_pinctrl_of_match, &pdev->dev); +- int err; +- +- hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL); +- if (!hw) +- return -ENOMEM; +- +- hw->soc = of_id->data; +- +- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- if (!res) { +- dev_err(&pdev->dev, "missing IO resource\n"); +- return -ENXIO; +- } +- +- hw->dev = &pdev->dev; +- hw->base = devm_ioremap_resource(&pdev->dev, res); +- if (IS_ERR(hw->base)) +- return PTR_ERR(hw->base); +- +- /* Setup pins descriptions per SoC types */ +- mtk_desc.pins = hw->soc->pins; +- mtk_desc.npins = hw->soc->npins; +- mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings); +- mtk_desc.custom_params = mtk_custom_bindings; +-#ifdef CONFIG_DEBUG_FS +- mtk_desc.custom_conf_items = mtk_conf_items; +-#endif +- +- err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw, +- &hw->pctrl); +- if (err) +- return err; +- +- /* Setup groups descriptions per SoC types */ +- err = mtk_build_groups(hw); +- if (err) { +- dev_err(&pdev->dev, "Failed to build groups\n"); +- return err; +- } +- +- /* Setup functions descriptions per SoC types */ +- err = mtk_build_functions(hw); +- if (err) { +- dev_err(&pdev->dev, "Failed to build functions\n"); +- return err; +- } +- +- /* For able to make pinctrl_claim_hogs, we must not enable pinctrl +- * until all groups and functions are being added one. +- */ +- err = pinctrl_enable(hw->pctrl); +- if (err) +- return err; +- +- err = mtk_build_eint(hw, pdev); +- if (err) +- dev_warn(&pdev->dev, +- "Failed to add EINT, but pinctrl still can work\n"); +- +- /* Build gpiochip should be after pinctrl_enable is done */ +- err = mtk_build_gpiochip(hw, pdev->dev.of_node); +- if (err) { +- dev_err(&pdev->dev, "Failed to add gpio_chip\n"); +- return err; +- } +- +- platform_set_drvdata(pdev, hw); +- +- return 0; ++ return mtk_moore_pinctrl_probe(pdev, &mt7622_data); + } + +-static struct platform_driver mtk_pinctrl_driver = { ++static struct platform_driver mt7622_pinctrl_driver = { + .driver = { +- .name = "mtk-pinctrl", +- .of_match_table = mtk_pinctrl_of_match, ++ .name = "mt7622-pinctrl", ++ .of_match_table = mt7622_pinctrl_of_match, + }, +- .probe = mtk_pinctrl_probe, ++ .probe = mt7622_pinctrl_probe, + }; + +-static int __init mtk_pinctrl_init(void) ++static int __init mt7622_pinctrl_init(void) + { +- return platform_driver_register(&mtk_pinctrl_driver); ++ return platform_driver_register(&mt7622_pinctrl_driver); + } +-arch_initcall(mtk_pinctrl_init); ++arch_initcall(mt7622_pinctrl_init); +diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c +new file mode 100644 +index 000000000000..b8d9d31db74f +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c +@@ -0,0 +1,1441 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * The MT7623 driver based on Linux generic pinctrl binding. ++ * ++ * Copyright (C) 2015 - 2018 MediaTek Inc. ++ * Author: Biao Huang <biao.huang@mediatek.com> ++ * Ryder Lee <ryder.lee@mediatek.com> ++ * Sean Wang <sean.wang@mediatek.com> ++ */ ++ ++#include "pinctrl-moore.h" ++ ++#define PIN_BOND_REG0 0xb10 ++#define PIN_BOND_REG1 0xf20 ++#define PIN_BOND_REG2 0xef0 ++#define BOND_PCIE_CLR (0x77 << 3) ++#define BOND_I2S_CLR 0x3 ++#define BOND_MSDC0E_CLR 0x1 ++ ++#define PIN_FIELD15(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ ++ PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \ ++ _x_bits, 15, false) ++ ++#define PIN_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ ++ PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \ ++ _x_bits, 16, 0) ++ ++#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ ++ PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \ ++ _x_bits, 16, 1) ++ ++#define MT7623_PIN(_number, _name, _eint_n, _drv_grp) \ ++ MTK_PIN(_number, _name, 0, _eint_n, _drv_grp) ++ ++static const struct mtk_pin_field_calc mt7623_pin_mode_range[] = { ++ PIN_FIELD15(0, 278, 0x760, 0x10, 0, 3), ++}; ++ ++static const struct mtk_pin_field_calc mt7623_pin_dir_range[] = { ++ PIN_FIELD16(0, 175, 0x0, 0x10, 0, 1), ++ PIN_FIELD16(176, 278, 0xc0, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7623_pin_di_range[] = { ++ PIN_FIELD16(0, 278, 0x630, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7623_pin_do_range[] = { ++ PIN_FIELD16(0, 278, 0x500, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7623_pin_ies_range[] = { ++ PINS_FIELD16(0, 6, 0xb20, 0x10, 0, 1), ++ PINS_FIELD16(7, 9, 0xb20, 0x10, 1, 1), ++ PINS_FIELD16(10, 13, 0xb30, 0x10, 3, 1), ++ PINS_FIELD16(14, 15, 0xb30, 0x10, 13, 1), ++ PINS_FIELD16(16, 17, 0xb40, 0x10, 7, 1), ++ PINS_FIELD16(18, 29, 0xb40, 0x10, 13, 1), ++ PINS_FIELD16(30, 32, 0xb40, 0x10, 7, 1), ++ PINS_FIELD16(33, 37, 0xb40, 0x10, 13, 1), ++ PIN_FIELD16(38, 38, 0xb20, 0x10, 13, 1), ++ PINS_FIELD16(39, 42, 0xb40, 0x10, 13, 1), ++ PINS_FIELD16(43, 45, 0xb20, 0x10, 10, 1), ++ PINS_FIELD16(47, 48, 0xb20, 0x10, 11, 1), ++ PIN_FIELD16(49, 49, 0xb20, 0x10, 12, 1), ++ PINS_FIELD16(50, 52, 0xb20, 0x10, 13, 1), ++ PINS_FIELD16(53, 56, 0xb20, 0x10, 14, 1), ++ PINS_FIELD16(57, 58, 0xb20, 0x10, 15, 1), ++ PIN_FIELD16(59, 59, 0xb30, 0x10, 10, 1), ++ PINS_FIELD16(60, 62, 0xb30, 0x10, 0, 1), ++ PINS_FIELD16(63, 65, 0xb30, 0x10, 1, 1), ++ PINS_FIELD16(66, 71, 0xb30, 0x10, 2, 1), ++ PINS_FIELD16(72, 74, 0xb20, 0x10, 12, 1), ++ PINS_FIELD16(75, 76, 0xb30, 0x10, 3, 1), ++ PINS_FIELD16(77, 78, 0xb30, 0x10, 4, 1), ++ PINS_FIELD16(79, 82, 0xb30, 0x10, 5, 1), ++ PINS_FIELD16(83, 84, 0xb30, 0x10, 2, 1), ++ PIN_FIELD16(85, 85, 0xda0, 0x10, 4, 1), ++ PIN_FIELD16(86, 86, 0xd90, 0x10, 4, 1), ++ PINS_FIELD16(87, 90, 0xdb0, 0x10, 4, 1), ++ PINS_FIELD16(101, 104, 0xb30, 0x10, 6, 1), ++ PIN_FIELD16(105, 105, 0xd40, 0x10, 4, 1), ++ PIN_FIELD16(106, 106, 0xd30, 0x10, 4, 1), ++ PINS_FIELD16(107, 110, 0xd50, 0x10, 4, 1), ++ PINS_FIELD16(111, 115, 0xce0, 0x10, 4, 1), ++ PIN_FIELD16(116, 116, 0xcd0, 0x10, 4, 1), ++ PIN_FIELD16(117, 117, 0xcc0, 0x10, 4, 1), ++ PINS_FIELD16(118, 121, 0xce0, 0x10, 4, 1), ++ PINS_FIELD16(122, 125, 0xb30, 0x10, 7, 1), ++ PIN_FIELD16(126, 126, 0xb20, 0x10, 12, 1), ++ PINS_FIELD16(127, 142, 0xb30, 0x10, 9, 1), ++ PINS_FIELD16(143, 160, 0xb30, 0x10, 10, 1), ++ PINS_FIELD16(161, 168, 0xb30, 0x10, 12, 1), ++ PINS_FIELD16(169, 183, 0xb30, 0x10, 10, 1), ++ PINS_FIELD16(184, 186, 0xb30, 0x10, 9, 1), ++ PIN_FIELD16(187, 187, 0xb30, 0x10, 14, 1), ++ PIN_FIELD16(188, 188, 0xb20, 0x10, 13, 1), ++ PINS_FIELD16(189, 193, 0xb30, 0x10, 15, 1), ++ PINS_FIELD16(194, 198, 0xb40, 0x10, 0, 1), ++ PIN_FIELD16(199, 199, 0xb20, 0x10, 1, 1), ++ PINS_FIELD16(200, 202, 0xb40, 0x10, 1, 1), ++ PINS_FIELD16(203, 207, 0xb40, 0x10, 2, 1), ++ PINS_FIELD16(208, 209, 0xb40, 0x10, 3, 1), ++ PIN_FIELD16(210, 210, 0xb40, 0x10, 4, 1), ++ PINS_FIELD16(211, 235, 0xb40, 0x10, 5, 1), ++ PINS_FIELD16(236, 241, 0xb40, 0x10, 6, 1), ++ PINS_FIELD16(242, 243, 0xb40, 0x10, 7, 1), ++ PINS_FIELD16(244, 247, 0xb40, 0x10, 8, 1), ++ PIN_FIELD16(248, 248, 0xb40, 0x10, 9, 1), ++ PINS_FIELD16(249, 257, 0xfc0, 0x10, 4, 1), ++ PIN_FIELD16(258, 258, 0xcb0, 0x10, 4, 1), ++ PIN_FIELD16(259, 259, 0xc90, 0x10, 4, 1), ++ PIN_FIELD16(260, 260, 0x3a0, 0x10, 4, 1), ++ PIN_FIELD16(261, 261, 0xd50, 0x10, 4, 1), ++ PINS_FIELD16(262, 277, 0xb40, 0x10, 12, 1), ++ PIN_FIELD16(278, 278, 0xb40, 0x10, 13, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7623_pin_smt_range[] = { ++ PINS_FIELD16(0, 6, 0xb50, 0x10, 0, 1), ++ PINS_FIELD16(7, 9, 0xb50, 0x10, 1, 1), ++ PINS_FIELD16(10, 13, 0xb60, 0x10, 3, 1), ++ PINS_FIELD16(14, 15, 0xb60, 0x10, 13, 1), ++ PINS_FIELD16(16, 17, 0xb70, 0x10, 7, 1), ++ PINS_FIELD16(18, 29, 0xb70, 0x10, 13, 1), ++ PINS_FIELD16(30, 32, 0xb70, 0x10, 7, 1), ++ PINS_FIELD16(33, 37, 0xb70, 0x10, 13, 1), ++ PIN_FIELD16(38, 38, 0xb50, 0x10, 13, 1), ++ PINS_FIELD16(39, 42, 0xb70, 0x10, 13, 1), ++ PINS_FIELD16(43, 45, 0xb50, 0x10, 10, 1), ++ PINS_FIELD16(47, 48, 0xb50, 0x10, 11, 1), ++ PIN_FIELD16(49, 49, 0xb50, 0x10, 12, 1), ++ PINS_FIELD16(50, 52, 0xb50, 0x10, 13, 1), ++ PINS_FIELD16(53, 56, 0xb50, 0x10, 14, 1), ++ PINS_FIELD16(57, 58, 0xb50, 0x10, 15, 1), ++ PIN_FIELD16(59, 59, 0xb60, 0x10, 10, 1), ++ PINS_FIELD16(60, 62, 0xb60, 0x10, 0, 1), ++ PINS_FIELD16(63, 65, 0xb60, 0x10, 1, 1), ++ PINS_FIELD16(66, 71, 0xb60, 0x10, 2, 1), ++ PINS_FIELD16(72, 74, 0xb50, 0x10, 12, 1), ++ PINS_FIELD16(75, 76, 0xb60, 0x10, 3, 1), ++ PINS_FIELD16(77, 78, 0xb60, 0x10, 4, 1), ++ PINS_FIELD16(79, 82, 0xb60, 0x10, 5, 1), ++ PINS_FIELD16(83, 84, 0xb60, 0x10, 2, 1), ++ PIN_FIELD16(85, 85, 0xda0, 0x10, 11, 1), ++ PIN_FIELD16(86, 86, 0xd90, 0x10, 11, 1), ++ PIN_FIELD16(87, 87, 0xdc0, 0x10, 3, 1), ++ PIN_FIELD16(88, 88, 0xdc0, 0x10, 7, 1), ++ PIN_FIELD16(89, 89, 0xdc0, 0x10, 11, 1), ++ PIN_FIELD16(90, 90, 0xdc0, 0x10, 15, 1), ++ PINS_FIELD16(101, 104, 0xb60, 0x10, 6, 1), ++ PIN_FIELD16(105, 105, 0xd40, 0x10, 11, 1), ++ PIN_FIELD16(106, 106, 0xd30, 0x10, 11, 1), ++ PIN_FIELD16(107, 107, 0xd60, 0x10, 3, 1), ++ PIN_FIELD16(108, 108, 0xd60, 0x10, 7, 1), ++ PIN_FIELD16(109, 109, 0xd60, 0x10, 11, 1), ++ PIN_FIELD16(110, 110, 0xd60, 0x10, 15, 1), ++ PIN_FIELD16(111, 111, 0xd00, 0x10, 15, 1), ++ PIN_FIELD16(112, 112, 0xd00, 0x10, 11, 1), ++ PIN_FIELD16(113, 113, 0xd00, 0x10, 7, 1), ++ PIN_FIELD16(114, 114, 0xd00, 0x10, 3, 1), ++ PIN_FIELD16(115, 115, 0xd10, 0x10, 3, 1), ++ PIN_FIELD16(116, 116, 0xcd0, 0x10, 11, 1), ++ PIN_FIELD16(117, 117, 0xcc0, 0x10, 11, 1), ++ PIN_FIELD16(118, 118, 0xcf0, 0x10, 15, 1), ++ PIN_FIELD16(119, 119, 0xcf0, 0x10, 7, 1), ++ PIN_FIELD16(120, 120, 0xcf0, 0x10, 3, 1), ++ PIN_FIELD16(121, 121, 0xcf0, 0x10, 7, 1), ++ PINS_FIELD16(122, 125, 0xb60, 0x10, 7, 1), ++ PIN_FIELD16(126, 126, 0xb50, 0x10, 12, 1), ++ PINS_FIELD16(127, 142, 0xb60, 0x10, 9, 1), ++ PINS_FIELD16(143, 160, 0xb60, 0x10, 10, 1), ++ PINS_FIELD16(161, 168, 0xb60, 0x10, 12, 1), ++ PINS_FIELD16(169, 183, 0xb60, 0x10, 10, 1), ++ PINS_FIELD16(184, 186, 0xb60, 0x10, 9, 1), ++ PIN_FIELD16(187, 187, 0xb60, 0x10, 14, 1), ++ PIN_FIELD16(188, 188, 0xb50, 0x10, 13, 1), ++ PINS_FIELD16(189, 193, 0xb60, 0x10, 15, 1), ++ PINS_FIELD16(194, 198, 0xb70, 0x10, 0, 1), ++ PIN_FIELD16(199, 199, 0xb50, 0x10, 1, 1), ++ PINS_FIELD16(200, 202, 0xb70, 0x10, 1, 1), ++ PINS_FIELD16(203, 207, 0xb70, 0x10, 2, 1), ++ PINS_FIELD16(208, 209, 0xb70, 0x10, 3, 1), ++ PIN_FIELD16(210, 210, 0xb70, 0x10, 4, 1), ++ PINS_FIELD16(211, 235, 0xb70, 0x10, 5, 1), ++ PINS_FIELD16(236, 241, 0xb70, 0x10, 6, 1), ++ PINS_FIELD16(242, 243, 0xb70, 0x10, 7, 1), ++ PINS_FIELD16(244, 247, 0xb70, 0x10, 8, 1), ++ PIN_FIELD16(248, 248, 0xb70, 0x10, 9, 10), ++ PIN_FIELD16(249, 249, 0x140, 0x10, 3, 1), ++ PIN_FIELD16(250, 250, 0x130, 0x10, 15, 1), ++ PIN_FIELD16(251, 251, 0x130, 0x10, 11, 1), ++ PIN_FIELD16(252, 252, 0x130, 0x10, 7, 1), ++ PIN_FIELD16(253, 253, 0x130, 0x10, 3, 1), ++ PIN_FIELD16(254, 254, 0xf40, 0x10, 15, 1), ++ PIN_FIELD16(255, 255, 0xf40, 0x10, 11, 1), ++ PIN_FIELD16(256, 256, 0xf40, 0x10, 7, 1), ++ PIN_FIELD16(257, 257, 0xf40, 0x10, 3, 1), ++ PIN_FIELD16(258, 258, 0xcb0, 0x10, 11, 1), ++ PIN_FIELD16(259, 259, 0xc90, 0x10, 11, 1), ++ PIN_FIELD16(260, 260, 0x3a0, 0x10, 11, 1), ++ PIN_FIELD16(261, 261, 0x0b0, 0x10, 3, 1), ++ PINS_FIELD16(262, 277, 0xb70, 0x10, 12, 1), ++ PIN_FIELD16(278, 278, 0xb70, 0x10, 13, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7623_pin_pullen_range[] = { ++ PIN_FIELD16(0, 278, 0x150, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7623_pin_pullsel_range[] = { ++ PIN_FIELD16(0, 278, 0x280, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7623_pin_drv_range[] = { ++ PINS_FIELD16(0, 6, 0xf50, 0x10, 0, 4), ++ PINS_FIELD16(7, 9, 0xf50, 0x10, 4, 4), ++ PINS_FIELD16(10, 13, 0xf50, 0x10, 4, 4), ++ PINS_FIELD16(14, 15, 0xf50, 0x10, 12, 4), ++ PINS_FIELD16(16, 17, 0xf60, 0x10, 0, 4), ++ PINS_FIELD16(18, 21, 0xf60, 0x10, 0, 4), ++ PINS_FIELD16(22, 26, 0xf60, 0x10, 8, 4), ++ PINS_FIELD16(27, 29, 0xf60, 0x10, 12, 4), ++ PINS_FIELD16(30, 32, 0xf60, 0x10, 0, 4), ++ PINS_FIELD16(33, 37, 0xf70, 0x10, 0, 4), ++ PIN_FIELD16(38, 38, 0xf70, 0x10, 4, 4), ++ PINS_FIELD16(39, 42, 0xf70, 0x10, 8, 4), ++ PINS_FIELD16(43, 45, 0xf70, 0x10, 12, 4), ++ PINS_FIELD16(47, 48, 0xf80, 0x10, 0, 4), ++ PIN_FIELD16(49, 49, 0xf80, 0x10, 4, 4), ++ PINS_FIELD16(50, 52, 0xf70, 0x10, 4, 4), ++ PINS_FIELD16(53, 56, 0xf80, 0x10, 12, 4), ++ PINS_FIELD16(60, 62, 0xf90, 0x10, 8, 4), ++ PINS_FIELD16(63, 65, 0xf90, 0x10, 12, 4), ++ PINS_FIELD16(66, 71, 0xfa0, 0x10, 0, 4), ++ PINS_FIELD16(72, 74, 0xf80, 0x10, 4, 4), ++ PIN_FIELD16(85, 85, 0xda0, 0x10, 0, 4), ++ PIN_FIELD16(86, 86, 0xd90, 0x10, 0, 4), ++ PINS_FIELD16(87, 90, 0xdb0, 0x10, 0, 4), ++ PIN_FIELD16(105, 105, 0xd40, 0x10, 0, 4), ++ PIN_FIELD16(106, 106, 0xd30, 0x10, 0, 4), ++ PINS_FIELD16(107, 110, 0xd50, 0x10, 0, 4), ++ PINS_FIELD16(111, 115, 0xce0, 0x10, 0, 4), ++ PIN_FIELD16(116, 116, 0xcd0, 0x10, 0, 4), ++ PIN_FIELD16(117, 117, 0xcc0, 0x10, 0, 4), ++ PINS_FIELD16(118, 121, 0xce0, 0x10, 0, 4), ++ PIN_FIELD16(126, 126, 0xf80, 0x10, 4, 4), ++ PIN_FIELD16(188, 188, 0xf70, 0x10, 4, 4), ++ PINS_FIELD16(189, 193, 0xfe0, 0x10, 8, 4), ++ PINS_FIELD16(194, 198, 0xfe0, 0x10, 12, 4), ++ PIN_FIELD16(199, 199, 0xf50, 0x10, 4, 4), ++ PINS_FIELD16(200, 202, 0xfd0, 0x10, 0, 4), ++ PINS_FIELD16(203, 207, 0xfd0, 0x10, 4, 4), ++ PINS_FIELD16(208, 209, 0xfd0, 0x10, 8, 4), ++ PIN_FIELD16(210, 210, 0xfd0, 0x10, 12, 4), ++ PINS_FIELD16(211, 235, 0xff0, 0x10, 0, 4), ++ PINS_FIELD16(236, 241, 0xff0, 0x10, 4, 4), ++ PINS_FIELD16(242, 243, 0xff0, 0x10, 8, 4), ++ PIN_FIELD16(248, 248, 0xf00, 0x10, 0, 4), ++ PINS_FIELD16(249, 256, 0xfc0, 0x10, 0, 4), ++ PIN_FIELD16(257, 257, 0xce0, 0x10, 0, 4), ++ PIN_FIELD16(258, 258, 0xcb0, 0x10, 0, 4), ++ PIN_FIELD16(259, 259, 0xc90, 0x10, 0, 4), ++ PIN_FIELD16(260, 260, 0x3a0, 0x10, 0, 4), ++ PIN_FIELD16(261, 261, 0xd50, 0x10, 0, 4), ++ PINS_FIELD16(262, 277, 0xf00, 0x10, 8, 4), ++ PIN_FIELD16(278, 278, 0xf70, 0x10, 8, 4), ++}; ++ ++static const struct mtk_pin_field_calc mt7623_pin_tdsel_range[] = { ++ PINS_FIELD16(262, 276, 0x4c0, 0x10, 0, 4), ++}; ++ ++static const struct mtk_pin_field_calc mt7623_pin_pupd_range[] = { ++ /* MSDC0 */ ++ PIN_FIELD16(111, 111, 0xd00, 0x10, 12, 1), ++ PIN_FIELD16(112, 112, 0xd00, 0x10, 8, 1), ++ PIN_FIELD16(113, 113, 0xd00, 0x10, 4, 1), ++ PIN_FIELD16(114, 114, 0xd00, 0x10, 0, 1), ++ PIN_FIELD16(115, 115, 0xd10, 0x10, 0, 1), ++ PIN_FIELD16(116, 116, 0xcd0, 0x10, 8, 1), ++ PIN_FIELD16(117, 117, 0xcc0, 0x10, 8, 1), ++ PIN_FIELD16(118, 118, 0xcf0, 0x10, 12, 1), ++ PIN_FIELD16(119, 119, 0xcf0, 0x10, 8, 1), ++ PIN_FIELD16(120, 120, 0xcf0, 0x10, 4, 1), ++ PIN_FIELD16(121, 121, 0xcf0, 0x10, 0, 1), ++ /* MSDC1 */ ++ PIN_FIELD16(105, 105, 0xd40, 0x10, 8, 1), ++ PIN_FIELD16(106, 106, 0xd30, 0x10, 8, 1), ++ PIN_FIELD16(107, 107, 0xd60, 0x10, 0, 1), ++ PIN_FIELD16(108, 108, 0xd60, 0x10, 10, 1), ++ PIN_FIELD16(109, 109, 0xd60, 0x10, 4, 1), ++ PIN_FIELD16(110, 110, 0xc60, 0x10, 12, 1), ++ /* MSDC1 */ ++ PIN_FIELD16(85, 85, 0xda0, 0x10, 8, 1), ++ PIN_FIELD16(86, 86, 0xd90, 0x10, 8, 1), ++ PIN_FIELD16(87, 87, 0xdc0, 0x10, 0, 1), ++ PIN_FIELD16(88, 88, 0xdc0, 0x10, 10, 1), ++ PIN_FIELD16(89, 89, 0xdc0, 0x10, 4, 1), ++ PIN_FIELD16(90, 90, 0xdc0, 0x10, 12, 1), ++ /* MSDC0E */ ++ PIN_FIELD16(249, 249, 0x140, 0x10, 0, 1), ++ PIN_FIELD16(250, 250, 0x130, 0x10, 12, 1), ++ PIN_FIELD16(251, 251, 0x130, 0x10, 8, 1), ++ PIN_FIELD16(252, 252, 0x130, 0x10, 4, 1), ++ PIN_FIELD16(253, 253, 0x130, 0x10, 0, 1), ++ PIN_FIELD16(254, 254, 0xf40, 0x10, 12, 1), ++ PIN_FIELD16(255, 255, 0xf40, 0x10, 8, 1), ++ PIN_FIELD16(256, 256, 0xf40, 0x10, 4, 1), ++ PIN_FIELD16(257, 257, 0xf40, 0x10, 0, 1), ++ PIN_FIELD16(258, 258, 0xcb0, 0x10, 8, 1), ++ PIN_FIELD16(259, 259, 0xc90, 0x10, 8, 1), ++ PIN_FIELD16(261, 261, 0x140, 0x10, 8, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7623_pin_r1_range[] = { ++ /* MSDC0 */ ++ PIN_FIELD16(111, 111, 0xd00, 0x10, 13, 1), ++ PIN_FIELD16(112, 112, 0xd00, 0x10, 9, 1), ++ PIN_FIELD16(113, 113, 0xd00, 0x10, 5, 1), ++ PIN_FIELD16(114, 114, 0xd00, 0x10, 1, 1), ++ PIN_FIELD16(115, 115, 0xd10, 0x10, 1, 1), ++ PIN_FIELD16(116, 116, 0xcd0, 0x10, 9, 1), ++ PIN_FIELD16(117, 117, 0xcc0, 0x10, 9, 1), ++ PIN_FIELD16(118, 118, 0xcf0, 0x10, 13, 1), ++ PIN_FIELD16(119, 119, 0xcf0, 0x10, 9, 1), ++ PIN_FIELD16(120, 120, 0xcf0, 0x10, 5, 1), ++ PIN_FIELD16(121, 121, 0xcf0, 0x10, 1, 1), ++ /* MSDC1 */ ++ PIN_FIELD16(105, 105, 0xd40, 0x10, 9, 1), ++ PIN_FIELD16(106, 106, 0xd30, 0x10, 9, 1), ++ PIN_FIELD16(107, 107, 0xd60, 0x10, 1, 1), ++ PIN_FIELD16(108, 108, 0xd60, 0x10, 9, 1), ++ PIN_FIELD16(109, 109, 0xd60, 0x10, 5, 1), ++ PIN_FIELD16(110, 110, 0xc60, 0x10, 13, 1), ++ /* MSDC2 */ ++ PIN_FIELD16(85, 85, 0xda0, 0x10, 9, 1), ++ PIN_FIELD16(86, 86, 0xd90, 0x10, 9, 1), ++ PIN_FIELD16(87, 87, 0xdc0, 0x10, 1, 1), ++ PIN_FIELD16(88, 88, 0xdc0, 0x10, 9, 1), ++ PIN_FIELD16(89, 89, 0xdc0, 0x10, 5, 1), ++ PIN_FIELD16(90, 90, 0xdc0, 0x10, 13, 1), ++ /* MSDC0E */ ++ PIN_FIELD16(249, 249, 0x140, 0x10, 1, 1), ++ PIN_FIELD16(250, 250, 0x130, 0x10, 13, 1), ++ PIN_FIELD16(251, 251, 0x130, 0x10, 9, 1), ++ PIN_FIELD16(252, 252, 0x130, 0x10, 5, 1), ++ PIN_FIELD16(253, 253, 0x130, 0x10, 1, 1), ++ PIN_FIELD16(254, 254, 0xf40, 0x10, 13, 1), ++ PIN_FIELD16(255, 255, 0xf40, 0x10, 9, 1), ++ PIN_FIELD16(256, 256, 0xf40, 0x10, 5, 1), ++ PIN_FIELD16(257, 257, 0xf40, 0x10, 1, 1), ++ PIN_FIELD16(258, 258, 0xcb0, 0x10, 9, 1), ++ PIN_FIELD16(259, 259, 0xc90, 0x10, 9, 1), ++ PIN_FIELD16(261, 261, 0x140, 0x10, 9, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7623_pin_r0_range[] = { ++ /* MSDC0 */ ++ PIN_FIELD16(111, 111, 0xd00, 0x10, 14, 1), ++ PIN_FIELD16(112, 112, 0xd00, 0x10, 10, 1), ++ PIN_FIELD16(113, 113, 0xd00, 0x10, 6, 1), ++ PIN_FIELD16(114, 114, 0xd00, 0x10, 2, 1), ++ PIN_FIELD16(115, 115, 0xd10, 0x10, 2, 1), ++ PIN_FIELD16(116, 116, 0xcd0, 0x10, 10, 1), ++ PIN_FIELD16(117, 117, 0xcc0, 0x10, 10, 1), ++ PIN_FIELD16(118, 118, 0xcf0, 0x10, 14, 1), ++ PIN_FIELD16(119, 119, 0xcf0, 0x10, 10, 1), ++ PIN_FIELD16(120, 120, 0xcf0, 0x10, 6, 1), ++ PIN_FIELD16(121, 121, 0xcf0, 0x10, 2, 1), ++ /* MSDC1 */ ++ PIN_FIELD16(105, 105, 0xd40, 0x10, 10, 1), ++ PIN_FIELD16(106, 106, 0xd30, 0x10, 10, 1), ++ PIN_FIELD16(107, 107, 0xd60, 0x10, 2, 1), ++ PIN_FIELD16(108, 108, 0xd60, 0x10, 8, 1), ++ PIN_FIELD16(109, 109, 0xd60, 0x10, 6, 1), ++ PIN_FIELD16(110, 110, 0xc60, 0x10, 14, 1), ++ /* MSDC2 */ ++ PIN_FIELD16(85, 85, 0xda0, 0x10, 10, 1), ++ PIN_FIELD16(86, 86, 0xd90, 0x10, 10, 1), ++ PIN_FIELD16(87, 87, 0xdc0, 0x10, 2, 1), ++ PIN_FIELD16(88, 88, 0xdc0, 0x10, 8, 1), ++ PIN_FIELD16(89, 89, 0xdc0, 0x10, 6, 1), ++ PIN_FIELD16(90, 90, 0xdc0, 0x10, 14, 1), ++ /* MSDC0E */ ++ PIN_FIELD16(249, 249, 0x140, 0x10, 2, 1), ++ PIN_FIELD16(250, 250, 0x130, 0x10, 14, 1), ++ PIN_FIELD16(251, 251, 0x130, 0x10, 10, 1), ++ PIN_FIELD16(252, 252, 0x130, 0x10, 6, 1), ++ PIN_FIELD16(253, 253, 0x130, 0x10, 2, 1), ++ PIN_FIELD16(254, 254, 0xf40, 0x10, 14, 1), ++ PIN_FIELD16(255, 255, 0xf40, 0x10, 10, 1), ++ PIN_FIELD16(256, 256, 0xf40, 0x10, 6, 1), ++ PIN_FIELD16(257, 257, 0xf40, 0x10, 5, 1), ++ PIN_FIELD16(258, 258, 0xcb0, 0x10, 10, 1), ++ PIN_FIELD16(259, 259, 0xc90, 0x10, 10, 1), ++ PIN_FIELD16(261, 261, 0x140, 0x10, 10, 1), ++}; ++ ++static const struct mtk_pin_reg_calc mt7623_reg_cals[] = { ++ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7623_pin_mode_range), ++ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7623_pin_dir_range), ++ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7623_pin_di_range), ++ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7623_pin_do_range), ++ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7623_pin_smt_range), ++ [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7623_pin_pullsel_range), ++ [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7623_pin_pullen_range), ++ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7623_pin_drv_range), ++ [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7623_pin_tdsel_range), ++ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7623_pin_ies_range), ++ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7623_pin_pupd_range), ++ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7623_pin_r0_range), ++ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7623_pin_r1_range), ++}; ++ ++static const struct mtk_pin_desc mt7623_pins[] = { ++ MT7623_PIN(0, "PWRAP_SPI0_MI", 148, DRV_GRP3), ++ MT7623_PIN(1, "PWRAP_SPI0_MO", 149, DRV_GRP3), ++ MT7623_PIN(2, "PWRAP_INT", 150, DRV_GRP3), ++ MT7623_PIN(3, "PWRAP_SPI0_CK", 151, DRV_GRP3), ++ MT7623_PIN(4, "PWRAP_SPI0_CSN", 152, DRV_GRP3), ++ MT7623_PIN(5, "PWRAP_SPI0_CK2", 153, DRV_GRP3), ++ MT7623_PIN(6, "PWRAP_SPI0_CSN2", 154, DRV_GRP3), ++ MT7623_PIN(7, "SPI1_CSN", 155, DRV_GRP3), ++ MT7623_PIN(8, "SPI1_MI", 156, DRV_GRP3), ++ MT7623_PIN(9, "SPI1_MO", 157, DRV_GRP3), ++ MT7623_PIN(10, "RTC32K_CK", 158, DRV_GRP3), ++ MT7623_PIN(11, "WATCHDOG", 159, DRV_GRP3), ++ MT7623_PIN(12, "SRCLKENA", 160, DRV_GRP3), ++ MT7623_PIN(13, "SRCLKENAI", 161, DRV_GRP3), ++ MT7623_PIN(14, "URXD2", 162, DRV_GRP1), ++ MT7623_PIN(15, "UTXD2", 163, DRV_GRP1), ++ MT7623_PIN(16, "I2S5_DATA_IN", 164, DRV_GRP1), ++ MT7623_PIN(17, "I2S5_BCK", 165, DRV_GRP1), ++ MT7623_PIN(18, "PCM_CLK", 166, DRV_GRP1), ++ MT7623_PIN(19, "PCM_SYNC", 167, DRV_GRP1), ++ MT7623_PIN(20, "PCM_RX", EINT_NA, DRV_GRP1), ++ MT7623_PIN(21, "PCM_TX", EINT_NA, DRV_GRP1), ++ MT7623_PIN(22, "EINT0", 0, DRV_GRP1), ++ MT7623_PIN(23, "EINT1", 1, DRV_GRP1), ++ MT7623_PIN(24, "EINT2", 2, DRV_GRP1), ++ MT7623_PIN(25, "EINT3", 3, DRV_GRP1), ++ MT7623_PIN(26, "EINT4", 4, DRV_GRP1), ++ MT7623_PIN(27, "EINT5", 5, DRV_GRP1), ++ MT7623_PIN(28, "EINT6", 6, DRV_GRP1), ++ MT7623_PIN(29, "EINT7", 7, DRV_GRP1), ++ MT7623_PIN(30, "I2S5_LRCK", 12, DRV_GRP1), ++ MT7623_PIN(31, "I2S5_MCLK", 13, DRV_GRP1), ++ MT7623_PIN(32, "I2S5_DATA", 14, DRV_GRP1), ++ MT7623_PIN(33, "I2S1_DATA", 15, DRV_GRP1), ++ MT7623_PIN(34, "I2S1_DATA_IN", 16, DRV_GRP1), ++ MT7623_PIN(35, "I2S1_BCK", 17, DRV_GRP1), ++ MT7623_PIN(36, "I2S1_LRCK", 18, DRV_GRP1), ++ MT7623_PIN(37, "I2S1_MCLK", 19, DRV_GRP1), ++ MT7623_PIN(38, "I2S2_DATA", 20, DRV_GRP1), ++ MT7623_PIN(39, "JTMS", 21, DRV_GRP3), ++ MT7623_PIN(40, "JTCK", 22, DRV_GRP3), ++ MT7623_PIN(41, "JTDI", 23, DRV_GRP3), ++ MT7623_PIN(42, "JTDO", 24, DRV_GRP3), ++ MT7623_PIN(43, "NCLE", 25, DRV_GRP1), ++ MT7623_PIN(44, "NCEB1", 26, DRV_GRP1), ++ MT7623_PIN(45, "NCEB0", 27, DRV_GRP1), ++ MT7623_PIN(46, "IR", 28, DRV_FIXED), ++ MT7623_PIN(47, "NREB", 29, DRV_GRP1), ++ MT7623_PIN(48, "NRNB", 30, DRV_GRP1), ++ MT7623_PIN(49, "I2S0_DATA", 31, DRV_GRP1), ++ MT7623_PIN(50, "I2S2_BCK", 32, DRV_GRP1), ++ MT7623_PIN(51, "I2S2_DATA_IN", 33, DRV_GRP1), ++ MT7623_PIN(52, "I2S2_LRCK", 34, DRV_GRP1), ++ MT7623_PIN(53, "SPI0_CSN", 35, DRV_GRP1), ++ MT7623_PIN(54, "SPI0_CK", 36, DRV_GRP1), ++ MT7623_PIN(55, "SPI0_MI", 37, DRV_GRP1), ++ MT7623_PIN(56, "SPI0_MO", 38, DRV_GRP1), ++ MT7623_PIN(57, "SDA1", 39, DRV_FIXED), ++ MT7623_PIN(58, "SCL1", 40, DRV_FIXED), ++ MT7623_PIN(59, "RAMBUF_I_CLK", EINT_NA, DRV_FIXED), ++ MT7623_PIN(60, "WB_RSTB", 41, DRV_GRP3), ++ MT7623_PIN(61, "F2W_DATA", 42, DRV_GRP3), ++ MT7623_PIN(62, "F2W_CLK", 43, DRV_GRP3), ++ MT7623_PIN(63, "WB_SCLK", 44, DRV_GRP3), ++ MT7623_PIN(64, "WB_SDATA", 45, DRV_GRP3), ++ MT7623_PIN(65, "WB_SEN", 46, DRV_GRP3), ++ MT7623_PIN(66, "WB_CRTL0", 47, DRV_GRP3), ++ MT7623_PIN(67, "WB_CRTL1", 48, DRV_GRP3), ++ MT7623_PIN(68, "WB_CRTL2", 49, DRV_GRP3), ++ MT7623_PIN(69, "WB_CRTL3", 50, DRV_GRP3), ++ MT7623_PIN(70, "WB_CRTL4", 51, DRV_GRP3), ++ MT7623_PIN(71, "WB_CRTL5", 52, DRV_GRP3), ++ MT7623_PIN(72, "I2S0_DATA_IN", 53, DRV_GRP1), ++ MT7623_PIN(73, "I2S0_LRCK", 54, DRV_GRP1), ++ MT7623_PIN(74, "I2S0_BCK", 55, DRV_GRP1), ++ MT7623_PIN(75, "SDA0", 56, DRV_FIXED), ++ MT7623_PIN(76, "SCL0", 57, DRV_FIXED), ++ MT7623_PIN(77, "SDA2", 58, DRV_FIXED), ++ MT7623_PIN(78, "SCL2", 59, DRV_FIXED), ++ MT7623_PIN(79, "URXD0", 60, DRV_FIXED), ++ MT7623_PIN(80, "UTXD0", 61, DRV_FIXED), ++ MT7623_PIN(81, "URXD1", 62, DRV_FIXED), ++ MT7623_PIN(82, "UTXD1", 63, DRV_FIXED), ++ MT7623_PIN(83, "LCM_RST", 64, DRV_FIXED), ++ MT7623_PIN(84, "DSI_TE", 65, DRV_FIXED), ++ MT7623_PIN(85, "MSDC2_CMD", 66, DRV_GRP4), ++ MT7623_PIN(86, "MSDC2_CLK", 67, DRV_GRP4), ++ MT7623_PIN(87, "MSDC2_DAT0", 68, DRV_GRP4), ++ MT7623_PIN(88, "MSDC2_DAT1", 69, DRV_GRP4), ++ MT7623_PIN(89, "MSDC2_DAT2", 70, DRV_GRP4), ++ MT7623_PIN(90, "MSDC2_DAT3", 71, DRV_GRP4), ++ MT7623_PIN(91, "TDN3", EINT_NA, DRV_FIXED), ++ MT7623_PIN(92, "TDP3", EINT_NA, DRV_FIXED), ++ MT7623_PIN(93, "TDN2", EINT_NA, DRV_FIXED), ++ MT7623_PIN(94, "TDP2", EINT_NA, DRV_FIXED), ++ MT7623_PIN(95, "TCN", EINT_NA, DRV_FIXED), ++ MT7623_PIN(96, "TCP", EINT_NA, DRV_FIXED), ++ MT7623_PIN(97, "TDN1", EINT_NA, DRV_FIXED), ++ MT7623_PIN(98, "TDP1", EINT_NA, DRV_FIXED), ++ MT7623_PIN(99, "TDN0", EINT_NA, DRV_FIXED), ++ MT7623_PIN(100, "TDP0", EINT_NA, DRV_FIXED), ++ MT7623_PIN(101, "SPI2_CSN", 74, DRV_FIXED), ++ MT7623_PIN(102, "SPI2_MI", 75, DRV_FIXED), ++ MT7623_PIN(103, "SPI2_MO", 76, DRV_FIXED), ++ MT7623_PIN(104, "SPI2_CLK", 77, DRV_FIXED), ++ MT7623_PIN(105, "MSDC1_CMD", 78, DRV_GRP4), ++ MT7623_PIN(106, "MSDC1_CLK", 79, DRV_GRP4), ++ MT7623_PIN(107, "MSDC1_DAT0", 80, DRV_GRP4), ++ MT7623_PIN(108, "MSDC1_DAT1", 81, DRV_GRP4), ++ MT7623_PIN(109, "MSDC1_DAT2", 82, DRV_GRP4), ++ MT7623_PIN(110, "MSDC1_DAT3", 83, DRV_GRP4), ++ MT7623_PIN(111, "MSDC0_DAT7", 84, DRV_GRP4), ++ MT7623_PIN(112, "MSDC0_DAT6", 85, DRV_GRP4), ++ MT7623_PIN(113, "MSDC0_DAT5", 86, DRV_GRP4), ++ MT7623_PIN(114, "MSDC0_DAT4", 87, DRV_GRP4), ++ MT7623_PIN(115, "MSDC0_RSTB", 88, DRV_GRP4), ++ MT7623_PIN(116, "MSDC0_CMD", 89, DRV_GRP4), ++ MT7623_PIN(117, "MSDC0_CLK", 90, DRV_GRP4), ++ MT7623_PIN(118, "MSDC0_DAT3", 91, DRV_GRP4), ++ MT7623_PIN(119, "MSDC0_DAT2", 92, DRV_GRP4), ++ MT7623_PIN(120, "MSDC0_DAT1", 93, DRV_GRP4), ++ MT7623_PIN(121, "MSDC0_DAT0", 94, DRV_GRP4), ++ MT7623_PIN(122, "CEC", 95, DRV_FIXED), ++ MT7623_PIN(123, "HTPLG", 96, DRV_FIXED), ++ MT7623_PIN(124, "HDMISCK", 97, DRV_FIXED), ++ MT7623_PIN(125, "HDMISD", 98, DRV_FIXED), ++ MT7623_PIN(126, "I2S0_MCLK", 99, DRV_GRP1), ++ MT7623_PIN(127, "RAMBUF_IDATA0", EINT_NA, DRV_FIXED), ++ MT7623_PIN(128, "RAMBUF_IDATA1", EINT_NA, DRV_FIXED), ++ MT7623_PIN(129, "RAMBUF_IDATA2", EINT_NA, DRV_FIXED), ++ MT7623_PIN(130, "RAMBUF_IDATA3", EINT_NA, DRV_FIXED), ++ MT7623_PIN(131, "RAMBUF_IDATA4", EINT_NA, DRV_FIXED), ++ MT7623_PIN(132, "RAMBUF_IDATA5", EINT_NA, DRV_FIXED), ++ MT7623_PIN(133, "RAMBUF_IDATA6", EINT_NA, DRV_FIXED), ++ MT7623_PIN(134, "RAMBUF_IDATA7", EINT_NA, DRV_FIXED), ++ MT7623_PIN(135, "RAMBUF_IDATA8", EINT_NA, DRV_FIXED), ++ MT7623_PIN(136, "RAMBUF_IDATA9", EINT_NA, DRV_FIXED), ++ MT7623_PIN(137, "RAMBUF_IDATA10", EINT_NA, DRV_FIXED), ++ MT7623_PIN(138, "RAMBUF_IDATA11", EINT_NA, DRV_FIXED), ++ MT7623_PIN(139, "RAMBUF_IDATA12", EINT_NA, DRV_FIXED), ++ MT7623_PIN(140, "RAMBUF_IDATA13", EINT_NA, DRV_FIXED), ++ MT7623_PIN(141, "RAMBUF_IDATA14", EINT_NA, DRV_FIXED), ++ MT7623_PIN(142, "RAMBUF_IDATA15", EINT_NA, DRV_FIXED), ++ MT7623_PIN(143, "RAMBUF_ODATA0", EINT_NA, DRV_FIXED), ++ MT7623_PIN(144, "RAMBUF_ODATA1", EINT_NA, DRV_FIXED), ++ MT7623_PIN(145, "RAMBUF_ODATA2", EINT_NA, DRV_FIXED), ++ MT7623_PIN(146, "RAMBUF_ODATA3", EINT_NA, DRV_FIXED), ++ MT7623_PIN(147, "RAMBUF_ODATA4", EINT_NA, DRV_FIXED), ++ MT7623_PIN(148, "RAMBUF_ODATA5", EINT_NA, DRV_FIXED), ++ MT7623_PIN(149, "RAMBUF_ODATA6", EINT_NA, DRV_FIXED), ++ MT7623_PIN(150, "RAMBUF_ODATA7", EINT_NA, DRV_FIXED), ++ MT7623_PIN(151, "RAMBUF_ODATA8", EINT_NA, DRV_FIXED), ++ MT7623_PIN(152, "RAMBUF_ODATA9", EINT_NA, DRV_FIXED), ++ MT7623_PIN(153, "RAMBUF_ODATA10", EINT_NA, DRV_FIXED), ++ MT7623_PIN(154, "RAMBUF_ODATA11", EINT_NA, DRV_FIXED), ++ MT7623_PIN(155, "RAMBUF_ODATA12", EINT_NA, DRV_FIXED), ++ MT7623_PIN(156, "RAMBUF_ODATA13", EINT_NA, DRV_FIXED), ++ MT7623_PIN(157, "RAMBUF_ODATA14", EINT_NA, DRV_FIXED), ++ MT7623_PIN(158, "RAMBUF_ODATA15", EINT_NA, DRV_FIXED), ++ MT7623_PIN(159, "RAMBUF_BE0", EINT_NA, DRV_FIXED), ++ MT7623_PIN(160, "RAMBUF_BE1", EINT_NA, DRV_FIXED), ++ MT7623_PIN(161, "AP2PT_INT", EINT_NA, DRV_FIXED), ++ MT7623_PIN(162, "AP2PT_INT_CLR", EINT_NA, DRV_FIXED), ++ MT7623_PIN(163, "PT2AP_INT", EINT_NA, DRV_FIXED), ++ MT7623_PIN(164, "PT2AP_INT_CLR", EINT_NA, DRV_FIXED), ++ MT7623_PIN(165, "AP2UP_INT", EINT_NA, DRV_FIXED), ++ MT7623_PIN(166, "AP2UP_INT_CLR", EINT_NA, DRV_FIXED), ++ MT7623_PIN(167, "UP2AP_INT", EINT_NA, DRV_FIXED), ++ MT7623_PIN(168, "UP2AP_INT_CLR", EINT_NA, DRV_FIXED), ++ MT7623_PIN(169, "RAMBUF_ADDR0", EINT_NA, DRV_FIXED), ++ MT7623_PIN(170, "RAMBUF_ADDR1", EINT_NA, DRV_FIXED), ++ MT7623_PIN(171, "RAMBUF_ADDR2", EINT_NA, DRV_FIXED), ++ MT7623_PIN(172, "RAMBUF_ADDR3", EINT_NA, DRV_FIXED), ++ MT7623_PIN(173, "RAMBUF_ADDR4", EINT_NA, DRV_FIXED), ++ MT7623_PIN(174, "RAMBUF_ADDR5", EINT_NA, DRV_FIXED), ++ MT7623_PIN(175, "RAMBUF_ADDR6", EINT_NA, DRV_FIXED), ++ MT7623_PIN(176, "RAMBUF_ADDR7", EINT_NA, DRV_FIXED), ++ MT7623_PIN(177, "RAMBUF_ADDR8", EINT_NA, DRV_FIXED), ++ MT7623_PIN(178, "RAMBUF_ADDR9", EINT_NA, DRV_FIXED), ++ MT7623_PIN(179, "RAMBUF_ADDR10", EINT_NA, DRV_FIXED), ++ MT7623_PIN(180, "RAMBUF_RW", EINT_NA, DRV_FIXED), ++ MT7623_PIN(181, "RAMBUF_LAST", EINT_NA, DRV_FIXED), ++ MT7623_PIN(182, "RAMBUF_HP", EINT_NA, DRV_FIXED), ++ MT7623_PIN(183, "RAMBUF_REQ", EINT_NA, DRV_FIXED), ++ MT7623_PIN(184, "RAMBUF_ALE", EINT_NA, DRV_FIXED), ++ MT7623_PIN(185, "RAMBUF_DLE", EINT_NA, DRV_FIXED), ++ MT7623_PIN(186, "RAMBUF_WDLE", EINT_NA, DRV_FIXED), ++ MT7623_PIN(187, "RAMBUF_O_CLK", EINT_NA, DRV_FIXED), ++ MT7623_PIN(188, "I2S2_MCLK", 100, DRV_GRP1), ++ MT7623_PIN(189, "I2S3_DATA", 101, DRV_GRP1), ++ MT7623_PIN(190, "I2S3_DATA_IN", 102, DRV_GRP1), ++ MT7623_PIN(191, "I2S3_BCK", 103, DRV_GRP1), ++ MT7623_PIN(192, "I2S3_LRCK", 104, DRV_GRP1), ++ MT7623_PIN(193, "I2S3_MCLK", 105, DRV_GRP1), ++ MT7623_PIN(194, "I2S4_DATA", 106, DRV_GRP1), ++ MT7623_PIN(195, "I2S4_DATA_IN", 107, DRV_GRP1), ++ MT7623_PIN(196, "I2S4_BCK", 108, DRV_GRP1), ++ MT7623_PIN(197, "I2S4_LRCK", 109, DRV_GRP1), ++ MT7623_PIN(198, "I2S4_MCLK", 110, DRV_GRP1), ++ MT7623_PIN(199, "SPI1_CLK", 111, DRV_GRP3), ++ MT7623_PIN(200, "SPDIF_OUT", 112, DRV_GRP1), ++ MT7623_PIN(201, "SPDIF_IN0", 113, DRV_GRP1), ++ MT7623_PIN(202, "SPDIF_IN1", 114, DRV_GRP1), ++ MT7623_PIN(203, "PWM0", 115, DRV_GRP1), ++ MT7623_PIN(204, "PWM1", 116, DRV_GRP1), ++ MT7623_PIN(205, "PWM2", 117, DRV_GRP1), ++ MT7623_PIN(206, "PWM3", 118, DRV_GRP1), ++ MT7623_PIN(207, "PWM4", 119, DRV_GRP1), ++ MT7623_PIN(208, "AUD_EXT_CK1", 120, DRV_GRP1), ++ MT7623_PIN(209, "AUD_EXT_CK2", 121, DRV_GRP1), ++ MT7623_PIN(210, "AUD_CLOCK", EINT_NA, DRV_GRP3), ++ MT7623_PIN(211, "DVP_RESET", EINT_NA, DRV_GRP3), ++ MT7623_PIN(212, "DVP_CLOCK", EINT_NA, DRV_GRP3), ++ MT7623_PIN(213, "DVP_CS", EINT_NA, DRV_GRP3), ++ MT7623_PIN(214, "DVP_CK", EINT_NA, DRV_GRP3), ++ MT7623_PIN(215, "DVP_DI", EINT_NA, DRV_GRP3), ++ MT7623_PIN(216, "DVP_DO", EINT_NA, DRV_GRP3), ++ MT7623_PIN(217, "AP_CS", EINT_NA, DRV_GRP3), ++ MT7623_PIN(218, "AP_CK", EINT_NA, DRV_GRP3), ++ MT7623_PIN(219, "AP_DI", EINT_NA, DRV_GRP3), ++ MT7623_PIN(220, "AP_DO", EINT_NA, DRV_GRP3), ++ MT7623_PIN(221, "DVD_BCLK", EINT_NA, DRV_GRP3), ++ MT7623_PIN(222, "T8032_CLK", EINT_NA, DRV_GRP3), ++ MT7623_PIN(223, "AP_BCLK", EINT_NA, DRV_GRP3), ++ MT7623_PIN(224, "HOST_CS", EINT_NA, DRV_GRP3), ++ MT7623_PIN(225, "HOST_CK", EINT_NA, DRV_GRP3), ++ MT7623_PIN(226, "HOST_DO0", EINT_NA, DRV_GRP3), ++ MT7623_PIN(227, "HOST_DO1", EINT_NA, DRV_GRP3), ++ MT7623_PIN(228, "SLV_CS", EINT_NA, DRV_GRP3), ++ MT7623_PIN(229, "SLV_CK", EINT_NA, DRV_GRP3), ++ MT7623_PIN(230, "SLV_DI0", EINT_NA, DRV_GRP3), ++ MT7623_PIN(231, "SLV_DI1", EINT_NA, DRV_GRP3), ++ MT7623_PIN(232, "AP2DSP_INT", EINT_NA, DRV_GRP3), ++ MT7623_PIN(233, "AP2DSP_INT_CLR", EINT_NA, DRV_GRP3), ++ MT7623_PIN(234, "DSP2AP_INT", EINT_NA, DRV_GRP3), ++ MT7623_PIN(235, "DSP2AP_INT_CLR", EINT_NA, DRV_GRP3), ++ MT7623_PIN(236, "EXT_SDIO3", 122, DRV_GRP1), ++ MT7623_PIN(237, "EXT_SDIO2", 123, DRV_GRP1), ++ MT7623_PIN(238, "EXT_SDIO1", 124, DRV_GRP1), ++ MT7623_PIN(239, "EXT_SDIO0", 125, DRV_GRP1), ++ MT7623_PIN(240, "EXT_XCS", 126, DRV_GRP1), ++ MT7623_PIN(241, "EXT_SCK", 127, DRV_GRP1), ++ MT7623_PIN(242, "URTS2", 128, DRV_GRP1), ++ MT7623_PIN(243, "UCTS2", 129, DRV_GRP1), ++ MT7623_PIN(244, "HDMI_SDA_RX", 130, DRV_FIXED), ++ MT7623_PIN(245, "HDMI_SCL_RX", 131, DRV_FIXED), ++ MT7623_PIN(246, "MHL_SENCE", 132, DRV_FIXED), ++ MT7623_PIN(247, "HDMI_HPD_CBUS_RX", 69, DRV_FIXED), ++ MT7623_PIN(248, "HDMI_TESTOUTP_RX", 133, DRV_GRP1), ++ MT7623_PIN(249, "MSDC0E_RSTB", 134, DRV_GRP4), ++ MT7623_PIN(250, "MSDC0E_DAT7", 135, DRV_GRP4), ++ MT7623_PIN(251, "MSDC0E_DAT6", 136, DRV_GRP4), ++ MT7623_PIN(252, "MSDC0E_DAT5", 137, DRV_GRP4), ++ MT7623_PIN(253, "MSDC0E_DAT4", 138, DRV_GRP4), ++ MT7623_PIN(254, "MSDC0E_DAT3", 139, DRV_GRP4), ++ MT7623_PIN(255, "MSDC0E_DAT2", 140, DRV_GRP4), ++ MT7623_PIN(256, "MSDC0E_DAT1", 141, DRV_GRP4), ++ MT7623_PIN(257, "MSDC0E_DAT0", 142, DRV_GRP4), ++ MT7623_PIN(258, "MSDC0E_CMD", 143, DRV_GRP4), ++ MT7623_PIN(259, "MSDC0E_CLK", 144, DRV_GRP4), ++ MT7623_PIN(260, "MSDC0E_DSL", 145, DRV_GRP4), ++ MT7623_PIN(261, "MSDC1_INS", 146, DRV_GRP4), ++ MT7623_PIN(262, "G2_TXEN", 8, DRV_GRP1), ++ MT7623_PIN(263, "G2_TXD3", 9, DRV_GRP1), ++ MT7623_PIN(264, "G2_TXD2", 10, DRV_GRP1), ++ MT7623_PIN(265, "G2_TXD1", 11, DRV_GRP1), ++ MT7623_PIN(266, "G2_TXD0", EINT_NA, DRV_GRP1), ++ MT7623_PIN(267, "G2_TXC", EINT_NA, DRV_GRP1), ++ MT7623_PIN(268, "G2_RXC", EINT_NA, DRV_GRP1), ++ MT7623_PIN(269, "G2_RXD0", EINT_NA, DRV_GRP1), ++ MT7623_PIN(270, "G2_RXD1", EINT_NA, DRV_GRP1), ++ MT7623_PIN(271, "G2_RXD2", EINT_NA, DRV_GRP1), ++ MT7623_PIN(272, "G2_RXD3", EINT_NA, DRV_GRP1), ++ MT7623_PIN(273, "ESW_INT", 168, DRV_GRP1), ++ MT7623_PIN(274, "G2_RXDV", EINT_NA, DRV_GRP1), ++ MT7623_PIN(275, "MDC", EINT_NA, DRV_GRP1), ++ MT7623_PIN(276, "MDIO", EINT_NA, DRV_GRP1), ++ MT7623_PIN(277, "ESW_RST", EINT_NA, DRV_GRP1), ++ MT7623_PIN(278, "JTAG_RESET", 147, DRV_GRP3), ++ MT7623_PIN(279, "USB3_RES_BOND", EINT_NA, DRV_GRP1), ++}; ++ ++/* List all groups consisting of these pins dedicated to the enablement of ++ * certain hardware block and the corresponding mode for all of the pins. ++ * The hardware probably has multiple combinations of these pinouts. ++ */ ++ ++/* AUDIO EXT CLK */ ++static int mt7623_aud_ext_clk0_pins[] = { 208, }; ++static int mt7623_aud_ext_clk0_funcs[] = { 1, }; ++static int mt7623_aud_ext_clk1_pins[] = { 209, }; ++static int mt7623_aud_ext_clk1_funcs[] = { 1, }; ++ ++/* DISP PWM */ ++static int mt7623_disp_pwm_0_pins[] = { 72, }; ++static int mt7623_disp_pwm_0_funcs[] = { 5, }; ++static int mt7623_disp_pwm_1_pins[] = { 203, }; ++static int mt7623_disp_pwm_1_funcs[] = { 2, }; ++static int mt7623_disp_pwm_2_pins[] = { 208, }; ++static int mt7623_disp_pwm_2_funcs[] = { 5, }; ++ ++/* ESW */ ++static int mt7623_esw_int_pins[] = { 273, }; ++static int mt7623_esw_int_funcs[] = { 1, }; ++static int mt7623_esw_rst_pins[] = { 277, }; ++static int mt7623_esw_rst_funcs[] = { 1, }; ++ ++/* EPHY */ ++static int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268, ++ 269, 270, 271, 272, 274, }; ++static int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; ++ ++/* EXT_SDIO */ ++static int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, }; ++static int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, }; ++ ++/* HDMI RX */ ++static int mt7623_hdmi_rx_pins[] = { 247, 248, }; ++static int mt7623_hdmi_rx_funcs[] = { 1, 1 }; ++static int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, }; ++static int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 }; ++ ++/* HDMI TX */ ++static int mt7623_hdmi_cec_pins[] = { 122, }; ++static int mt7623_hdmi_cec_funcs[] = { 1, }; ++static int mt7623_hdmi_htplg_pins[] = { 123, }; ++static int mt7623_hdmi_htplg_funcs[] = { 1, }; ++static int mt7623_hdmi_i2c_pins[] = { 124, 125, }; ++static int mt7623_hdmi_i2c_funcs[] = { 1, 1 }; ++ ++/* I2C */ ++static int mt7623_i2c0_pins[] = { 75, 76, }; ++static int mt7623_i2c0_funcs[] = { 1, 1, }; ++static int mt7623_i2c1_0_pins[] = { 57, 58, }; ++static int mt7623_i2c1_0_funcs[] = { 1, 1, }; ++static int mt7623_i2c1_1_pins[] = { 242, 243, }; ++static int mt7623_i2c1_1_funcs[] = { 4, 4, }; ++static int mt7623_i2c1_2_pins[] = { 85, 86, }; ++static int mt7623_i2c1_2_funcs[] = { 3, 3, }; ++static int mt7623_i2c1_3_pins[] = { 105, 106, }; ++static int mt7623_i2c1_3_funcs[] = { 3, 3, }; ++static int mt7623_i2c1_4_pins[] = { 124, 125, }; ++static int mt7623_i2c1_4_funcs[] = { 4, 4, }; ++static int mt7623_i2c2_0_pins[] = { 77, 78, }; ++static int mt7623_i2c2_0_funcs[] = { 1, 1, }; ++static int mt7623_i2c2_1_pins[] = { 89, 90, }; ++static int mt7623_i2c2_1_funcs[] = { 3, 3, }; ++static int mt7623_i2c2_2_pins[] = { 109, 110, }; ++static int mt7623_i2c2_2_funcs[] = { 3, 3, }; ++static int mt7623_i2c2_3_pins[] = { 122, 123, }; ++static int mt7623_i2c2_3_funcs[] = { 4, 4, }; ++ ++/* I2S */ ++static int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, }; ++static int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, }; ++static int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, }; ++static int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, }; ++static int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, }; ++static int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, }; ++static int mt7623_i2s2_data_in_pins[] = { 51, }; ++static int mt7623_i2s2_data_in_funcs[] = { 1, }; ++static int mt7623_i2s2_data_0_pins[] = { 203, }; ++static int mt7623_i2s2_data_0_funcs[] = { 9, }; ++static int mt7623_i2s2_data_1_pins[] = { 38, }; ++static int mt7623_i2s2_data_1_funcs[] = { 4, }; ++static int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, }; ++static int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, }; ++static int mt7623_i2s3_data_in_pins[] = { 190, }; ++static int mt7623_i2s3_data_in_funcs[] = { 1, }; ++static int mt7623_i2s3_data_0_pins[] = { 204, }; ++static int mt7623_i2s3_data_0_funcs[] = { 9, }; ++static int mt7623_i2s3_data_1_pins[] = { 2, }; ++static int mt7623_i2s3_data_1_funcs[] = { 0, }; ++static int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, }; ++static int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, }; ++static int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, }; ++static int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, }; ++ ++/* IR */ ++static int mt7623_ir_pins[] = { 46, }; ++static int mt7623_ir_funcs[] = { 1, }; ++ ++/* LCD */ ++static int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98, ++ 99, 100, }; ++static int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; ++static int mt7623_dsi_te_pins[] = { 84, }; ++static int mt7623_dsi_te_funcs[] = { 1, }; ++static int mt7623_lcm_rst_pins[] = { 83, }; ++static int mt7623_lcm_rst_funcs[] = { 1, }; ++ ++/* MDC/MDIO */ ++static int mt7623_mdc_mdio_pins[] = { 275, 276, }; ++static int mt7623_mdc_mdio_funcs[] = { 1, 1, }; ++ ++/* MSDC */ ++static int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118, ++ 119, 120, 121, }; ++static int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; ++static int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, }; ++static int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, }; ++static int mt7623_msdc1_ins_pins[] = { 261, }; ++static int mt7623_msdc1_ins_funcs[] = { 1, }; ++static int mt7623_msdc1_wp_0_pins[] = { 29, }; ++static int mt7623_msdc1_wp_0_funcs[] = { 1, }; ++static int mt7623_msdc1_wp_1_pins[] = { 55, }; ++static int mt7623_msdc1_wp_1_funcs[] = { 3, }; ++static int mt7623_msdc1_wp_2_pins[] = { 209, }; ++static int mt7623_msdc1_wp_2_funcs[] = { 2, }; ++static int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, }; ++static int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, }; ++static int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256, ++ 257, 258, 259, 260, }; ++static int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; ++ ++/* NAND */ ++static int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115, ++ 116, 117, 118, 119, 120, 121, }; ++static int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4, ++ 4, 4, }; ++static int mt7623_nandc_ceb0_pins[] = { 45, }; ++static int mt7623_nandc_ceb0_funcs[] = { 1, }; ++static int mt7623_nandc_ceb1_pins[] = { 44, }; ++static int mt7623_nandc_ceb1_funcs[] = { 1, }; ++ ++/* RTC */ ++static int mt7623_rtc_pins[] = { 10, }; ++static int mt7623_rtc_funcs[] = { 1, }; ++ ++/* OTG */ ++static int mt7623_otg_iddig0_0_pins[] = { 29, }; ++static int mt7623_otg_iddig0_0_funcs[] = { 1, }; ++static int mt7623_otg_iddig0_1_pins[] = { 44, }; ++static int mt7623_otg_iddig0_1_funcs[] = { 2, }; ++static int mt7623_otg_iddig0_2_pins[] = { 236, }; ++static int mt7623_otg_iddig0_2_funcs[] = { 2, }; ++static int mt7623_otg_iddig1_0_pins[] = { 27, }; ++static int mt7623_otg_iddig1_0_funcs[] = { 2, }; ++static int mt7623_otg_iddig1_1_pins[] = { 47, }; ++static int mt7623_otg_iddig1_1_funcs[] = { 2, }; ++static int mt7623_otg_iddig1_2_pins[] = { 238, }; ++static int mt7623_otg_iddig1_2_funcs[] = { 2, }; ++static int mt7623_otg_drv_vbus0_0_pins[] = { 28, }; ++static int mt7623_otg_drv_vbus0_0_funcs[] = { 1, }; ++static int mt7623_otg_drv_vbus0_1_pins[] = { 45, }; ++static int mt7623_otg_drv_vbus0_1_funcs[] = { 2, }; ++static int mt7623_otg_drv_vbus0_2_pins[] = { 237, }; ++static int mt7623_otg_drv_vbus0_2_funcs[] = { 2, }; ++static int mt7623_otg_drv_vbus1_0_pins[] = { 26, }; ++static int mt7623_otg_drv_vbus1_0_funcs[] = { 2, }; ++static int mt7623_otg_drv_vbus1_1_pins[] = { 48, }; ++static int mt7623_otg_drv_vbus1_1_funcs[] = { 2, }; ++static int mt7623_otg_drv_vbus1_2_pins[] = { 239, }; ++static int mt7623_otg_drv_vbus1_2_funcs[] = { 2, }; ++ ++/* PCIE */ ++static int mt7623_pcie0_0_perst_pins[] = { 208, }; ++static int mt7623_pcie0_0_perst_funcs[] = { 3, }; ++static int mt7623_pcie0_1_perst_pins[] = { 22, }; ++static int mt7623_pcie0_1_perst_funcs[] = { 2, }; ++static int mt7623_pcie1_0_perst_pins[] = { 209, }; ++static int mt7623_pcie1_0_perst_funcs[] = { 3, }; ++static int mt7623_pcie1_1_perst_pins[] = { 23, }; ++static int mt7623_pcie1_1_perst_funcs[] = { 2, }; ++static int mt7623_pcie2_0_perst_pins[] = { 24, }; ++static int mt7623_pcie2_0_perst_funcs[] = { 2, }; ++static int mt7623_pcie2_1_perst_pins[] = { 29, }; ++static int mt7623_pcie2_1_perst_funcs[] = { 6, }; ++static int mt7623_pcie0_0_wake_pins[] = { 28, }; ++static int mt7623_pcie0_0_wake_funcs[] = { 6, }; ++static int mt7623_pcie0_1_wake_pins[] = { 251, }; ++static int mt7623_pcie0_1_wake_funcs[] = { 6, }; ++static int mt7623_pcie1_0_wake_pins[] = { 27, }; ++static int mt7623_pcie1_0_wake_funcs[] = { 6, }; ++static int mt7623_pcie1_1_wake_pins[] = { 253, }; ++static int mt7623_pcie1_1_wake_funcs[] = { 6, }; ++static int mt7623_pcie2_0_wake_pins[] = { 26, }; ++static int mt7623_pcie2_0_wake_funcs[] = { 6, }; ++static int mt7623_pcie2_1_wake_pins[] = { 255, }; ++static int mt7623_pcie2_1_wake_funcs[] = { 6, }; ++static int mt7623_pcie0_clkreq_pins[] = { 250, }; ++static int mt7623_pcie0_clkreq_funcs[] = { 6, }; ++static int mt7623_pcie1_clkreq_pins[] = { 252, }; ++static int mt7623_pcie1_clkreq_funcs[] = { 6, }; ++static int mt7623_pcie2_clkreq_pins[] = { 254, }; ++static int mt7623_pcie2_clkreq_funcs[] = { 6, }; ++ ++/* the pcie_*_rev are only used for MT7623 */ ++static int mt7623_pcie0_0_rev_perst_pins[] = { 208, }; ++static int mt7623_pcie0_0_rev_perst_funcs[] = { 11, }; ++static int mt7623_pcie0_1_rev_perst_pins[] = { 22, }; ++static int mt7623_pcie0_1_rev_perst_funcs[] = { 10, }; ++static int mt7623_pcie1_0_rev_perst_pins[] = { 209, }; ++static int mt7623_pcie1_0_rev_perst_funcs[] = { 11, }; ++static int mt7623_pcie1_1_rev_perst_pins[] = { 23, }; ++static int mt7623_pcie1_1_rev_perst_funcs[] = { 10, }; ++static int mt7623_pcie2_0_rev_perst_pins[] = { 24, }; ++static int mt7623_pcie2_0_rev_perst_funcs[] = { 11, }; ++static int mt7623_pcie2_1_rev_perst_pins[] = { 29, }; ++static int mt7623_pcie2_1_rev_perst_funcs[] = { 14, }; ++ ++/* PCM */ ++static int mt7623_pcm_clk_0_pins[] = { 18, }; ++static int mt7623_pcm_clk_0_funcs[] = { 1, }; ++static int mt7623_pcm_clk_1_pins[] = { 17, }; ++static int mt7623_pcm_clk_1_funcs[] = { 3, }; ++static int mt7623_pcm_clk_2_pins[] = { 35, }; ++static int mt7623_pcm_clk_2_funcs[] = { 3, }; ++static int mt7623_pcm_clk_3_pins[] = { 50, }; ++static int mt7623_pcm_clk_3_funcs[] = { 3, }; ++static int mt7623_pcm_clk_4_pins[] = { 74, }; ++static int mt7623_pcm_clk_4_funcs[] = { 3, }; ++static int mt7623_pcm_clk_5_pins[] = { 191, }; ++static int mt7623_pcm_clk_5_funcs[] = { 3, }; ++static int mt7623_pcm_clk_6_pins[] = { 196, }; ++static int mt7623_pcm_clk_6_funcs[] = { 3, }; ++static int mt7623_pcm_sync_0_pins[] = { 19, }; ++static int mt7623_pcm_sync_0_funcs[] = { 1, }; ++static int mt7623_pcm_sync_1_pins[] = { 30, }; ++static int mt7623_pcm_sync_1_funcs[] = { 3, }; ++static int mt7623_pcm_sync_2_pins[] = { 36, }; ++static int mt7623_pcm_sync_2_funcs[] = { 3, }; ++static int mt7623_pcm_sync_3_pins[] = { 52, }; ++static int mt7623_pcm_sync_3_funcs[] = { 31, }; ++static int mt7623_pcm_sync_4_pins[] = { 73, }; ++static int mt7623_pcm_sync_4_funcs[] = { 3, }; ++static int mt7623_pcm_sync_5_pins[] = { 192, }; ++static int mt7623_pcm_sync_5_funcs[] = { 3, }; ++static int mt7623_pcm_sync_6_pins[] = { 197, }; ++static int mt7623_pcm_sync_6_funcs[] = { 3, }; ++static int mt7623_pcm_rx_0_pins[] = { 20, }; ++static int mt7623_pcm_rx_0_funcs[] = { 1, }; ++static int mt7623_pcm_rx_1_pins[] = { 16, }; ++static int mt7623_pcm_rx_1_funcs[] = { 3, }; ++static int mt7623_pcm_rx_2_pins[] = { 34, }; ++static int mt7623_pcm_rx_2_funcs[] = { 3, }; ++static int mt7623_pcm_rx_3_pins[] = { 51, }; ++static int mt7623_pcm_rx_3_funcs[] = { 3, }; ++static int mt7623_pcm_rx_4_pins[] = { 72, }; ++static int mt7623_pcm_rx_4_funcs[] = { 3, }; ++static int mt7623_pcm_rx_5_pins[] = { 190, }; ++static int mt7623_pcm_rx_5_funcs[] = { 3, }; ++static int mt7623_pcm_rx_6_pins[] = { 195, }; ++static int mt7623_pcm_rx_6_funcs[] = { 3, }; ++static int mt7623_pcm_tx_0_pins[] = { 21, }; ++static int mt7623_pcm_tx_0_funcs[] = { 1, }; ++static int mt7623_pcm_tx_1_pins[] = { 32, }; ++static int mt7623_pcm_tx_1_funcs[] = { 3, }; ++static int mt7623_pcm_tx_2_pins[] = { 33, }; ++static int mt7623_pcm_tx_2_funcs[] = { 3, }; ++static int mt7623_pcm_tx_3_pins[] = { 38, }; ++static int mt7623_pcm_tx_3_funcs[] = { 3, }; ++static int mt7623_pcm_tx_4_pins[] = { 49, }; ++static int mt7623_pcm_tx_4_funcs[] = { 3, }; ++static int mt7623_pcm_tx_5_pins[] = { 189, }; ++static int mt7623_pcm_tx_5_funcs[] = { 3, }; ++static int mt7623_pcm_tx_6_pins[] = { 194, }; ++static int mt7623_pcm_tx_6_funcs[] = { 3, }; ++ ++/* PWM */ ++static int mt7623_pwm_ch1_0_pins[] = { 203, }; ++static int mt7623_pwm_ch1_0_funcs[] = { 1, }; ++static int mt7623_pwm_ch1_1_pins[] = { 208, }; ++static int mt7623_pwm_ch1_1_funcs[] = { 2, }; ++static int mt7623_pwm_ch1_2_pins[] = { 72, }; ++static int mt7623_pwm_ch1_2_funcs[] = { 4, }; ++static int mt7623_pwm_ch1_3_pins[] = { 88, }; ++static int mt7623_pwm_ch1_3_funcs[] = { 3, }; ++static int mt7623_pwm_ch1_4_pins[] = { 108, }; ++static int mt7623_pwm_ch1_4_funcs[] = { 3, }; ++static int mt7623_pwm_ch2_0_pins[] = { 204, }; ++static int mt7623_pwm_ch2_0_funcs[] = { 1, }; ++static int mt7623_pwm_ch2_1_pins[] = { 53, }; ++static int mt7623_pwm_ch2_1_funcs[] = { 5, }; ++static int mt7623_pwm_ch2_2_pins[] = { 88, }; ++static int mt7623_pwm_ch2_2_funcs[] = { 6, }; ++static int mt7623_pwm_ch2_3_pins[] = { 108, }; ++static int mt7623_pwm_ch2_3_funcs[] = { 6, }; ++static int mt7623_pwm_ch2_4_pins[] = { 209, }; ++static int mt7623_pwm_ch2_4_funcs[] = { 5, }; ++static int mt7623_pwm_ch3_0_pins[] = { 205, }; ++static int mt7623_pwm_ch3_0_funcs[] = { 1, }; ++static int mt7623_pwm_ch3_1_pins[] = { 55, }; ++static int mt7623_pwm_ch3_1_funcs[] = { 5, }; ++static int mt7623_pwm_ch3_2_pins[] = { 89, }; ++static int mt7623_pwm_ch3_2_funcs[] = { 6, }; ++static int mt7623_pwm_ch3_3_pins[] = { 109, }; ++static int mt7623_pwm_ch3_3_funcs[] = { 6, }; ++static int mt7623_pwm_ch4_0_pins[] = { 206, }; ++static int mt7623_pwm_ch4_0_funcs[] = { 1, }; ++static int mt7623_pwm_ch4_1_pins[] = { 90, }; ++static int mt7623_pwm_ch4_1_funcs[] = { 6, }; ++static int mt7623_pwm_ch4_2_pins[] = { 110, }; ++static int mt7623_pwm_ch4_2_funcs[] = { 6, }; ++static int mt7623_pwm_ch4_3_pins[] = { 124, }; ++static int mt7623_pwm_ch4_3_funcs[] = { 5, }; ++static int mt7623_pwm_ch5_0_pins[] = { 207, }; ++static int mt7623_pwm_ch5_0_funcs[] = { 1, }; ++static int mt7623_pwm_ch5_1_pins[] = { 125, }; ++static int mt7623_pwm_ch5_1_funcs[] = { 5, }; ++ ++/* PWRAP */ ++static int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, }; ++static int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, }; ++ ++/* SPDIF */ ++static int mt7623_spdif_in0_0_pins[] = { 56, }; ++static int mt7623_spdif_in0_0_funcs[] = { 3, }; ++static int mt7623_spdif_in0_1_pins[] = { 201, }; ++static int mt7623_spdif_in0_1_funcs[] = { 1, }; ++static int mt7623_spdif_in1_0_pins[] = { 54, }; ++static int mt7623_spdif_in1_0_funcs[] = { 3, }; ++static int mt7623_spdif_in1_1_pins[] = { 202, }; ++static int mt7623_spdif_in1_1_funcs[] = { 1, }; ++static int mt7623_spdif_out_pins[] = { 202, }; ++static int mt7623_spdif_out_funcs[] = { 1, }; ++ ++/* SPI */ ++static int mt7623_spi0_pins[] = { 53, 54, 55, 56, }; ++static int mt7623_spi0_funcs[] = { 1, 1, 1, 1, }; ++static int mt7623_spi1_pins[] = { 7, 199, 8, 9, }; ++static int mt7623_spi1_funcs[] = { 1, 1, 1, 1, }; ++static int mt7623_spi2_pins[] = { 101, 104, 102, 103, }; ++static int mt7623_spi2_funcs[] = { 1, 1, 1, 1, }; ++ ++/* UART */ ++static int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, }; ++static int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, }; ++static int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, }; ++static int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, }; ++static int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, }; ++static int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, }; ++static int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, }; ++static int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, }; ++static int mt7623_uart0_rts_cts_pins[] = { 22, 23, }; ++static int mt7623_uart0_rts_cts_funcs[] = { 1, 1, }; ++static int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, }; ++static int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, }; ++static int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, }; ++static int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, }; ++static int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, }; ++static int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, }; ++static int mt7623_uart1_rts_cts_pins[] = { 24, 25, }; ++static int mt7623_uart1_rts_cts_funcs[] = { 1, 1, }; ++static int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, }; ++static int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, }; ++static int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, }; ++static int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, }; ++static int mt7623_uart2_rts_cts_pins[] = { 242, 243, }; ++static int mt7623_uart2_rts_cts_funcs[] = { 1, 1, }; ++static int mt7623_uart3_txd_rxd_pins[] = { 242, 243, }; ++static int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, }; ++static int mt7623_uart3_rts_cts_pins[] = { 26, 27, }; ++static int mt7623_uart3_rts_cts_funcs[] = { 1, 1, }; ++ ++/* Watchdog */ ++static int mt7623_watchdog_0_pins[] = { 11, }; ++static int mt7623_watchdog_0_funcs[] = { 1, }; ++static int mt7623_watchdog_1_pins[] = { 121, }; ++static int mt7623_watchdog_1_funcs[] = { 5, }; ++ ++static const struct group_desc mt7623_groups[] = { ++ PINCTRL_PIN_GROUP("aud_ext_clk0", mt7623_aud_ext_clk0), ++ PINCTRL_PIN_GROUP("aud_ext_clk1", mt7623_aud_ext_clk1), ++ PINCTRL_PIN_GROUP("dsi_te", mt7623_dsi_te), ++ PINCTRL_PIN_GROUP("disp_pwm_0", mt7623_disp_pwm_0), ++ PINCTRL_PIN_GROUP("disp_pwm_1", mt7623_disp_pwm_1), ++ PINCTRL_PIN_GROUP("disp_pwm_2", mt7623_disp_pwm_2), ++ PINCTRL_PIN_GROUP("ephy", mt7623_ephy), ++ PINCTRL_PIN_GROUP("esw_int", mt7623_esw_int), ++ PINCTRL_PIN_GROUP("esw_rst", mt7623_esw_rst), ++ PINCTRL_PIN_GROUP("ext_sdio", mt7623_ext_sdio), ++ PINCTRL_PIN_GROUP("hdmi_cec", mt7623_hdmi_cec), ++ PINCTRL_PIN_GROUP("hdmi_htplg", mt7623_hdmi_htplg), ++ PINCTRL_PIN_GROUP("hdmi_i2c", mt7623_hdmi_i2c), ++ PINCTRL_PIN_GROUP("hdmi_rx", mt7623_hdmi_rx), ++ PINCTRL_PIN_GROUP("hdmi_rx_i2c", mt7623_hdmi_rx_i2c), ++ PINCTRL_PIN_GROUP("i2c0", mt7623_i2c0), ++ PINCTRL_PIN_GROUP("i2c1_0", mt7623_i2c1_0), ++ PINCTRL_PIN_GROUP("i2c1_1", mt7623_i2c1_1), ++ PINCTRL_PIN_GROUP("i2c1_2", mt7623_i2c1_2), ++ PINCTRL_PIN_GROUP("i2c1_3", mt7623_i2c1_3), ++ PINCTRL_PIN_GROUP("i2c1_4", mt7623_i2c1_4), ++ PINCTRL_PIN_GROUP("i2c2_0", mt7623_i2c2_0), ++ PINCTRL_PIN_GROUP("i2c2_1", mt7623_i2c2_1), ++ PINCTRL_PIN_GROUP("i2c2_2", mt7623_i2c2_2), ++ PINCTRL_PIN_GROUP("i2c2_3", mt7623_i2c2_3), ++ PINCTRL_PIN_GROUP("i2s0", mt7623_i2s0), ++ PINCTRL_PIN_GROUP("i2s1", mt7623_i2s1), ++ PINCTRL_PIN_GROUP("i2s4", mt7623_i2s4), ++ PINCTRL_PIN_GROUP("i2s5", mt7623_i2s5), ++ PINCTRL_PIN_GROUP("i2s2_bclk_lrclk_mclk", mt7623_i2s2_bclk_lrclk_mclk), ++ PINCTRL_PIN_GROUP("i2s3_bclk_lrclk_mclk", mt7623_i2s3_bclk_lrclk_mclk), ++ PINCTRL_PIN_GROUP("i2s2_data_in", mt7623_i2s2_data_in), ++ PINCTRL_PIN_GROUP("i2s3_data_in", mt7623_i2s3_data_in), ++ PINCTRL_PIN_GROUP("i2s2_data_0", mt7623_i2s2_data_0), ++ PINCTRL_PIN_GROUP("i2s2_data_1", mt7623_i2s2_data_1), ++ PINCTRL_PIN_GROUP("i2s3_data_0", mt7623_i2s3_data_0), ++ PINCTRL_PIN_GROUP("i2s3_data_1", mt7623_i2s3_data_1), ++ PINCTRL_PIN_GROUP("ir", mt7623_ir), ++ PINCTRL_PIN_GROUP("lcm_rst", mt7623_lcm_rst), ++ PINCTRL_PIN_GROUP("mdc_mdio", mt7623_mdc_mdio), ++ PINCTRL_PIN_GROUP("mipi_tx", mt7623_mipi_tx), ++ PINCTRL_PIN_GROUP("msdc0", mt7623_msdc0), ++ PINCTRL_PIN_GROUP("msdc1", mt7623_msdc1), ++ PINCTRL_PIN_GROUP("msdc1_ins", mt7623_msdc1_ins), ++ PINCTRL_PIN_GROUP("msdc1_wp_0", mt7623_msdc1_wp_0), ++ PINCTRL_PIN_GROUP("msdc1_wp_1", mt7623_msdc1_wp_1), ++ PINCTRL_PIN_GROUP("msdc1_wp_2", mt7623_msdc1_wp_2), ++ PINCTRL_PIN_GROUP("msdc2", mt7623_msdc2), ++ PINCTRL_PIN_GROUP("msdc3", mt7623_msdc3), ++ PINCTRL_PIN_GROUP("nandc", mt7623_nandc), ++ PINCTRL_PIN_GROUP("nandc_ceb0", mt7623_nandc_ceb0), ++ PINCTRL_PIN_GROUP("nandc_ceb1", mt7623_nandc_ceb1), ++ PINCTRL_PIN_GROUP("otg_iddig0_0", mt7623_otg_iddig0_0), ++ PINCTRL_PIN_GROUP("otg_iddig0_1", mt7623_otg_iddig0_1), ++ PINCTRL_PIN_GROUP("otg_iddig0_2", mt7623_otg_iddig0_2), ++ PINCTRL_PIN_GROUP("otg_iddig1_0", mt7623_otg_iddig1_0), ++ PINCTRL_PIN_GROUP("otg_iddig1_1", mt7623_otg_iddig1_1), ++ PINCTRL_PIN_GROUP("otg_iddig1_2", mt7623_otg_iddig1_2), ++ PINCTRL_PIN_GROUP("otg_drv_vbus0_0", mt7623_otg_drv_vbus0_0), ++ PINCTRL_PIN_GROUP("otg_drv_vbus0_1", mt7623_otg_drv_vbus0_1), ++ PINCTRL_PIN_GROUP("otg_drv_vbus0_2", mt7623_otg_drv_vbus0_2), ++ PINCTRL_PIN_GROUP("otg_drv_vbus1_0", mt7623_otg_drv_vbus1_0), ++ PINCTRL_PIN_GROUP("otg_drv_vbus1_1", mt7623_otg_drv_vbus1_1), ++ PINCTRL_PIN_GROUP("otg_drv_vbus1_2", mt7623_otg_drv_vbus1_2), ++ PINCTRL_PIN_GROUP("pcie0_0_perst", mt7623_pcie0_0_perst), ++ PINCTRL_PIN_GROUP("pcie0_1_perst", mt7623_pcie0_1_perst), ++ PINCTRL_PIN_GROUP("pcie1_0_perst", mt7623_pcie1_0_perst), ++ PINCTRL_PIN_GROUP("pcie1_1_perst", mt7623_pcie1_1_perst), ++ PINCTRL_PIN_GROUP("pcie1_1_perst", mt7623_pcie1_1_perst), ++ PINCTRL_PIN_GROUP("pcie0_0_rev_perst", mt7623_pcie0_0_rev_perst), ++ PINCTRL_PIN_GROUP("pcie0_1_rev_perst", mt7623_pcie0_1_rev_perst), ++ PINCTRL_PIN_GROUP("pcie1_0_rev_perst", mt7623_pcie1_0_rev_perst), ++ PINCTRL_PIN_GROUP("pcie1_1_rev_perst", mt7623_pcie1_1_rev_perst), ++ PINCTRL_PIN_GROUP("pcie2_0_rev_perst", mt7623_pcie2_0_rev_perst), ++ PINCTRL_PIN_GROUP("pcie2_1_rev_perst", mt7623_pcie2_1_rev_perst), ++ PINCTRL_PIN_GROUP("pcie2_0_perst", mt7623_pcie2_0_perst), ++ PINCTRL_PIN_GROUP("pcie2_1_perst", mt7623_pcie2_1_perst), ++ PINCTRL_PIN_GROUP("pcie0_0_wake", mt7623_pcie0_0_wake), ++ PINCTRL_PIN_GROUP("pcie0_1_wake", mt7623_pcie0_1_wake), ++ PINCTRL_PIN_GROUP("pcie1_0_wake", mt7623_pcie1_0_wake), ++ PINCTRL_PIN_GROUP("pcie1_1_wake", mt7623_pcie1_1_wake), ++ PINCTRL_PIN_GROUP("pcie2_0_wake", mt7623_pcie2_0_wake), ++ PINCTRL_PIN_GROUP("pcie2_1_wake", mt7623_pcie2_1_wake), ++ PINCTRL_PIN_GROUP("pcie0_clkreq", mt7623_pcie0_clkreq), ++ PINCTRL_PIN_GROUP("pcie1_clkreq", mt7623_pcie1_clkreq), ++ PINCTRL_PIN_GROUP("pcie2_clkreq", mt7623_pcie2_clkreq), ++ PINCTRL_PIN_GROUP("pcm_clk_0", mt7623_pcm_clk_0), ++ PINCTRL_PIN_GROUP("pcm_clk_1", mt7623_pcm_clk_1), ++ PINCTRL_PIN_GROUP("pcm_clk_2", mt7623_pcm_clk_2), ++ PINCTRL_PIN_GROUP("pcm_clk_3", mt7623_pcm_clk_3), ++ PINCTRL_PIN_GROUP("pcm_clk_4", mt7623_pcm_clk_4), ++ PINCTRL_PIN_GROUP("pcm_clk_5", mt7623_pcm_clk_5), ++ PINCTRL_PIN_GROUP("pcm_clk_6", mt7623_pcm_clk_6), ++ PINCTRL_PIN_GROUP("pcm_sync_0", mt7623_pcm_sync_0), ++ PINCTRL_PIN_GROUP("pcm_sync_1", mt7623_pcm_sync_1), ++ PINCTRL_PIN_GROUP("pcm_sync_2", mt7623_pcm_sync_2), ++ PINCTRL_PIN_GROUP("pcm_sync_3", mt7623_pcm_sync_3), ++ PINCTRL_PIN_GROUP("pcm_sync_4", mt7623_pcm_sync_4), ++ PINCTRL_PIN_GROUP("pcm_sync_5", mt7623_pcm_sync_5), ++ PINCTRL_PIN_GROUP("pcm_sync_6", mt7623_pcm_sync_6), ++ PINCTRL_PIN_GROUP("pcm_rx_0", mt7623_pcm_rx_0), ++ PINCTRL_PIN_GROUP("pcm_rx_1", mt7623_pcm_rx_1), ++ PINCTRL_PIN_GROUP("pcm_rx_2", mt7623_pcm_rx_2), ++ PINCTRL_PIN_GROUP("pcm_rx_3", mt7623_pcm_rx_3), ++ PINCTRL_PIN_GROUP("pcm_rx_4", mt7623_pcm_rx_4), ++ PINCTRL_PIN_GROUP("pcm_rx_5", mt7623_pcm_rx_5), ++ PINCTRL_PIN_GROUP("pcm_rx_6", mt7623_pcm_rx_6), ++ PINCTRL_PIN_GROUP("pcm_tx_0", mt7623_pcm_tx_0), ++ PINCTRL_PIN_GROUP("pcm_tx_1", mt7623_pcm_tx_1), ++ PINCTRL_PIN_GROUP("pcm_tx_2", mt7623_pcm_tx_2), ++ PINCTRL_PIN_GROUP("pcm_tx_3", mt7623_pcm_tx_3), ++ PINCTRL_PIN_GROUP("pcm_tx_4", mt7623_pcm_tx_4), ++ PINCTRL_PIN_GROUP("pcm_tx_5", mt7623_pcm_tx_5), ++ PINCTRL_PIN_GROUP("pcm_tx_6", mt7623_pcm_tx_6), ++ PINCTRL_PIN_GROUP("pwm_ch1_0", mt7623_pwm_ch1_0), ++ PINCTRL_PIN_GROUP("pwm_ch1_1", mt7623_pwm_ch1_1), ++ PINCTRL_PIN_GROUP("pwm_ch1_2", mt7623_pwm_ch1_2), ++ PINCTRL_PIN_GROUP("pwm_ch1_3", mt7623_pwm_ch1_3), ++ PINCTRL_PIN_GROUP("pwm_ch1_4", mt7623_pwm_ch1_4), ++ PINCTRL_PIN_GROUP("pwm_ch2_0", mt7623_pwm_ch2_0), ++ PINCTRL_PIN_GROUP("pwm_ch2_1", mt7623_pwm_ch2_1), ++ PINCTRL_PIN_GROUP("pwm_ch2_2", mt7623_pwm_ch2_2), ++ PINCTRL_PIN_GROUP("pwm_ch2_3", mt7623_pwm_ch2_3), ++ PINCTRL_PIN_GROUP("pwm_ch2_4", mt7623_pwm_ch2_4), ++ PINCTRL_PIN_GROUP("pwm_ch3_0", mt7623_pwm_ch3_0), ++ PINCTRL_PIN_GROUP("pwm_ch3_1", mt7623_pwm_ch3_1), ++ PINCTRL_PIN_GROUP("pwm_ch3_2", mt7623_pwm_ch3_2), ++ PINCTRL_PIN_GROUP("pwm_ch3_3", mt7623_pwm_ch3_3), ++ PINCTRL_PIN_GROUP("pwm_ch4_0", mt7623_pwm_ch4_0), ++ PINCTRL_PIN_GROUP("pwm_ch4_1", mt7623_pwm_ch4_1), ++ PINCTRL_PIN_GROUP("pwm_ch4_2", mt7623_pwm_ch4_2), ++ PINCTRL_PIN_GROUP("pwm_ch4_3", mt7623_pwm_ch4_3), ++ PINCTRL_PIN_GROUP("pwm_ch5_0", mt7623_pwm_ch5_0), ++ PINCTRL_PIN_GROUP("pwm_ch5_1", mt7623_pwm_ch5_1), ++ PINCTRL_PIN_GROUP("pwrap", mt7623_pwrap), ++ PINCTRL_PIN_GROUP("rtc", mt7623_rtc), ++ PINCTRL_PIN_GROUP("spdif_in0_0", mt7623_spdif_in0_0), ++ PINCTRL_PIN_GROUP("spdif_in0_1", mt7623_spdif_in0_1), ++ PINCTRL_PIN_GROUP("spdif_in1_0", mt7623_spdif_in1_0), ++ PINCTRL_PIN_GROUP("spdif_in1_1", mt7623_spdif_in1_1), ++ PINCTRL_PIN_GROUP("spdif_out", mt7623_spdif_out), ++ PINCTRL_PIN_GROUP("spi0", mt7623_spi0), ++ PINCTRL_PIN_GROUP("spi1", mt7623_spi1), ++ PINCTRL_PIN_GROUP("spi2", mt7623_spi2), ++ PINCTRL_PIN_GROUP("uart0_0_txd_rxd", mt7623_uart0_0_txd_rxd), ++ PINCTRL_PIN_GROUP("uart0_1_txd_rxd", mt7623_uart0_1_txd_rxd), ++ PINCTRL_PIN_GROUP("uart0_2_txd_rxd", mt7623_uart0_2_txd_rxd), ++ PINCTRL_PIN_GROUP("uart0_3_txd_rxd", mt7623_uart0_3_txd_rxd), ++ PINCTRL_PIN_GROUP("uart1_0_txd_rxd", mt7623_uart1_0_txd_rxd), ++ PINCTRL_PIN_GROUP("uart1_1_txd_rxd", mt7623_uart1_1_txd_rxd), ++ PINCTRL_PIN_GROUP("uart1_2_txd_rxd", mt7623_uart1_2_txd_rxd), ++ PINCTRL_PIN_GROUP("uart2_0_txd_rxd", mt7623_uart2_0_txd_rxd), ++ PINCTRL_PIN_GROUP("uart2_1_txd_rxd", mt7623_uart2_1_txd_rxd), ++ PINCTRL_PIN_GROUP("uart3_txd_rxd", mt7623_uart3_txd_rxd), ++ PINCTRL_PIN_GROUP("uart0_rts_cts", mt7623_uart0_rts_cts), ++ PINCTRL_PIN_GROUP("uart1_rts_cts", mt7623_uart1_rts_cts), ++ PINCTRL_PIN_GROUP("uart2_rts_cts", mt7623_uart2_rts_cts), ++ PINCTRL_PIN_GROUP("uart3_rts_cts", mt7623_uart3_rts_cts), ++ PINCTRL_PIN_GROUP("watchdog_0", mt7623_watchdog_0), ++ PINCTRL_PIN_GROUP("watchdog_1", mt7623_watchdog_1), ++}; ++ ++/* Joint those groups owning the same capability in user point of view which ++ * allows that people tend to use through the device tree. ++ */ ++static const char *mt7623_aud_clk_groups[] = { "aud_ext_clk0", ++ "aud_ext_clk1", }; ++static const char *mt7623_disp_pwm_groups[] = { "disp_pwm_0", "disp_pwm_1", ++ "disp_pwm_2", }; ++static const char *mt7623_ethernet_groups[] = { "esw_int", "esw_rst", ++ "ephy", "mdc_mdio", }; ++static const char *mt7623_ext_sdio_groups[] = { "ext_sdio", }; ++static const char *mt7623_hdmi_groups[] = { "hdmi_cec", "hdmi_htplg", ++ "hdmi_i2c", "hdmi_rx", ++ "hdmi_rx_i2c", }; ++static const char *mt7623_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1", ++ "i2c1_2", "i2c1_3", "i2c1_4", ++ "i2c2_0", "i2c2_1", "i2c2_2", ++ "i2c2_3", }; ++static const char *mt7623_i2s_groups[] = { "i2s0", "i2s1", ++ "i2s2_bclk_lrclk_mclk", ++ "i2s3_bclk_lrclk_mclk", ++ "i2s4", "i2s5", ++ "i2s2_data_in", "i2s3_data_in", ++ "i2s2_data_0", "i2s2_data_1", ++ "i2s3_data_0", "i2s3_data_1", }; ++static const char *mt7623_ir_groups[] = { "ir", }; ++static const char *mt7623_lcd_groups[] = { "dsi_te", "lcm_rst", "mipi_tx", }; ++static const char *mt7623_msdc_groups[] = { "msdc0", "msdc1", "msdc1_ins", ++ "msdc1_wp_0", "msdc1_wp_1", ++ "msdc1_wp_2", "msdc2", ++ "msdc3", }; ++static const char *mt7623_nandc_groups[] = { "nandc", "nandc_ceb0", ++ "nandc_ceb1", }; ++static const char *mt7623_otg_groups[] = { "otg_iddig0_0", "otg_iddig0_1", ++ "otg_iddig0_2", "otg_iddig1_0", ++ "otg_iddig1_1", "otg_iddig1_2", ++ "otg_drv_vbus0_0", ++ "otg_drv_vbus0_1", ++ "otg_drv_vbus0_2", ++ "otg_drv_vbus1_0", ++ "otg_drv_vbus1_1", ++ "otg_drv_vbus1_2", }; ++static const char *mt7623_pcie_groups[] = { "pcie0_0_perst", "pcie0_1_perst", ++ "pcie1_0_perst", "pcie1_1_perst", ++ "pcie2_0_perst", "pcie2_1_perst", ++ "pcie0_0_rev_perst", ++ "pcie0_1_rev_perst", ++ "pcie1_0_rev_perst", ++ "pcie1_1_rev_perst", ++ "pcie2_0_rev_perst", ++ "pcie2_1_rev_perst", ++ "pcie0_0_wake", "pcie0_1_wake", ++ "pcie2_0_wake", "pcie2_1_wake", ++ "pcie0_clkreq", "pcie1_clkreq", ++ "pcie2_clkreq", }; ++static const char *mt7623_pcm_groups[] = { "pcm_clk_0", "pcm_clk_1", ++ "pcm_clk_2", "pcm_clk_3", ++ "pcm_clk_4", "pcm_clk_5", ++ "pcm_clk_6", "pcm_sync_0", ++ "pcm_sync_1", "pcm_sync_2", ++ "pcm_sync_3", "pcm_sync_4", ++ "pcm_sync_5", "pcm_sync_6", ++ "pcm_rx_0", "pcm_rx_1", ++ "pcm_rx_2", "pcm_rx_3", ++ "pcm_rx_4", "pcm_rx_5", ++ "pcm_rx_6", "pcm_tx_0", ++ "pcm_tx_1", "pcm_tx_2", ++ "pcm_tx_3", "pcm_tx_4", ++ "pcm_tx_5", "pcm_tx_6", }; ++static const char *mt7623_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1", ++ "pwm_ch1_2", "pwm_ch2_0", ++ "pwm_ch2_1", "pwm_ch2_2", ++ "pwm_ch3_0", "pwm_ch3_1", ++ "pwm_ch3_2", "pwm_ch4_0", ++ "pwm_ch4_1", "pwm_ch4_2", ++ "pwm_ch4_3", "pwm_ch5_0", ++ "pwm_ch5_1", "pwm_ch5_2", ++ "pwm_ch6_0", "pwm_ch6_1", ++ "pwm_ch6_2", "pwm_ch6_3", ++ "pwm_ch7_0", "pwm_ch7_1", ++ "pwm_ch7_2", }; ++static const char *mt7623_pwrap_groups[] = { "pwrap", }; ++static const char *mt7623_rtc_groups[] = { "rtc", }; ++static const char *mt7623_spi_groups[] = { "spi0", "spi2", "spi2", }; ++static const char *mt7623_spdif_groups[] = { "spdif_in0_0", "spdif_in0_1", ++ "spdif_in1_0", "spdif_in1_1", ++ "spdif_out", }; ++static const char *mt7623_uart_groups[] = { "uart0_0_txd_rxd", ++ "uart0_1_txd_rxd", ++ "uart0_2_txd_rxd", ++ "uart0_3_txd_rxd", ++ "uart1_0_txd_rxd", ++ "uart1_1_txd_rxd", ++ "uart1_2_txd_rxd", ++ "uart2_0_txd_rxd", ++ "uart2_1_txd_rxd", ++ "uart3_txd_rxd", ++ "uart0_rts_cts", ++ "uart1_rts_cts", ++ "uart2_rts_cts", ++ "uart3_rts_cts", }; ++static const char *mt7623_wdt_groups[] = { "watchdog_0", "watchdog_1", }; ++ ++static const struct function_desc mt7623_functions[] = { ++ {"audck", mt7623_aud_clk_groups, ARRAY_SIZE(mt7623_aud_clk_groups)}, ++ {"disp", mt7623_disp_pwm_groups, ARRAY_SIZE(mt7623_disp_pwm_groups)}, ++ {"eth", mt7623_ethernet_groups, ARRAY_SIZE(mt7623_ethernet_groups)}, ++ {"sdio", mt7623_ext_sdio_groups, ARRAY_SIZE(mt7623_ext_sdio_groups)}, ++ {"hdmi", mt7623_hdmi_groups, ARRAY_SIZE(mt7623_hdmi_groups)}, ++ {"i2c", mt7623_i2c_groups, ARRAY_SIZE(mt7623_i2c_groups)}, ++ {"i2s", mt7623_i2s_groups, ARRAY_SIZE(mt7623_i2s_groups)}, ++ {"ir", mt7623_ir_groups, ARRAY_SIZE(mt7623_ir_groups)}, ++ {"lcd", mt7623_lcd_groups, ARRAY_SIZE(mt7623_lcd_groups)}, ++ {"msdc", mt7623_msdc_groups, ARRAY_SIZE(mt7623_msdc_groups)}, ++ {"nand", mt7623_nandc_groups, ARRAY_SIZE(mt7623_nandc_groups)}, ++ {"otg", mt7623_otg_groups, ARRAY_SIZE(mt7623_otg_groups)}, ++ {"pcie", mt7623_pcie_groups, ARRAY_SIZE(mt7623_pcie_groups)}, ++ {"pcm", mt7623_pcm_groups, ARRAY_SIZE(mt7623_pcm_groups)}, ++ {"pwm", mt7623_pwm_groups, ARRAY_SIZE(mt7623_pwm_groups)}, ++ {"pwrap", mt7623_pwrap_groups, ARRAY_SIZE(mt7623_pwrap_groups)}, ++ {"rtc", mt7623_rtc_groups, ARRAY_SIZE(mt7623_rtc_groups)}, ++ {"spi", mt7623_spi_groups, ARRAY_SIZE(mt7623_spi_groups)}, ++ {"spdif", mt7623_spdif_groups, ARRAY_SIZE(mt7623_spdif_groups)}, ++ {"uart", mt7623_uart_groups, ARRAY_SIZE(mt7623_uart_groups)}, ++ {"watchdog", mt7623_wdt_groups, ARRAY_SIZE(mt7623_wdt_groups)}, ++}; ++ ++static const struct mtk_eint_hw mt7623_eint_hw = { ++ .port_mask = 6, ++ .ports = 6, ++ .ap_num = 169, ++ .db_cnt = 20, ++}; ++ ++static struct mtk_pin_soc mt7623_data = { ++ .reg_cal = mt7623_reg_cals, ++ .pins = mt7623_pins, ++ .npins = ARRAY_SIZE(mt7623_pins), ++ .grps = mt7623_groups, ++ .ngrps = ARRAY_SIZE(mt7623_groups), ++ .funcs = mt7623_functions, ++ .nfuncs = ARRAY_SIZE(mt7623_functions), ++ .eint_hw = &mt7623_eint_hw, ++ .gpio_m = 0, ++ .ies_present = true, ++ .base_names = mtk_default_register_base_names, ++ .nbase_names = ARRAY_SIZE(mtk_default_register_base_names), ++ .bias_disable_set = mtk_pinconf_bias_disable_set_rev1, ++ .bias_disable_get = mtk_pinconf_bias_disable_get_rev1, ++ .bias_set = mtk_pinconf_bias_set_rev1, ++ .bias_get = mtk_pinconf_bias_get_rev1, ++ .drive_set = mtk_pinconf_drive_set_rev1, ++ .drive_get = mtk_pinconf_drive_get_rev1, ++ .adv_pull_get = mtk_pinconf_adv_pull_get, ++ .adv_pull_set = mtk_pinconf_adv_pull_set, ++}; ++ ++/* ++ * There are some specific pins have mux functions greater than 8, ++ * and if we want to switch thees high modes we need to disable ++ * bonding constraints firstly. ++ */ ++static void mt7623_bonding_disable(struct platform_device *pdev) ++{ ++ struct mtk_pinctrl *hw = platform_get_drvdata(pdev); ++ ++ mtk_rmw(hw, 0, PIN_BOND_REG0, BOND_PCIE_CLR, BOND_PCIE_CLR); ++ mtk_rmw(hw, 0, PIN_BOND_REG1, BOND_I2S_CLR, BOND_I2S_CLR); ++ mtk_rmw(hw, 0, PIN_BOND_REG2, BOND_MSDC0E_CLR, BOND_MSDC0E_CLR); ++} ++ ++static const struct of_device_id mt7623_pctrl_match[] = { ++ { .compatible = "mediatek,mt7623-moore-pinctrl", }, ++ {} ++}; ++ ++static int mt7623_pinctrl_probe(struct platform_device *pdev) ++{ ++ int err; ++ ++ err = mtk_moore_pinctrl_probe(pdev, &mt7623_data); ++ if (err) ++ return err; ++ ++ mt7623_bonding_disable(pdev); ++ ++ return 0; ++} ++ ++static struct platform_driver mtk_pinctrl_driver = { ++ .probe = mt7623_pinctrl_probe, ++ .driver = { ++ .name = "mt7623-moore-pinctrl", ++ .of_match_table = mt7623_pctrl_match, ++ }, ++}; ++ ++static int __init mtk_pinctrl_init(void) ++{ ++ return platform_driver_register(&mtk_pinctrl_driver); ++} ++arch_initcall(mtk_pinctrl_init); +diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7629.c b/drivers/pinctrl/mediatek/pinctrl-mt7629.c +new file mode 100644 +index 000000000000..b5f0fa43245f +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c +@@ -0,0 +1,450 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * The MT7629 driver based on Linux generic pinctrl binding. ++ * ++ * Copyright (C) 2018 MediaTek Inc. ++ * Author: Ryder Lee <ryder.lee@mediatek.com> ++ */ ++ ++#include "pinctrl-moore.h" ++ ++#define MT7629_PIN(_number, _name, _eint_n) \ ++ MTK_PIN(_number, _name, 0, _eint_n, DRV_GRP1) ++ ++static const struct mtk_pin_field_calc mt7629_pin_mode_range[] = { ++ PIN_FIELD(0, 78, 0x300, 0x10, 0, 4), ++}; ++ ++static const struct mtk_pin_field_calc mt7629_pin_dir_range[] = { ++ PIN_FIELD(0, 78, 0x0, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7629_pin_di_range[] = { ++ PIN_FIELD(0, 78, 0x200, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7629_pin_do_range[] = { ++ PIN_FIELD(0, 78, 0x100, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7629_pin_ies_range[] = { ++ PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1), ++ PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1), ++ PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1), ++ PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1), ++ PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1), ++ PIN_FIELD(51, 69, 0x6000, 0x10, 0, 1), ++ PIN_FIELD(70, 78, 0x7000, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7629_pin_smt_range[] = { ++ PIN_FIELD(0, 10, 0x1100, 0x10, 0, 1), ++ PIN_FIELD(11, 18, 0x2100, 0x10, 0, 1), ++ PIN_FIELD(19, 32, 0x3100, 0x10, 0, 1), ++ PIN_FIELD(33, 48, 0x4100, 0x10, 0, 1), ++ PIN_FIELD(49, 50, 0x5100, 0x10, 0, 1), ++ PIN_FIELD(51, 69, 0x6100, 0x10, 0, 1), ++ PIN_FIELD(70, 78, 0x7100, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7629_pin_pullen_range[] = { ++ PIN_FIELD(0, 10, 0x1400, 0x10, 0, 1), ++ PIN_FIELD(11, 18, 0x2400, 0x10, 0, 1), ++ PIN_FIELD(19, 32, 0x3400, 0x10, 0, 1), ++ PIN_FIELD(33, 48, 0x4400, 0x10, 0, 1), ++ PIN_FIELD(49, 50, 0x5400, 0x10, 0, 1), ++ PIN_FIELD(51, 69, 0x6400, 0x10, 0, 1), ++ PIN_FIELD(70, 78, 0x7400, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7629_pin_pullsel_range[] = { ++ PIN_FIELD(0, 10, 0x1500, 0x10, 0, 1), ++ PIN_FIELD(11, 18, 0x2500, 0x10, 0, 1), ++ PIN_FIELD(19, 32, 0x3500, 0x10, 0, 1), ++ PIN_FIELD(33, 48, 0x4500, 0x10, 0, 1), ++ PIN_FIELD(49, 50, 0x5500, 0x10, 0, 1), ++ PIN_FIELD(51, 69, 0x6500, 0x10, 0, 1), ++ PIN_FIELD(70, 78, 0x7500, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7629_pin_drv_range[] = { ++ PIN_FIELD(0, 10, 0x1600, 0x10, 0, 4), ++ PIN_FIELD(11, 18, 0x2600, 0x10, 0, 4), ++ PIN_FIELD(19, 32, 0x3600, 0x10, 0, 4), ++ PIN_FIELD(33, 48, 0x4600, 0x10, 0, 4), ++ PIN_FIELD(49, 50, 0x5600, 0x10, 0, 4), ++ PIN_FIELD(51, 69, 0x6600, 0x10, 0, 4), ++ PIN_FIELD(70, 78, 0x7600, 0x10, 0, 4), ++}; ++ ++static const struct mtk_pin_field_calc mt7629_pin_tdsel_range[] = { ++ PIN_FIELD(0, 10, 0x1200, 0x10, 0, 4), ++ PIN_FIELD(11, 18, 0x2200, 0x10, 0, 4), ++ PIN_FIELD(19, 32, 0x3200, 0x10, 0, 4), ++ PIN_FIELD(33, 48, 0x4200, 0x10, 0, 4), ++ PIN_FIELD(49, 50, 0x5200, 0x10, 0, 4), ++ PIN_FIELD(51, 69, 0x6200, 0x10, 0, 4), ++ PIN_FIELD(70, 78, 0x7200, 0x10, 0, 4), ++}; ++ ++static const struct mtk_pin_field_calc mt7629_pin_rdsel_range[] = { ++ PIN_FIELD(0, 10, 0x1300, 0x10, 0, 4), ++ PIN_FIELD(11, 18, 0x2300, 0x10, 0, 4), ++ PIN_FIELD(19, 32, 0x3300, 0x10, 0, 4), ++ PIN_FIELD(33, 48, 0x4300, 0x10, 0, 4), ++ PIN_FIELD(49, 50, 0x5300, 0x10, 0, 4), ++ PIN_FIELD(51, 69, 0x6300, 0x10, 0, 4), ++ PIN_FIELD(70, 78, 0x7300, 0x10, 0, 4), ++}; ++ ++static const struct mtk_pin_reg_calc mt7629_reg_cals[] = { ++ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7629_pin_mode_range), ++ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7629_pin_dir_range), ++ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7629_pin_di_range), ++ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7629_pin_do_range), ++ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7629_pin_ies_range), ++ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7629_pin_smt_range), ++ [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7629_pin_pullsel_range), ++ [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7629_pin_pullen_range), ++ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7629_pin_drv_range), ++ [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7629_pin_tdsel_range), ++ [PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt7629_pin_rdsel_range), ++}; ++ ++static const struct mtk_pin_desc mt7629_pins[] = { ++ MT7629_PIN(0, "TOP_5G_CLK", 53), ++ MT7629_PIN(1, "TOP_5G_DATA", 54), ++ MT7629_PIN(2, "WF0_5G_HB0", 55), ++ MT7629_PIN(3, "WF0_5G_HB1", 56), ++ MT7629_PIN(4, "WF0_5G_HB2", 57), ++ MT7629_PIN(5, "WF0_5G_HB3", 58), ++ MT7629_PIN(6, "WF0_5G_HB4", 59), ++ MT7629_PIN(7, "WF0_5G_HB5", 60), ++ MT7629_PIN(8, "WF0_5G_HB6", 61), ++ MT7629_PIN(9, "XO_REQ", 9), ++ MT7629_PIN(10, "TOP_RST_N", 10), ++ MT7629_PIN(11, "SYS_WATCHDOG", 11), ++ MT7629_PIN(12, "EPHY_LED0_N_JTDO", 12), ++ MT7629_PIN(13, "EPHY_LED1_N_JTDI", 13), ++ MT7629_PIN(14, "EPHY_LED2_N_JTMS", 14), ++ MT7629_PIN(15, "EPHY_LED3_N_JTCLK", 15), ++ MT7629_PIN(16, "EPHY_LED4_N_JTRST_N", 16), ++ MT7629_PIN(17, "WF2G_LED_N", 17), ++ MT7629_PIN(18, "WF5G_LED_N", 18), ++ MT7629_PIN(19, "I2C_SDA", 19), ++ MT7629_PIN(20, "I2C_SCL", 20), ++ MT7629_PIN(21, "GPIO_9", 21), ++ MT7629_PIN(22, "GPIO_10", 22), ++ MT7629_PIN(23, "GPIO_11", 23), ++ MT7629_PIN(24, "GPIO_12", 24), ++ MT7629_PIN(25, "UART1_TXD", 25), ++ MT7629_PIN(26, "UART1_RXD", 26), ++ MT7629_PIN(27, "UART1_CTS", 27), ++ MT7629_PIN(28, "UART1_RTS", 28), ++ MT7629_PIN(29, "UART2_TXD", 29), ++ MT7629_PIN(30, "UART2_RXD", 30), ++ MT7629_PIN(31, "UART2_CTS", 31), ++ MT7629_PIN(32, "UART2_RTS", 32), ++ MT7629_PIN(33, "MDI_TP_P1", 33), ++ MT7629_PIN(34, "MDI_TN_P1", 34), ++ MT7629_PIN(35, "MDI_RP_P1", 35), ++ MT7629_PIN(36, "MDI_RN_P1", 36), ++ MT7629_PIN(37, "MDI_RP_P2", 37), ++ MT7629_PIN(38, "MDI_RN_P2", 38), ++ MT7629_PIN(39, "MDI_TP_P2", 39), ++ MT7629_PIN(40, "MDI_TN_P2", 40), ++ MT7629_PIN(41, "MDI_TP_P3", 41), ++ MT7629_PIN(42, "MDI_TN_P3", 42), ++ MT7629_PIN(43, "MDI_RP_P3", 43), ++ MT7629_PIN(44, "MDI_RN_P3", 44), ++ MT7629_PIN(45, "MDI_RP_P4", 45), ++ MT7629_PIN(46, "MDI_RN_P4", 46), ++ MT7629_PIN(47, "MDI_TP_P4", 47), ++ MT7629_PIN(48, "MDI_TN_P4", 48), ++ MT7629_PIN(49, "SMI_MDC", 49), ++ MT7629_PIN(50, "SMI_MDIO", 50), ++ MT7629_PIN(51, "PCIE_PERESET_N", 51), ++ MT7629_PIN(52, "PWM_0", 52), ++ MT7629_PIN(53, "GPIO_0", 0), ++ MT7629_PIN(54, "GPIO_1", 1), ++ MT7629_PIN(55, "GPIO_2", 2), ++ MT7629_PIN(56, "GPIO_3", 3), ++ MT7629_PIN(57, "GPIO_4", 4), ++ MT7629_PIN(58, "GPIO_5", 5), ++ MT7629_PIN(59, "GPIO_6", 6), ++ MT7629_PIN(60, "GPIO_7", 7), ++ MT7629_PIN(61, "GPIO_8", 8), ++ MT7629_PIN(62, "SPI_CLK", 62), ++ MT7629_PIN(63, "SPI_CS", 63), ++ MT7629_PIN(64, "SPI_MOSI", 64), ++ MT7629_PIN(65, "SPI_MISO", 65), ++ MT7629_PIN(66, "SPI_WP", 66), ++ MT7629_PIN(67, "SPI_HOLD", 67), ++ MT7629_PIN(68, "UART0_TXD", 68), ++ MT7629_PIN(69, "UART0_RXD", 69), ++ MT7629_PIN(70, "TOP_2G_CLK", 70), ++ MT7629_PIN(71, "TOP_2G_DATA", 71), ++ MT7629_PIN(72, "WF0_2G_HB0", 72), ++ MT7629_PIN(73, "WF0_2G_HB1", 73), ++ MT7629_PIN(74, "WF0_2G_HB2", 74), ++ MT7629_PIN(75, "WF0_2G_HB3", 75), ++ MT7629_PIN(76, "WF0_2G_HB4", 76), ++ MT7629_PIN(77, "WF0_2G_HB5", 77), ++ MT7629_PIN(78, "WF0_2G_HB6", 78), ++}; ++ ++/* List all groups consisting of these pins dedicated to the enablement of ++ * certain hardware block and the corresponding mode for all of the pins. ++ * The hardware probably has multiple combinations of these pinouts. ++ */ ++ ++/* LED for EPHY */ ++static int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, }; ++static int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, }; ++static int mt7629_ephy_led0_pins[] = { 12, }; ++static int mt7629_ephy_led0_funcs[] = { 1, }; ++static int mt7629_ephy_led1_pins[] = { 13, }; ++static int mt7629_ephy_led1_funcs[] = { 1, }; ++static int mt7629_ephy_led2_pins[] = { 14, }; ++static int mt7629_ephy_led2_funcs[] = { 1, }; ++static int mt7629_ephy_led3_pins[] = { 15, }; ++static int mt7629_ephy_led3_funcs[] = { 1, }; ++static int mt7629_ephy_led4_pins[] = { 16, }; ++static int mt7629_ephy_led4_funcs[] = { 1, }; ++static int mt7629_wf2g_led_pins[] = { 17, }; ++static int mt7629_wf2g_led_funcs[] = { 1, }; ++static int mt7629_wf5g_led_pins[] = { 18, }; ++static int mt7629_wf5g_led_funcs[] = { 1, }; ++ ++/* Watchdog */ ++static int mt7629_watchdog_pins[] = { 11, }; ++static int mt7629_watchdog_funcs[] = { 1, }; ++ ++/* LED for GPHY */ ++static int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, }; ++static int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, }; ++static int mt7629_gphy_led1_0_pins[] = { 21, }; ++static int mt7629_gphy_led1_0_funcs[] = { 2, }; ++static int mt7629_gphy_led2_0_pins[] = { 22, }; ++static int mt7629_gphy_led2_0_funcs[] = { 2, }; ++static int mt7629_gphy_led3_0_pins[] = { 23, }; ++static int mt7629_gphy_led3_0_funcs[] = { 2, }; ++static int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, }; ++static int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, }; ++static int mt7629_gphy_led1_1_pins[] = { 57, }; ++static int mt7629_gphy_led1_1_funcs[] = { 1, }; ++static int mt7629_gphy_led2_1_pins[] = { 58, }; ++static int mt7629_gphy_led2_1_funcs[] = { 1, }; ++static int mt7629_gphy_led3_1_pins[] = { 59, }; ++static int mt7629_gphy_led3_1_funcs[] = { 1, }; ++ ++/* I2C */ ++static int mt7629_i2c_0_pins[] = { 19, 20, }; ++static int mt7629_i2c_0_funcs[] = { 1, 1, }; ++static int mt7629_i2c_1_pins[] = { 53, 54, }; ++static int mt7629_i2c_1_funcs[] = { 1, 1, }; ++ ++/* SPI */ ++static int mt7629_spi_0_pins[] = { 21, 22, 23, 24, }; ++static int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, }; ++static int mt7629_spi_1_pins[] = { 62, 63, 64, 65, }; ++static int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, }; ++static int mt7629_spi_wp_pins[] = { 66, }; ++static int mt7629_spi_wp_funcs[] = { 1, }; ++static int mt7629_spi_hold_pins[] = { 67, }; ++static int mt7629_spi_hold_funcs[] = { 1, }; ++ ++/* UART */ ++static int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, }; ++static int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, }; ++static int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, }; ++static int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, }; ++static int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, }; ++static int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, }; ++static int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, }; ++static int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, }; ++static int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, }; ++static int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, }; ++static int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, }; ++static int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, }; ++static int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, }; ++static int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, }; ++static int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, }; ++static int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, }; ++static int mt7629_uart0_txd_rxd_pins[] = { 68, 69, }; ++static int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, }; ++ ++/* MDC/MDIO */ ++static int mt7629_mdc_mdio_pins[] = { 49, 50, }; ++static int mt7629_mdc_mdio_funcs[] = { 1, 1, }; ++ ++/* PCIE */ ++static int mt7629_pcie_pereset_pins[] = { 51, }; ++static int mt7629_pcie_pereset_funcs[] = { 1, }; ++static int mt7629_pcie_wake_pins[] = { 55, }; ++static int mt7629_pcie_wake_funcs[] = { 1, }; ++static int mt7629_pcie_clkreq_pins[] = { 56, }; ++static int mt7629_pcie_clkreq_funcs[] = { 1, }; ++ ++/* PWM */ ++static int mt7629_pwm_0_pins[] = { 52, }; ++static int mt7629_pwm_0_funcs[] = { 1, }; ++static int mt7629_pwm_1_pins[] = { 61, }; ++static int mt7629_pwm_1_funcs[] = { 2, }; ++ ++/* WF 2G */ ++static int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, }; ++static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; ++ ++/* WF 5G */ ++static int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, }; ++static int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; ++ ++/* SNFI */ ++static int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 }; ++static int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; ++ ++/* SPI NOR */ ++static int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 }; ++static int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 }; ++ ++static const struct group_desc mt7629_groups[] = { ++ PINCTRL_PIN_GROUP("ephy_leds", mt7629_ephy_leds), ++ PINCTRL_PIN_GROUP("ephy_led0", mt7629_ephy_led0), ++ PINCTRL_PIN_GROUP("ephy_led1", mt7629_ephy_led1), ++ PINCTRL_PIN_GROUP("ephy_led2", mt7629_ephy_led2), ++ PINCTRL_PIN_GROUP("ephy_led3", mt7629_ephy_led3), ++ PINCTRL_PIN_GROUP("ephy_led4", mt7629_ephy_led4), ++ PINCTRL_PIN_GROUP("wf2g_led", mt7629_wf2g_led), ++ PINCTRL_PIN_GROUP("wf5g_led", mt7629_wf5g_led), ++ PINCTRL_PIN_GROUP("watchdog", mt7629_watchdog), ++ PINCTRL_PIN_GROUP("gphy_leds_0", mt7629_gphy_leds_0), ++ PINCTRL_PIN_GROUP("gphy_led1_0", mt7629_gphy_led1_0), ++ PINCTRL_PIN_GROUP("gphy_led2_0", mt7629_gphy_led2_0), ++ PINCTRL_PIN_GROUP("gphy_led3_0", mt7629_gphy_led3_0), ++ PINCTRL_PIN_GROUP("gphy_leds_1", mt7629_gphy_leds_1), ++ PINCTRL_PIN_GROUP("gphy_led1_1", mt7629_gphy_led1_1), ++ PINCTRL_PIN_GROUP("gphy_led2_1", mt7629_gphy_led2_1), ++ PINCTRL_PIN_GROUP("gphy_led3_1", mt7629_gphy_led3_1), ++ PINCTRL_PIN_GROUP("i2c_0", mt7629_i2c_0), ++ PINCTRL_PIN_GROUP("i2c_1", mt7629_i2c_1), ++ PINCTRL_PIN_GROUP("spi_0", mt7629_spi_0), ++ PINCTRL_PIN_GROUP("spi_1", mt7629_spi_1), ++ PINCTRL_PIN_GROUP("spi_wp", mt7629_spi_wp), ++ PINCTRL_PIN_GROUP("spi_hold", mt7629_spi_hold), ++ PINCTRL_PIN_GROUP("uart1_0_txd_rxd", mt7629_uart1_0_txd_rxd), ++ PINCTRL_PIN_GROUP("uart1_1_txd_rxd", mt7629_uart1_1_txd_rxd), ++ PINCTRL_PIN_GROUP("uart2_0_txd_rxd", mt7629_uart2_0_txd_rxd), ++ PINCTRL_PIN_GROUP("uart2_1_txd_rxd", mt7629_uart2_1_txd_rxd), ++ PINCTRL_PIN_GROUP("uart1_0_cts_rts", mt7629_uart1_0_cts_rts), ++ PINCTRL_PIN_GROUP("uart1_1_cts_rts", mt7629_uart1_1_cts_rts), ++ PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7629_uart2_0_cts_rts), ++ PINCTRL_PIN_GROUP("uart2_1_cts_rts", mt7629_uart2_1_cts_rts), ++ PINCTRL_PIN_GROUP("uart0_txd_rxd", mt7629_uart0_txd_rxd), ++ PINCTRL_PIN_GROUP("mdc_mdio", mt7629_mdc_mdio), ++ PINCTRL_PIN_GROUP("pcie_pereset", mt7629_pcie_pereset), ++ PINCTRL_PIN_GROUP("pcie_wake", mt7629_pcie_wake), ++ PINCTRL_PIN_GROUP("pcie_clkreq", mt7629_pcie_clkreq), ++ PINCTRL_PIN_GROUP("pwm_0", mt7629_pwm_0), ++ PINCTRL_PIN_GROUP("pwm_1", mt7629_pwm_1), ++ PINCTRL_PIN_GROUP("wf0_5g", mt7629_wf0_5g), ++ PINCTRL_PIN_GROUP("wf0_2g", mt7629_wf0_2g), ++ PINCTRL_PIN_GROUP("snfi", mt7629_snfi), ++ PINCTRL_PIN_GROUP("spi_nor", mt7629_snor), ++}; ++ ++/* Joint those groups owning the same capability in user point of view which ++ * allows that people tend to use through the device tree. ++ */ ++static const char *mt7629_ethernet_groups[] = { "mdc_mdio", }; ++static const char *mt7629_i2c_groups[] = { "i2c_0", "i2c_1", }; ++static const char *mt7629_led_groups[] = { "ephy_leds", "ephy_led0", ++ "ephy_led1", "ephy_led2", ++ "ephy_led3", "ephy_led4", ++ "wf2g_led", "wf5g_led", ++ "gphy_leds_0", "gphy_led1_0", ++ "gphy_led2_0", "gphy_led3_0", ++ "gphy_leds_1", "gphy_led1_1", ++ "gphy_led2_1", "gphy_led3_1",}; ++static const char *mt7629_pcie_groups[] = { "pcie_pereset", "pcie_wake", ++ "pcie_clkreq", }; ++static const char *mt7629_pwm_groups[] = { "pwm_0", "pwm_1", }; ++static const char *mt7629_spi_groups[] = { "spi_0", "spi_1", "spi_wp", ++ "spi_hold", }; ++static const char *mt7629_uart_groups[] = { "uart1_0_txd_rxd", ++ "uart1_1_txd_rxd", ++ "uart2_0_txd_rxd", ++ "uart2_1_txd_rxd", ++ "uart1_0_cts_rts", ++ "uart1_1_cts_rts", ++ "uart2_0_cts_rts", ++ "uart2_1_cts_rts", ++ "uart0_txd_rxd", }; ++static const char *mt7629_wdt_groups[] = { "watchdog", }; ++static const char *mt7629_wifi_groups[] = { "wf0_5g", "wf0_2g", }; ++static const char *mt7629_flash_groups[] = { "snfi", "spi_nor" }; ++ ++static const struct function_desc mt7629_functions[] = { ++ {"eth", mt7629_ethernet_groups, ARRAY_SIZE(mt7629_ethernet_groups)}, ++ {"i2c", mt7629_i2c_groups, ARRAY_SIZE(mt7629_i2c_groups)}, ++ {"led", mt7629_led_groups, ARRAY_SIZE(mt7629_led_groups)}, ++ {"pcie", mt7629_pcie_groups, ARRAY_SIZE(mt7629_pcie_groups)}, ++ {"pwm", mt7629_pwm_groups, ARRAY_SIZE(mt7629_pwm_groups)}, ++ {"spi", mt7629_spi_groups, ARRAY_SIZE(mt7629_spi_groups)}, ++ {"uart", mt7629_uart_groups, ARRAY_SIZE(mt7629_uart_groups)}, ++ {"watchdog", mt7629_wdt_groups, ARRAY_SIZE(mt7629_wdt_groups)}, ++ {"wifi", mt7629_wifi_groups, ARRAY_SIZE(mt7629_wifi_groups)}, ++ {"flash", mt7629_flash_groups, ARRAY_SIZE(mt7629_flash_groups)}, ++}; ++ ++static const struct mtk_eint_hw mt7629_eint_hw = { ++ .port_mask = 7, ++ .ports = 7, ++ .ap_num = ARRAY_SIZE(mt7629_pins), ++ .db_cnt = 16, ++}; ++ ++static struct mtk_pin_soc mt7629_data = { ++ .reg_cal = mt7629_reg_cals, ++ .pins = mt7629_pins, ++ .npins = ARRAY_SIZE(mt7629_pins), ++ .grps = mt7629_groups, ++ .ngrps = ARRAY_SIZE(mt7629_groups), ++ .funcs = mt7629_functions, ++ .nfuncs = ARRAY_SIZE(mt7629_functions), ++ .eint_hw = &mt7629_eint_hw, ++ .gpio_m = 0, ++ .ies_present = true, ++ .base_names = mtk_default_register_base_names, ++ .nbase_names = ARRAY_SIZE(mtk_default_register_base_names), ++ .bias_disable_set = mtk_pinconf_bias_disable_set_rev1, ++ .bias_disable_get = mtk_pinconf_bias_disable_get_rev1, ++ .bias_set = mtk_pinconf_bias_set_rev1, ++ .bias_get = mtk_pinconf_bias_get_rev1, ++ .drive_set = mtk_pinconf_drive_set_rev1, ++ .drive_get = mtk_pinconf_drive_get_rev1, ++}; ++ ++static const struct of_device_id mt7629_pinctrl_of_match[] = { ++ { .compatible = "mediatek,mt7629-pinctrl", }, ++ {} ++}; ++ ++static int mt7629_pinctrl_probe(struct platform_device *pdev) ++{ ++ return mtk_moore_pinctrl_probe(pdev, &mt7629_data); ++} ++ ++static struct platform_driver mt7629_pinctrl_driver = { ++ .driver = { ++ .name = "mt7629-pinctrl", ++ .of_match_table = mt7629_pinctrl_of_match, ++ }, ++ .probe = mt7629_pinctrl_probe, ++}; ++ ++static int __init mt7629_pinctrl_init(void) ++{ ++ return platform_driver_register(&mt7629_pinctrl_driver); ++} ++arch_initcall(mt7629_pinctrl_init); +diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8183.c b/drivers/pinctrl/mediatek/pinctrl-mt8183.c +new file mode 100644 +index 000000000000..9a74d5025be6 +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mt8183.c +@@ -0,0 +1,595 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2018 MediaTek Inc. ++ * ++ * Author: Zhiyong Tao <zhiyong.tao@mediatek.com> ++ * ++ */ ++ ++#include "pinctrl-mtk-mt8183.h" ++#include "pinctrl-paris.h" ++ ++/* MT8183 have multiple bases to program pin configuration listed as the below: ++ * iocfg[0]:0x10005000, iocfg[1]:0x11F20000, iocfg[2]:0x11E80000, ++ * iocfg[3]:0x11E70000, iocfg[4]:0x11E90000, iocfg[5]:0x11D30000, ++ * iocfg[6]:0x11D20000, iocfg[7]:0x11C50000, iocfg[8]:0x11F30000. ++ * _i_based could be used to indicate what base the pin should be mapped into. ++ */ ++ ++#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ ++ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ ++ _x_bits, 32, 0) ++ ++#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ ++ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ ++ _x_bits, 32, 1) ++ ++static const struct mtk_pin_field_calc mt8183_pin_mode_range[] = { ++ PIN_FIELD(0, 192, 0x300, 0x10, 0, 4), ++}; ++ ++static const struct mtk_pin_field_calc mt8183_pin_dir_range[] = { ++ PIN_FIELD(0, 192, 0x0, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt8183_pin_di_range[] = { ++ PIN_FIELD(0, 192, 0x200, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt8183_pin_do_range[] = { ++ PIN_FIELD(0, 192, 0x100, 0x10, 0, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt8183_pin_ies_range[] = { ++ PINS_FIELD_BASE(0, 3, 6, 0x000, 0x10, 3, 1), ++ PINS_FIELD_BASE(4, 7, 6, 0x000, 0x10, 5, 1), ++ PIN_FIELD_BASE(8, 8, 6, 0x000, 0x10, 0, 1), ++ PINS_FIELD_BASE(9, 10, 6, 0x000, 0x10, 12, 1), ++ PIN_FIELD_BASE(11, 11, 1, 0x000, 0x10, 3, 1), ++ PIN_FIELD_BASE(12, 12, 1, 0x000, 0x10, 7, 1), ++ PINS_FIELD_BASE(13, 16, 2, 0x000, 0x10, 2, 1), ++ PINS_FIELD_BASE(17, 20, 2, 0x000, 0x10, 3, 1), ++ PINS_FIELD_BASE(21, 24, 2, 0x000, 0x10, 4, 1), ++ PINS_FIELD_BASE(25, 28, 2, 0x000, 0x10, 5, 1), ++ PIN_FIELD_BASE(29, 29, 2, 0x000, 0x10, 6, 1), ++ PIN_FIELD_BASE(30, 30, 2, 0x000, 0x10, 7, 1), ++ PINS_FIELD_BASE(31, 31, 2, 0x000, 0x10, 8, 1), ++ PINS_FIELD_BASE(32, 34, 2, 0x000, 0x10, 7, 1), ++ PINS_FIELD_BASE(35, 37, 3, 0x000, 0x10, 0, 1), ++ PINS_FIELD_BASE(38, 40, 3, 0x000, 0x10, 1, 1), ++ PINS_FIELD_BASE(41, 42, 3, 0x000, 0x10, 2, 1), ++ PINS_FIELD_BASE(43, 45, 3, 0x000, 0x10, 3, 1), ++ PINS_FIELD_BASE(46, 47, 3, 0x000, 0x10, 4, 1), ++ PINS_FIELD_BASE(48, 49, 3, 0x000, 0x10, 5, 1), ++ PINS_FIELD_BASE(50, 51, 4, 0x000, 0x10, 0, 1), ++ PINS_FIELD_BASE(52, 57, 4, 0x000, 0x10, 1, 1), ++ PINS_FIELD_BASE(58, 60, 4, 0x000, 0x10, 2, 1), ++ PINS_FIELD_BASE(61, 64, 5, 0x000, 0x10, 0, 1), ++ PINS_FIELD_BASE(65, 66, 5, 0x000, 0x10, 1, 1), ++ PINS_FIELD_BASE(67, 68, 5, 0x000, 0x10, 2, 1), ++ PINS_FIELD_BASE(69, 71, 5, 0x000, 0x10, 3, 1), ++ PINS_FIELD_BASE(72, 76, 5, 0x000, 0x10, 4, 1), ++ PINS_FIELD_BASE(77, 80, 5, 0x000, 0x10, 5, 1), ++ PIN_FIELD_BASE(81, 81, 5, 0x000, 0x10, 6, 1), ++ PINS_FIELD_BASE(82, 83, 5, 0x000, 0x10, 7, 1), ++ PIN_FIELD_BASE(84, 84, 5, 0x000, 0x10, 6, 1), ++ PINS_FIELD_BASE(85, 88, 5, 0x000, 0x10, 8, 1), ++ PIN_FIELD_BASE(89, 89, 6, 0x000, 0x10, 11, 1), ++ PIN_FIELD_BASE(90, 90, 6, 0x000, 0x10, 1, 1), ++ PINS_FIELD_BASE(91, 94, 6, 0x000, 0x10, 2, 1), ++ PINS_FIELD_BASE(95, 96, 6, 0x000, 0x10, 6, 1), ++ PINS_FIELD_BASE(97, 98, 6, 0x000, 0x10, 7, 1), ++ PIN_FIELD_BASE(99, 99, 6, 0x000, 0x10, 8, 1), ++ PIN_FIELD_BASE(100, 100, 6, 0x000, 0x10, 9, 1), ++ PINS_FIELD_BASE(101, 102, 6, 0x000, 0x10, 10, 1), ++ PINS_FIELD_BASE(103, 104, 6, 0x000, 0x10, 13, 1), ++ PINS_FIELD_BASE(105, 106, 6, 0x000, 0x10, 14, 1), ++ PIN_FIELD_BASE(107, 107, 7, 0x000, 0x10, 0, 1), ++ PIN_FIELD_BASE(108, 108, 7, 0x000, 0x10, 1, 1), ++ PIN_FIELD_BASE(109, 109, 7, 0x000, 0x10, 2, 1), ++ PIN_FIELD_BASE(110, 110, 7, 0x000, 0x10, 0, 1), ++ PIN_FIELD_BASE(111, 111, 7, 0x000, 0x10, 3, 1), ++ PIN_FIELD_BASE(112, 112, 7, 0x000, 0x10, 2, 1), ++ PIN_FIELD_BASE(113, 113, 7, 0x000, 0x10, 4, 1), ++ PIN_FIELD_BASE(114, 114, 7, 0x000, 0x10, 5, 1), ++ PIN_FIELD_BASE(115, 115, 7, 0x000, 0x10, 6, 1), ++ PIN_FIELD_BASE(116, 116, 7, 0x000, 0x10, 7, 1), ++ PIN_FIELD_BASE(117, 117, 7, 0x000, 0x10, 8, 1), ++ PIN_FIELD_BASE(118, 118, 7, 0x000, 0x10, 9, 1), ++ PIN_FIELD_BASE(119, 119, 7, 0x000, 0x10, 10, 1), ++ PIN_FIELD_BASE(120, 120, 7, 0x000, 0x10, 11, 1), ++ PIN_FIELD_BASE(121, 121, 7, 0x000, 0x10, 12, 1), ++ PIN_FIELD_BASE(122, 122, 8, 0x000, 0x10, 0, 1), ++ PIN_FIELD_BASE(123, 123, 8, 0x000, 0x10, 1, 1), ++ PIN_FIELD_BASE(124, 124, 8, 0x000, 0x10, 2, 1), ++ PINS_FIELD_BASE(125, 130, 8, 0x000, 0x10, 1, 1), ++ PIN_FIELD_BASE(131, 131, 8, 0x000, 0x10, 3, 1), ++ PIN_FIELD_BASE(132, 132, 8, 0x000, 0x10, 1, 1), ++ PIN_FIELD_BASE(133, 133, 8, 0x000, 0x10, 4, 1), ++ PIN_FIELD_BASE(134, 134, 1, 0x000, 0x10, 0, 1), ++ PIN_FIELD_BASE(135, 135, 1, 0x000, 0x10, 1, 1), ++ PINS_FIELD_BASE(136, 143, 1, 0x000, 0x10, 2, 1), ++ PINS_FIELD_BASE(144, 147, 1, 0x000, 0x10, 4, 1), ++ PIN_FIELD_BASE(148, 148, 1, 0x000, 0x10, 5, 1), ++ PIN_FIELD_BASE(149, 149, 1, 0x000, 0x10, 6, 1), ++ PINS_FIELD_BASE(150, 153, 1, 0x000, 0x10, 8, 1), ++ PIN_FIELD_BASE(154, 154, 1, 0x000, 0x10, 9, 1), ++ PINS_FIELD_BASE(155, 157, 1, 0x000, 0x10, 10, 1), ++ PINS_FIELD_BASE(158, 160, 1, 0x000, 0x10, 8, 1), ++ PINS_FIELD_BASE(161, 164, 2, 0x000, 0x10, 0, 1), ++ PINS_FIELD_BASE(165, 166, 2, 0x000, 0x10, 1, 1), ++ PINS_FIELD_BASE(167, 168, 4, 0x000, 0x10, 2, 1), ++ PIN_FIELD_BASE(169, 169, 4, 0x000, 0x10, 3, 1), ++ PINS_FIELD_BASE(170, 174, 4, 0x000, 0x10, 4, 1), ++ PINS_FIELD_BASE(175, 176, 4, 0x000, 0x10, 3, 1), ++ PINS_FIELD_BASE(177, 179, 6, 0x000, 0x10, 4, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt8183_pin_smt_range[] = { ++ PINS_FIELD_BASE(0, 3, 6, 0x010, 0x10, 3, 1), ++ PINS_FIELD_BASE(4, 7, 6, 0x010, 0x10, 5, 1), ++ PIN_FIELD_BASE(8, 8, 6, 0x010, 0x10, 0, 1), ++ PINS_FIELD_BASE(9, 10, 6, 0x010, 0x10, 12, 1), ++ PIN_FIELD_BASE(11, 11, 1, 0x010, 0x10, 3, 1), ++ PIN_FIELD_BASE(12, 12, 1, 0x010, 0x10, 7, 1), ++ PINS_FIELD_BASE(13, 16, 2, 0x010, 0x10, 2, 1), ++ PINS_FIELD_BASE(17, 20, 2, 0x010, 0x10, 3, 1), ++ PINS_FIELD_BASE(21, 24, 2, 0x010, 0x10, 4, 1), ++ PINS_FIELD_BASE(25, 28, 2, 0x010, 0x10, 5, 1), ++ PIN_FIELD_BASE(29, 29, 2, 0x010, 0x10, 6, 1), ++ PIN_FIELD_BASE(30, 30, 2, 0x010, 0x10, 7, 1), ++ PINS_FIELD_BASE(31, 31, 2, 0x010, 0x10, 8, 1), ++ PINS_FIELD_BASE(32, 34, 2, 0x010, 0x10, 7, 1), ++ PINS_FIELD_BASE(35, 37, 3, 0x010, 0x10, 0, 1), ++ PINS_FIELD_BASE(38, 40, 3, 0x010, 0x10, 1, 1), ++ PINS_FIELD_BASE(41, 42, 3, 0x010, 0x10, 2, 1), ++ PINS_FIELD_BASE(43, 45, 3, 0x010, 0x10, 3, 1), ++ PINS_FIELD_BASE(46, 47, 3, 0x010, 0x10, 4, 1), ++ PINS_FIELD_BASE(48, 49, 3, 0x010, 0x10, 5, 1), ++ PINS_FIELD_BASE(50, 51, 4, 0x010, 0x10, 0, 1), ++ PINS_FIELD_BASE(52, 57, 4, 0x010, 0x10, 1, 1), ++ PINS_FIELD_BASE(58, 60, 4, 0x010, 0x10, 2, 1), ++ PINS_FIELD_BASE(61, 64, 5, 0x010, 0x10, 0, 1), ++ PINS_FIELD_BASE(65, 66, 5, 0x010, 0x10, 1, 1), ++ PINS_FIELD_BASE(67, 68, 5, 0x010, 0x10, 2, 1), ++ PINS_FIELD_BASE(69, 71, 5, 0x010, 0x10, 3, 1), ++ PINS_FIELD_BASE(72, 76, 5, 0x010, 0x10, 4, 1), ++ PINS_FIELD_BASE(77, 80, 5, 0x010, 0x10, 5, 1), ++ PIN_FIELD_BASE(81, 81, 5, 0x010, 0x10, 6, 1), ++ PINS_FIELD_BASE(82, 83, 5, 0x010, 0x10, 7, 1), ++ PIN_FIELD_BASE(84, 84, 5, 0x010, 0x10, 6, 1), ++ PINS_FIELD_BASE(85, 88, 5, 0x010, 0x10, 8, 1), ++ PIN_FIELD_BASE(89, 89, 6, 0x010, 0x10, 11, 1), ++ PIN_FIELD_BASE(90, 90, 6, 0x010, 0x10, 1, 1), ++ PINS_FIELD_BASE(91, 94, 6, 0x010, 0x10, 2, 1), ++ PINS_FIELD_BASE(95, 96, 6, 0x010, 0x10, 6, 1), ++ PINS_FIELD_BASE(97, 98, 6, 0x010, 0x10, 7, 1), ++ PIN_FIELD_BASE(99, 99, 6, 0x010, 0x10, 8, 1), ++ PIN_FIELD_BASE(100, 100, 6, 0x010, 0x10, 9, 1), ++ PINS_FIELD_BASE(101, 102, 6, 0x010, 0x10, 10, 1), ++ PINS_FIELD_BASE(103, 104, 6, 0x010, 0x10, 13, 1), ++ PINS_FIELD_BASE(105, 106, 6, 0x010, 0x10, 14, 1), ++ PIN_FIELD_BASE(107, 107, 7, 0x010, 0x10, 0, 1), ++ PIN_FIELD_BASE(108, 108, 7, 0x010, 0x10, 1, 1), ++ PIN_FIELD_BASE(109, 109, 7, 0x010, 0x10, 2, 1), ++ PIN_FIELD_BASE(110, 110, 7, 0x010, 0x10, 0, 1), ++ PIN_FIELD_BASE(111, 111, 7, 0x010, 0x10, 3, 1), ++ PIN_FIELD_BASE(112, 112, 7, 0x010, 0x10, 2, 1), ++ PIN_FIELD_BASE(113, 113, 7, 0x010, 0x10, 4, 1), ++ PIN_FIELD_BASE(114, 114, 7, 0x010, 0x10, 5, 1), ++ PIN_FIELD_BASE(115, 115, 7, 0x010, 0x10, 6, 1), ++ PIN_FIELD_BASE(116, 116, 7, 0x010, 0x10, 7, 1), ++ PIN_FIELD_BASE(117, 117, 7, 0x010, 0x10, 8, 1), ++ PIN_FIELD_BASE(118, 118, 7, 0x010, 0x10, 9, 1), ++ PIN_FIELD_BASE(119, 119, 7, 0x010, 0x10, 10, 1), ++ PIN_FIELD_BASE(120, 120, 7, 0x010, 0x10, 11, 1), ++ PIN_FIELD_BASE(121, 121, 7, 0x010, 0x10, 12, 1), ++ PIN_FIELD_BASE(122, 122, 8, 0x010, 0x10, 0, 1), ++ PIN_FIELD_BASE(123, 123, 8, 0x010, 0x10, 1, 1), ++ PIN_FIELD_BASE(124, 124, 8, 0x010, 0x10, 2, 1), ++ PINS_FIELD_BASE(125, 130, 8, 0x010, 0x10, 1, 1), ++ PIN_FIELD_BASE(131, 131, 8, 0x010, 0x10, 3, 1), ++ PIN_FIELD_BASE(132, 132, 8, 0x010, 0x10, 1, 1), ++ PIN_FIELD_BASE(133, 133, 8, 0x010, 0x10, 4, 1), ++ PIN_FIELD_BASE(134, 134, 1, 0x010, 0x10, 0, 1), ++ PIN_FIELD_BASE(135, 135, 1, 0x010, 0x10, 1, 1), ++ PINS_FIELD_BASE(136, 143, 1, 0x010, 0x10, 2, 1), ++ PINS_FIELD_BASE(144, 147, 1, 0x010, 0x10, 4, 1), ++ PIN_FIELD_BASE(148, 148, 1, 0x010, 0x10, 5, 1), ++ PIN_FIELD_BASE(149, 149, 1, 0x010, 0x10, 6, 1), ++ PINS_FIELD_BASE(150, 153, 1, 0x010, 0x10, 8, 1), ++ PIN_FIELD_BASE(154, 154, 1, 0x010, 0x10, 9, 1), ++ PINS_FIELD_BASE(155, 157, 1, 0x010, 0x10, 10, 1), ++ PINS_FIELD_BASE(158, 160, 1, 0x010, 0x10, 8, 1), ++ PINS_FIELD_BASE(161, 164, 2, 0x010, 0x10, 0, 1), ++ PINS_FIELD_BASE(165, 166, 2, 0x010, 0x10, 1, 1), ++ PINS_FIELD_BASE(167, 168, 4, 0x010, 0x10, 2, 1), ++ PIN_FIELD_BASE(169, 169, 4, 0x010, 0x10, 3, 1), ++ PINS_FIELD_BASE(170, 174, 4, 0x010, 0x10, 4, 1), ++ PINS_FIELD_BASE(175, 176, 4, 0x010, 0x10, 3, 1), ++ PINS_FIELD_BASE(177, 179, 6, 0x010, 0x10, 4, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt8183_pin_pullen_range[] = { ++ PIN_FIELD_BASE(0, 3, 6, 0x060, 0x10, 6, 1), ++ PIN_FIELD_BASE(4, 7, 6, 0x060, 0x10, 11, 1), ++ PIN_FIELD_BASE(8, 8, 6, 0x060, 0x10, 0, 1), ++ PIN_FIELD_BASE(9, 10, 6, 0x060, 0x10, 26, 1), ++ PIN_FIELD_BASE(11, 11, 1, 0x060, 0x10, 10, 1), ++ PIN_FIELD_BASE(12, 12, 1, 0x060, 0x10, 17, 1), ++ PIN_FIELD_BASE(13, 28, 2, 0x060, 0x10, 6, 1), ++ PIN_FIELD_BASE(43, 49, 3, 0x060, 0x10, 8, 1), ++ PIN_FIELD_BASE(50, 60, 4, 0x060, 0x10, 0, 1), ++ PIN_FIELD_BASE(61, 88, 5, 0x060, 0x10, 0, 1), ++ PIN_FIELD_BASE(89, 89, 6, 0x060, 0x10, 24, 1), ++ PIN_FIELD_BASE(90, 90, 6, 0x060, 0x10, 1, 1), ++ PIN_FIELD_BASE(95, 95, 6, 0x060, 0x10, 15, 1), ++ PIN_FIELD_BASE(96, 102, 6, 0x060, 0x10, 17, 1), ++ PIN_FIELD_BASE(103, 106, 6, 0x060, 0x10, 28, 1), ++ PIN_FIELD_BASE(107, 121, 7, 0x060, 0x10, 0, 1), ++ PIN_FIELD_BASE(134, 143, 1, 0x060, 0x10, 0, 1), ++ PIN_FIELD_BASE(144, 149, 1, 0x060, 0x10, 11, 1), ++ PIN_FIELD_BASE(150, 160, 1, 0x060, 0x10, 18, 1), ++ PIN_FIELD_BASE(161, 166, 2, 0x060, 0x10, 0, 1), ++ PIN_FIELD_BASE(167, 176, 4, 0x060, 0x10, 11, 1), ++ PIN_FIELD_BASE(177, 177, 6, 0x060, 0x10, 10, 1), ++ PIN_FIELD_BASE(178, 178, 6, 0x060, 0x10, 16, 1), ++ PIN_FIELD_BASE(179, 179, 6, 0x060, 0x10, 25, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt8183_pin_pullsel_range[] = { ++ PIN_FIELD_BASE(0, 3, 6, 0x080, 0x10, 6, 1), ++ PIN_FIELD_BASE(4, 7, 6, 0x080, 0x10, 11, 1), ++ PIN_FIELD_BASE(8, 8, 6, 0x080, 0x10, 0, 1), ++ PIN_FIELD_BASE(9, 10, 6, 0x080, 0x10, 26, 1), ++ PIN_FIELD_BASE(11, 11, 1, 0x080, 0x10, 10, 1), ++ PIN_FIELD_BASE(12, 12, 1, 0x080, 0x10, 17, 1), ++ PIN_FIELD_BASE(13, 28, 2, 0x080, 0x10, 6, 1), ++ PIN_FIELD_BASE(43, 49, 3, 0x080, 0x10, 8, 1), ++ PIN_FIELD_BASE(50, 60, 4, 0x080, 0x10, 0, 1), ++ PIN_FIELD_BASE(61, 88, 5, 0x080, 0x10, 0, 1), ++ PIN_FIELD_BASE(89, 89, 6, 0x080, 0x10, 24, 1), ++ PIN_FIELD_BASE(90, 90, 6, 0x080, 0x10, 1, 1), ++ PIN_FIELD_BASE(95, 95, 6, 0x080, 0x10, 15, 1), ++ PIN_FIELD_BASE(96, 102, 6, 0x080, 0x10, 17, 1), ++ PIN_FIELD_BASE(103, 106, 6, 0x080, 0x10, 28, 1), ++ PIN_FIELD_BASE(107, 121, 7, 0x080, 0x10, 0, 1), ++ PIN_FIELD_BASE(134, 143, 1, 0x080, 0x10, 0, 1), ++ PIN_FIELD_BASE(144, 149, 1, 0x080, 0x10, 11, 1), ++ PIN_FIELD_BASE(150, 160, 1, 0x080, 0x10, 18, 1), ++ PIN_FIELD_BASE(161, 166, 2, 0x080, 0x10, 0, 1), ++ PIN_FIELD_BASE(167, 176, 4, 0x080, 0x10, 11, 1), ++ PIN_FIELD_BASE(177, 177, 6, 0x080, 0x10, 10, 1), ++ PIN_FIELD_BASE(178, 178, 6, 0x080, 0x10, 16, 1), ++ PIN_FIELD_BASE(179, 179, 6, 0x080, 0x10, 25, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt8183_pin_drv_range[] = { ++ PINS_FIELD_BASE(0, 3, 6, 0x0A0, 0x10, 12, 3), ++ PINS_FIELD_BASE(4, 7, 6, 0x0A0, 0x10, 20, 3), ++ PIN_FIELD_BASE(8, 8, 6, 0x0A0, 0x10, 0, 3), ++ PINS_FIELD_BASE(9, 10, 6, 0x0B0, 0x10, 16, 3), ++ PIN_FIELD_BASE(11, 11, 1, 0x0A0, 0x10, 12, 3), ++ PIN_FIELD_BASE(12, 12, 1, 0x0A0, 0x10, 28, 3), ++ PINS_FIELD_BASE(13, 16, 2, 0x0A0, 0x10, 8, 3), ++ PINS_FIELD_BASE(17, 20, 2, 0x0A0, 0x10, 12, 3), ++ PINS_FIELD_BASE(21, 24, 2, 0x0A0, 0x10, 16, 3), ++ PINS_FIELD_BASE(25, 28, 2, 0x0A0, 0x10, 20, 3), ++ PIN_FIELD_BASE(29, 29, 2, 0x0A0, 0x10, 24, 3), ++ PIN_FIELD_BASE(30, 30, 2, 0x0A0, 0x10, 28, 3), ++ PINS_FIELD_BASE(31, 31, 2, 0x0B0, 0x10, 0, 3), ++ PINS_FIELD_BASE(32, 34, 2, 0x0A0, 0x10, 28, 3), ++ PINS_FIELD_BASE(35, 37, 3, 0x0A0, 0x10, 0, 3), ++ PINS_FIELD_BASE(38, 40, 3, 0x0A0, 0x10, 4, 3), ++ PINS_FIELD_BASE(41, 42, 3, 0x0A0, 0x10, 8, 3), ++ PINS_FIELD_BASE(43, 45, 3, 0x0A0, 0x10, 12, 3), ++ PINS_FIELD_BASE(46, 47, 3, 0x0A0, 0x10, 16, 3), ++ PINS_FIELD_BASE(48, 49, 3, 0x0A0, 0x10, 20, 3), ++ PINS_FIELD_BASE(50, 51, 4, 0x0A0, 0x10, 0, 3), ++ PINS_FIELD_BASE(52, 57, 4, 0x0A0, 0x10, 4, 3), ++ PINS_FIELD_BASE(58, 60, 4, 0x0A0, 0x10, 8, 3), ++ PINS_FIELD_BASE(61, 64, 5, 0x0A0, 0x10, 0, 3), ++ PINS_FIELD_BASE(65, 66, 5, 0x0A0, 0x10, 4, 3), ++ PINS_FIELD_BASE(67, 68, 5, 0x0A0, 0x10, 8, 3), ++ PINS_FIELD_BASE(69, 71, 5, 0x0A0, 0x10, 12, 3), ++ PINS_FIELD_BASE(72, 76, 5, 0x0A0, 0x10, 16, 3), ++ PINS_FIELD_BASE(77, 80, 5, 0x0A0, 0x10, 20, 3), ++ PIN_FIELD_BASE(81, 81, 5, 0x0A0, 0x10, 24, 3), ++ PINS_FIELD_BASE(82, 83, 5, 0x0A0, 0x10, 28, 3), ++ PIN_FIELD_BASE(84, 84, 5, 0x0A0, 0x10, 24, 3), ++ PINS_FIELD_BASE(85, 88, 5, 0x0B0, 0x10, 0, 3), ++ PIN_FIELD_BASE(89, 89, 6, 0x0B0, 0x10, 12, 3), ++ PIN_FIELD_BASE(90, 90, 6, 0x0A0, 0x10, 4, 3), ++ PINS_FIELD_BASE(91, 94, 6, 0x0A0, 0x10, 8, 3), ++ PINS_FIELD_BASE(95, 96, 6, 0x0A0, 0x10, 24, 3), ++ PINS_FIELD_BASE(97, 98, 6, 0x0A0, 0x10, 28, 3), ++ PIN_FIELD_BASE(99, 99, 6, 0x0B0, 0x10, 0, 3), ++ PIN_FIELD_BASE(100, 100, 6, 0x0B0, 0x10, 4, 3), ++ PINS_FIELD_BASE(101, 102, 6, 0x0B0, 0x10, 8, 3), ++ PINS_FIELD_BASE(103, 104, 6, 0x0B0, 0x10, 20, 3), ++ PINS_FIELD_BASE(105, 106, 6, 0x0B0, 0x10, 24, 3), ++ PIN_FIELD_BASE(107, 107, 7, 0x0A0, 0x10, 0, 3), ++ PIN_FIELD_BASE(108, 108, 7, 0x0A0, 0x10, 4, 3), ++ PIN_FIELD_BASE(109, 109, 7, 0x0A0, 0x10, 8, 3), ++ PIN_FIELD_BASE(110, 110, 7, 0x0A0, 0x10, 0, 3), ++ PIN_FIELD_BASE(111, 111, 7, 0x0A0, 0x10, 4, 3), ++ PIN_FIELD_BASE(112, 112, 7, 0x0A0, 0x10, 8, 3), ++ PIN_FIELD_BASE(113, 113, 7, 0x0A0, 0x10, 16, 3), ++ PIN_FIELD_BASE(114, 114, 7, 0x0A0, 0x10, 20, 3), ++ PIN_FIELD_BASE(115, 115, 7, 0x0A0, 0x10, 24, 3), ++ PIN_FIELD_BASE(116, 116, 7, 0x0A0, 0x10, 28, 3), ++ PIN_FIELD_BASE(117, 117, 7, 0x0B0, 0x10, 0, 3), ++ PIN_FIELD_BASE(118, 118, 7, 0x0B0, 0x10, 4, 3), ++ PIN_FIELD_BASE(119, 119, 7, 0x0B0, 0x10, 8, 3), ++ PIN_FIELD_BASE(120, 120, 7, 0x0B0, 0x10, 12, 3), ++ PIN_FIELD_BASE(121, 121, 7, 0x0B0, 0x10, 16, 3), ++ PIN_FIELD_BASE(122, 122, 8, 0x0A0, 0x10, 0, 3), ++ PIN_FIELD_BASE(123, 123, 8, 0x0A0, 0x10, 4, 3), ++ PIN_FIELD_BASE(124, 124, 8, 0x0A0, 0x10, 8, 3), ++ PINS_FIELD_BASE(125, 130, 8, 0x0A0, 0x10, 4, 3), ++ PIN_FIELD_BASE(131, 131, 8, 0x0A0, 0x10, 12, 3), ++ PIN_FIELD_BASE(132, 132, 8, 0x0A0, 0x10, 4, 3), ++ PIN_FIELD_BASE(133, 133, 8, 0x0A0, 0x10, 16, 3), ++ PIN_FIELD_BASE(134, 134, 1, 0x0A0, 0x10, 0, 3), ++ PIN_FIELD_BASE(135, 135, 1, 0x0A0, 0x10, 4, 3), ++ PINS_FIELD_BASE(136, 143, 1, 0x0A0, 0x10, 8, 3), ++ PINS_FIELD_BASE(144, 147, 1, 0x0A0, 0x10, 16, 3), ++ PIN_FIELD_BASE(148, 148, 1, 0x0A0, 0x10, 20, 3), ++ PIN_FIELD_BASE(149, 149, 1, 0x0A0, 0x10, 24, 3), ++ PINS_FIELD_BASE(150, 153, 1, 0x0B0, 0x10, 0, 3), ++ PIN_FIELD_BASE(154, 154, 1, 0x0B0, 0x10, 4, 3), ++ PINS_FIELD_BASE(155, 157, 1, 0x0B0, 0x10, 8, 3), ++ PINS_FIELD_BASE(158, 160, 1, 0x0B0, 0x10, 0, 3), ++ PINS_FIELD_BASE(161, 164, 2, 0x0A0, 0x10, 0, 3), ++ PINS_FIELD_BASE(165, 166, 2, 0x0A0, 0x10, 4, 3), ++ PINS_FIELD_BASE(167, 168, 4, 0x0A0, 0x10, 8, 3), ++ PIN_FIELD_BASE(169, 169, 4, 0x0A0, 0x10, 12, 3), ++ PINS_FIELD_BASE(170, 174, 4, 0x0A0, 0x10, 16, 3), ++ PINS_FIELD_BASE(175, 176, 4, 0x0A0, 0x10, 12, 3), ++ PINS_FIELD_BASE(177, 179, 6, 0x0A0, 0x10, 16, 3), ++}; ++ ++static const struct mtk_pin_field_calc mt8183_pin_pupd_range[] = { ++ PIN_FIELD_BASE(29, 29, 2, 0x0C0, 0x10, 2, 1), ++ PIN_FIELD_BASE(30, 30, 2, 0x0C0, 0x10, 6, 1), ++ PIN_FIELD_BASE(31, 31, 2, 0x0C0, 0x10, 10, 1), ++ PIN_FIELD_BASE(32, 32, 2, 0x0C0, 0x10, 14, 1), ++ PIN_FIELD_BASE(33, 33, 2, 0x0C0, 0x10, 18, 1), ++ PIN_FIELD_BASE(34, 34, 2, 0x0C0, 0x10, 22, 1), ++ PIN_FIELD_BASE(35, 35, 3, 0x0C0, 0x10, 2, 1), ++ PIN_FIELD_BASE(36, 36, 3, 0x0C0, 0x10, 6, 1), ++ PIN_FIELD_BASE(37, 37, 3, 0x0C0, 0x10, 10, 1), ++ PIN_FIELD_BASE(38, 38, 3, 0x0C0, 0x10, 14, 1), ++ PIN_FIELD_BASE(39, 39, 3, 0x0C0, 0x10, 18, 1), ++ PIN_FIELD_BASE(40, 40, 3, 0x0C0, 0x10, 22, 1), ++ PIN_FIELD_BASE(41, 41, 3, 0x0C0, 0x10, 26, 1), ++ PIN_FIELD_BASE(42, 42, 3, 0x0C0, 0x10, 30, 1), ++ PIN_FIELD_BASE(91, 91, 6, 0x0C0, 0x10, 2, 1), ++ PIN_FIELD_BASE(92, 92, 6, 0x0C0, 0x10, 6, 1), ++ PIN_FIELD_BASE(93, 93, 6, 0x0C0, 0x10, 10, 1), ++ PIN_FIELD_BASE(94, 94, 6, 0x0C0, 0x10, 14, 1), ++ PIN_FIELD_BASE(122, 122, 8, 0x0C0, 0x10, 2, 1), ++ PIN_FIELD_BASE(123, 123, 8, 0x0C0, 0x10, 6, 1), ++ PIN_FIELD_BASE(124, 124, 8, 0x0C0, 0x10, 10, 1), ++ PIN_FIELD_BASE(125, 125, 8, 0x0C0, 0x10, 14, 1), ++ PIN_FIELD_BASE(126, 126, 8, 0x0C0, 0x10, 18, 1), ++ PIN_FIELD_BASE(127, 127, 8, 0x0C0, 0x10, 22, 1), ++ PIN_FIELD_BASE(128, 128, 8, 0x0C0, 0x10, 26, 1), ++ PIN_FIELD_BASE(129, 129, 8, 0x0C0, 0x10, 30, 1), ++ PIN_FIELD_BASE(130, 130, 8, 0x0D0, 0x10, 2, 1), ++ PIN_FIELD_BASE(131, 131, 8, 0x0D0, 0x10, 6, 1), ++ PIN_FIELD_BASE(132, 132, 8, 0x0D0, 0x10, 10, 1), ++ PIN_FIELD_BASE(133, 133, 8, 0x0D0, 0x10, 14, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt8183_pin_r0_range[] = { ++ PIN_FIELD_BASE(29, 29, 2, 0x0C0, 0x10, 0, 1), ++ PIN_FIELD_BASE(30, 30, 2, 0x0C0, 0x10, 4, 1), ++ PIN_FIELD_BASE(31, 31, 2, 0x0C0, 0x10, 8, 1), ++ PIN_FIELD_BASE(32, 32, 2, 0x0C0, 0x10, 12, 1), ++ PIN_FIELD_BASE(33, 33, 2, 0x0C0, 0x10, 16, 1), ++ PIN_FIELD_BASE(34, 34, 2, 0x0C0, 0x10, 20, 1), ++ PIN_FIELD_BASE(35, 35, 3, 0x0C0, 0x10, 0, 1), ++ PIN_FIELD_BASE(36, 36, 3, 0x0C0, 0x10, 4, 1), ++ PIN_FIELD_BASE(37, 37, 3, 0x0C0, 0x10, 8, 1), ++ PIN_FIELD_BASE(38, 38, 3, 0x0C0, 0x10, 12, 1), ++ PIN_FIELD_BASE(39, 39, 3, 0x0C0, 0x10, 16, 1), ++ PIN_FIELD_BASE(40, 40, 3, 0x0C0, 0x10, 20, 1), ++ PIN_FIELD_BASE(41, 41, 3, 0x0C0, 0x10, 24, 1), ++ PIN_FIELD_BASE(42, 42, 3, 0x0C0, 0x10, 28, 1), ++ PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 18, 1), ++ PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 13, 1), ++ PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 10, 1), ++ PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 5, 1), ++ PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 7, 1), ++ PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 5, 1), ++ PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 15, 1), ++ PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 17, 1), ++ PIN_FIELD_BASE(91, 91, 6, 0x0C0, 0x10, 0, 1), ++ PIN_FIELD_BASE(92, 92, 6, 0x0C0, 0x10, 4, 1), ++ PIN_FIELD_BASE(93, 93, 6, 0x0C0, 0x10, 8, 1), ++ PIN_FIELD_BASE(94, 94, 6, 0x0C0, 0x10, 12, 1), ++ PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 20, 1), ++ PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 10, 1), ++ PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 22, 1), ++ PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 12, 1), ++ PIN_FIELD_BASE(122, 122, 8, 0x0C0, 0x10, 0, 1), ++ PIN_FIELD_BASE(123, 123, 8, 0x0C0, 0x10, 4, 1), ++ PIN_FIELD_BASE(124, 124, 8, 0x0C0, 0x10, 8, 1), ++ PIN_FIELD_BASE(125, 125, 8, 0x0C0, 0x10, 12, 1), ++ PIN_FIELD_BASE(126, 126, 8, 0x0C0, 0x10, 16, 1), ++ PIN_FIELD_BASE(127, 127, 8, 0x0C0, 0x10, 20, 1), ++ PIN_FIELD_BASE(128, 128, 8, 0x0C0, 0x10, 24, 1), ++ PIN_FIELD_BASE(129, 129, 8, 0x0C0, 0x10, 28, 1), ++ PIN_FIELD_BASE(130, 130, 8, 0x0D0, 0x10, 0, 1), ++ PIN_FIELD_BASE(131, 131, 8, 0x0D0, 0x10, 4, 1), ++ PIN_FIELD_BASE(132, 132, 8, 0x0D0, 0x10, 8, 1), ++ PIN_FIELD_BASE(133, 133, 8, 0x0D0, 0x10, 12, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt8183_pin_r1_range[] = { ++ PIN_FIELD_BASE(29, 29, 2, 0x0C0, 0x10, 1, 1), ++ PIN_FIELD_BASE(30, 30, 2, 0x0C0, 0x10, 5, 1), ++ PIN_FIELD_BASE(31, 31, 2, 0x0C0, 0x10, 9, 1), ++ PIN_FIELD_BASE(32, 32, 2, 0x0C0, 0x10, 13, 1), ++ PIN_FIELD_BASE(33, 33, 2, 0x0C0, 0x10, 17, 1), ++ PIN_FIELD_BASE(34, 34, 2, 0x0C0, 0x10, 21, 1), ++ PIN_FIELD_BASE(35, 35, 3, 0x0C0, 0x10, 1, 1), ++ PIN_FIELD_BASE(36, 36, 3, 0x0C0, 0x10, 5, 1), ++ PIN_FIELD_BASE(37, 37, 3, 0x0C0, 0x10, 9, 1), ++ PIN_FIELD_BASE(38, 38, 3, 0x0C0, 0x10, 13, 1), ++ PIN_FIELD_BASE(39, 39, 3, 0x0C0, 0x10, 17, 1), ++ PIN_FIELD_BASE(40, 40, 3, 0x0C0, 0x10, 21, 1), ++ PIN_FIELD_BASE(41, 41, 3, 0x0C0, 0x10, 25, 1), ++ PIN_FIELD_BASE(42, 42, 3, 0x0C0, 0x10, 29, 1), ++ PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 19, 1), ++ PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 14, 1), ++ PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 11, 1), ++ PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 6, 1), ++ PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 8, 1), ++ PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 6, 1), ++ PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 16, 1), ++ PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 18, 1), ++ PIN_FIELD_BASE(91, 91, 6, 0x0C0, 0x10, 1, 1), ++ PIN_FIELD_BASE(92, 92, 6, 0x0C0, 0x10, 5, 1), ++ PIN_FIELD_BASE(93, 93, 6, 0x0C0, 0x10, 9, 1), ++ PIN_FIELD_BASE(94, 94, 6, 0x0C0, 0x10, 13, 1), ++ PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 21, 1), ++ PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 11, 1), ++ PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 23, 1), ++ PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 13, 1), ++ PIN_FIELD_BASE(122, 122, 8, 0x0C0, 0x10, 1, 1), ++ PIN_FIELD_BASE(123, 123, 8, 0x0C0, 0x10, 5, 1), ++ PIN_FIELD_BASE(124, 124, 8, 0x0C0, 0x10, 9, 1), ++ PIN_FIELD_BASE(125, 125, 8, 0x0C0, 0x10, 13, 1), ++ PIN_FIELD_BASE(126, 126, 8, 0x0C0, 0x10, 17, 1), ++ PIN_FIELD_BASE(127, 127, 8, 0x0C0, 0x10, 21, 1), ++ PIN_FIELD_BASE(128, 128, 8, 0x0C0, 0x10, 25, 1), ++ PIN_FIELD_BASE(129, 129, 8, 0x0C0, 0x10, 29, 1), ++ PIN_FIELD_BASE(130, 130, 8, 0x0D0, 0x10, 1, 1), ++ PIN_FIELD_BASE(131, 131, 8, 0x0D0, 0x10, 5, 1), ++ PIN_FIELD_BASE(132, 132, 8, 0x0D0, 0x10, 9, 1), ++ PIN_FIELD_BASE(133, 133, 8, 0x0D0, 0x10, 13, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt8183_pin_e1e0en_range[] = { ++ PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 20, 1), ++ PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 15, 1), ++ PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 12, 1), ++ PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 7, 1), ++ PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 12, 1), ++ PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 9, 1), ++ PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 19, 1), ++ PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 22, 1), ++ PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 24, 1), ++ PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 14, 1), ++ PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 27, 1), ++ PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 17, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt8183_pin_e0_range[] = { ++ PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 21, 1), ++ PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 16, 1), ++ PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 13, 1), ++ PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 8, 1), ++ PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 13, 1), ++ PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 10, 1), ++ PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 20, 1), ++ PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 23, 1), ++ PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 25, 1), ++ PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 15, 1), ++ PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 28, 1), ++ PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 18, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt8183_pin_e1_range[] = { ++ PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 22, 1), ++ PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 17, 1), ++ PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 14, 1), ++ PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 9, 1), ++ PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 14, 1), ++ PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 11, 1), ++ PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 21, 1), ++ PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 24, 1), ++ PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 26, 1), ++ PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 16, 1), ++ PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 29, 1), ++ PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 19, 1), ++}; ++ ++static const struct mtk_pin_reg_calc mt8183_reg_cals[PINCTRL_PIN_REG_MAX] = { ++ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8183_pin_mode_range), ++ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8183_pin_dir_range), ++ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8183_pin_di_range), ++ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8183_pin_do_range), ++ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8183_pin_smt_range), ++ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8183_pin_ies_range), ++ [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8183_pin_pullen_range), ++ [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8183_pin_pullsel_range), ++ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8183_pin_drv_range), ++ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8183_pin_pupd_range), ++ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8183_pin_r0_range), ++ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8183_pin_r1_range), ++ [PINCTRL_PIN_REG_DRV_EN] = MTK_RANGE(mt8183_pin_e1e0en_range), ++ [PINCTRL_PIN_REG_DRV_E0] = MTK_RANGE(mt8183_pin_e0_range), ++ [PINCTRL_PIN_REG_DRV_E1] = MTK_RANGE(mt8183_pin_e1_range), ++}; ++ ++static const char * const mt8183_pinctrl_register_base_names[] = { ++ "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4", "iocfg5", ++ "iocfg6", "iocfg7", "iocfg8", ++}; ++ ++static const struct mtk_eint_hw mt8183_eint_hw = { ++ .port_mask = 7, ++ .ports = 6, ++ .ap_num = 212, ++ .db_cnt = 13, ++}; ++ ++static const struct mtk_pin_soc mt8183_data = { ++ .reg_cal = mt8183_reg_cals, ++ .pins = mtk_pins_mt8183, ++ .npins = ARRAY_SIZE(mtk_pins_mt8183), ++ .ngrps = ARRAY_SIZE(mtk_pins_mt8183), ++ .eint_hw = &mt8183_eint_hw, ++ .gpio_m = 0, ++ .ies_present = true, ++ .base_names = mt8183_pinctrl_register_base_names, ++ .nbase_names = ARRAY_SIZE(mt8183_pinctrl_register_base_names), ++ .bias_disable_set = mtk_pinconf_bias_disable_set_rev1, ++ .bias_disable_get = mtk_pinconf_bias_disable_get_rev1, ++ .bias_set = mtk_pinconf_bias_set_rev1, ++ .bias_get = mtk_pinconf_bias_get_rev1, ++ .drive_set = mtk_pinconf_drive_set_rev1, ++ .drive_get = mtk_pinconf_drive_get_rev1, ++ .adv_pull_get = mtk_pinconf_adv_pull_get, ++ .adv_pull_set = mtk_pinconf_adv_pull_set, ++ .adv_drive_get = mtk_pinconf_adv_drive_get, ++ .adv_drive_set = mtk_pinconf_adv_drive_set, ++}; ++ ++static const struct of_device_id mt8183_pinctrl_of_match[] = { ++ { .compatible = "mediatek,mt8183-pinctrl", }, ++ { } ++}; ++ ++static int mt8183_pinctrl_probe(struct platform_device *pdev) ++{ ++ return mtk_paris_pinctrl_probe(pdev, &mt8183_data); ++} ++ ++static struct platform_driver mt8183_pinctrl_driver = { ++ .driver = { ++ .name = "mt8183-pinctrl", ++ .of_match_table = mt8183_pinctrl_of_match, ++ .pm = &mtk_paris_pinctrl_pm_ops, ++ }, ++ .probe = mt8183_pinctrl_probe, ++}; ++ ++static int __init mt8183_pinctrl_init(void) ++{ ++ return platform_driver_register(&mt8183_pinctrl_driver); ++} ++arch_initcall(mt8183_pinctrl_init); +diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c +new file mode 100644 +index 000000000000..b375426aa61e +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c +@@ -0,0 +1,362 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2019 MediaTek Inc. ++ * Author: Min.Guo <min.guo@mediatek.com> ++ */ ++ ++#include <dt-bindings/pinctrl/mt65xx.h> ++#include <linux/of.h> ++#include <linux/of_device.h> ++#include <linux/module.h> ++#include <linux/pinctrl/pinctrl.h> ++#include <linux/platform_device.h> ++#include <linux/regmap.h> ++ ++#include "pinctrl-mtk-common.h" ++#include "pinctrl-mtk-mt8516.h" ++ ++static const struct mtk_drv_group_desc mt8516_drv_grp[] = { ++ /* 0E4E8SR 4/8/12/16 */ ++ MTK_DRV_GRP(4, 16, 1, 2, 4), ++ /* 0E2E4SR 2/4/6/8 */ ++ MTK_DRV_GRP(2, 8, 1, 2, 2), ++ /* E8E4E2 2/4/6/8/10/12/14/16 */ ++ MTK_DRV_GRP(2, 16, 0, 2, 2) ++}; ++ ++static const struct mtk_pin_drv_grp mt8516_pin_drv[] = { ++ MTK_PIN_DRV_GRP(0, 0xd00, 0, 0), ++ MTK_PIN_DRV_GRP(1, 0xd00, 0, 0), ++ MTK_PIN_DRV_GRP(2, 0xd00, 0, 0), ++ MTK_PIN_DRV_GRP(3, 0xd00, 0, 0), ++ MTK_PIN_DRV_GRP(4, 0xd00, 0, 0), ++ ++ MTK_PIN_DRV_GRP(5, 0xd00, 4, 0), ++ MTK_PIN_DRV_GRP(6, 0xd00, 4, 0), ++ MTK_PIN_DRV_GRP(7, 0xd00, 4, 0), ++ MTK_PIN_DRV_GRP(8, 0xd00, 4, 0), ++ MTK_PIN_DRV_GRP(9, 0xd00, 4, 0), ++ MTK_PIN_DRV_GRP(10, 0xd00, 4, 0), ++ ++ MTK_PIN_DRV_GRP(11, 0xd00, 8, 0), ++ MTK_PIN_DRV_GRP(12, 0xd00, 8, 0), ++ MTK_PIN_DRV_GRP(13, 0xd00, 8, 0), ++ ++ MTK_PIN_DRV_GRP(14, 0xd00, 12, 2), ++ MTK_PIN_DRV_GRP(15, 0xd00, 12, 2), ++ MTK_PIN_DRV_GRP(16, 0xd00, 12, 2), ++ MTK_PIN_DRV_GRP(17, 0xd00, 12, 2), ++ ++ MTK_PIN_DRV_GRP(18, 0xd10, 0, 0), ++ MTK_PIN_DRV_GRP(19, 0xd10, 0, 0), ++ MTK_PIN_DRV_GRP(20, 0xd10, 0, 0), ++ ++ MTK_PIN_DRV_GRP(21, 0xd00, 12, 2), ++ MTK_PIN_DRV_GRP(22, 0xd00, 12, 2), ++ MTK_PIN_DRV_GRP(23, 0xd00, 12, 2), ++ ++ MTK_PIN_DRV_GRP(24, 0xd00, 8, 0), ++ MTK_PIN_DRV_GRP(25, 0xd00, 8, 0), ++ ++ MTK_PIN_DRV_GRP(26, 0xd10, 4, 1), ++ MTK_PIN_DRV_GRP(27, 0xd10, 4, 1), ++ MTK_PIN_DRV_GRP(28, 0xd10, 4, 1), ++ MTK_PIN_DRV_GRP(29, 0xd10, 4, 1), ++ MTK_PIN_DRV_GRP(30, 0xd10, 4, 1), ++ ++ MTK_PIN_DRV_GRP(31, 0xd10, 8, 1), ++ MTK_PIN_DRV_GRP(32, 0xd10, 8, 1), ++ MTK_PIN_DRV_GRP(33, 0xd10, 8, 1), ++ ++ MTK_PIN_DRV_GRP(34, 0xd10, 12, 0), ++ MTK_PIN_DRV_GRP(35, 0xd10, 12, 0), ++ ++ MTK_PIN_DRV_GRP(36, 0xd20, 0, 0), ++ MTK_PIN_DRV_GRP(37, 0xd20, 0, 0), ++ MTK_PIN_DRV_GRP(38, 0xd20, 0, 0), ++ MTK_PIN_DRV_GRP(39, 0xd20, 0, 0), ++ ++ MTK_PIN_DRV_GRP(40, 0xd20, 4, 1), ++ ++ MTK_PIN_DRV_GRP(41, 0xd20, 8, 1), ++ MTK_PIN_DRV_GRP(42, 0xd20, 8, 1), ++ MTK_PIN_DRV_GRP(43, 0xd20, 8, 1), ++ ++ MTK_PIN_DRV_GRP(44, 0xd20, 12, 1), ++ MTK_PIN_DRV_GRP(45, 0xd20, 12, 1), ++ MTK_PIN_DRV_GRP(46, 0xd20, 12, 1), ++ MTK_PIN_DRV_GRP(47, 0xd20, 12, 1), ++ ++ MTK_PIN_DRV_GRP(48, 0xd30, 0, 1), ++ MTK_PIN_DRV_GRP(49, 0xd30, 0, 1), ++ MTK_PIN_DRV_GRP(50, 0xd30, 0, 1), ++ MTK_PIN_DRV_GRP(51, 0xd30, 0, 1), ++ ++ MTK_PIN_DRV_GRP(54, 0xd30, 8, 1), ++ ++ MTK_PIN_DRV_GRP(55, 0xd30, 12, 1), ++ MTK_PIN_DRV_GRP(56, 0xd30, 12, 1), ++ MTK_PIN_DRV_GRP(57, 0xd30, 12, 1), ++ ++ MTK_PIN_DRV_GRP(62, 0xd40, 8, 1), ++ MTK_PIN_DRV_GRP(63, 0xd40, 8, 1), ++ MTK_PIN_DRV_GRP(64, 0xd40, 8, 1), ++ MTK_PIN_DRV_GRP(65, 0xd40, 8, 1), ++ MTK_PIN_DRV_GRP(66, 0xd40, 8, 1), ++ MTK_PIN_DRV_GRP(67, 0xd40, 8, 1), ++ ++ MTK_PIN_DRV_GRP(68, 0xd40, 12, 2), ++ ++ MTK_PIN_DRV_GRP(69, 0xd50, 0, 2), ++ ++ MTK_PIN_DRV_GRP(70, 0xd50, 4, 2), ++ MTK_PIN_DRV_GRP(71, 0xd50, 4, 2), ++ MTK_PIN_DRV_GRP(72, 0xd50, 4, 2), ++ MTK_PIN_DRV_GRP(73, 0xd50, 4, 2), ++ ++ MTK_PIN_DRV_GRP(100, 0xd50, 8, 1), ++ MTK_PIN_DRV_GRP(101, 0xd50, 8, 1), ++ MTK_PIN_DRV_GRP(102, 0xd50, 8, 1), ++ MTK_PIN_DRV_GRP(103, 0xd50, 8, 1), ++ ++ MTK_PIN_DRV_GRP(104, 0xd50, 12, 2), ++ ++ MTK_PIN_DRV_GRP(105, 0xd60, 0, 2), ++ ++ MTK_PIN_DRV_GRP(106, 0xd60, 4, 2), ++ MTK_PIN_DRV_GRP(107, 0xd60, 4, 2), ++ MTK_PIN_DRV_GRP(108, 0xd60, 4, 2), ++ MTK_PIN_DRV_GRP(109, 0xd60, 4, 2), ++ ++ MTK_PIN_DRV_GRP(110, 0xd70, 0, 2), ++ MTK_PIN_DRV_GRP(111, 0xd70, 0, 2), ++ MTK_PIN_DRV_GRP(112, 0xd70, 0, 2), ++ MTK_PIN_DRV_GRP(113, 0xd70, 0, 2), ++ ++ MTK_PIN_DRV_GRP(114, 0xd70, 4, 2), ++ ++ MTK_PIN_DRV_GRP(115, 0xd60, 12, 2), ++ ++ MTK_PIN_DRV_GRP(116, 0xd60, 8, 2), ++ ++ MTK_PIN_DRV_GRP(117, 0xd70, 0, 2), ++ MTK_PIN_DRV_GRP(118, 0xd70, 0, 2), ++ MTK_PIN_DRV_GRP(119, 0xd70, 0, 2), ++ MTK_PIN_DRV_GRP(120, 0xd70, 0, 2), ++}; ++ ++static const struct mtk_pin_spec_pupd_set_samereg mt8516_spec_pupd[] = { ++ MTK_PIN_PUPD_SPEC_SR(14, 0xe50, 14, 13, 12), ++ MTK_PIN_PUPD_SPEC_SR(15, 0xe60, 2, 1, 0), ++ MTK_PIN_PUPD_SPEC_SR(16, 0xe60, 6, 5, 4), ++ MTK_PIN_PUPD_SPEC_SR(17, 0xe60, 10, 9, 8), ++ ++ MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 14, 13, 12), ++ MTK_PIN_PUPD_SPEC_SR(22, 0xe70, 2, 1, 0), ++ MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 6, 5, 4), ++ ++ MTK_PIN_PUPD_SPEC_SR(40, 0xe80, 2, 1, 0), ++ MTK_PIN_PUPD_SPEC_SR(41, 0xe80, 6, 5, 4), ++ MTK_PIN_PUPD_SPEC_SR(42, 0xe90, 2, 1, 0), ++ MTK_PIN_PUPD_SPEC_SR(43, 0xe90, 6, 5, 4), ++ ++ MTK_PIN_PUPD_SPEC_SR(68, 0xe50, 10, 9, 8), ++ MTK_PIN_PUPD_SPEC_SR(69, 0xe50, 6, 5, 4), ++ MTK_PIN_PUPD_SPEC_SR(70, 0xe40, 6, 5, 4), ++ MTK_PIN_PUPD_SPEC_SR(71, 0xe40, 10, 9, 8), ++ MTK_PIN_PUPD_SPEC_SR(72, 0xe40, 14, 13, 12), ++ MTK_PIN_PUPD_SPEC_SR(73, 0xe50, 2, 1, 0), ++ ++ MTK_PIN_PUPD_SPEC_SR(104, 0xe40, 2, 1, 0), ++ MTK_PIN_PUPD_SPEC_SR(105, 0xe30, 14, 13, 12), ++ MTK_PIN_PUPD_SPEC_SR(106, 0xe20, 14, 13, 12), ++ MTK_PIN_PUPD_SPEC_SR(107, 0xe30, 2, 1, 0), ++ MTK_PIN_PUPD_SPEC_SR(108, 0xe30, 6, 5, 4), ++ MTK_PIN_PUPD_SPEC_SR(109, 0xe30, 10, 9, 8), ++ MTK_PIN_PUPD_SPEC_SR(110, 0xe10, 14, 13, 12), ++ MTK_PIN_PUPD_SPEC_SR(111, 0xe10, 10, 9, 8), ++ MTK_PIN_PUPD_SPEC_SR(112, 0xe10, 6, 5, 4), ++ MTK_PIN_PUPD_SPEC_SR(113, 0xe10, 2, 1, 0), ++ MTK_PIN_PUPD_SPEC_SR(114, 0xe20, 10, 9, 8), ++ MTK_PIN_PUPD_SPEC_SR(115, 0xe20, 2, 1, 0), ++ MTK_PIN_PUPD_SPEC_SR(116, 0xe20, 6, 5, 4), ++ MTK_PIN_PUPD_SPEC_SR(117, 0xe00, 14, 13, 12), ++ MTK_PIN_PUPD_SPEC_SR(118, 0xe00, 10, 9, 8), ++ MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 6, 5, 4), ++ MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0), ++}; ++ ++static int mt8516_spec_pull_set(struct regmap *regmap, unsigned int pin, ++ unsigned char align, bool isup, unsigned int r1r0) ++{ ++ return mtk_pctrl_spec_pull_set_samereg(regmap, mt8516_spec_pupd, ++ ARRAY_SIZE(mt8516_spec_pupd), pin, align, isup, r1r0); ++} ++ ++static const struct mtk_pin_ies_smt_set mt8516_ies_set[] = { ++ MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2), ++ MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3), ++ MTK_PIN_IES_SMT_SPEC(11, 13, 0x900, 12), ++ MTK_PIN_IES_SMT_SPEC(14, 17, 0x900, 13), ++ MTK_PIN_IES_SMT_SPEC(18, 20, 0x910, 10), ++ MTK_PIN_IES_SMT_SPEC(21, 23, 0x900, 13), ++ MTK_PIN_IES_SMT_SPEC(24, 25, 0x900, 12), ++ MTK_PIN_IES_SMT_SPEC(26, 30, 0x900, 0), ++ MTK_PIN_IES_SMT_SPEC(31, 33, 0x900, 1), ++ MTK_PIN_IES_SMT_SPEC(34, 39, 0x900, 2), ++ MTK_PIN_IES_SMT_SPEC(40, 40, 0x910, 11), ++ MTK_PIN_IES_SMT_SPEC(41, 43, 0x900, 10), ++ MTK_PIN_IES_SMT_SPEC(44, 47, 0x900, 11), ++ MTK_PIN_IES_SMT_SPEC(48, 51, 0x900, 14), ++ MTK_PIN_IES_SMT_SPEC(52, 53, 0x910, 0), ++ MTK_PIN_IES_SMT_SPEC(54, 54, 0x910, 2), ++ MTK_PIN_IES_SMT_SPEC(55, 57, 0x910, 4), ++ MTK_PIN_IES_SMT_SPEC(58, 59, 0x900, 15), ++ MTK_PIN_IES_SMT_SPEC(60, 61, 0x910, 1), ++ MTK_PIN_IES_SMT_SPEC(62, 65, 0x910, 5), ++ MTK_PIN_IES_SMT_SPEC(66, 67, 0x910, 6), ++ MTK_PIN_IES_SMT_SPEC(68, 68, 0x930, 2), ++ MTK_PIN_IES_SMT_SPEC(69, 69, 0x930, 1), ++ MTK_PIN_IES_SMT_SPEC(70, 70, 0x930, 6), ++ MTK_PIN_IES_SMT_SPEC(71, 71, 0x930, 5), ++ MTK_PIN_IES_SMT_SPEC(72, 72, 0x930, 4), ++ MTK_PIN_IES_SMT_SPEC(73, 73, 0x930, 3), ++ MTK_PIN_IES_SMT_SPEC(100, 103, 0x910, 7), ++ MTK_PIN_IES_SMT_SPEC(104, 104, 0x920, 12), ++ MTK_PIN_IES_SMT_SPEC(105, 105, 0x920, 11), ++ MTK_PIN_IES_SMT_SPEC(106, 106, 0x930, 0), ++ MTK_PIN_IES_SMT_SPEC(107, 107, 0x920, 15), ++ MTK_PIN_IES_SMT_SPEC(108, 108, 0x920, 14), ++ MTK_PIN_IES_SMT_SPEC(109, 109, 0x920, 13), ++ MTK_PIN_IES_SMT_SPEC(110, 110, 0x920, 9), ++ MTK_PIN_IES_SMT_SPEC(111, 111, 0x920, 8), ++ MTK_PIN_IES_SMT_SPEC(112, 112, 0x920, 7), ++ MTK_PIN_IES_SMT_SPEC(113, 113, 0x920, 6), ++ MTK_PIN_IES_SMT_SPEC(114, 114, 0x920, 10), ++ MTK_PIN_IES_SMT_SPEC(115, 115, 0x920, 1), ++ MTK_PIN_IES_SMT_SPEC(116, 116, 0x920, 0), ++ MTK_PIN_IES_SMT_SPEC(117, 117, 0x920, 5), ++ MTK_PIN_IES_SMT_SPEC(118, 118, 0x920, 4), ++ MTK_PIN_IES_SMT_SPEC(119, 119, 0x920, 3), ++ MTK_PIN_IES_SMT_SPEC(120, 120, 0x920, 2), ++ MTK_PIN_IES_SMT_SPEC(121, 124, 0x910, 9), ++}; ++ ++static const struct mtk_pin_ies_smt_set mt8516_smt_set[] = { ++ MTK_PIN_IES_SMT_SPEC(0, 6, 0xA00, 2), ++ MTK_PIN_IES_SMT_SPEC(7, 10, 0xA00, 3), ++ MTK_PIN_IES_SMT_SPEC(11, 13, 0xA00, 12), ++ MTK_PIN_IES_SMT_SPEC(14, 17, 0xA00, 13), ++ MTK_PIN_IES_SMT_SPEC(18, 20, 0xA10, 10), ++ MTK_PIN_IES_SMT_SPEC(21, 23, 0xA00, 13), ++ MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12), ++ MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0), ++ MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1), ++ MTK_PIN_IES_SMT_SPEC(34, 39, 0xA900, 2), ++ MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11), ++ MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10), ++ MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11), ++ MTK_PIN_IES_SMT_SPEC(48, 51, 0xA00, 14), ++ MTK_PIN_IES_SMT_SPEC(52, 53, 0xA10, 0), ++ MTK_PIN_IES_SMT_SPEC(54, 54, 0xA10, 2), ++ MTK_PIN_IES_SMT_SPEC(55, 57, 0xA10, 4), ++ MTK_PIN_IES_SMT_SPEC(58, 59, 0xA00, 15), ++ MTK_PIN_IES_SMT_SPEC(60, 61, 0xA10, 1), ++ MTK_PIN_IES_SMT_SPEC(62, 65, 0xA10, 5), ++ MTK_PIN_IES_SMT_SPEC(66, 67, 0xA10, 6), ++ MTK_PIN_IES_SMT_SPEC(68, 68, 0xA30, 2), ++ MTK_PIN_IES_SMT_SPEC(69, 69, 0xA30, 1), ++ MTK_PIN_IES_SMT_SPEC(70, 70, 0xA30, 3), ++ MTK_PIN_IES_SMT_SPEC(71, 71, 0xA30, 4), ++ MTK_PIN_IES_SMT_SPEC(72, 72, 0xA30, 5), ++ MTK_PIN_IES_SMT_SPEC(73, 73, 0xA30, 6), ++ ++ MTK_PIN_IES_SMT_SPEC(100, 103, 0xA10, 7), ++ MTK_PIN_IES_SMT_SPEC(104, 104, 0xA20, 12), ++ MTK_PIN_IES_SMT_SPEC(105, 105, 0xA20, 11), ++ MTK_PIN_IES_SMT_SPEC(106, 106, 0xA30, 13), ++ MTK_PIN_IES_SMT_SPEC(107, 107, 0xA20, 14), ++ MTK_PIN_IES_SMT_SPEC(108, 108, 0xA20, 15), ++ MTK_PIN_IES_SMT_SPEC(109, 109, 0xA30, 0), ++ MTK_PIN_IES_SMT_SPEC(110, 110, 0xA20, 9), ++ MTK_PIN_IES_SMT_SPEC(111, 111, 0xA20, 8), ++ MTK_PIN_IES_SMT_SPEC(112, 112, 0xA20, 7), ++ MTK_PIN_IES_SMT_SPEC(113, 113, 0xA20, 6), ++ MTK_PIN_IES_SMT_SPEC(114, 114, 0xA20, 10), ++ MTK_PIN_IES_SMT_SPEC(115, 115, 0xA20, 1), ++ MTK_PIN_IES_SMT_SPEC(116, 116, 0xA20, 0), ++ MTK_PIN_IES_SMT_SPEC(117, 117, 0xA20, 5), ++ MTK_PIN_IES_SMT_SPEC(118, 118, 0xA20, 4), ++ MTK_PIN_IES_SMT_SPEC(119, 119, 0xA20, 3), ++ MTK_PIN_IES_SMT_SPEC(120, 120, 0xA20, 2), ++ MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9), ++}; ++ ++static int mt8516_ies_smt_set(struct regmap *regmap, unsigned int pin, ++ unsigned char align, int value, enum pin_config_param arg) ++{ ++ if (arg == PIN_CONFIG_INPUT_ENABLE) ++ return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_ies_set, ++ ARRAY_SIZE(mt8516_ies_set), pin, align, value); ++ else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) ++ return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_smt_set, ++ ARRAY_SIZE(mt8516_smt_set), pin, align, value); ++ return -EINVAL; ++} ++ ++static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = { ++ .pins = mtk_pins_mt8516, ++ .npins = ARRAY_SIZE(mtk_pins_mt8516), ++ .grp_desc = mt8516_drv_grp, ++ .n_grp_cls = ARRAY_SIZE(mt8516_drv_grp), ++ .pin_drv_grp = mt8516_pin_drv, ++ .n_pin_drv_grps = ARRAY_SIZE(mt8516_pin_drv), ++ .spec_pull_set = mt8516_spec_pull_set, ++ .spec_ies_smt_set = mt8516_ies_smt_set, ++ .dir_offset = 0x0000, ++ .pullen_offset = 0x0500, ++ .pullsel_offset = 0x0600, ++ .dout_offset = 0x0100, ++ .din_offset = 0x0200, ++ .pinmux_offset = 0x0300, ++ .type1_start = 125, ++ .type1_end = 125, ++ .port_shf = 4, ++ .port_mask = 0xf, ++ .port_align = 4, ++ .eint_hw = { ++ .port_mask = 7, ++ .ports = 6, ++ .ap_num = 169, ++ .db_cnt = 64, ++ }, ++}; ++ ++static int mt8516_pinctrl_probe(struct platform_device *pdev) ++{ ++ return mtk_pctrl_init(pdev, &mt8516_pinctrl_data, NULL); ++} ++ ++static const struct of_device_id mt8516_pctrl_match[] = { ++ { ++ .compatible = "mediatek,mt8516-pinctrl", ++ }, ++ {} ++}; ++ ++MODULE_DEVICE_TABLE(of, mt8516_pctrl_match); ++ ++static struct platform_driver mtk_pinctrl_driver = { ++ .probe = mt8516_pinctrl_probe, ++ .driver = { ++ .name = "mediatek-mt8516-pinctrl", ++ .of_match_table = mt8516_pctrl_match, ++ .pm = &mtk_eint_pm_ops, ++ }, ++}; ++ ++static int __init mtk_pinctrl_init(void) ++{ ++ return platform_driver_register(&mtk_pinctrl_driver); ++} ++arch_initcall(mtk_pinctrl_init); +diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +new file mode 100644 +index 000000000000..20e1c890e73b +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +@@ -0,0 +1,725 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2018 MediaTek Inc. ++ * ++ * Author: Sean Wang <sean.wang@mediatek.com> ++ * ++ */ ++ ++#include <linux/device.h> ++#include <linux/err.h> ++#include <linux/gpio/driver.h> ++#include <linux/platform_device.h> ++#include <linux/io.h> ++#include <linux/of_irq.h> ++ ++#include "mtk-eint.h" ++#include "pinctrl-mtk-common-v2.h" ++ ++/** ++ * struct mtk_drive_desc - the structure that holds the information ++ * of the driving current ++ * @min: the minimum current of this group ++ * @max: the maximum current of this group ++ * @step: the step current of this group ++ * @scal: the weight factor ++ * ++ * formula: output = ((input) / step - 1) * scal ++ */ ++struct mtk_drive_desc { ++ u8 min; ++ u8 max; ++ u8 step; ++ u8 scal; ++}; ++ ++/* The groups of drive strength */ ++static const struct mtk_drive_desc mtk_drive[] = { ++ [DRV_GRP0] = { 4, 16, 4, 1 }, ++ [DRV_GRP1] = { 4, 16, 4, 2 }, ++ [DRV_GRP2] = { 2, 8, 2, 1 }, ++ [DRV_GRP3] = { 2, 8, 2, 2 }, ++ [DRV_GRP4] = { 2, 16, 2, 1 }, ++}; ++ ++static void mtk_w32(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 val) ++{ ++ writel_relaxed(val, pctl->base[i] + reg); ++} ++ ++static u32 mtk_r32(struct mtk_pinctrl *pctl, u8 i, u32 reg) ++{ ++ return readl_relaxed(pctl->base[i] + reg); ++} ++ ++void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set) ++{ ++ u32 val; ++ ++ val = mtk_r32(pctl, i, reg); ++ val &= ~mask; ++ val |= set; ++ mtk_w32(pctl, i, reg, val); ++} ++ ++static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, ++ int field, struct mtk_pin_field *pfd) ++{ ++ const struct mtk_pin_field_calc *c, *e; ++ const struct mtk_pin_reg_calc *rc; ++ u32 bits; ++ ++ if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) { ++ rc = &hw->soc->reg_cal[field]; ++ } else { ++ dev_dbg(hw->dev, ++ "Not support field %d for pin %d (%s)\n", ++ field, desc->number, desc->name); ++ return -ENOTSUPP; ++ } ++ ++ c = rc->range; ++ e = c + rc->nranges; ++ ++ while (c < e) { ++ if (desc->number >= c->s_pin && desc->number <= c->e_pin) ++ break; ++ c++; ++ } ++ ++ if (c >= e) { ++ dev_dbg(hw->dev, "Not support field %d for pin = %d (%s)\n", ++ field, desc->number, desc->name); ++ return -ENOTSUPP; ++ } ++ ++ if (c->i_base > hw->nbase - 1) { ++ dev_err(hw->dev, ++ "Invalid base for field %d for pin = %d (%s)\n", ++ field, desc->number, desc->name); ++ return -EINVAL; ++ } ++ ++ /* Calculated bits as the overall offset the pin is located at, ++ * if c->fixed is held, that determines the all the pins in the ++ * range use the same field with the s_pin. ++ */ ++ bits = c->fixed ? c->s_bit : c->s_bit + ++ (desc->number - c->s_pin) * (c->x_bits); ++ ++ /* Fill pfd from bits. For example 32-bit register applied is assumed ++ * when c->sz_reg is equal to 32. ++ */ ++ pfd->index = c->i_base; ++ pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg); ++ pfd->bitpos = bits % c->sz_reg; ++ pfd->mask = (1 << c->x_bits) - 1; ++ ++ /* pfd->next is used for indicating that bit wrapping-around happens ++ * which requires the manipulation for bit 0 starting in the next ++ * register to form the complete field read/write. ++ */ ++ pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0; ++ ++ return 0; ++} ++ ++static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, ++ int field, struct mtk_pin_field *pfd) ++{ ++ if (field < 0 || field >= PINCTRL_PIN_REG_MAX) { ++ dev_err(hw->dev, "Invalid Field %d\n", field); ++ return -EINVAL; ++ } ++ ++ return mtk_hw_pin_field_lookup(hw, desc, field, pfd); ++} ++ ++static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l) ++{ ++ *l = 32 - pf->bitpos; ++ *h = get_count_order(pf->mask) - *l; ++} ++ ++static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw, ++ struct mtk_pin_field *pf, int value) ++{ ++ int nbits_l, nbits_h; ++ ++ mtk_hw_bits_part(pf, &nbits_h, &nbits_l); ++ ++ mtk_rmw(hw, pf->index, pf->offset, pf->mask << pf->bitpos, ++ (value & pf->mask) << pf->bitpos); ++ ++ mtk_rmw(hw, pf->index, pf->offset + pf->next, BIT(nbits_h) - 1, ++ (value & pf->mask) >> nbits_l); ++} ++ ++static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw, ++ struct mtk_pin_field *pf, int *value) ++{ ++ int nbits_l, nbits_h, h, l; ++ ++ mtk_hw_bits_part(pf, &nbits_h, &nbits_l); ++ ++ l = (mtk_r32(hw, pf->index, pf->offset) ++ >> pf->bitpos) & (BIT(nbits_l) - 1); ++ h = (mtk_r32(hw, pf->index, pf->offset + pf->next)) ++ & (BIT(nbits_h) - 1); ++ ++ *value = (h << nbits_l) | l; ++} ++ ++int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, ++ int field, int value) ++{ ++ struct mtk_pin_field pf; ++ int err; ++ ++ err = mtk_hw_pin_field_get(hw, desc, field, &pf); ++ if (err) ++ return err; ++ ++ if (!pf.next) ++ mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos, ++ (value & pf.mask) << pf.bitpos); ++ else ++ mtk_hw_write_cross_field(hw, &pf, value); ++ ++ return 0; ++} ++ ++int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, ++ int field, int *value) ++{ ++ struct mtk_pin_field pf; ++ int err; ++ ++ err = mtk_hw_pin_field_get(hw, desc, field, &pf); ++ if (err) ++ return err; ++ ++ if (!pf.next) ++ *value = (mtk_r32(hw, pf.index, pf.offset) ++ >> pf.bitpos) & pf.mask; ++ else ++ mtk_hw_read_cross_field(hw, &pf, value); ++ ++ return 0; ++} ++ ++static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n) ++{ ++ const struct mtk_pin_desc *desc; ++ int i = 0; ++ ++ desc = (const struct mtk_pin_desc *)hw->soc->pins; ++ ++ while (i < hw->soc->npins) { ++ if (desc[i].eint.eint_n == eint_n) ++ return desc[i].number; ++ i++; ++ } ++ ++ return EINT_NA; ++} ++ ++static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n, ++ unsigned int *gpio_n, ++ struct gpio_chip **gpio_chip) ++{ ++ struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data; ++ const struct mtk_pin_desc *desc; ++ ++ desc = (const struct mtk_pin_desc *)hw->soc->pins; ++ *gpio_chip = &hw->chip; ++ ++ /* Be greedy to guess first gpio_n is equal to eint_n */ ++ if (desc[eint_n].eint.eint_n == eint_n) ++ *gpio_n = eint_n; ++ else ++ *gpio_n = mtk_xt_find_eint_num(hw, eint_n); ++ ++ return *gpio_n == EINT_NA ? -EINVAL : 0; ++} ++ ++static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n) ++{ ++ struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data; ++ const struct mtk_pin_desc *desc; ++ struct gpio_chip *gpio_chip; ++ unsigned int gpio_n; ++ int value, err; ++ ++ err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip); ++ if (err) ++ return err; ++ ++ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n]; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value); ++ if (err) ++ return err; ++ ++ return !!value; ++} ++ ++static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n) ++{ ++ struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data; ++ const struct mtk_pin_desc *desc; ++ struct gpio_chip *gpio_chip; ++ unsigned int gpio_n; ++ int err; ++ ++ err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip); ++ if (err) ++ return err; ++ ++ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n]; ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, ++ desc->eint.eint_m); ++ if (err) ++ return err; ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT); ++ if (err) ++ return err; ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, MTK_ENABLE); ++ /* SMT is supposed to be supported by every real GPIO and doesn't ++ * support virtual GPIOs, so the extra condition err != -ENOTSUPP ++ * is just for adding EINT support to these virtual GPIOs. It should ++ * add an extra flag in the pin descriptor when more pins with ++ * distinctive characteristic come out. ++ */ ++ if (err && err != -ENOTSUPP) ++ return err; ++ ++ return 0; ++} ++ ++static const struct mtk_eint_xt mtk_eint_xt = { ++ .get_gpio_n = mtk_xt_get_gpio_n, ++ .get_gpio_state = mtk_xt_get_gpio_state, ++ .set_gpio_as_eint = mtk_xt_set_gpio_as_eint, ++}; ++ ++int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ struct resource *res; ++ ++ if (!IS_ENABLED(CONFIG_EINT_MTK)) ++ return 0; ++ ++ if (!of_property_read_bool(np, "interrupt-controller")) ++ return -ENODEV; ++ ++ hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL); ++ if (!hw->eint) ++ return -ENOMEM; ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eint"); ++ if (!res) { ++ dev_err(&pdev->dev, "Unable to get eint resource\n"); ++ return -ENODEV; ++ } ++ ++ hw->eint->base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(hw->eint->base)) ++ return PTR_ERR(hw->eint->base); ++ ++ hw->eint->irq = irq_of_parse_and_map(np, 0); ++ if (!hw->eint->irq) ++ return -EINVAL; ++ ++ if (!hw->soc->eint_hw) ++ return -ENODEV; ++ ++ hw->eint->dev = &pdev->dev; ++ hw->eint->hw = hw->soc->eint_hw; ++ hw->eint->pctl = hw; ++ hw->eint->gpio_xlate = &mtk_eint_xt; ++ ++ return mtk_eint_do_init(hw->eint); ++} ++ ++/* Revision 0 */ ++int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc) ++{ ++ int err; ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, ++ MTK_DISABLE); ++ if (err) ++ return err; ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, ++ MTK_DISABLE); ++ if (err) ++ return err; ++ ++ return 0; ++} ++ ++int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, int *res) ++{ ++ int v, v2; ++ int err; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &v); ++ if (err) ++ return err; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &v2); ++ if (err) ++ return err; ++ ++ if (v == MTK_ENABLE || v2 == MTK_ENABLE) ++ return -EINVAL; ++ ++ *res = 1; ++ ++ return 0; ++} ++ ++int mtk_pinconf_bias_set(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, bool pullup) ++{ ++ int err, arg; ++ ++ arg = pullup ? 1 : 2; ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, arg & 1); ++ if (err) ++ return err; ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, ++ !!(arg & 2)); ++ if (err) ++ return err; ++ ++ return 0; ++} ++ ++int mtk_pinconf_bias_get(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, bool pullup, int *res) ++{ ++ int reg, err, v; ++ ++ reg = pullup ? PINCTRL_PIN_REG_PU : PINCTRL_PIN_REG_PD; ++ ++ err = mtk_hw_get_value(hw, desc, reg, &v); ++ if (err) ++ return err; ++ ++ if (!v) ++ return -EINVAL; ++ ++ *res = 1; ++ ++ return 0; ++} ++ ++/* Revision 1 */ ++int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc) ++{ ++ int err; ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, ++ MTK_DISABLE); ++ if (err) ++ return err; ++ ++ return 0; ++} ++ ++int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, int *res) ++{ ++ int v, err; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v); ++ if (err) ++ return err; ++ ++ if (v == MTK_ENABLE) ++ return -EINVAL; ++ ++ *res = 1; ++ ++ return 0; ++} ++ ++int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, bool pullup) ++{ ++ int err, arg; ++ ++ arg = pullup ? MTK_PULLUP : MTK_PULLDOWN; ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, ++ MTK_ENABLE); ++ if (err) ++ return err; ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, arg); ++ if (err) ++ return err; ++ ++ return 0; ++} ++ ++int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, bool pullup, ++ int *res) ++{ ++ int err, v; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v); ++ if (err) ++ return err; ++ ++ if (v == MTK_DISABLE) ++ return -EINVAL; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, &v); ++ if (err) ++ return err; ++ ++ if (pullup ^ (v == MTK_PULLUP)) ++ return -EINVAL; ++ ++ *res = 1; ++ ++ return 0; ++} ++ ++/* Revision 0 */ ++int mtk_pinconf_drive_set(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, u32 arg) ++{ ++ const struct mtk_drive_desc *tb; ++ int err = -ENOTSUPP; ++ ++ tb = &mtk_drive[desc->drv_n]; ++ /* 4mA when (e8, e4) = (0, 0) ++ * 8mA when (e8, e4) = (0, 1) ++ * 12mA when (e8, e4) = (1, 0) ++ * 16mA when (e8, e4) = (1, 1) ++ */ ++ if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) { ++ arg = (arg / tb->step - 1) * tb->scal; ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E4, ++ arg & 0x1); ++ if (err) ++ return err; ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E8, ++ (arg & 0x2) >> 1); ++ if (err) ++ return err; ++ } ++ ++ return err; ++} ++ ++int mtk_pinconf_drive_get(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, int *val) ++{ ++ const struct mtk_drive_desc *tb; ++ int err, val1, val2; ++ ++ tb = &mtk_drive[desc->drv_n]; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E4, &val1); ++ if (err) ++ return err; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E8, &val2); ++ if (err) ++ return err; ++ ++ /* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1) ++ * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1) ++ */ ++ *val = (((val2 << 1) + val1) / tb->scal + 1) * tb->step; ++ ++ return 0; ++} ++ ++/* Revision 1 */ ++int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, u32 arg) ++{ ++ const struct mtk_drive_desc *tb; ++ int err = -ENOTSUPP; ++ ++ tb = &mtk_drive[desc->drv_n]; ++ ++ if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) { ++ arg = (arg / tb->step - 1) * tb->scal; ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV, ++ arg); ++ if (err) ++ return err; ++ } ++ ++ return err; ++} ++ ++int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, int *val) ++{ ++ const struct mtk_drive_desc *tb; ++ int err, val1; ++ ++ tb = &mtk_drive[desc->drv_n]; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, &val1); ++ if (err) ++ return err; ++ ++ *val = ((val1 & 0x7) / tb->scal + 1) * tb->step; ++ ++ return 0; ++} ++ ++int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, bool pullup, ++ u32 arg) ++{ ++ int err; ++ ++ /* 10K off & 50K (75K) off, when (R0, R1) = (0, 0); ++ * 10K off & 50K (75K) on, when (R0, R1) = (0, 1); ++ * 10K on & 50K (75K) off, when (R0, R1) = (1, 0); ++ * 10K on & 50K (75K) on, when (R0, R1) = (1, 1) ++ */ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, arg & 1); ++ if (err) ++ return 0; ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1, ++ !!(arg & 2)); ++ if (err) ++ return 0; ++ ++ arg = pullup ? 0 : 1; ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, arg); ++ ++ /* If PUPD register is not supported for that pin, let's fallback to ++ * general bias control. ++ */ ++ if (err == -ENOTSUPP) { ++ if (hw->soc->bias_set) { ++ err = hw->soc->bias_set(hw, desc, pullup); ++ if (err) ++ return err; ++ } else { ++ return -ENOTSUPP; ++ } ++ } ++ ++ return err; ++} ++ ++int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, bool pullup, ++ u32 *val) ++{ ++ u32 t, t2; ++ int err; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, &t); ++ ++ /* If PUPD register is not supported for that pin, let's fallback to ++ * general bias control. ++ */ ++ if (err == -ENOTSUPP) { ++ if (hw->soc->bias_get) { ++ err = hw->soc->bias_get(hw, desc, pullup, val); ++ if (err) ++ return err; ++ } else { ++ return -ENOTSUPP; ++ } ++ } else { ++ /* t == 0 supposes PULLUP for the customized PULL setup */ ++ if (err) ++ return err; ++ ++ if (pullup ^ !t) ++ return -EINVAL; ++ } ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &t); ++ if (err) ++ return err; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &t2); ++ if (err) ++ return err; ++ ++ *val = (t | t2 << 1) & 0x7; ++ ++ return 0; ++} ++ ++int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, u32 arg) ++{ ++ int err; ++ int en = arg & 1; ++ int e0 = !!(arg & 2); ++ int e1 = !!(arg & 4); ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, en); ++ if (err) ++ return err; ++ ++ if (!en) ++ return err; ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, e0); ++ if (err) ++ return err; ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1); ++ if (err) ++ return err; ++ ++ return err; ++} ++ ++int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, u32 *val) ++{ ++ u32 en, e0, e1; ++ int err; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, &en); ++ if (err) ++ return err; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, &e0); ++ if (err) ++ return err; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, &e1); ++ if (err) ++ return err; ++ ++ *val = (en | e0 << 1 | e1 << 2) & 0x7; ++ ++ return 0; ++} +diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h +new file mode 100644 +index 000000000000..1b7da42aa1d5 +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h +@@ -0,0 +1,302 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2018 MediaTek Inc. ++ * ++ * Author: Sean Wang <sean.wang@mediatek.com> ++ * ++ */ ++ ++#ifndef __PINCTRL_MTK_COMMON_V2_H ++#define __PINCTRL_MTK_COMMON_V2_H ++ ++#include <linux/gpio/driver.h> ++ ++#define MTK_INPUT 0 ++#define MTK_OUTPUT 1 ++#define MTK_DISABLE 0 ++#define MTK_ENABLE 1 ++#define MTK_PULLDOWN 0 ++#define MTK_PULLUP 1 ++ ++#define EINT_NA U16_MAX ++#define NO_EINT_SUPPORT EINT_NA ++ ++#define PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \ ++ _s_bit, _x_bits, _sz_reg, _fixed) { \ ++ .s_pin = _s_pin, \ ++ .e_pin = _e_pin, \ ++ .i_base = _i_base, \ ++ .s_addr = _s_addr, \ ++ .x_addrs = _x_addrs, \ ++ .s_bit = _s_bit, \ ++ .x_bits = _x_bits, \ ++ .sz_reg = _sz_reg, \ ++ .fixed = _fixed, \ ++ } ++ ++#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ ++ PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \ ++ _x_bits, 32, 0) ++ ++#define PINS_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ ++ PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \ ++ _x_bits, 32, 1) ++ ++/* List these attributes which could be modified for the pin */ ++enum { ++ PINCTRL_PIN_REG_MODE, ++ PINCTRL_PIN_REG_DIR, ++ PINCTRL_PIN_REG_DI, ++ PINCTRL_PIN_REG_DO, ++ PINCTRL_PIN_REG_SR, ++ PINCTRL_PIN_REG_SMT, ++ PINCTRL_PIN_REG_PD, ++ PINCTRL_PIN_REG_PU, ++ PINCTRL_PIN_REG_E4, ++ PINCTRL_PIN_REG_E8, ++ PINCTRL_PIN_REG_TDSEL, ++ PINCTRL_PIN_REG_RDSEL, ++ PINCTRL_PIN_REG_DRV, ++ PINCTRL_PIN_REG_PUPD, ++ PINCTRL_PIN_REG_R0, ++ PINCTRL_PIN_REG_R1, ++ PINCTRL_PIN_REG_IES, ++ PINCTRL_PIN_REG_PULLEN, ++ PINCTRL_PIN_REG_PULLSEL, ++ PINCTRL_PIN_REG_DRV_EN, ++ PINCTRL_PIN_REG_DRV_E0, ++ PINCTRL_PIN_REG_DRV_E1, ++ PINCTRL_PIN_REG_MAX, ++}; ++ ++/* Group the pins by the driving current */ ++enum { ++ DRV_FIXED, ++ DRV_GRP0, ++ DRV_GRP1, ++ DRV_GRP2, ++ DRV_GRP3, ++ DRV_GRP4, ++ DRV_GRP_MAX, ++}; ++ ++static const char * const mtk_default_register_base_names[] = { ++ "base", ++}; ++ ++/* struct mtk_pin_field - the structure that holds the information of the field ++ * used to describe the attribute for the pin ++ * @base: the index pointing to the entry in base address list ++ * @offset: the register offset relative to the base address ++ * @mask: the mask used to filter out the field from the register ++ * @bitpos: the start bit relative to the register ++ * @next: the indication that the field would be extended to the ++ next register ++ */ ++struct mtk_pin_field { ++ u8 index; ++ u32 offset; ++ u32 mask; ++ u8 bitpos; ++ u8 next; ++}; ++ ++/* struct mtk_pin_field_calc - the structure that holds the range providing ++ * the guide used to look up the relevant field ++ * @s_pin: the start pin within the range ++ * @e_pin: the end pin within the range ++ * @i_base: the index pointing to the entry in base address list ++ * @s_addr: the start address for the range ++ * @x_addrs: the address distance between two consecutive registers ++ * within the range ++ * @s_bit: the start bit for the first register within the range ++ * @x_bits: the bit distance between two consecutive pins within ++ * the range ++ * @sz_reg: the size of bits in a register ++ * @fixed: the consecutive pins share the same bits with the 1st ++ * pin ++ */ ++struct mtk_pin_field_calc { ++ u16 s_pin; ++ u16 e_pin; ++ u8 i_base; ++ u32 s_addr; ++ u8 x_addrs; ++ u8 s_bit; ++ u8 x_bits; ++ u8 sz_reg; ++ u8 fixed; ++}; ++ ++/* struct mtk_pin_reg_calc - the structure that holds all ranges used to ++ * determine which register the pin would make use of ++ * for certain pin attribute. ++ * @range: the start address for the range ++ * @nranges: the number of items in the range ++ */ ++struct mtk_pin_reg_calc { ++ const struct mtk_pin_field_calc *range; ++ unsigned int nranges; ++}; ++ ++/** ++ * struct mtk_func_desc - the structure that providing information ++ * all the funcs for this pin ++ * @name: the name of function ++ * @muxval: the mux to the function ++ */ ++struct mtk_func_desc { ++ const char *name; ++ u8 muxval; ++}; ++ ++/** ++ * struct mtk_eint_desc - the structure that providing information ++ * for eint data per pin ++ * @eint_m: the eint mux for this pin ++ * @eitn_n: the eint number for this pin ++ */ ++struct mtk_eint_desc { ++ u16 eint_m; ++ u16 eint_n; ++}; ++ ++/** ++ * struct mtk_pin_desc - the structure that providing information ++ * for each pin of chips ++ * @number: unique pin number from the global pin number space ++ * @name: name for this pin ++ * @eint: the eint data for this pin ++ * @drv_n: the index with the driving group ++ * @funcs: all available functions for this pins (only used in ++ * those drivers compatible to pinctrl-mtk-common.c-like ++ * ones) ++ */ ++struct mtk_pin_desc { ++ unsigned int number; ++ const char *name; ++ struct mtk_eint_desc eint; ++ u8 drv_n; ++ struct mtk_func_desc *funcs; ++}; ++ ++struct mtk_pinctrl_group { ++ const char *name; ++ unsigned long config; ++ unsigned pin; ++}; ++ ++struct mtk_pinctrl; ++ ++/* struct mtk_pin_soc - the structure that holds SoC-specific data */ ++struct mtk_pin_soc { ++ const struct mtk_pin_reg_calc *reg_cal; ++ const struct mtk_pin_desc *pins; ++ unsigned int npins; ++ const struct group_desc *grps; ++ unsigned int ngrps; ++ const struct function_desc *funcs; ++ unsigned int nfuncs; ++ const struct mtk_eint_regs *eint_regs; ++ const struct mtk_eint_hw *eint_hw; ++ ++ /* Specific parameters per SoC */ ++ u8 gpio_m; ++ bool ies_present; ++ const char * const *base_names; ++ unsigned int nbase_names; ++ ++ /* Specific pinconfig operations */ ++ int (*bias_disable_set)(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc); ++ int (*bias_disable_get)(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, int *res); ++ int (*bias_set)(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, bool pullup); ++ int (*bias_get)(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, bool pullup, int *res); ++ ++ int (*drive_set)(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, u32 arg); ++ int (*drive_get)(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, int *val); ++ ++ int (*adv_pull_set)(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, bool pullup, ++ u32 arg); ++ int (*adv_pull_get)(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, bool pullup, ++ u32 *val); ++ int (*adv_drive_set)(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, u32 arg); ++ int (*adv_drive_get)(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, u32 *val); ++ ++ /* Specific driver data */ ++ void *driver_data; ++}; ++ ++struct mtk_pinctrl { ++ struct pinctrl_dev *pctrl; ++ void __iomem **base; ++ u8 nbase; ++ struct device *dev; ++ struct gpio_chip chip; ++ const struct mtk_pin_soc *soc; ++ struct mtk_eint *eint; ++ struct mtk_pinctrl_group *groups; ++ const char **grp_names; ++}; ++ ++void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set); ++ ++int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, ++ int field, int value); ++int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, ++ int field, int *value); ++ ++int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev); ++ ++int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc); ++int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, int *res); ++int mtk_pinconf_bias_set(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, bool pullup); ++int mtk_pinconf_bias_get(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, bool pullup, ++ int *res); ++ ++int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc); ++int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, ++ int *res); ++int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, bool pullup); ++int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, bool pullup, ++ int *res); ++ ++int mtk_pinconf_drive_set(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, u32 arg); ++int mtk_pinconf_drive_get(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, int *val); ++ ++int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, u32 arg); ++int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, int *val); ++ ++int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, bool pullup, ++ u32 arg); ++int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, bool pullup, ++ u32 *val); ++int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, u32 arg); ++int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, u32 *val); ++ ++#endif /* __PINCTRL_MTK_COMMON_V2_H */ +diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +index 16ff56f93501..071623873ca5 100644 +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +@@ -514,8 +514,8 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, + + pins = of_find_property(node, "pinmux", NULL); + if (!pins) { +- dev_err(pctl->dev, "missing pins property in node %s .\n", +- node->name); ++ dev_err(pctl->dev, "missing pins property in node %pOFn .\n", ++ node); + return -EINVAL; + } + +diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6765.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6765.h +new file mode 100644 +index 000000000000..772563720461 +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6765.h +@@ -0,0 +1,1754 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2018 MediaTek Inc. ++ * ++ * Author: ZH Chen <zh.chen@mediatek.com> ++ * ++ */ ++ ++#ifndef __PINCTRL_MTK_MT6765_H ++#define __PINCTRL_MTK_MT6765_H ++ ++#include "pinctrl-paris.h" ++ ++static struct mtk_pin_desc mtk_pins_mt6765[] = { ++ MTK_PIN( ++ 0, "GPIO0", ++ MTK_EINT_FUNCTION(0, 0), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO0"), ++ MTK_FUNCTION(1, "UTXD1"), ++ MTK_FUNCTION(2, "CLKM0"), ++ MTK_FUNCTION(3, "MD_INT0"), ++ MTK_FUNCTION(4, "I2S0_MCK"), ++ MTK_FUNCTION(5, "MD_UTXD1"), ++ MTK_FUNCTION(6, "TP_GPIO0_AO"), ++ MTK_FUNCTION(7, "DBG_MON_B9") ++ ), ++ MTK_PIN( ++ 1, "GPIO1", ++ MTK_EINT_FUNCTION(0, 1), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO1"), ++ MTK_FUNCTION(1, "URXD1"), ++ MTK_FUNCTION(2, "CLKM1"), ++ MTK_FUNCTION(4, "I2S0_BCK"), ++ MTK_FUNCTION(5, "MD_URXD1"), ++ MTK_FUNCTION(6, "TP_GPIO1_AO"), ++ MTK_FUNCTION(7, "DBG_MON_B10") ++ ), ++ MTK_PIN( ++ 2, "GPIO2", ++ MTK_EINT_FUNCTION(0, 2), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO2"), ++ MTK_FUNCTION(1, "UCTS0"), ++ MTK_FUNCTION(2, "CLKM2"), ++ MTK_FUNCTION(3, "UTXD1"), ++ MTK_FUNCTION(4, "I2S0_LRCK"), ++ MTK_FUNCTION(5, "ANT_SEL6"), ++ MTK_FUNCTION(6, "TP_GPIO2_AO"), ++ MTK_FUNCTION(7, "DBG_MON_B11") ++ ), ++ MTK_PIN( ++ 3, "GPIO3", ++ MTK_EINT_FUNCTION(0, 3), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO3"), ++ MTK_FUNCTION(1, "URTS0"), ++ MTK_FUNCTION(2, "CLKM3"), ++ MTK_FUNCTION(3, "URXD1"), ++ MTK_FUNCTION(4, "I2S0_DI"), ++ MTK_FUNCTION(5, "ANT_SEL7"), ++ MTK_FUNCTION(6, "TP_GPIO3_AO"), ++ MTK_FUNCTION(7, "DBG_MON_B12") ++ ), ++ MTK_PIN( ++ 4, "GPIO4", ++ MTK_EINT_FUNCTION(0, 4), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO4"), ++ MTK_FUNCTION(1, "SPI1_B_MI"), ++ MTK_FUNCTION(2, "SCP_SPI1_MI"), ++ MTK_FUNCTION(3, "UCTS0"), ++ MTK_FUNCTION(4, "I2S3_MCK"), ++ MTK_FUNCTION(5, "SSPM_URXD_AO"), ++ MTK_FUNCTION(6, "TP_GPIO4_AO") ++ ), ++ MTK_PIN( ++ 5, "GPIO5", ++ MTK_EINT_FUNCTION(0, 5), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO5"), ++ MTK_FUNCTION(1, "SPI1_B_CSB"), ++ MTK_FUNCTION(2, "SCP_SPI1_CS"), ++ MTK_FUNCTION(3, "URTS0"), ++ MTK_FUNCTION(4, "I2S3_BCK"), ++ MTK_FUNCTION(5, "SSPM_UTXD_AO"), ++ MTK_FUNCTION(6, "TP_GPIO5_AO") ++ ), ++ MTK_PIN( ++ 6, "GPIO6", ++ MTK_EINT_FUNCTION(0, 6), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO6"), ++ MTK_FUNCTION(1, "SPI1_B_MO"), ++ MTK_FUNCTION(2, "SCP_SPI1_MO"), ++ MTK_FUNCTION(3, "PWM0"), ++ MTK_FUNCTION(4, "I2S3_LRCK"), ++ MTK_FUNCTION(5, "MD_UTXD0"), ++ MTK_FUNCTION(6, "TP_GPIO6_AO") ++ ), ++ MTK_PIN( ++ 7, "GPIO7", ++ MTK_EINT_FUNCTION(0, 7), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO7"), ++ MTK_FUNCTION(1, "SPI1_B_CLK"), ++ MTK_FUNCTION(2, "SCP_SPI1_CK"), ++ MTK_FUNCTION(3, "PWM1"), ++ MTK_FUNCTION(4, "I2S3_DO"), ++ MTK_FUNCTION(5, "MD_URXD0"), ++ MTK_FUNCTION(6, "TP_GPIO7_AO") ++ ), ++ MTK_PIN( ++ 8, "GPIO8", ++ MTK_EINT_FUNCTION(0, 8), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO8"), ++ MTK_FUNCTION(1, "UTXD1"), ++ MTK_FUNCTION(2, "SRCLKENAI0"), ++ MTK_FUNCTION(3, "MD_INT1_C2K_UIM0_HOT_PLUG"), ++ MTK_FUNCTION(4, "ANT_SEL3"), ++ MTK_FUNCTION(5, "MFG_JTAG_TRSTN"), ++ MTK_FUNCTION(6, "I2S2_MCK"), ++ MTK_FUNCTION(7, "JTRSTN_SEL1") ++ ), ++ MTK_PIN( ++ 9, "GPIO9", ++ MTK_EINT_FUNCTION(0, 9), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO9"), ++ MTK_FUNCTION(1, "MD_INT0"), ++ MTK_FUNCTION(2, "CMMCLK2"), ++ MTK_FUNCTION(3, "CONN_MCU_TRST_B"), ++ MTK_FUNCTION(4, "IDDIG"), ++ MTK_FUNCTION(5, "SDA_6306"), ++ MTK_FUNCTION(6, "MCUPM_JTAG_TRSTN"), ++ MTK_FUNCTION(7, "DBG_MON_B22") ++ ), ++ MTK_PIN( ++ 10, "GPIO10", ++ MTK_EINT_FUNCTION(0, 10), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO10"), ++ MTK_FUNCTION(1, "MD_INT1_C2K_UIM0_HOT_PLUG"), ++ MTK_FUNCTION(3, "CONN_MCU_DBGI_N"), ++ MTK_FUNCTION(4, "SRCLKENAI1"), ++ MTK_FUNCTION(5, "EXT_FRAME_SYNC"), ++ MTK_FUNCTION(6, "CMVREF1"), ++ MTK_FUNCTION(7, "DBG_MON_B23") ++ ), ++ MTK_PIN( ++ 11, "GPIO11", ++ MTK_EINT_FUNCTION(0, 11), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO11"), ++ MTK_FUNCTION(1, "MD_INT2_C2K_UIM1_HOT_PLUG"), ++ MTK_FUNCTION(2, "CLKM3"), ++ MTK_FUNCTION(3, "ANT_SEL6"), ++ MTK_FUNCTION(4, "SRCLKENAI0"), ++ MTK_FUNCTION(5, "EXT_FRAME_SYNC"), ++ MTK_FUNCTION(6, "UCTS1"), ++ MTK_FUNCTION(7, "DBG_MON_B24") ++ ), ++ MTK_PIN( ++ 12, "GPIO12", ++ MTK_EINT_FUNCTION(0, 12), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO12"), ++ MTK_FUNCTION(1, "PWM0"), ++ MTK_FUNCTION(2, "SRCLKENAI1"), ++ MTK_FUNCTION(3, "EXT_FRAME_SYNC"), ++ MTK_FUNCTION(4, "MD_INT0"), ++ MTK_FUNCTION(5, "DVFSRC_EXT_REQ"), ++ MTK_FUNCTION(6, "URTS1") ++ ), ++ MTK_PIN( ++ 13, "GPIO13", ++ MTK_EINT_FUNCTION(0, 13), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO13"), ++ MTK_FUNCTION(1, "ANT_SEL0"), ++ MTK_FUNCTION(2, "SPI4_MI"), ++ MTK_FUNCTION(3, "SCP_SPI0_MI"), ++ MTK_FUNCTION(4, "MD_URXD0"), ++ MTK_FUNCTION(5, "CLKM0"), ++ MTK_FUNCTION(6, "I2S0_MCK"), ++ MTK_FUNCTION(7, "DBG_MON_A0") ++ ), ++ MTK_PIN( ++ 14, "GPIO14", ++ MTK_EINT_FUNCTION(0, 14), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO14"), ++ MTK_FUNCTION(1, "ANT_SEL1"), ++ MTK_FUNCTION(2, "SPI4_CSB"), ++ MTK_FUNCTION(3, "SCP_SPI0_CS"), ++ MTK_FUNCTION(4, "MD_UTXD0"), ++ MTK_FUNCTION(5, "CLKM1"), ++ MTK_FUNCTION(6, "I2S0_BCK"), ++ MTK_FUNCTION(7, "DBG_MON_A1") ++ ), ++ MTK_PIN( ++ 15, "GPIO15", ++ MTK_EINT_FUNCTION(0, 15), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO15"), ++ MTK_FUNCTION(1, "ANT_SEL2"), ++ MTK_FUNCTION(2, "SPI4_MO"), ++ MTK_FUNCTION(3, "SCP_SPI0_MO"), ++ MTK_FUNCTION(4, "MD_URXD1"), ++ MTK_FUNCTION(5, "CLKM2"), ++ MTK_FUNCTION(6, "I2S0_LRCK"), ++ MTK_FUNCTION(7, "DBG_MON_A2") ++ ), ++ MTK_PIN( ++ 16, "GPIO16", ++ MTK_EINT_FUNCTION(0, 16), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO16"), ++ MTK_FUNCTION(1, "ANT_SEL3"), ++ MTK_FUNCTION(2, "SPI4_CLK"), ++ MTK_FUNCTION(3, "SCP_SPI0_CK"), ++ MTK_FUNCTION(4, "MD_UTXD1"), ++ MTK_FUNCTION(5, "CLKM3"), ++ MTK_FUNCTION(6, "I2S3_MCK"), ++ MTK_FUNCTION(7, "DBG_MON_A3") ++ ), ++ MTK_PIN( ++ 17, "GPIO17", ++ MTK_EINT_FUNCTION(0, 17), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO17"), ++ MTK_FUNCTION(1, "ANT_SEL4"), ++ MTK_FUNCTION(2, "SPI2_MO"), ++ MTK_FUNCTION(3, "SCP_SPI0_MO"), ++ MTK_FUNCTION(4, "PWM1"), ++ MTK_FUNCTION(5, "IDDIG"), ++ MTK_FUNCTION(6, "I2S0_DI"), ++ MTK_FUNCTION(7, "DBG_MON_A4") ++ ), ++ MTK_PIN( ++ 18, "GPIO18", ++ MTK_EINT_FUNCTION(0, 18), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO18"), ++ MTK_FUNCTION(1, "ANT_SEL5"), ++ MTK_FUNCTION(2, "SPI2_CLK"), ++ MTK_FUNCTION(3, "SCP_SPI0_CK"), ++ MTK_FUNCTION(4, "MD_INT0"), ++ MTK_FUNCTION(5, "USB_DRVVBUS"), ++ MTK_FUNCTION(6, "I2S3_BCK"), ++ MTK_FUNCTION(7, "DBG_MON_A5") ++ ), ++ MTK_PIN( ++ 19, "GPIO19", ++ MTK_EINT_FUNCTION(0, 19), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO19"), ++ MTK_FUNCTION(1, "ANT_SEL6"), ++ MTK_FUNCTION(2, "SPI2_MI"), ++ MTK_FUNCTION(3, "SCP_SPI0_MI"), ++ MTK_FUNCTION(4, "MD_INT2_C2K_UIM1_HOT_PLUG"), ++ MTK_FUNCTION(6, "I2S3_LRCK"), ++ MTK_FUNCTION(7, "DBG_MON_A6") ++ ), ++ MTK_PIN( ++ 20, "GPIO20", ++ MTK_EINT_FUNCTION(0, 20), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO20"), ++ MTK_FUNCTION(1, "ANT_SEL7"), ++ MTK_FUNCTION(2, "SPI2_CSB"), ++ MTK_FUNCTION(3, "SCP_SPI0_CS"), ++ MTK_FUNCTION(4, "MD_INT1_C2K_UIM0_HOT_PLUG"), ++ MTK_FUNCTION(5, "CMMCLK3"), ++ MTK_FUNCTION(6, "I2S3_DO"), ++ MTK_FUNCTION(7, "DBG_MON_A7") ++ ), ++ MTK_PIN( ++ 21, "GPIO21", ++ MTK_EINT_FUNCTION(0, 21), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO21"), ++ MTK_FUNCTION(1, "SPI3_MI"), ++ MTK_FUNCTION(2, "SRCLKENAI1"), ++ MTK_FUNCTION(3, "DAP_MD32_SWD"), ++ MTK_FUNCTION(4, "CMVREF0"), ++ MTK_FUNCTION(5, "SCP_SPI0_MI"), ++ MTK_FUNCTION(6, "I2S2_MCK"), ++ MTK_FUNCTION(7, "DBG_MON_A8") ++ ), ++ MTK_PIN( ++ 22, "GPIO22", ++ MTK_EINT_FUNCTION(0, 22), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO22"), ++ MTK_FUNCTION(1, "SPI3_CSB"), ++ MTK_FUNCTION(2, "SRCLKENAI0"), ++ MTK_FUNCTION(3, "DAP_MD32_SWCK"), ++ MTK_FUNCTION(4, "CMVREF1"), ++ MTK_FUNCTION(5, "SCP_SPI0_CS"), ++ MTK_FUNCTION(6, "I2S2_BCK"), ++ MTK_FUNCTION(7, "DBG_MON_A9") ++ ), ++ MTK_PIN( ++ 23, "GPIO23", ++ MTK_EINT_FUNCTION(0, 23), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO23"), ++ MTK_FUNCTION(1, "SPI3_MO"), ++ MTK_FUNCTION(2, "PWM0"), ++ MTK_FUNCTION(3, "KPROW7"), ++ MTK_FUNCTION(4, "ANT_SEL3"), ++ MTK_FUNCTION(5, "SCP_SPI0_MO"), ++ MTK_FUNCTION(6, "I2S2_LRCK"), ++ MTK_FUNCTION(7, "DBG_MON_A10") ++ ), ++ MTK_PIN( ++ 24, "GPIO24", ++ MTK_EINT_FUNCTION(0, 24), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO24"), ++ MTK_FUNCTION(1, "SPI3_CLK"), ++ MTK_FUNCTION(2, "UDI_TCK"), ++ MTK_FUNCTION(3, "IO_JTAG_TCK"), ++ MTK_FUNCTION(4, "SSPM_JTAG_TCK"), ++ MTK_FUNCTION(5, "SCP_SPI0_CK"), ++ MTK_FUNCTION(6, "I2S2_DI"), ++ MTK_FUNCTION(7, "DBG_MON_A11") ++ ), ++ MTK_PIN( ++ 25, "GPIO25", ++ MTK_EINT_FUNCTION(0, 25), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO25"), ++ MTK_FUNCTION(1, "SPI1_A_MI"), ++ MTK_FUNCTION(2, "UDI_TMS"), ++ MTK_FUNCTION(3, "IO_JTAG_TMS"), ++ MTK_FUNCTION(4, "SSPM_JTAG_TMS"), ++ MTK_FUNCTION(5, "KPROW3"), ++ MTK_FUNCTION(6, "I2S1_MCK"), ++ MTK_FUNCTION(7, "DBG_MON_A12") ++ ), ++ MTK_PIN( ++ 26, "GPIO26", ++ MTK_EINT_FUNCTION(0, 26), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO26"), ++ MTK_FUNCTION(1, "SPI1_A_CSB"), ++ MTK_FUNCTION(2, "UDI_TDI"), ++ MTK_FUNCTION(3, "IO_JTAG_TDI"), ++ MTK_FUNCTION(4, "SSPM_JTAG_TDI"), ++ MTK_FUNCTION(5, "KPROW4"), ++ MTK_FUNCTION(6, "I2S1_BCK"), ++ MTK_FUNCTION(7, "DBG_MON_A13") ++ ), ++ MTK_PIN( ++ 27, "GPIO27", ++ MTK_EINT_FUNCTION(0, 27), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO27"), ++ MTK_FUNCTION(1, "SPI1_A_MO"), ++ MTK_FUNCTION(2, "UDI_TDO"), ++ MTK_FUNCTION(3, "IO_JTAG_TDO"), ++ MTK_FUNCTION(4, "SSPM_JTAG_TDO"), ++ MTK_FUNCTION(5, "KPROW5"), ++ MTK_FUNCTION(6, "I2S1_LRCK"), ++ MTK_FUNCTION(7, "DBG_MON_A14") ++ ), ++ MTK_PIN( ++ 28, "GPIO28", ++ MTK_EINT_FUNCTION(0, 28), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO28"), ++ MTK_FUNCTION(1, "SPI1_A_CLK"), ++ MTK_FUNCTION(2, "UDI_NTRST"), ++ MTK_FUNCTION(3, "IO_JTAG_TRSTN"), ++ MTK_FUNCTION(4, "SSPM_JTAG_TRSTN"), ++ MTK_FUNCTION(5, "KPROW6"), ++ MTK_FUNCTION(6, "I2S1_DO"), ++ MTK_FUNCTION(7, "DBG_MON_A15") ++ ), ++ MTK_PIN( ++ 29, "GPIO29", ++ MTK_EINT_FUNCTION(0, 29), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO29"), ++ MTK_FUNCTION(1, "MSDC1_CLK"), ++ MTK_FUNCTION(2, "IO_JTAG_TCK"), ++ MTK_FUNCTION(3, "UDI_TCK"), ++ MTK_FUNCTION(4, "CONN_DSP_JCK"), ++ MTK_FUNCTION(5, "SSPM_JTAG_TCK"), ++ MTK_FUNCTION(6, "CONN_MCU_AICE_TCKC"), ++ MTK_FUNCTION(7, "DAP_MD32_SWCK") ++ ), ++ MTK_PIN( ++ 30, "GPIO30", ++ MTK_EINT_FUNCTION(0, 30), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO30"), ++ MTK_FUNCTION(1, "MSDC1_CMD"), ++ MTK_FUNCTION(2, "IO_JTAG_TMS"), ++ MTK_FUNCTION(3, "UDI_TMS"), ++ MTK_FUNCTION(4, "CONN_DSP_JMS"), ++ MTK_FUNCTION(5, "SSPM_JTAG_TMS"), ++ MTK_FUNCTION(6, "CONN_MCU_AICE_TMSC"), ++ MTK_FUNCTION(7, "DAP_MD32_SWD") ++ ), ++ MTK_PIN( ++ 31, "GPIO31", ++ MTK_EINT_FUNCTION(0, 31), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO31"), ++ MTK_FUNCTION(1, "MSDC1_DAT3") ++ ), ++ MTK_PIN( ++ 32, "GPIO32", ++ MTK_EINT_FUNCTION(0, 32), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO32"), ++ MTK_FUNCTION(1, "MSDC1_DAT0"), ++ MTK_FUNCTION(2, "IO_JTAG_TDI"), ++ MTK_FUNCTION(3, "UDI_TDI"), ++ MTK_FUNCTION(4, "CONN_DSP_JDI"), ++ MTK_FUNCTION(5, "SSPM_JTAG_TDI") ++ ), ++ MTK_PIN( ++ 33, "GPIO33", ++ MTK_EINT_FUNCTION(0, 33), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO33"), ++ MTK_FUNCTION(1, "MSDC1_DAT2"), ++ MTK_FUNCTION(2, "IO_JTAG_TRSTN"), ++ MTK_FUNCTION(3, "UDI_NTRST"), ++ MTK_FUNCTION(4, "CONN_DSP_JINTP"), ++ MTK_FUNCTION(5, "SSPM_JTAG_TRSTN") ++ ), ++ MTK_PIN( ++ 34, "GPIO34", ++ MTK_EINT_FUNCTION(0, 34), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO34"), ++ MTK_FUNCTION(1, "MSDC1_DAT1"), ++ MTK_FUNCTION(2, "IO_JTAG_TDO"), ++ MTK_FUNCTION(3, "UDI_TDO"), ++ MTK_FUNCTION(4, "CONN_DSP_JDO"), ++ MTK_FUNCTION(5, "SSPM_JTAG_TDO") ++ ), ++ MTK_PIN( ++ 35, "GPIO35", ++ MTK_EINT_FUNCTION(0, 35), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO35"), ++ MTK_FUNCTION(1, "MD1_SIM2_SIO"), ++ MTK_FUNCTION(2, "CCU_JTAG_TDO"), ++ MTK_FUNCTION(3, "MD1_SIM1_SIO"), ++ MTK_FUNCTION(5, "SCP_JTAG_TDO"), ++ MTK_FUNCTION(6, "CONN_DSP_JDO"), ++ MTK_FUNCTION(7, "DBG_MON_A16") ++ ), ++ MTK_PIN( ++ 36, "GPIO36", ++ MTK_EINT_FUNCTION(0, 36), ++ DRV_GRP0, ++ MTK_FUNCTION(0, "GPIO36"), ++ MTK_FUNCTION(1, "MD1_SIM2_SRST"), ++ MTK_FUNCTION(2, "CCU_JTAG_TMS"), ++ MTK_FUNCTION(3, "MD1_SIM1_SRST"), ++ MTK_FUNCTION(4, "CONN_MCU_AICE_TMSC"), ++ MTK_FUNCTION(5, "SCP_JTAG_TMS"), ++ MTK_FUNCTION(6, "CONN_DSP_JMS"), ++ MTK_FUNCTION(7, "DBG_MON_A17") ++ ), ++ MTK_PIN( ++ 37, "GPIO37", ++ MTK_EINT_FUNCTION(0, 37), ++ DRV_GRP0, ++ MTK_FUNCTION(0, "GPIO37"), ++ MTK_FUNCTION(1, "MD1_SIM2_SCLK"), ++ MTK_FUNCTION(2, "CCU_JTAG_TDI"), ++ MTK_FUNCTION(3, "MD1_SIM1_SCLK"), ++ MTK_FUNCTION(5, "SCP_JTAG_TDI"), ++ MTK_FUNCTION(6, "CONN_DSP_JDI"), ++ MTK_FUNCTION(7, "DBG_MON_A18") ++ ), ++ MTK_PIN( ++ 38, "GPIO38", ++ MTK_EINT_FUNCTION(0, 38), ++ DRV_GRP0, ++ MTK_FUNCTION(0, "GPIO38"), ++ MTK_FUNCTION(1, "MD1_SIM1_SCLK"), ++ MTK_FUNCTION(3, "MD1_SIM2_SCLK"), ++ MTK_FUNCTION(7, "DBG_MON_A19") ++ ), ++ MTK_PIN( ++ 39, "GPIO39", ++ MTK_EINT_FUNCTION(0, 39), ++ DRV_GRP0, ++ MTK_FUNCTION(0, "GPIO39"), ++ MTK_FUNCTION(1, "MD1_SIM1_SRST"), ++ MTK_FUNCTION(2, "CCU_JTAG_TCK"), ++ MTK_FUNCTION(3, "MD1_SIM2_SRST"), ++ MTK_FUNCTION(4, "CONN_MCU_AICE_TCKC"), ++ MTK_FUNCTION(5, "SCP_JTAG_TCK"), ++ MTK_FUNCTION(6, "CONN_DSP_JCK"), ++ MTK_FUNCTION(7, "DBG_MON_A20") ++ ), ++ MTK_PIN( ++ 40, "GPIO40", ++ MTK_EINT_FUNCTION(0, 40), ++ DRV_GRP0, ++ MTK_FUNCTION(0, "GPIO40"), ++ MTK_FUNCTION(1, "MD1_SIM1_SIO"), ++ MTK_FUNCTION(2, "CCU_JTAG_TRST"), ++ MTK_FUNCTION(3, "MD1_SIM2_SIO"), ++ MTK_FUNCTION(5, "SCP_JTAG_TRSTN"), ++ MTK_FUNCTION(6, "CONN_DSP_JINTP"), ++ MTK_FUNCTION(7, "DBG_MON_A21") ++ ), ++ MTK_PIN( ++ 41, "GPIO41", ++ MTK_EINT_FUNCTION(0, 41), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO41"), ++ MTK_FUNCTION(1, "IDDIG"), ++ MTK_FUNCTION(2, "URXD1"), ++ MTK_FUNCTION(3, "UCTS0"), ++ MTK_FUNCTION(4, "KPCOL2"), ++ MTK_FUNCTION(5, "SSPM_UTXD_AO"), ++ MTK_FUNCTION(6, "MD_INT0"), ++ MTK_FUNCTION(7, "DBG_MON_A22") ++ ), ++ MTK_PIN( ++ 42, "GPIO42", ++ MTK_EINT_FUNCTION(0, 42), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO42"), ++ MTK_FUNCTION(1, "USB_DRVVBUS"), ++ MTK_FUNCTION(2, "UTXD1"), ++ MTK_FUNCTION(3, "URTS0"), ++ MTK_FUNCTION(4, "KPROW2"), ++ MTK_FUNCTION(5, "SSPM_URXD_AO"), ++ MTK_FUNCTION(6, "MD_INT1_C2K_UIM0_HOT_PLUG"), ++ MTK_FUNCTION(7, "DBG_MON_A23") ++ ), ++ MTK_PIN( ++ 43, "GPIO43", ++ MTK_EINT_FUNCTION(0, 43), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO43"), ++ MTK_FUNCTION(1, "DISP_PWM"), ++ MTK_FUNCTION(7, "DBG_MON_A24") ++ ), ++ MTK_PIN( ++ 44, "GPIO44", ++ MTK_EINT_FUNCTION(0, 44), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO44"), ++ MTK_FUNCTION(1, "DSI_TE"), ++ MTK_FUNCTION(7, "DBG_MON_A25") ++ ), ++ MTK_PIN( ++ 45, "GPIO45", ++ MTK_EINT_FUNCTION(0, 45), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO45"), ++ MTK_FUNCTION(1, "LCM_RST"), ++ MTK_FUNCTION(7, "DBG_MON_A26") ++ ), ++ MTK_PIN( ++ 46, "GPIO46", ++ MTK_EINT_FUNCTION(0, 46), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO46"), ++ MTK_FUNCTION(1, "MD_INT2_C2K_UIM1_HOT_PLUG"), ++ MTK_FUNCTION(2, "UCTS0"), ++ MTK_FUNCTION(3, "UCTS1"), ++ MTK_FUNCTION(4, "IDDIG"), ++ MTK_FUNCTION(5, "SCL_6306"), ++ MTK_FUNCTION(6, "TP_UCTS1_AO"), ++ MTK_FUNCTION(7, "DBG_MON_A27") ++ ), ++ MTK_PIN( ++ 47, "GPIO47", ++ MTK_EINT_FUNCTION(0, 47), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO47"), ++ MTK_FUNCTION(1, "MD_INT1_C2K_UIM0_HOT_PLUG"), ++ MTK_FUNCTION(2, "URTS0"), ++ MTK_FUNCTION(3, "URTS1"), ++ MTK_FUNCTION(4, "USB_DRVVBUS"), ++ MTK_FUNCTION(5, "SDA_6306"), ++ MTK_FUNCTION(6, "TP_URTS1_AO"), ++ MTK_FUNCTION(7, "DBG_MON_A28") ++ ), ++ MTK_PIN( ++ 48, "GPIO48", ++ MTK_EINT_FUNCTION(0, 48), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO48"), ++ MTK_FUNCTION(1, "SCL5"), ++ MTK_FUNCTION(7, "DBG_MON_A29") ++ ), ++ MTK_PIN( ++ 49, "GPIO49", ++ MTK_EINT_FUNCTION(0, 49), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO49"), ++ MTK_FUNCTION(1, "SDA5"), ++ MTK_FUNCTION(7, "DBG_MON_A30") ++ ), ++ MTK_PIN( ++ 50, "GPIO50", ++ MTK_EINT_FUNCTION(0, 50), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO50"), ++ MTK_FUNCTION(1, "SCL3"), ++ MTK_FUNCTION(2, "URXD1"), ++ MTK_FUNCTION(3, "MD_URXD1"), ++ MTK_FUNCTION(4, "SSPM_URXD_AO"), ++ MTK_FUNCTION(5, "IDDIG"), ++ MTK_FUNCTION(6, "TP_URXD1_AO"), ++ MTK_FUNCTION(7, "DBG_MON_A31") ++ ), ++ MTK_PIN( ++ 51, "GPIO51", ++ MTK_EINT_FUNCTION(0, 51), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO51"), ++ MTK_FUNCTION(1, "SDA3"), ++ MTK_FUNCTION(2, "UTXD1"), ++ MTK_FUNCTION(3, "MD_UTXD1"), ++ MTK_FUNCTION(4, "SSPM_UTXD_AO"), ++ MTK_FUNCTION(5, "USB_DRVVBUS"), ++ MTK_FUNCTION(6, "TP_UTXD1_AO"), ++ MTK_FUNCTION(7, "DBG_MON_A32") ++ ), ++ MTK_PIN( ++ 52, "GPIO52", ++ MTK_EINT_FUNCTION(0, 52), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO52"), ++ MTK_FUNCTION(1, "BPI_BUS15") ++ ), ++ MTK_PIN( ++ 53, "GPIO53", ++ MTK_EINT_FUNCTION(0, 53), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO53"), ++ MTK_FUNCTION(1, "BPI_BUS13") ++ ), ++ MTK_PIN( ++ 54, "GPIO54", ++ MTK_EINT_FUNCTION(0, 54), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO54"), ++ MTK_FUNCTION(1, "BPI_BUS12") ++ ), ++ MTK_PIN( ++ 55, "GPIO55", ++ MTK_EINT_FUNCTION(0, 55), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO55"), ++ MTK_FUNCTION(1, "BPI_BUS8") ++ ), ++ MTK_PIN( ++ 56, "GPIO56", ++ MTK_EINT_FUNCTION(0, 56), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO56"), ++ MTK_FUNCTION(1, "BPI_BUS9"), ++ MTK_FUNCTION(2, "SCL_6306") ++ ), ++ MTK_PIN( ++ 57, "GPIO57", ++ MTK_EINT_FUNCTION(0, 57), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO57"), ++ MTK_FUNCTION(1, "BPI_BUS10"), ++ MTK_FUNCTION(2, "SDA_6306") ++ ), ++ MTK_PIN( ++ 58, "GPIO58", ++ MTK_EINT_FUNCTION(0, 58), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO58"), ++ MTK_FUNCTION(1, "RFIC0_BSI_D2") ++ ), ++ MTK_PIN( ++ 59, "GPIO59", ++ MTK_EINT_FUNCTION(0, 59), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO59"), ++ MTK_FUNCTION(1, "RFIC0_BSI_D1") ++ ), ++ MTK_PIN( ++ 60, "GPIO60", ++ MTK_EINT_FUNCTION(0, 60), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO60"), ++ MTK_FUNCTION(1, "RFIC0_BSI_D0") ++ ), ++ MTK_PIN( ++ 61, "GPIO61", ++ MTK_EINT_FUNCTION(0, 61), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO61"), ++ MTK_FUNCTION(1, "MIPI1_SDATA") ++ ), ++ MTK_PIN( ++ 62, "GPIO62", ++ MTK_EINT_FUNCTION(0, 62), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO62"), ++ MTK_FUNCTION(1, "MIPI1_SCLK") ++ ), ++ MTK_PIN( ++ 63, "GPIO63", ++ MTK_EINT_FUNCTION(0, 63), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO63"), ++ MTK_FUNCTION(1, "MIPI0_SDATA") ++ ), ++ MTK_PIN( ++ 64, "GPIO64", ++ MTK_EINT_FUNCTION(0, 64), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO64"), ++ MTK_FUNCTION(1, "MIPI0_SCLK") ++ ), ++ MTK_PIN( ++ 65, "GPIO65", ++ MTK_EINT_FUNCTION(0, 65), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO65"), ++ MTK_FUNCTION(1, "MIPI3_SDATA"), ++ MTK_FUNCTION(2, "BPI_BUS16") ++ ), ++ MTK_PIN( ++ 66, "GPIO66", ++ MTK_EINT_FUNCTION(0, 66), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO66"), ++ MTK_FUNCTION(1, "MIPI3_SCLK"), ++ MTK_FUNCTION(2, "BPI_BUS17") ++ ), ++ MTK_PIN( ++ 67, "GPIO67", ++ MTK_EINT_FUNCTION(0, 67), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO67"), ++ MTK_FUNCTION(1, "MIPI2_SDATA") ++ ), ++ MTK_PIN( ++ 68, "GPIO68", ++ MTK_EINT_FUNCTION(0, 68), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO68"), ++ MTK_FUNCTION(1, "MIPI2_SCLK") ++ ), ++ MTK_PIN( ++ 69, "GPIO69", ++ MTK_EINT_FUNCTION(0, 69), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO69"), ++ MTK_FUNCTION(1, "BPI_BUS7") ++ ), ++ MTK_PIN( ++ 70, "GPIO70", ++ MTK_EINT_FUNCTION(0, 70), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO70"), ++ MTK_FUNCTION(1, "BPI_BUS6") ++ ), ++ MTK_PIN( ++ 71, "GPIO71", ++ MTK_EINT_FUNCTION(0, 71), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO71"), ++ MTK_FUNCTION(1, "BPI_BUS5") ++ ), ++ MTK_PIN( ++ 72, "GPIO72", ++ MTK_EINT_FUNCTION(0, 72), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO72"), ++ MTK_FUNCTION(1, "BPI_BUS4") ++ ), ++ MTK_PIN( ++ 73, "GPIO73", ++ MTK_EINT_FUNCTION(0, 73), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO73"), ++ MTK_FUNCTION(1, "BPI_BUS3") ++ ), ++ MTK_PIN( ++ 74, "GPIO74", ++ MTK_EINT_FUNCTION(0, 74), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO74"), ++ MTK_FUNCTION(1, "BPI_BUS2") ++ ), ++ MTK_PIN( ++ 75, "GPIO75", ++ MTK_EINT_FUNCTION(0, 75), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO75"), ++ MTK_FUNCTION(1, "BPI_BUS1") ++ ), ++ MTK_PIN( ++ 76, "GPIO76", ++ MTK_EINT_FUNCTION(0, 76), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO76"), ++ MTK_FUNCTION(1, "BPI_BUS0") ++ ), ++ MTK_PIN( ++ 77, "GPIO77", ++ MTK_EINT_FUNCTION(0, 77), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO77"), ++ MTK_FUNCTION(1, "BPI_BUS14") ++ ), ++ MTK_PIN( ++ 78, "GPIO78", ++ MTK_EINT_FUNCTION(0, 78), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO78"), ++ MTK_FUNCTION(1, "BPI_BUS11") ++ ), ++ MTK_PIN( ++ 79, "GPIO79", ++ MTK_EINT_FUNCTION(0, 79), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO79"), ++ MTK_FUNCTION(1, "BPI_PA_VM1"), ++ MTK_FUNCTION(2, "MIPI4_SDATA") ++ ), ++ MTK_PIN( ++ 80, "GPIO80", ++ MTK_EINT_FUNCTION(0, 80), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO80"), ++ MTK_FUNCTION(1, "BPI_PA_VM0"), ++ MTK_FUNCTION(2, "MIPI4_SCLK") ++ ), ++ MTK_PIN( ++ 81, "GPIO81", ++ MTK_EINT_FUNCTION(0, 81), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO81"), ++ MTK_FUNCTION(1, "SDA1"), ++ MTK_FUNCTION(7, "DBG_MON_B0") ++ ), ++ MTK_PIN( ++ 82, "GPIO82", ++ MTK_EINT_FUNCTION(0, 82), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO82"), ++ MTK_FUNCTION(1, "SDA0"), ++ MTK_FUNCTION(7, "DBG_MON_B1") ++ ), ++ MTK_PIN( ++ 83, "GPIO83", ++ MTK_EINT_FUNCTION(0, 83), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO83"), ++ MTK_FUNCTION(1, "SCL0"), ++ MTK_FUNCTION(7, "DBG_MON_B2") ++ ), ++ MTK_PIN( ++ 84, "GPIO84", ++ MTK_EINT_FUNCTION(0, 84), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO84"), ++ MTK_FUNCTION(1, "SCL1"), ++ MTK_FUNCTION(7, "DBG_MON_B3") ++ ), ++ MTK_PIN( ++ 85, "GPIO85", ++ MTK_EINT_FUNCTION(0, 85), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO85"), ++ MTK_FUNCTION(1, "RFIC0_BSI_EN") ++ ), ++ MTK_PIN( ++ 86, "GPIO86", ++ MTK_EINT_FUNCTION(0, 86), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO86"), ++ MTK_FUNCTION(1, "RFIC0_BSI_CK") ++ ), ++ MTK_PIN( ++ 87, "GPIO87", ++ MTK_EINT_FUNCTION(0, 87), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO87"), ++ MTK_FUNCTION(2, "MD_INT1_C2K_UIM0_HOT_PLUG"), ++ MTK_FUNCTION(3, "CMVREF0"), ++ MTK_FUNCTION(4, "MD_URXD0"), ++ MTK_FUNCTION(5, "AGPS_SYNC"), ++ MTK_FUNCTION(6, "EXT_FRAME_SYNC") ++ ), ++ MTK_PIN( ++ 88, "GPIO88", ++ MTK_EINT_FUNCTION(0, 88), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO88"), ++ MTK_FUNCTION(1, "CMMCLK3"), ++ MTK_FUNCTION(2, "MD_INT2_C2K_UIM1_HOT_PLUG"), ++ MTK_FUNCTION(3, "CMVREF1"), ++ MTK_FUNCTION(4, "MD_UTXD0"), ++ MTK_FUNCTION(5, "AGPS_SYNC"), ++ MTK_FUNCTION(6, "DVFSRC_EXT_REQ") ++ ), ++ MTK_PIN( ++ 89, "GPIO89", ++ MTK_EINT_FUNCTION(0, 89), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO89"), ++ MTK_FUNCTION(1, "SRCLKENAI0"), ++ MTK_FUNCTION(2, "PWM2"), ++ MTK_FUNCTION(3, "MD_INT0"), ++ MTK_FUNCTION(4, "USB_DRVVBUS"), ++ MTK_FUNCTION(5, "SCL_6306"), ++ MTK_FUNCTION(6, "TP_GPIO4_AO"), ++ MTK_FUNCTION(7, "DBG_MON_B21") ++ ), ++ MTK_PIN( ++ 90, "GPIO90", ++ MTK_EINT_FUNCTION(0, 90), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO90"), ++ MTK_FUNCTION(1, "URXD1"), ++ MTK_FUNCTION(2, "PWM0"), ++ MTK_FUNCTION(3, "MD_INT2_C2K_UIM1_HOT_PLUG"), ++ MTK_FUNCTION(4, "ANT_SEL4"), ++ MTK_FUNCTION(5, "USB_DRVVBUS"), ++ MTK_FUNCTION(6, "I2S2_BCK"), ++ MTK_FUNCTION(7, "DBG_MON_B4") ++ ), ++ MTK_PIN( ++ 91, "GPIO91", ++ MTK_EINT_FUNCTION(0, 91), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO91"), ++ MTK_FUNCTION(1, "KPROW1"), ++ MTK_FUNCTION(2, "PWM2"), ++ MTK_FUNCTION(3, "MD_INT0"), ++ MTK_FUNCTION(4, "ANT_SEL5"), ++ MTK_FUNCTION(5, "IDDIG"), ++ MTK_FUNCTION(6, "I2S2_LRCK"), ++ MTK_FUNCTION(7, "DBG_MON_B5") ++ ), ++ MTK_PIN( ++ 92, "GPIO92", ++ MTK_EINT_FUNCTION(0, 92), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO92"), ++ MTK_FUNCTION(1, "KPROW0"), ++ MTK_FUNCTION(5, "DVFSRC_EXT_REQ"), ++ MTK_FUNCTION(6, "I2S2_DI"), ++ MTK_FUNCTION(7, "DBG_MON_B6") ++ ), ++ MTK_PIN( ++ 93, "GPIO93", ++ MTK_EINT_FUNCTION(0, 93), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO93"), ++ MTK_FUNCTION(1, "KPCOL0"), ++ MTK_FUNCTION(7, "DBG_MON_B7") ++ ), ++ MTK_PIN( ++ 94, "GPIO94", ++ MTK_EINT_FUNCTION(0, 94), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO94"), ++ MTK_FUNCTION(1, "KPCOL1"), ++ MTK_FUNCTION(5, "CMFLASH"), ++ MTK_FUNCTION(6, "CMVREF0"), ++ MTK_FUNCTION(7, "DBG_MON_B8") ++ ), ++ MTK_PIN( ++ 95, "GPIO95", ++ MTK_EINT_FUNCTION(0, 95), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO95"), ++ MTK_FUNCTION(1, "URXD0"), ++ MTK_FUNCTION(2, "UTXD0"), ++ MTK_FUNCTION(3, "MD_URXD0"), ++ MTK_FUNCTION(4, "PTA_RXD"), ++ MTK_FUNCTION(5, "SSPM_URXD_AO"), ++ MTK_FUNCTION(6, "WIFI_RXD") ++ ), ++ MTK_PIN( ++ 96, "GPIO96", ++ MTK_EINT_FUNCTION(0, 96), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO96"), ++ MTK_FUNCTION(1, "UTXD0"), ++ MTK_FUNCTION(2, "URXD0"), ++ MTK_FUNCTION(3, "MD_UTXD0"), ++ MTK_FUNCTION(4, "PTA_TXD"), ++ MTK_FUNCTION(5, "SSPM_UTXD_AO"), ++ MTK_FUNCTION(6, "WIFI_TXD") ++ ), ++ MTK_PIN( ++ 97, "GPIO97", ++ MTK_EINT_FUNCTION(0, 97), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO97"), ++ MTK_FUNCTION(1, "UCTS0"), ++ MTK_FUNCTION(2, "I2S1_MCK"), ++ MTK_FUNCTION(3, "CONN_MCU_TDO"), ++ MTK_FUNCTION(4, "SPI5_MI"), ++ MTK_FUNCTION(5, "SCL_6306"), ++ MTK_FUNCTION(6, "MCUPM_JTAG_TDO"), ++ MTK_FUNCTION(7, "DBG_MON_B15") ++ ), ++ MTK_PIN( ++ 98, "GPIO98", ++ MTK_EINT_FUNCTION(0, 98), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO98"), ++ MTK_FUNCTION(1, "URTS0"), ++ MTK_FUNCTION(2, "I2S1_BCK"), ++ MTK_FUNCTION(3, "CONN_MCU_TMS"), ++ MTK_FUNCTION(4, "SPI5_CSB"), ++ MTK_FUNCTION(6, "MCUPM_JTAG_TMS"), ++ MTK_FUNCTION(7, "DBG_MON_B16") ++ ), ++ MTK_PIN( ++ 99, "GPIO99", ++ MTK_EINT_FUNCTION(0, 99), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO99"), ++ MTK_FUNCTION(1, "CMMCLK0"), ++ MTK_FUNCTION(4, "AUXIF_CLK"), ++ MTK_FUNCTION(5, "PTA_RXD"), ++ MTK_FUNCTION(6, "CONN_UART0_RXD"), ++ MTK_FUNCTION(7, "DBG_MON_B17") ++ ), ++ ++ MTK_PIN( ++ 100, "GPIO100", ++ MTK_EINT_FUNCTION(0, 100), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO100"), ++ MTK_FUNCTION(1, "CMMCLK1"), ++ MTK_FUNCTION(4, "AUXIF_ST"), ++ MTK_FUNCTION(5, "PTA_TXD"), ++ MTK_FUNCTION(6, "CONN_UART0_TXD"), ++ MTK_FUNCTION(7, "DBG_MON_B18") ++ ), ++ MTK_PIN( ++ 101, "GPIO101", ++ MTK_EINT_FUNCTION(0, 101), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO101"), ++ MTK_FUNCTION(1, "CMFLASH"), ++ MTK_FUNCTION(2, "I2S1_LRCK"), ++ MTK_FUNCTION(3, "CONN_MCU_TCK"), ++ MTK_FUNCTION(4, "SPI5_MO"), ++ MTK_FUNCTION(6, "MCUPM_JTAG_TCK"), ++ MTK_FUNCTION(7, "DBG_MON_B19") ++ ), ++ MTK_PIN( ++ 102, "GPIO102", ++ MTK_EINT_FUNCTION(0, 102), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO102"), ++ MTK_FUNCTION(1, "CMVREF0"), ++ MTK_FUNCTION(2, "I2S1_DO"), ++ MTK_FUNCTION(3, "CONN_MCU_TDI"), ++ MTK_FUNCTION(4, "SPI5_CLK"), ++ MTK_FUNCTION(5, "AGPS_SYNC"), ++ MTK_FUNCTION(6, "MCUPM_JTAG_TDI"), ++ MTK_FUNCTION(7, "DBG_MON_B20") ++ ), ++ MTK_PIN( ++ 103, "GPIO103", ++ MTK_EINT_FUNCTION(0, 103), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO103"), ++ MTK_FUNCTION(1, "SCL2"), ++ MTK_FUNCTION(2, "TP_UTXD1_AO"), ++ MTK_FUNCTION(3, "MD_UTXD0"), ++ MTK_FUNCTION(4, "MD_UTXD1"), ++ MTK_FUNCTION(5, "TP_URTS2_AO"), ++ MTK_FUNCTION(6, "WIFI_TXD"), ++ MTK_FUNCTION(7, "DBG_MON_B25") ++ ), ++ MTK_PIN( ++ 104, "GPIO104", ++ MTK_EINT_FUNCTION(0, 104), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO104"), ++ MTK_FUNCTION(1, "SDA2"), ++ MTK_FUNCTION(2, "TP_URXD1_AO"), ++ MTK_FUNCTION(3, "MD_URXD0"), ++ MTK_FUNCTION(4, "MD_URXD1"), ++ MTK_FUNCTION(5, "TP_UCTS2_AO"), ++ MTK_FUNCTION(6, "WIFI_RXD"), ++ MTK_FUNCTION(7, "DBG_MON_B26") ++ ), ++ MTK_PIN( ++ 105, "GPIO105", ++ MTK_EINT_FUNCTION(0, 105), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO105"), ++ MTK_FUNCTION(1, "SCL4"), ++ MTK_FUNCTION(3, "MD_UTXD1"), ++ MTK_FUNCTION(4, "MD_UTXD0"), ++ MTK_FUNCTION(5, "TP_UTXD2_AO"), ++ MTK_FUNCTION(6, "PTA_TXD"), ++ MTK_FUNCTION(7, "DBG_MON_B27") ++ ), ++ MTK_PIN( ++ 106, "GPIO106", ++ MTK_EINT_FUNCTION(0, 106), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO106"), ++ MTK_FUNCTION(1, "SDA4"), ++ MTK_FUNCTION(3, "MD_URXD1"), ++ MTK_FUNCTION(4, "MD_URXD0"), ++ MTK_FUNCTION(5, "TP_URXD2_AO"), ++ MTK_FUNCTION(6, "PTA_RXD"), ++ MTK_FUNCTION(7, "DBG_MON_B28") ++ ), ++ MTK_PIN( ++ 107, "GPIO107", ++ MTK_EINT_FUNCTION(0, 107), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO107"), ++ MTK_FUNCTION(1, "UTXD1"), ++ MTK_FUNCTION(2, "MD_UTXD0"), ++ MTK_FUNCTION(3, "SDA_6306"), ++ MTK_FUNCTION(4, "KPCOL3"), ++ MTK_FUNCTION(5, "CMVREF0"), ++ MTK_FUNCTION(6, "URTS0"), ++ MTK_FUNCTION(7, "DBG_MON_B29") ++ ), ++ MTK_PIN( ++ 108, "GPIO108", ++ MTK_EINT_FUNCTION(0, 108), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO108"), ++ MTK_FUNCTION(1, "CMMCLK2"), ++ MTK_FUNCTION(2, "MD_INT0"), ++ MTK_FUNCTION(3, "CONN_MCU_DBGACK_N"), ++ MTK_FUNCTION(4, "KPCOL4"), ++ MTK_FUNCTION(6, "I2S3_MCK"), ++ MTK_FUNCTION(7, "DBG_MON_B30") ++ ), ++ MTK_PIN( ++ 109, "GPIO109", ++ MTK_EINT_FUNCTION(0, 109), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO109"), ++ MTK_FUNCTION(1, "URXD1"), ++ MTK_FUNCTION(2, "MD_URXD0"), ++ MTK_FUNCTION(3, "ANT_SEL7"), ++ MTK_FUNCTION(4, "KPCOL5"), ++ MTK_FUNCTION(5, "CMVREF1"), ++ MTK_FUNCTION(6, "UCTS0"), ++ MTK_FUNCTION(7, "DBG_MON_B31") ++ ), ++ MTK_PIN( ++ 110, "GPIO110", ++ MTK_EINT_FUNCTION(0, 110), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO110"), ++ MTK_FUNCTION(1, "ANT_SEL0"), ++ MTK_FUNCTION(2, "CLKM0"), ++ MTK_FUNCTION(3, "PWM3"), ++ MTK_FUNCTION(4, "MD_INT0"), ++ MTK_FUNCTION(5, "IDDIG"), ++ MTK_FUNCTION(6, "I2S3_BCK"), ++ MTK_FUNCTION(7, "DBG_MON_B13") ++ ), ++ MTK_PIN( ++ 111, "GPIO111", ++ MTK_EINT_FUNCTION(0, 111), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO111"), ++ MTK_FUNCTION(1, "ANT_SEL1"), ++ MTK_FUNCTION(2, "CLKM1"), ++ MTK_FUNCTION(3, "PWM4"), ++ MTK_FUNCTION(4, "PTA_RXD"), ++ MTK_FUNCTION(5, "CMVREF0"), ++ MTK_FUNCTION(6, "I2S3_LRCK"), ++ MTK_FUNCTION(7, "DBG_MON_B14") ++ ), ++ MTK_PIN( ++ 112, "GPIO112", ++ MTK_EINT_FUNCTION(0, 112), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO112"), ++ MTK_FUNCTION(1, "ANT_SEL2"), ++ MTK_FUNCTION(2, "CLKM2"), ++ MTK_FUNCTION(3, "PWM5"), ++ MTK_FUNCTION(4, "PTA_TXD"), ++ MTK_FUNCTION(5, "CMVREF1"), ++ MTK_FUNCTION(6, "I2S3_DO") ++ ), ++ MTK_PIN( ++ 113, "GPIO113", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO113"), ++ MTK_FUNCTION(1, "CONN_TOP_CLK") ++ ), ++ MTK_PIN( ++ 114, "GPIO114", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO114"), ++ MTK_FUNCTION(1, "CONN_TOP_DATA") ++ ), ++ MTK_PIN( ++ 115, "GPIO115", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO115"), ++ MTK_FUNCTION(1, "CONN_BT_CLK") ++ ), ++ MTK_PIN( ++ 116, "GPIO116", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO116"), ++ MTK_FUNCTION(1, "CONN_BT_DATA") ++ ), ++ MTK_PIN( ++ 117, "GPIO117", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO117"), ++ MTK_FUNCTION(1, "CONN_WF_CTRL0") ++ ), ++ MTK_PIN( ++ 118, "GPIO118", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO118"), ++ MTK_FUNCTION(1, "CONN_WF_CTRL1") ++ ), ++ MTK_PIN( ++ 119, "GPIO119", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO119"), ++ MTK_FUNCTION(1, "CONN_WF_CTRL2") ++ ), ++ MTK_PIN( ++ 120, "GPIO120", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO120"), ++ MTK_FUNCTION(1, "CONN_WB_PTA") ++ ), ++ MTK_PIN( ++ 121, "GPIO121", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO121"), ++ MTK_FUNCTION(1, "CONN_HRST_B") ++ ), ++ MTK_PIN( ++ 122, "GPIO122", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO122"), ++ MTK_FUNCTION(1, "MSDC0_CMD"), ++ MTK_FUNCTION(2, "MSDC0_CMD") ++ ), ++ MTK_PIN( ++ 123, "GPIO123", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO123"), ++ MTK_FUNCTION(1, "MSDC0_DAT0"), ++ MTK_FUNCTION(2, "MSDC0_DAT4") ++ ), ++ MTK_PIN( ++ 124, "GPIO124", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO124"), ++ MTK_FUNCTION(1, "MSDC0_CLK"), ++ MTK_FUNCTION(2, "MSDC0_CLK") ++ ), ++ MTK_PIN( ++ 125, "GPIO125", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO125"), ++ MTK_FUNCTION(1, "MSDC0_DAT2"), ++ MTK_FUNCTION(2, "MSDC0_DAT5") ++ ), ++ MTK_PIN( ++ 126, "GPIO126", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO126"), ++ MTK_FUNCTION(1, "MSDC0_DAT4"), ++ MTK_FUNCTION(2, "MSDC0_DAT2") ++ ), ++ MTK_PIN( ++ 127, "GPIO127", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO127"), ++ MTK_FUNCTION(1, "MSDC0_DAT6"), ++ MTK_FUNCTION(2, "MSDC0_DAT1") ++ ), ++ MTK_PIN( ++ 128, "GPIO128", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO128"), ++ MTK_FUNCTION(1, "MSDC0_DAT1"), ++ MTK_FUNCTION(2, "MSDC0_DAT6") ++ ), ++ MTK_PIN( ++ 129, "GPIO129", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO129"), ++ MTK_FUNCTION(1, "MSDC0_DAT5"), ++ MTK_FUNCTION(2, "MSDC0_DAT0") ++ ), ++ MTK_PIN( ++ 130, "GPIO130", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO130"), ++ MTK_FUNCTION(1, "MSDC0_DAT7"), ++ MTK_FUNCTION(2, "MSDC0_DAT7") ++ ), ++ MTK_PIN( ++ 131, "GPIO131", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO131"), ++ MTK_FUNCTION(1, "MSDC0_DSL"), ++ MTK_FUNCTION(2, "MSDC0_DSL") ++ ), ++ MTK_PIN( ++ 132, "GPIO132", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO132"), ++ MTK_FUNCTION(1, "MSDC0_DAT3"), ++ MTK_FUNCTION(2, "MSDC0_DAT3") ++ ), ++ MTK_PIN( ++ 133, "GPIO133", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO133"), ++ MTK_FUNCTION(1, "MSDC0_RSTB"), ++ MTK_FUNCTION(2, "MSDC0_RSTB") ++ ), ++ MTK_PIN( ++ 134, "GPIO134", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO134"), ++ MTK_FUNCTION(1, "RTC32K_CK") ++ ), ++ MTK_PIN( ++ 135, "GPIO135", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO135"), ++ MTK_FUNCTION(1, "WATCHDOG") ++ ), ++ MTK_PIN( ++ 136, "GPIO136", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO136"), ++ MTK_FUNCTION(1, "AUD_CLK_MOSI"), ++ MTK_FUNCTION(2, "AUD_CLK_MISO"), ++ MTK_FUNCTION(3, "I2S1_MCK") ++ ), ++ MTK_PIN( ++ 137, "GPIO137", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO137"), ++ MTK_FUNCTION(1, "AUD_SYNC_MOSI"), ++ MTK_FUNCTION(2, "AUD_SYNC_MISO"), ++ MTK_FUNCTION(3, "I2S1_BCK") ++ ), ++ MTK_PIN( ++ 138, "GPIO138", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO138"), ++ MTK_FUNCTION(1, "AUD_DAT_MOSI0"), ++ MTK_FUNCTION(2, "AUD_DAT_MISO0"), ++ MTK_FUNCTION(3, "I2S1_LRCK") ++ ), ++ MTK_PIN( ++ 139, "GPIO139", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO139"), ++ MTK_FUNCTION(1, "AUD_DAT_MOSI1"), ++ MTK_FUNCTION(2, "AUD_DAT_MISO1"), ++ MTK_FUNCTION(3, "I2S1_DO") ++ ), ++ MTK_PIN( ++ 140, "GPIO140", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO140"), ++ MTK_FUNCTION(1, "AUD_CLK_MISO"), ++ MTK_FUNCTION(2, "AUD_CLK_MOSI"), ++ MTK_FUNCTION(3, "I2S2_MCK") ++ ), ++ MTK_PIN( ++ 141, "GPIO141", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO141"), ++ MTK_FUNCTION(1, "AUD_SYNC_MISO"), ++ MTK_FUNCTION(2, "AUD_SYNC_MOSI"), ++ MTK_FUNCTION(3, "I2S2_BCK") ++ ), ++ MTK_PIN( ++ 142, "GPIO142", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO142"), ++ MTK_FUNCTION(1, "AUD_DAT_MISO0"), ++ MTK_FUNCTION(2, "AUD_DAT_MOSI0"), ++ MTK_FUNCTION(3, "I2S2_LRCK") ++ ), ++ MTK_PIN( ++ 143, "GPIO143", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO143"), ++ MTK_FUNCTION(1, "AUD_DAT_MISO1"), ++ MTK_FUNCTION(2, "AUD_DAT_MOSI1"), ++ MTK_FUNCTION(3, "I2S2_DI") ++ ), ++ MTK_PIN( ++ 144, "GPIO144", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO144"), ++ MTK_FUNCTION(1, "PWRAP_SPI0_MI"), ++ MTK_FUNCTION(2, "PWRAP_SPI0_MO") ++ ), ++ MTK_PIN( ++ 145, "GPIO145", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO145"), ++ MTK_FUNCTION(1, "PWRAP_SPI0_CSN") ++ ), ++ MTK_PIN( ++ 146, "GPIO146", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO146"), ++ MTK_FUNCTION(1, "PWRAP_SPI0_MO"), ++ MTK_FUNCTION(2, "PWRAP_SPI0_MI") ++ ), ++ MTK_PIN( ++ 147, "GPIO147", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO147"), ++ MTK_FUNCTION(1, "PWRAP_SPI0_CK") ++ ), ++ MTK_PIN( ++ 148, "GPIO148", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO148"), ++ MTK_FUNCTION(1, "SRCLKENA0") ++ ), ++ MTK_PIN( ++ 149, "GPIO149", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO149"), ++ MTK_FUNCTION(1, "SRCLKENA1") ++ ), ++ MTK_PIN( ++ 150, "GPIO150", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO150"), ++ MTK_FUNCTION(1, "PWM0"), ++ MTK_FUNCTION(2, "CMFLASH"), ++ MTK_FUNCTION(3, "ANT_SEL3"), ++ MTK_FUNCTION(5, "MD_URXD0"), ++ MTK_FUNCTION(6, "TP_URXD2_AO") ++ ), ++ MTK_PIN( ++ 151, "GPIO151", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO151"), ++ MTK_FUNCTION(1, "PWM1"), ++ MTK_FUNCTION(2, "CMVREF0"), ++ MTK_FUNCTION(3, "ANT_SEL4"), ++ MTK_FUNCTION(5, "MD_UTXD0"), ++ MTK_FUNCTION(6, "TP_UTXD2_AO") ++ ), ++ MTK_PIN( ++ 152, "GPIO152", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO152"), ++ MTK_FUNCTION(1, "PWM2"), ++ MTK_FUNCTION(2, "CMVREF1"), ++ MTK_FUNCTION(3, "ANT_SEL5"), ++ MTK_FUNCTION(5, "MD_URXD1"), ++ MTK_FUNCTION(6, "TP_UCTS1_AO") ++ ), ++ MTK_PIN( ++ 153, "GPIO153", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO153"), ++ MTK_FUNCTION(1, "PWM3"), ++ MTK_FUNCTION(2, "CLKM0"), ++ MTK_FUNCTION(3, "ANT_SEL6"), ++ MTK_FUNCTION(5, "MD_UTXD1"), ++ MTK_FUNCTION(6, "TP_URTS1_AO") ++ ), ++ MTK_PIN( ++ 154, "GPIO154", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO154"), ++ MTK_FUNCTION(1, "PWM5"), ++ MTK_FUNCTION(2, "CLKM2"), ++ MTK_FUNCTION(3, "USB_DRVVBUS"), ++ MTK_FUNCTION(5, "PTA_TXD"), ++ MTK_FUNCTION(6, "CONN_UART0_TXD") ++ ), ++ MTK_PIN( ++ 155, "GPIO155", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO155"), ++ MTK_FUNCTION(1, "SPI0_MI"), ++ MTK_FUNCTION(2, "IDDIG"), ++ MTK_FUNCTION(3, "AGPS_SYNC"), ++ MTK_FUNCTION(4, "TP_GPIO0_AO"), ++ MTK_FUNCTION(5, "MFG_JTAG_TDO"), ++ MTK_FUNCTION(6, "DFD_TDO"), ++ MTK_FUNCTION(7, "JTDO_SEL1") ++ ), ++ MTK_PIN( ++ 156, "GPIO156", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO156"), ++ MTK_FUNCTION(1, "SPI0_CSB"), ++ MTK_FUNCTION(2, "USB_DRVVBUS"), ++ MTK_FUNCTION(3, "DVFSRC_EXT_REQ"), ++ MTK_FUNCTION(4, "TP_GPIO1_AO"), ++ MTK_FUNCTION(5, "MFG_JTAG_TMS"), ++ MTK_FUNCTION(6, "DFD_TMS"), ++ MTK_FUNCTION(7, "JTMS_SEL1") ++ ), ++ MTK_PIN( ++ 157, "GPIO157", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO157"), ++ MTK_FUNCTION(1, "SPI0_MO"), ++ MTK_FUNCTION(2, "MD_INT1_C2K_UIM0_HOT_PLUG"), ++ MTK_FUNCTION(3, "CLKM0"), ++ MTK_FUNCTION(4, "TP_GPIO2_AO"), ++ MTK_FUNCTION(5, "MFG_JTAG_TDI"), ++ MTK_FUNCTION(6, "DFD_TDI"), ++ MTK_FUNCTION(7, "JTDI_SEL1") ++ ), ++ MTK_PIN( ++ 158, "GPIO158", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO158"), ++ MTK_FUNCTION(1, "SPI0_CLK"), ++ MTK_FUNCTION(2, "MD_INT2_C2K_UIM1_HOT_PLUG"), ++ MTK_FUNCTION(3, "EXT_FRAME_SYNC"), ++ MTK_FUNCTION(4, "TP_GPIO3_AO"), ++ MTK_FUNCTION(5, "MFG_JTAG_TCK"), ++ MTK_FUNCTION(6, "DFD_TCK_XI"), ++ MTK_FUNCTION(7, "JTCK_SEL1") ++ ), ++ MTK_PIN( ++ 159, "GPIO159", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO159"), ++ MTK_FUNCTION(1, "PWM4"), ++ MTK_FUNCTION(2, "CLKM1"), ++ MTK_FUNCTION(3, "ANT_SEL7"), ++ MTK_FUNCTION(5, "PTA_RXD"), ++ MTK_FUNCTION(6, "CONN_UART0_RXD") ++ ), ++ MTK_PIN( ++ 160, "GPIO160", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO160"), ++ MTK_FUNCTION(1, "CLKM0"), ++ MTK_FUNCTION(2, "PWM2"), ++ MTK_FUNCTION(3, "EXT_FRAME_SYNC"), ++ MTK_FUNCTION(4, "TP_GPIO5_AO"), ++ MTK_FUNCTION(5, "AGPS_SYNC"), ++ MTK_FUNCTION(6, "DVFSRC_EXT_REQ") ++ ), ++ MTK_PIN( ++ 161, "GPIO161", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO161"), ++ MTK_FUNCTION(1, "SCL6"), ++ MTK_FUNCTION(2, "SCL_6306"), ++ MTK_FUNCTION(3, "TP_GPIO6_AO"), ++ MTK_FUNCTION(4, "KPCOL6"), ++ MTK_FUNCTION(5, "PTA_RXD"), ++ MTK_FUNCTION(6, "CONN_UART0_RXD") ++ ), ++ MTK_PIN( ++ 162, "GPIO162", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO162"), ++ MTK_FUNCTION(1, "SDA6"), ++ MTK_FUNCTION(2, "SDA_6306"), ++ MTK_FUNCTION(3, "TP_GPIO7_AO"), ++ MTK_FUNCTION(4, "KPCOL7"), ++ MTK_FUNCTION(5, "PTA_TXD"), ++ MTK_FUNCTION(6, "CONN_UART0_TXD") ++ ), ++ MTK_PIN( ++ 163, "GPIO163", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO163") ++ ), ++ MTK_PIN( ++ 164, "GPIO164", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO164") ++ ), ++ MTK_PIN( ++ 165, "GPIO165", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO165") ++ ), ++ MTK_PIN( ++ 166, "GPIO166", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO166") ++ ), ++ MTK_PIN( ++ 167, "GPIO167", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO167") ++ ), ++ MTK_PIN( ++ 168, "GPIO168", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO168") ++ ), ++ MTK_PIN( ++ 169, "GPIO169", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO169") ++ ), ++ MTK_PIN( ++ 170, "GPIO170", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO170") ++ ), ++ MTK_PIN( ++ 171, "GPIO171", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO171") ++ ), ++ MTK_PIN( ++ 172, "GPIO172", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO172") ++ ), ++ MTK_PIN( ++ 173, "GPIO173", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO173") ++ ), ++ MTK_PIN( ++ 174, "GPIO174", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO174") ++ ), ++ MTK_PIN( ++ 175, "GPIO175", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO175") ++ ), ++ MTK_PIN( ++ 176, "GPIO176", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO176") ++ ), ++ MTK_PIN( ++ 177, "GPIO177", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO177") ++ ), ++ MTK_PIN( ++ 178, "GPIO178", ++ MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO178") ++ ), ++ MTK_PIN( ++ 179, "GPIO179", ++ MTK_EINT_FUNCTION(0, 151), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO179") ++ ), ++}; ++ ++#endif /* __PINCTRL_MTK_MT6765_H */ +diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6797.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6797.h +new file mode 100644 +index 000000000000..86ab78e80326 +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6797.h +@@ -0,0 +1,2429 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Based on pinctrl-mtk-mt6765.h ++ * ++ * Copyright (C) 2018 MediaTek Inc. ++ * ++ * Author: ZH Chen <zh.chen@mediatek.com> ++ * ++ * Copyright (c) 2018 Manivannan Sadhasivam ++ */ ++ ++#ifndef __PINCTRL_MTK_MT6797_H ++#define __PINCTRL_MTK_MT6797_H ++ ++#include "pinctrl-paris.h" ++ ++static const struct mtk_pin_desc mtk_pins_mt6797[] = { ++ MTK_PIN( ++ 0, "GPIO0", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO0"), ++ MTK_FUNCTION(1, "CSI0A_L0P_T0A") ++ ), ++ MTK_PIN( ++ 1, "GPIO1", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO1"), ++ MTK_FUNCTION(1, "CSI0A_L0N_T0B") ++ ), ++ MTK_PIN( ++ 2, "GPIO2", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO2"), ++ MTK_FUNCTION(1, "CSI0A_L1P_T0C") ++ ), ++ MTK_PIN( ++ 3, "GPIO3", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO3"), ++ MTK_FUNCTION(1, "CSI0A_L1N_T1A") ++ ), ++ MTK_PIN( ++ 4, "GPIO4", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO4"), ++ MTK_FUNCTION(1, "CSI0A_L2P_T1B") ++ ), ++ MTK_PIN( ++ 5, "GPIO5", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO5"), ++ MTK_FUNCTION(1, "CSI0A_L2N_T1C") ++ ), ++ MTK_PIN( ++ 6, "GPIO6", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO6"), ++ MTK_FUNCTION(1, "CSI0B_L0P_T0A") ++ ), ++ MTK_PIN( ++ 7, "GPIO7", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO7"), ++ MTK_FUNCTION(1, "CSI0B_L0N_T0B") ++ ), ++ MTK_PIN( ++ 8, "GPIO8", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO8"), ++ MTK_FUNCTION(1, "CSI0B_L1P_T0C") ++ ), ++ MTK_PIN( ++ 9, "GPIO9", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO9"), ++ MTK_FUNCTION(1, "CSI0B_L1N_T1A") ++ ), ++ MTK_PIN( ++ 10, "GPIO10", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO10"), ++ MTK_FUNCTION(1, "CSI1A_L0P_T0A") ++ ), ++ MTK_PIN( ++ 11, "GPIO11", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO11"), ++ MTK_FUNCTION(1, "CSI1A_L0N_T0B") ++ ), ++ MTK_PIN( ++ 12, "GPIO12", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO12"), ++ MTK_FUNCTION(1, "CSI1A_L1P_T0C") ++ ), ++ MTK_PIN( ++ 13, "GPIO13", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO13"), ++ MTK_FUNCTION(1, "CSI1A_L1N_T1A") ++ ), ++ MTK_PIN( ++ 14, "GPIO14", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO14"), ++ MTK_FUNCTION(1, "CSI1A_L2P_T1B") ++ ), ++ MTK_PIN( ++ 15, "GPIO15", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO15"), ++ MTK_FUNCTION(1, "CSI1A_L2N_T1C") ++ ), ++ MTK_PIN( ++ 16, "GPIO16", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO16"), ++ MTK_FUNCTION(1, "CSI1B_L0P_T0A") ++ ), ++ MTK_PIN( ++ 17, "GPIO17", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO17"), ++ MTK_FUNCTION(1, "CSI1B_L0N_T0B") ++ ), ++ MTK_PIN( ++ 18, "GPIO18", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO18"), ++ MTK_FUNCTION(1, "CSI1B_L1P_T0C") ++ ), ++ MTK_PIN( ++ 19, "GPIO19", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO19"), ++ MTK_FUNCTION(1, "CSI1B_L1N_T1A") ++ ), ++ MTK_PIN( ++ 20, "GPIO20", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO20"), ++ MTK_FUNCTION(1, "CSI1B_L2P_T1B") ++ ), ++ MTK_PIN( ++ 21, "GPIO21", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO21"), ++ MTK_FUNCTION(1, "CSI1B_L2N_T1C") ++ ), ++ MTK_PIN( ++ 22, "GPIO22", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO22"), ++ MTK_FUNCTION(1, "CSI2_L0P_T0A") ++ ), ++ MTK_PIN( ++ 23, "GPIO23", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO23"), ++ MTK_FUNCTION(1, "CSI2_L0N_T0B") ++ ), ++ MTK_PIN( ++ 24, "GPIO24", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO24"), ++ MTK_FUNCTION(1, "CSI2_L1P_T0C") ++ ), ++ MTK_PIN( ++ 25, "GPIO25", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO25"), ++ MTK_FUNCTION(1, "CSI2_L1N_T1A") ++ ), ++ MTK_PIN( ++ 26, "GPIO26", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO26"), ++ MTK_FUNCTION(1, "CSI2_L2P_T1B") ++ ), ++ MTK_PIN( ++ 27, "GPIO27", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO27"), ++ MTK_FUNCTION(1, "CSI2_L2N_T1C") ++ ), ++ MTK_PIN( ++ 28, "GPIO28", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO28"), ++ MTK_FUNCTION(1, "SPI5_CLK_A"), ++ MTK_FUNCTION(2, "IRTX_OUT"), ++ MTK_FUNCTION(3, "UDI_TDO"), ++ MTK_FUNCTION(4, "SCP_JTAG_TDO"), ++ MTK_FUNCTION(5, "CONN_MCU_TDO"), ++ MTK_FUNCTION(6, "PWM_A"), ++ MTK_FUNCTION(7, "C2K_DM_OTDO") ++ ), ++ MTK_PIN( ++ 29, "GPIO29", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO29"), ++ MTK_FUNCTION(1, "SPI5_MI_A"), ++ MTK_FUNCTION(2, "DAP_SIB1_SWD"), ++ MTK_FUNCTION(3, "UDI_TMS"), ++ MTK_FUNCTION(4, "SCP_JTAG_TMS"), ++ MTK_FUNCTION(5, "CONN_MCU_TMS"), ++ MTK_FUNCTION(6, "CONN_MCU_AICE_TMSC"), ++ MTK_FUNCTION(7, "C2K_DM_OTMS") ++ ), ++ MTK_PIN( ++ 30, "GPIO30", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO30"), ++ MTK_FUNCTION(1, "CMMCLK0"), ++ MTK_FUNCTION(7, "MD_CLKM0") ++ ), ++ MTK_PIN( ++ 31, "GPIO31", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO31"), ++ MTK_FUNCTION(1, "CMMCLK1"), ++ MTK_FUNCTION(7, "MD_CLKM1") ++ ), ++ MTK_PIN( ++ 32, "GPIO32", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO32"), ++ MTK_FUNCTION(1, "SPI5_CS_A"), ++ MTK_FUNCTION(2, "DAP_SIB1_SWCK"), ++ MTK_FUNCTION(3, "UDI_TCK_XI"), ++ MTK_FUNCTION(4, "SCP_JTAG_TCK"), ++ MTK_FUNCTION(5, "CONN_MCU_TCK"), ++ MTK_FUNCTION(6, "CONN_MCU_AICE_TCKC"), ++ MTK_FUNCTION(7, "C2K_DM_OTCK") ++ ), ++ MTK_PIN( ++ 33, "GPIO33", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO33"), ++ MTK_FUNCTION(1, "SPI5_MO_A"), ++ MTK_FUNCTION(2, "CMFLASH"), ++ MTK_FUNCTION(3, "UDI_TDI"), ++ MTK_FUNCTION(4, "SCP_JTAG_TDI"), ++ MTK_FUNCTION(5, "CONN_MCU_TDI"), ++ MTK_FUNCTION(6, "MD_URXD0"), ++ MTK_FUNCTION(7, "C2K_DM_OTDI") ++ ), ++ MTK_PIN( ++ 34, "GPIO34", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO34"), ++ MTK_FUNCTION(1, "CMFLASH"), ++ MTK_FUNCTION(2, "CLKM0"), ++ MTK_FUNCTION(3, "UDI_NTRST"), ++ MTK_FUNCTION(4, "SCP_JTAG_TRSTN"), ++ MTK_FUNCTION(5, "CONN_MCU_TRST_B"), ++ MTK_FUNCTION(6, "MD_UTXD0"), ++ MTK_FUNCTION(7, "C2K_DM_JTINTP") ++ ), ++ MTK_PIN( ++ 35, "GPIO35", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO35"), ++ MTK_FUNCTION(1, "CMMCLK3"), ++ MTK_FUNCTION(2, "CLKM1"), ++ MTK_FUNCTION(3, "MD_URXD1"), ++ MTK_FUNCTION(4, "PTA_RXD"), ++ MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"), ++ MTK_FUNCTION(6, "PWM_B"), ++ MTK_FUNCTION(7, "PCC_PPC_IO") ++ ), ++ MTK_PIN( ++ 36, "GPIO36", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO36"), ++ MTK_FUNCTION(1, "CMMCLK2"), ++ MTK_FUNCTION(2, "CLKM2"), ++ MTK_FUNCTION(3, "MD_UTXD1"), ++ MTK_FUNCTION(4, "PTA_TXD"), ++ MTK_FUNCTION(5, "CONN_MCU_DBGI_N"), ++ MTK_FUNCTION(6, "PWM_C"), ++ MTK_FUNCTION(7, "EXT_FRAME_SYNC") ++ ), ++ MTK_PIN( ++ 37, "GPIO37", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO37"), ++ MTK_FUNCTION(1, "SCL0_0") ++ ), ++ MTK_PIN( ++ 38, "GPIO38", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO38"), ++ MTK_FUNCTION(1, "SDA0_0") ++ ), ++ MTK_PIN( ++ 39, "GPIO39", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO39"), ++ MTK_FUNCTION(1, "DPI_D0"), ++ MTK_FUNCTION(2, "SPI1_CLK_A"), ++ MTK_FUNCTION(3, "PCM0_SYNC"), ++ MTK_FUNCTION(4, "I2S0_LRCK"), ++ MTK_FUNCTION(5, "CONN_MCU_TRST_B"), ++ MTK_FUNCTION(6, "URXD3"), ++ MTK_FUNCTION(7, "C2K_NTRST") ++ ), ++ MTK_PIN( ++ 40, "GPIO40", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO40"), ++ MTK_FUNCTION(1, "DPI_D1"), ++ MTK_FUNCTION(2, "SPI1_MI_A"), ++ MTK_FUNCTION(3, "PCM0_CLK"), ++ MTK_FUNCTION(4, "I2S0_BCK"), ++ MTK_FUNCTION(5, "CONN_MCU_TDO"), ++ MTK_FUNCTION(6, "UTXD3"), ++ MTK_FUNCTION(7, "C2K_TCK") ++ ), ++ MTK_PIN( ++ 41, "GPIO41", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO41"), ++ MTK_FUNCTION(1, "DPI_D2"), ++ MTK_FUNCTION(2, "SPI1_CS_A"), ++ MTK_FUNCTION(3, "PCM0_DO"), ++ MTK_FUNCTION(4, "I2S3_DO"), ++ MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"), ++ MTK_FUNCTION(6, "URTS3"), ++ MTK_FUNCTION(7, "C2K_TDI") ++ ), ++ MTK_PIN( ++ 42, "GPIO42", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO42"), ++ MTK_FUNCTION(1, "DPI_D3"), ++ MTK_FUNCTION(2, "SPI1_MO_A"), ++ MTK_FUNCTION(3, "PCM0_DI"), ++ MTK_FUNCTION(4, "I2S0_DI"), ++ MTK_FUNCTION(5, "CONN_MCU_TDI"), ++ MTK_FUNCTION(6, "UCTS3"), ++ MTK_FUNCTION(7, "C2K_TMS") ++ ), ++ MTK_PIN( ++ 43, "GPIO43", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO43"), ++ MTK_FUNCTION(1, "DPI_D4"), ++ MTK_FUNCTION(2, "SPI2_CLK_A"), ++ MTK_FUNCTION(3, "PCM1_SYNC"), ++ MTK_FUNCTION(4, "I2S2_LRCK"), ++ MTK_FUNCTION(5, "CONN_MCU_TMS"), ++ MTK_FUNCTION(6, "CONN_MCU_AICE_TMSC"), ++ MTK_FUNCTION(7, "C2K_TDO") ++ ), ++ MTK_PIN( ++ 44, "GPIO44", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO44"), ++ MTK_FUNCTION(1, "DPI_D5"), ++ MTK_FUNCTION(2, "SPI2_MI_A"), ++ MTK_FUNCTION(3, "PCM1_CLK"), ++ MTK_FUNCTION(4, "I2S2_BCK"), ++ MTK_FUNCTION(5, "CONN_MCU_TCK"), ++ MTK_FUNCTION(6, "CONN_MCU_AICE_TCKC"), ++ MTK_FUNCTION(7, "C2K_RTCK") ++ ), ++ MTK_PIN( ++ 45, "GPIO45", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO45"), ++ MTK_FUNCTION(1, "DPI_D6"), ++ MTK_FUNCTION(2, "SPI2_CS_A"), ++ MTK_FUNCTION(3, "PCM1_DI"), ++ MTK_FUNCTION(4, "I2S2_DI"), ++ MTK_FUNCTION(5, "CONN_MCU_DBGI_N"), ++ MTK_FUNCTION(6, "MD_URXD0") ++ ), ++ MTK_PIN( ++ 46, "GPIO46", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO46"), ++ MTK_FUNCTION(1, "DPI_D7"), ++ MTK_FUNCTION(2, "SPI2_MO_A"), ++ MTK_FUNCTION(3, "PCM1_DO0"), ++ MTK_FUNCTION(4, "I2S1_DO"), ++ MTK_FUNCTION(5, "ANT_SEL0"), ++ MTK_FUNCTION(6, "MD_UTXD0") ++ ), ++ MTK_PIN( ++ 47, "GPIO47", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO47"), ++ MTK_FUNCTION(1, "DPI_D8"), ++ MTK_FUNCTION(2, "CLKM0"), ++ MTK_FUNCTION(3, "PCM1_DO1"), ++ MTK_FUNCTION(4, "I2S0_MCK"), ++ MTK_FUNCTION(5, "ANT_SEL1"), ++ MTK_FUNCTION(6, "PTA_RXD"), ++ MTK_FUNCTION(7, "C2K_URXD0") ++ ), ++ MTK_PIN( ++ 48, "GPIO48", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO48"), ++ MTK_FUNCTION(1, "DPI_D9"), ++ MTK_FUNCTION(2, "CLKM1"), ++ MTK_FUNCTION(3, "CMFLASH"), ++ MTK_FUNCTION(4, "I2S2_MCK"), ++ MTK_FUNCTION(5, "ANT_SEL2"), ++ MTK_FUNCTION(6, "PTA_TXD"), ++ MTK_FUNCTION(7, "C2K_UTXD0") ++ ), ++ MTK_PIN( ++ 49, "GPIO49", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO49"), ++ MTK_FUNCTION(1, "DPI_D10"), ++ MTK_FUNCTION(2, "MD_INT1_C2K_UIM1_HOT_PLUG_IN"), ++ MTK_FUNCTION(3, "PWM_C"), ++ MTK_FUNCTION(4, "IRTX_OUT"), ++ MTK_FUNCTION(5, "ANT_SEL3"), ++ MTK_FUNCTION(6, "MD_URXD1") ++ ), ++ MTK_PIN( ++ 50, "GPIO50", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO50"), ++ MTK_FUNCTION(1, "DPI_D11"), ++ MTK_FUNCTION(2, "MD_INT2"), ++ MTK_FUNCTION(3, "PWM_D"), ++ MTK_FUNCTION(4, "CLKM2"), ++ MTK_FUNCTION(5, "ANT_SEL4"), ++ MTK_FUNCTION(6, "MD_UTXD1") ++ ), ++ MTK_PIN( ++ 51, "GPIO51", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO51"), ++ MTK_FUNCTION(1, "DPI_DE"), ++ MTK_FUNCTION(2, "SPI4_CLK_A"), ++ MTK_FUNCTION(3, "IRTX_OUT"), ++ MTK_FUNCTION(4, "SCL0_1"), ++ MTK_FUNCTION(5, "ANT_SEL5"), ++ MTK_FUNCTION(7, "C2K_UTXD1") ++ ), ++ MTK_PIN( ++ 52, "GPIO52", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO52"), ++ MTK_FUNCTION(1, "DPI_CK"), ++ MTK_FUNCTION(2, "SPI4_MI_A"), ++ MTK_FUNCTION(3, "SPI4_MO_A"), ++ MTK_FUNCTION(4, "SDA0_1"), ++ MTK_FUNCTION(5, "ANT_SEL6"), ++ MTK_FUNCTION(7, "C2K_URXD1") ++ ), ++ MTK_PIN( ++ 53, "GPIO53", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO53"), ++ MTK_FUNCTION(1, "DPI_HSYNC"), ++ MTK_FUNCTION(2, "SPI4_CS_A"), ++ MTK_FUNCTION(3, "CMFLASH"), ++ MTK_FUNCTION(4, "SCL1_1"), ++ MTK_FUNCTION(5, "ANT_SEL7"), ++ MTK_FUNCTION(6, "MD_URXD2"), ++ MTK_FUNCTION(7, "PCC_PPC_IO") ++ ), ++ MTK_PIN( ++ 54, "GPIO54", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO54"), ++ MTK_FUNCTION(1, "DPI_VSYNC"), ++ MTK_FUNCTION(2, "SPI4_MO_A"), ++ MTK_FUNCTION(3, "SPI4_MI_A"), ++ MTK_FUNCTION(4, "SDA1_1"), ++ MTK_FUNCTION(5, "PWM_A"), ++ MTK_FUNCTION(6, "MD_UTXD2"), ++ MTK_FUNCTION(7, "EXT_FRAME_SYNC") ++ ), ++ MTK_PIN( ++ 55, "GPIO55", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO55"), ++ MTK_FUNCTION(1, "SCL1_0") ++ ), ++ MTK_PIN( ++ 56, "GPIO56", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO56"), ++ MTK_FUNCTION(1, "SDA1_0") ++ ), ++ MTK_PIN( ++ 57, "GPIO57", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO57"), ++ MTK_FUNCTION(1, "SPI0_CLK"), ++ MTK_FUNCTION(2, "SCL0_2"), ++ MTK_FUNCTION(3, "PWM_B"), ++ MTK_FUNCTION(4, "UTXD3"), ++ MTK_FUNCTION(5, "PCM0_SYNC") ++ ), ++ MTK_PIN( ++ 58, "GPIO58", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO58"), ++ MTK_FUNCTION(1, "SPI0_MI"), ++ MTK_FUNCTION(2, "SPI0_MO"), ++ MTK_FUNCTION(3, "SDA1_2"), ++ MTK_FUNCTION(4, "URXD3"), ++ MTK_FUNCTION(5, "PCM0_CLK") ++ ), ++ MTK_PIN( ++ 59, "GPIO59", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO59"), ++ MTK_FUNCTION(1, "SPI0_MO"), ++ MTK_FUNCTION(2, "SPI0_MI"), ++ MTK_FUNCTION(3, "PWM_C"), ++ MTK_FUNCTION(4, "URTS3"), ++ MTK_FUNCTION(5, "PCM0_DO") ++ ), ++ MTK_PIN( ++ 60, "GPIO60", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO60"), ++ MTK_FUNCTION(1, "SPI0_CS"), ++ MTK_FUNCTION(2, "SDA0_2"), ++ MTK_FUNCTION(3, "SCL1_2"), ++ MTK_FUNCTION(4, "UCTS3"), ++ MTK_FUNCTION(5, "PCM0_DI") ++ ), ++ MTK_PIN( ++ 61, "GPIO61", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO61"), ++ MTK_FUNCTION(1, "EINT0"), ++ MTK_FUNCTION(2, "IDDIG"), ++ MTK_FUNCTION(3, "SPI4_CLK_B"), ++ MTK_FUNCTION(4, "I2S0_LRCK"), ++ MTK_FUNCTION(5, "PCM0_SYNC"), ++ MTK_FUNCTION(7, "C2K_EINT0") ++ ), ++ MTK_PIN( ++ 62, "GPIO62", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO62"), ++ MTK_FUNCTION(1, "EINT1"), ++ MTK_FUNCTION(2, "USB_DRVVBUS"), ++ MTK_FUNCTION(3, "SPI4_MI_B"), ++ MTK_FUNCTION(4, "I2S0_BCK"), ++ MTK_FUNCTION(5, "PCM0_CLK"), ++ MTK_FUNCTION(7, "C2K_EINT1") ++ ), ++ MTK_PIN( ++ 63, "GPIO63", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO63"), ++ MTK_FUNCTION(1, "EINT2"), ++ MTK_FUNCTION(2, "IRTX_OUT"), ++ MTK_FUNCTION(3, "SPI4_MO_B"), ++ MTK_FUNCTION(4, "I2S0_MCK"), ++ MTK_FUNCTION(5, "PCM0_DI"), ++ MTK_FUNCTION(7, "C2K_DM_EINT0") ++ ), ++ MTK_PIN( ++ 64, "GPIO64", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO64"), ++ MTK_FUNCTION(1, "EINT3"), ++ MTK_FUNCTION(2, "CMFLASH"), ++ MTK_FUNCTION(3, "SPI4_CS_B"), ++ MTK_FUNCTION(4, "I2S0_DI"), ++ MTK_FUNCTION(5, "PCM0_DO"), ++ MTK_FUNCTION(7, "C2K_DM_EINT1") ++ ), ++ MTK_PIN( ++ 65, "GPIO65", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO65"), ++ MTK_FUNCTION(1, "EINT4"), ++ MTK_FUNCTION(2, "CLKM0"), ++ MTK_FUNCTION(3, "SPI5_CLK_B"), ++ MTK_FUNCTION(4, "I2S1_LRCK"), ++ MTK_FUNCTION(5, "PWM_A"), ++ MTK_FUNCTION(7, "C2K_DM_EINT2") ++ ), ++ MTK_PIN( ++ 66, "GPIO66", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO66"), ++ MTK_FUNCTION(1, "EINT5"), ++ MTK_FUNCTION(2, "CLKM1"), ++ MTK_FUNCTION(3, "SPI5_MI_B"), ++ MTK_FUNCTION(4, "I2S1_BCK"), ++ MTK_FUNCTION(5, "PWM_B"), ++ MTK_FUNCTION(7, "C2K_DM_EINT3") ++ ), ++ MTK_PIN( ++ 67, "GPIO67", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO67"), ++ MTK_FUNCTION(1, "EINT6"), ++ MTK_FUNCTION(2, "CLKM2"), ++ MTK_FUNCTION(3, "SPI5_MO_B"), ++ MTK_FUNCTION(4, "I2S1_MCK"), ++ MTK_FUNCTION(5, "PWM_C"), ++ MTK_FUNCTION(7, "DBG_MON_A0") ++ ), ++ MTK_PIN( ++ 68, "GPIO68", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO68"), ++ MTK_FUNCTION(1, "EINT7"), ++ MTK_FUNCTION(2, "CLKM3"), ++ MTK_FUNCTION(3, "SPI5_CS_B"), ++ MTK_FUNCTION(4, "I2S1_DO"), ++ MTK_FUNCTION(5, "PWM_D"), ++ MTK_FUNCTION(7, "DBG_MON_A1") ++ ), ++ MTK_PIN( ++ 69, "GPIO69", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO69"), ++ MTK_FUNCTION(1, "I2S0_LRCK"), ++ MTK_FUNCTION(2, "I2S3_LRCK"), ++ MTK_FUNCTION(3, "I2S1_LRCK"), ++ MTK_FUNCTION(4, "I2S2_LRCK"), ++ MTK_FUNCTION(7, "DBG_MON_A2") ++ ), ++ MTK_PIN( ++ 70, "GPIO70", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO70"), ++ MTK_FUNCTION(1, "I2S0_BCK"), ++ MTK_FUNCTION(2, "I2S3_BCK"), ++ MTK_FUNCTION(3, "I2S1_BCK"), ++ MTK_FUNCTION(4, "I2S2_BCK"), ++ MTK_FUNCTION(7, "DBG_MON_A3") ++ ), ++ MTK_PIN( ++ 71, "GPIO71", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO71"), ++ MTK_FUNCTION(1, "I2S0_MCK"), ++ MTK_FUNCTION(2, "I2S3_MCK"), ++ MTK_FUNCTION(3, "I2S1_MCK"), ++ MTK_FUNCTION(4, "I2S2_MCK"), ++ MTK_FUNCTION(7, "DBG_MON_A4") ++ ), ++ MTK_PIN( ++ 72, "GPIO72", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO72"), ++ MTK_FUNCTION(1, "I2S0_DI"), ++ MTK_FUNCTION(2, "I2S0_DI"), ++ MTK_FUNCTION(3, "I2S2_DI"), ++ MTK_FUNCTION(4, "I2S2_DI"), ++ MTK_FUNCTION(7, "DBG_MON_A5") ++ ), ++ MTK_PIN( ++ 73, "GPIO73", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO73"), ++ MTK_FUNCTION(1, "I2S3_DO"), ++ MTK_FUNCTION(2, "I2S3_DO"), ++ MTK_FUNCTION(3, "I2S1_DO"), ++ MTK_FUNCTION(4, "I2S1_DO"), ++ MTK_FUNCTION(7, "DBG_MON_A6") ++ ), ++ MTK_PIN( ++ 74, "GPIO74", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO74"), ++ MTK_FUNCTION(1, "SCL3_0"), ++ MTK_FUNCTION(7, "AUXIF_CLK1") ++ ), ++ MTK_PIN( ++ 75, "GPIO75", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO75"), ++ MTK_FUNCTION(1, "SDA3_0"), ++ MTK_FUNCTION(7, "AUXIF_ST1") ++ ), ++ MTK_PIN( ++ 76, "GPIO76", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO76"), ++ MTK_FUNCTION(1, "CONN_HRST_B"), ++ MTK_FUNCTION(7, "C2K_DM_EINT0") ++ ), ++ MTK_PIN( ++ 77, "GPIO77", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO77"), ++ MTK_FUNCTION(1, "CONN_TOP_CLK"), ++ MTK_FUNCTION(7, "C2K_DM_EINT1") ++ ), ++ MTK_PIN( ++ 78, "GPIO78", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO78"), ++ MTK_FUNCTION(1, "CONN_TOP_DATA"), ++ MTK_FUNCTION(7, "C2K_DM_EINT2") ++ ), ++ MTK_PIN( ++ 79, "GPIO79", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO79"), ++ MTK_FUNCTION(1, "CONN_WB_PTA"), ++ MTK_FUNCTION(7, "C2K_DM_EINT3") ++ ), ++ MTK_PIN( ++ 80, "GPIO80", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO80"), ++ MTK_FUNCTION(1, "CONN_WF_HB0"), ++ MTK_FUNCTION(7, "C2K_EINT0") ++ ), ++ MTK_PIN( ++ 81, "GPIO81", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO81"), ++ MTK_FUNCTION(1, "CONN_WF_HB1"), ++ MTK_FUNCTION(7, "C2K_EINT1") ++ ), ++ MTK_PIN( ++ 82, "GPIO82", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO82"), ++ MTK_FUNCTION(1, "CONN_WF_HB2"), ++ MTK_FUNCTION(7, "MD_CLKM0") ++ ), ++ MTK_PIN( ++ 83, "GPIO83", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO83"), ++ MTK_FUNCTION(1, "CONN_BT_CLK"), ++ MTK_FUNCTION(7, "MD_CLKM1") ++ ), ++ MTK_PIN( ++ 84, "GPIO84", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO84"), ++ MTK_FUNCTION(1, "CONN_BT_DATA") ++ ), ++ MTK_PIN( ++ 85, "GPIO85", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO85"), ++ MTK_FUNCTION(1, "EINT8"), ++ MTK_FUNCTION(2, "I2S1_LRCK"), ++ MTK_FUNCTION(3, "I2S2_LRCK"), ++ MTK_FUNCTION(4, "URXD1"), ++ MTK_FUNCTION(5, "MD_URXD0"), ++ MTK_FUNCTION(7, "DBG_MON_A7") ++ ), ++ MTK_PIN( ++ 86, "GPIO86", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO86"), ++ MTK_FUNCTION(1, "EINT9"), ++ MTK_FUNCTION(2, "I2S1_BCK"), ++ MTK_FUNCTION(3, "I2S2_BCK"), ++ MTK_FUNCTION(4, "UTXD1"), ++ MTK_FUNCTION(5, "MD_UTXD0"), ++ MTK_FUNCTION(7, "DBG_MON_A8") ++ ), ++ MTK_PIN( ++ 87, "GPIO87", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO87"), ++ MTK_FUNCTION(1, "EINT10"), ++ MTK_FUNCTION(2, "I2S1_MCK"), ++ MTK_FUNCTION(3, "I2S2_MCK"), ++ MTK_FUNCTION(4, "URTS1"), ++ MTK_FUNCTION(5, "MD_URXD1"), ++ MTK_FUNCTION(7, "DBG_MON_A9") ++ ), ++ MTK_PIN( ++ 88, "GPIO88", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO88"), ++ MTK_FUNCTION(1, "EINT11"), ++ MTK_FUNCTION(2, "I2S1_DO"), ++ MTK_FUNCTION(3, "I2S2_DI"), ++ MTK_FUNCTION(4, "UCTS1"), ++ MTK_FUNCTION(5, "MD_UTXD1"), ++ MTK_FUNCTION(7, "DBG_MON_A10") ++ ), ++ MTK_PIN( ++ 89, "GPIO89", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO89"), ++ MTK_FUNCTION(1, "EINT12"), ++ MTK_FUNCTION(2, "IRTX_OUT"), ++ MTK_FUNCTION(3, "CLKM0"), ++ MTK_FUNCTION(4, "PCM1_SYNC"), ++ MTK_FUNCTION(5, "URTS0"), ++ MTK_FUNCTION(7, "DBG_MON_A11") ++ ), ++ MTK_PIN( ++ 90, "GPIO90", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO90"), ++ MTK_FUNCTION(1, "EINT13"), ++ MTK_FUNCTION(2, "CMFLASH"), ++ MTK_FUNCTION(3, "CLKM1"), ++ MTK_FUNCTION(4, "PCM1_CLK"), ++ MTK_FUNCTION(5, "UCTS0"), ++ MTK_FUNCTION(7, "C2K_DM_EINT0") ++ ), ++ MTK_PIN( ++ 91, "GPIO91", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO91"), ++ MTK_FUNCTION(1, "EINT14"), ++ MTK_FUNCTION(2, "PWM_A"), ++ MTK_FUNCTION(3, "CLKM2"), ++ MTK_FUNCTION(4, "PCM1_DI"), ++ MTK_FUNCTION(5, "SDA0_3"), ++ MTK_FUNCTION(7, "C2K_DM_EINT1") ++ ), ++ MTK_PIN( ++ 92, "GPIO92", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO92"), ++ MTK_FUNCTION(1, "EINT15"), ++ MTK_FUNCTION(2, "PWM_B"), ++ MTK_FUNCTION(3, "CLKM3"), ++ MTK_FUNCTION(4, "PCM1_DO0"), ++ MTK_FUNCTION(5, "SCL0_3") ++ ), ++ MTK_PIN( ++ 93, "GPIO93", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO93"), ++ MTK_FUNCTION(1, "EINT16"), ++ MTK_FUNCTION(2, "IDDIG"), ++ MTK_FUNCTION(3, "CLKM4"), ++ MTK_FUNCTION(4, "PCM1_DO1"), ++ MTK_FUNCTION(5, "MD_INT2"), ++ MTK_FUNCTION(7, "DROP_ZONE") ++ ), ++ MTK_PIN( ++ 94, "GPIO94", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO94"), ++ MTK_FUNCTION(1, "USB_DRVVBUS"), ++ MTK_FUNCTION(2, "PWM_C"), ++ MTK_FUNCTION(3, "CLKM5") ++ ), ++ MTK_PIN( ++ 95, "GPIO95", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO95"), ++ MTK_FUNCTION(1, "SDA2_0"), ++ MTK_FUNCTION(7, "AUXIF_ST0") ++ ), ++ MTK_PIN( ++ 96, "GPIO96", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO96"), ++ MTK_FUNCTION(1, "SCL2_0"), ++ MTK_FUNCTION(7, "AUXIF_CLK0") ++ ), ++ MTK_PIN( ++ 97, "GPIO97", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO97"), ++ MTK_FUNCTION(1, "URXD0"), ++ MTK_FUNCTION(2, "UTXD0"), ++ MTK_FUNCTION(3, "MD_URXD0"), ++ MTK_FUNCTION(4, "MD_URXD1"), ++ MTK_FUNCTION(5, "MD_URXD2"), ++ MTK_FUNCTION(6, "C2K_URXD0"), ++ MTK_FUNCTION(7, "C2K_URXD1") ++ ), ++ MTK_PIN( ++ 98, "GPIO98", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO98"), ++ MTK_FUNCTION(1, "UTXD0"), ++ MTK_FUNCTION(2, "URXD0"), ++ MTK_FUNCTION(3, "MD_UTXD0"), ++ MTK_FUNCTION(4, "MD_UTXD1"), ++ MTK_FUNCTION(5, "MD_UTXD2"), ++ MTK_FUNCTION(6, "C2K_UTXD0"), ++ MTK_FUNCTION(7, "C2K_UTXD1") ++ ), ++ MTK_PIN( ++ 99, "GPIO99", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO99"), ++ MTK_FUNCTION(1, "RTC32K_CK") ++ ), ++ MTK_PIN( ++ 100, "GPIO100", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO100"), ++ MTK_FUNCTION(1, "SRCLKENAI0") ++ ), ++ MTK_PIN( ++ 101, "GPIO101", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO101"), ++ MTK_FUNCTION(1, "SRCLKENAI1") ++ ), ++ MTK_PIN( ++ 102, "GPIO102", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO102"), ++ MTK_FUNCTION(1, "SRCLKENA0") ++ ), ++ MTK_PIN( ++ 103, "GPIO103", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO103"), ++ MTK_FUNCTION(1, "SRCLKENA1") ++ ), ++ MTK_PIN( ++ 104, "GPIO104", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO104"), ++ MTK_FUNCTION(1, "SYSRSTB") ++ ), ++ MTK_PIN( ++ 105, "GPIO105", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO105"), ++ MTK_FUNCTION(1, "WATCHDOG") ++ ), ++ MTK_PIN( ++ 106, "GPIO106", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO106"), ++ MTK_FUNCTION(1, "KPROW0"), ++ MTK_FUNCTION(2, "CMFLASH"), ++ MTK_FUNCTION(3, "CLKM4"), ++ MTK_FUNCTION(4, "TP_GPIO0_AO"), ++ MTK_FUNCTION(5, "IRTX_OUT") ++ ), ++ MTK_PIN( ++ 107, "GPIO107", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO107"), ++ MTK_FUNCTION(1, "KPROW1"), ++ MTK_FUNCTION(2, "IDDIG"), ++ MTK_FUNCTION(3, "CLKM5"), ++ MTK_FUNCTION(4, "TP_GPIO1_AO"), ++ MTK_FUNCTION(5, "I2S1_BCK"), ++ MTK_FUNCTION(7, "DAP_SIB1_SWD") ++ ), ++ MTK_PIN( ++ 108, "GPIO108", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO108"), ++ MTK_FUNCTION(1, "KPROW2"), ++ MTK_FUNCTION(2, "USB_DRVVBUS"), ++ MTK_FUNCTION(3, "PWM_A"), ++ MTK_FUNCTION(4, "CMFLASH"), ++ MTK_FUNCTION(5, "I2S1_LRCK"), ++ MTK_FUNCTION(7, "DAP_SIB1_SWCK") ++ ), ++ MTK_PIN( ++ 109, "GPIO109", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO109"), ++ MTK_FUNCTION(1, "KPCOL0") ++ ), ++ MTK_PIN( ++ 110, "GPIO110", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO110"), ++ MTK_FUNCTION(1, "KPCOL1"), ++ MTK_FUNCTION(2, "SDA1_3"), ++ MTK_FUNCTION(3, "PWM_B"), ++ MTK_FUNCTION(4, "CLKM0"), ++ MTK_FUNCTION(5, "I2S1_DO"), ++ MTK_FUNCTION(7, "C2K_DM_EINT3") ++ ), ++ MTK_PIN( ++ 111, "GPIO111", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO111"), ++ MTK_FUNCTION(1, "KPCOL2"), ++ MTK_FUNCTION(2, "SCL1_3"), ++ MTK_FUNCTION(3, "PWM_C"), ++ MTK_FUNCTION(4, "DISP_PWM"), ++ MTK_FUNCTION(5, "I2S1_MCK"), ++ MTK_FUNCTION(7, "C2K_DM_EINT2") ++ ), ++ MTK_PIN( ++ 112, "GPIO112", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO112"), ++ MTK_FUNCTION(1, "MD_INT1_C2K_UIM1_HOT_PLUG_IN"), ++ MTK_FUNCTION(7, "C2K_DM_EINT1") ++ ), ++ MTK_PIN( ++ 113, "GPIO113", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO113"), ++ MTK_FUNCTION(1, "MD_INT0_C2K_UIM0_HOT_PLUG_IN"), ++ MTK_FUNCTION(7, "C2K_DM_EINT0") ++ ), ++ MTK_PIN( ++ 114, "GPIO114", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO114"), ++ MTK_FUNCTION(1, "MSDC0_DAT0") ++ ), ++ MTK_PIN( ++ 115, "GPIO115", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO115"), ++ MTK_FUNCTION(1, "MSDC0_DAT1") ++ ), ++ MTK_PIN( ++ 116, "GPIO116", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO116"), ++ MTK_FUNCTION(1, "MSDC0_DAT2") ++ ), ++ MTK_PIN( ++ 117, "GPIO117", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO117"), ++ MTK_FUNCTION(1, "MSDC0_DAT3") ++ ), ++ MTK_PIN( ++ 118, "GPIO118", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO118"), ++ MTK_FUNCTION(1, "MSDC0_DAT4") ++ ), ++ MTK_PIN( ++ 119, "GPIO119", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO119"), ++ MTK_FUNCTION(1, "MSDC0_DAT5") ++ ), ++ MTK_PIN( ++ 120, "GPIO120", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO120"), ++ MTK_FUNCTION(1, "MSDC0_DAT6") ++ ), ++ MTK_PIN( ++ 121, "GPIO121", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO121"), ++ MTK_FUNCTION(1, "MSDC0_DAT7") ++ ), ++ MTK_PIN( ++ 122, "GPIO122", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO122"), ++ MTK_FUNCTION(1, "MSDC0_CMD") ++ ), ++ MTK_PIN( ++ 123, "GPIO123", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO123"), ++ MTK_FUNCTION(1, "MSDC0_CLK") ++ ), ++ MTK_PIN( ++ 124, "GPIO124", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO124"), ++ MTK_FUNCTION(1, "MSDC0_DSL") ++ ), ++ MTK_PIN( ++ 125, "GPIO125", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO125"), ++ MTK_FUNCTION(1, "MSDC0_RSTB") ++ ), ++ MTK_PIN( ++ 126, "GPIO126", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO126"), ++ MTK_FUNCTION(1, "MD1_SIM1_SCLK"), ++ MTK_FUNCTION(2, "MD1_SIM2_SCLK"), ++ MTK_FUNCTION(3, "C2K_UIM0_CLK"), ++ MTK_FUNCTION(4, "C2K_UIM1_CLK") ++ ), ++ MTK_PIN( ++ 127, "GPIO127", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO127"), ++ MTK_FUNCTION(1, "MD1_SIM1_SRST"), ++ MTK_FUNCTION(2, "MD1_SIM2_SRST"), ++ MTK_FUNCTION(3, "C2K_UIM0_RST"), ++ MTK_FUNCTION(4, "C2K_UIM1_RST") ++ ), ++ MTK_PIN( ++ 128, "GPIO128", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO128"), ++ MTK_FUNCTION(1, "MD1_SIM1_SIO"), ++ MTK_FUNCTION(2, "MD1_SIM2_SIO"), ++ MTK_FUNCTION(3, "C2K_UIM0_IO"), ++ MTK_FUNCTION(4, "C2K_UIM1_IO") ++ ), ++ MTK_PIN( ++ 129, "GPIO129", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO129"), ++ MTK_FUNCTION(1, "MSDC1_CMD"), ++ MTK_FUNCTION(2, "CONN_DSP_JMS"), ++ MTK_FUNCTION(3, "LTE_JTAG_TMS"), ++ MTK_FUNCTION(4, "UDI_TMS"), ++ MTK_FUNCTION(5, "C2K_TMS") ++ ), ++ MTK_PIN( ++ 130, "GPIO130", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO130"), ++ MTK_FUNCTION(1, "MSDC1_DAT0"), ++ MTK_FUNCTION(2, "CONN_DSP_JDI"), ++ MTK_FUNCTION(3, "LTE_JTAG_TDI"), ++ MTK_FUNCTION(4, "UDI_TDI"), ++ MTK_FUNCTION(5, "C2K_TDI") ++ ), ++ MTK_PIN( ++ 131, "GPIO131", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO131"), ++ MTK_FUNCTION(1, "MSDC1_DAT1"), ++ MTK_FUNCTION(2, "CONN_DSP_JDO"), ++ MTK_FUNCTION(3, "LTE_JTAG_TDO"), ++ MTK_FUNCTION(4, "UDI_TDO"), ++ MTK_FUNCTION(5, "C2K_TDO") ++ ), ++ MTK_PIN( ++ 132, "GPIO132", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO132"), ++ MTK_FUNCTION(1, "MSDC1_DAT2"), ++ MTK_FUNCTION(5, "C2K_RTCK") ++ ), ++ MTK_PIN( ++ 133, "GPIO133", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO133"), ++ MTK_FUNCTION(1, "MSDC1_DAT3"), ++ MTK_FUNCTION(2, "CONN_DSP_JINTP"), ++ MTK_FUNCTION(3, "LTE_JTAG_TRSTN"), ++ MTK_FUNCTION(4, "UDI_NTRST"), ++ MTK_FUNCTION(5, "C2K_NTRST") ++ ), ++ MTK_PIN( ++ 134, "GPIO134", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO134"), ++ MTK_FUNCTION(1, "MSDC1_CLK"), ++ MTK_FUNCTION(2, "CONN_DSP_JCK"), ++ MTK_FUNCTION(3, "LTE_JTAG_TCK"), ++ MTK_FUNCTION(4, "UDI_TCK_XI"), ++ MTK_FUNCTION(5, "C2K_TCK") ++ ), ++ MTK_PIN( ++ 135, "GPIO135", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO135"), ++ MTK_FUNCTION(1, "TDM_LRCK"), ++ MTK_FUNCTION(2, "I2S0_LRCK"), ++ MTK_FUNCTION(3, "CLKM0"), ++ MTK_FUNCTION(4, "PCM1_SYNC"), ++ MTK_FUNCTION(5, "PWM_A"), ++ MTK_FUNCTION(7, "DBG_MON_A12") ++ ), ++ MTK_PIN( ++ 136, "GPIO136", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO136"), ++ MTK_FUNCTION(1, "TDM_BCK"), ++ MTK_FUNCTION(2, "I2S0_BCK"), ++ MTK_FUNCTION(3, "CLKM1"), ++ MTK_FUNCTION(4, "PCM1_CLK"), ++ MTK_FUNCTION(5, "PWM_B"), ++ MTK_FUNCTION(7, "DBG_MON_A13") ++ ), ++ MTK_PIN( ++ 137, "GPIO137", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO137"), ++ MTK_FUNCTION(1, "TDM_MCK"), ++ MTK_FUNCTION(2, "I2S0_MCK"), ++ MTK_FUNCTION(3, "CLKM2"), ++ MTK_FUNCTION(4, "PCM1_DI"), ++ MTK_FUNCTION(5, "IRTX_OUT"), ++ MTK_FUNCTION(7, "DBG_MON_A14") ++ ), ++ MTK_PIN( ++ 138, "GPIO138", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO138"), ++ MTK_FUNCTION(1, "TDM_DATA0"), ++ MTK_FUNCTION(2, "I2S0_DI"), ++ MTK_FUNCTION(3, "CLKM3"), ++ MTK_FUNCTION(4, "PCM1_DO0"), ++ MTK_FUNCTION(5, "PWM_C"), ++ MTK_FUNCTION(6, "SDA3_1"), ++ MTK_FUNCTION(7, "DBG_MON_A15") ++ ), ++ MTK_PIN( ++ 139, "GPIO139", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO139"), ++ MTK_FUNCTION(1, "TDM_DATA1"), ++ MTK_FUNCTION(2, "I2S3_DO"), ++ MTK_FUNCTION(3, "CLKM4"), ++ MTK_FUNCTION(4, "PCM1_DO1"), ++ MTK_FUNCTION(5, "ANT_SEL2"), ++ MTK_FUNCTION(6, "SCL3_1"), ++ MTK_FUNCTION(7, "DBG_MON_A16") ++ ), ++ MTK_PIN( ++ 140, "GPIO140", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO140"), ++ MTK_FUNCTION(1, "TDM_DATA2"), ++ MTK_FUNCTION(2, "DISP_PWM"), ++ MTK_FUNCTION(3, "CLKM5"), ++ MTK_FUNCTION(4, "SDA1_4"), ++ MTK_FUNCTION(5, "ANT_SEL1"), ++ MTK_FUNCTION(6, "URXD3"), ++ MTK_FUNCTION(7, "DBG_MON_A17") ++ ), ++ MTK_PIN( ++ 141, "GPIO141", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO141"), ++ MTK_FUNCTION(1, "TDM_DATA3"), ++ MTK_FUNCTION(2, "CMFLASH"), ++ MTK_FUNCTION(3, "IRTX_OUT"), ++ MTK_FUNCTION(4, "SCL1_4"), ++ MTK_FUNCTION(5, "ANT_SEL0"), ++ MTK_FUNCTION(6, "UTXD3"), ++ MTK_FUNCTION(7, "DBG_MON_A18") ++ ), ++ MTK_PIN( ++ 142, "GPIO142", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO142"), ++ MTK_FUNCTION(1, "PWRAP_SPI0_MI"), ++ MTK_FUNCTION(2, "PWRAP_SPI0_MO") ++ ), ++ MTK_PIN( ++ 143, "GPIO143", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO143"), ++ MTK_FUNCTION(1, "PWRAP_SPI0_MO"), ++ MTK_FUNCTION(2, "PWRAP_SPI0_MI") ++ ), ++ MTK_PIN( ++ 144, "GPIO144", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO144"), ++ MTK_FUNCTION(1, "PWRAP_SPI0_CK") ++ ), ++ MTK_PIN( ++ 145, "GPIO145", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO145"), ++ MTK_FUNCTION(1, "PWRAP_SPI0_CSN") ++ ), ++ MTK_PIN( ++ 146, "GPIO146", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO146"), ++ MTK_FUNCTION(1, "AUD_CLK_MOSI") ++ ), ++ MTK_PIN( ++ 147, "GPIO147", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO147"), ++ MTK_FUNCTION(1, "AUD_DAT_MISO"), ++ MTK_FUNCTION(2, "AUD_DAT_MOSI"), ++ MTK_FUNCTION(3, "VOW_DAT_MISO") ++ ), ++ MTK_PIN( ++ 148, "GPIO148", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO148"), ++ MTK_FUNCTION(1, "AUD_DAT_MOSI"), ++ MTK_FUNCTION(2, "AUD_DAT_MISO") ++ ), ++ MTK_PIN( ++ 149, "GPIO149", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO149"), ++ MTK_FUNCTION(1, "VOW_CLK_MISO") ++ ), ++ MTK_PIN( ++ 150, "GPIO150", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO150"), ++ MTK_FUNCTION(1, "ANC_DAT_MOSI") ++ ), ++ MTK_PIN( ++ 151, "GPIO151", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO151"), ++ MTK_FUNCTION(1, "SCL6_0") ++ ), ++ MTK_PIN( ++ 152, "GPIO152", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO152"), ++ MTK_FUNCTION(1, "SDA6_0") ++ ), ++ MTK_PIN( ++ 153, "GPIO153", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO153"), ++ MTK_FUNCTION(1, "SCL7_0") ++ ), ++ MTK_PIN( ++ 154, "GPIO154", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO154"), ++ MTK_FUNCTION(1, "SDA7_0") ++ ), ++ MTK_PIN( ++ 155, "GPIO155", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO155"), ++ MTK_FUNCTION(1, "MD1_SIM2_SCLK"), ++ MTK_FUNCTION(2, "MD1_SIM1_SCLK"), ++ MTK_FUNCTION(3, "C2K_UIM0_CLK"), ++ MTK_FUNCTION(4, "C2K_UIM1_CLK") ++ ), ++ MTK_PIN( ++ 156, "GPIO156", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO156"), ++ MTK_FUNCTION(1, "MD1_SIM2_SRST"), ++ MTK_FUNCTION(2, "MD1_SIM1_SRST"), ++ MTK_FUNCTION(3, "C2K_UIM0_RST"), ++ MTK_FUNCTION(4, "C2K_UIM1_RST") ++ ), ++ MTK_PIN( ++ 157, "GPIO157", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO157"), ++ MTK_FUNCTION(1, "MD1_SIM2_SIO"), ++ MTK_FUNCTION(2, "MD1_SIM1_SIO"), ++ MTK_FUNCTION(3, "C2K_UIM0_IO"), ++ MTK_FUNCTION(4, "C2K_UIM1_IO") ++ ), ++ MTK_PIN( ++ 158, "GPIO158", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO158"), ++ MTK_FUNCTION(1, "MIPI_TDP0") ++ ), ++ MTK_PIN( ++ 159, "GPIO159", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO159"), ++ MTK_FUNCTION(1, "MIPI_TDN0") ++ ), ++ MTK_PIN( ++ 160, "GPIO160", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO160"), ++ MTK_FUNCTION(1, "MIPI_TDP1") ++ ), ++ MTK_PIN( ++ 161, "GPIO161", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO161"), ++ MTK_FUNCTION(1, "MIPI_TDN1") ++ ), ++ MTK_PIN( ++ 162, "GPIO162", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO162"), ++ MTK_FUNCTION(1, "MIPI_TCP") ++ ), ++ MTK_PIN( ++ 163, "GPIO163", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO163"), ++ MTK_FUNCTION(1, "MIPI_TCN") ++ ), ++ MTK_PIN( ++ 164, "GPIO164", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO164"), ++ MTK_FUNCTION(1, "MIPI_TDP2") ++ ), ++ MTK_PIN( ++ 165, "GPIO165", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO165"), ++ MTK_FUNCTION(1, "MIPI_TDN2") ++ ), ++ MTK_PIN( ++ 166, "GPIO166", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO166"), ++ MTK_FUNCTION(1, "MIPI_TDP3") ++ ), ++ MTK_PIN( ++ 167, "GPIO167", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO167"), ++ MTK_FUNCTION(1, "MIPI_TDN3") ++ ), ++ MTK_PIN( ++ 168, "GPIO168", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO168"), ++ MTK_FUNCTION(1, "MIPI_TDP0_A") ++ ), ++ MTK_PIN( ++ 169, "GPIO169", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO169"), ++ MTK_FUNCTION(1, "MIPI_TDN0_A") ++ ), ++ MTK_PIN( ++ 170, "GPIO170", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO170"), ++ MTK_FUNCTION(1, "MIPI_TDP1_A") ++ ), ++ MTK_PIN( ++ 171, "GPIO171", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO171"), ++ MTK_FUNCTION(1, "MIPI_TDN1_A") ++ ), ++ MTK_PIN( ++ 172, "GPIO172", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO172"), ++ MTK_FUNCTION(1, "MIPI_TCP_A") ++ ), ++ MTK_PIN( ++ 173, "GPIO173", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO173"), ++ MTK_FUNCTION(1, "MIPI_TCN_A") ++ ), ++ MTK_PIN( ++ 174, "GPIO174", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO174"), ++ MTK_FUNCTION(1, "MIPI_TDP2_A") ++ ), ++ MTK_PIN( ++ 175, "GPIO175", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO175"), ++ MTK_FUNCTION(1, "MIPI_TDN2_A") ++ ), ++ MTK_PIN( ++ 176, "GPIO176", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO176"), ++ MTK_FUNCTION(1, "MIPI_TDP3_A") ++ ), ++ MTK_PIN( ++ 177, "GPIO177", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO177"), ++ MTK_FUNCTION(1, "MIPI_TDN3_A") ++ ), ++ MTK_PIN( ++ 178, "GPIO178", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO178"), ++ MTK_FUNCTION(1, "DISP_PWM"), ++ MTK_FUNCTION(2, "PWM_D"), ++ MTK_FUNCTION(3, "CLKM5"), ++ MTK_FUNCTION(7, "DBG_MON_A19") ++ ), ++ MTK_PIN( ++ 179, "GPIO179", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO179"), ++ MTK_FUNCTION(1, "DSI_TE0"), ++ MTK_FUNCTION(7, "DBG_MON_A20") ++ ), ++ MTK_PIN( ++ 180, "GPIO180", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO180"), ++ MTK_FUNCTION(1, "LCM_RST"), ++ MTK_FUNCTION(2, "DSI_TE1"), ++ MTK_FUNCTION(7, "DBG_MON_A21") ++ ), ++ MTK_PIN( ++ 181, "GPIO181", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO181"), ++ MTK_FUNCTION(1, "IDDIG"), ++ MTK_FUNCTION(2, "DSI_TE1"), ++ MTK_FUNCTION(7, "DBG_MON_A22") ++ ), ++ MTK_PIN( ++ 182, "GPIO182", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO182"), ++ MTK_FUNCTION(1, "TESTMODE") ++ ), ++ MTK_PIN( ++ 183, "GPIO183", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO183"), ++ MTK_FUNCTION(1, "RFIC0_BSI_CK"), ++ MTK_FUNCTION(2, "SPM_BSI_CK"), ++ MTK_FUNCTION(7, "DBG_MON_B27") ++ ), ++ MTK_PIN( ++ 184, "GPIO184", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO184"), ++ MTK_FUNCTION(1, "RFIC0_BSI_EN"), ++ MTK_FUNCTION(2, "SPM_BSI_EN"), ++ MTK_FUNCTION(7, "DBG_MON_B28") ++ ), ++ MTK_PIN( ++ 185, "GPIO185", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO185"), ++ MTK_FUNCTION(1, "RFIC0_BSI_D0"), ++ MTK_FUNCTION(2, "SPM_BSI_D0"), ++ MTK_FUNCTION(7, "DBG_MON_B29") ++ ), ++ MTK_PIN( ++ 186, "GPIO186", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO186"), ++ MTK_FUNCTION(1, "RFIC0_BSI_D1"), ++ MTK_FUNCTION(2, "SPM_BSI_D1"), ++ MTK_FUNCTION(7, "DBG_MON_B30") ++ ), ++ MTK_PIN( ++ 187, "GPIO187", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO187"), ++ MTK_FUNCTION(1, "RFIC0_BSI_D2"), ++ MTK_FUNCTION(2, "SPM_BSI_D2"), ++ MTK_FUNCTION(7, "DBG_MON_B31") ++ ), ++ MTK_PIN( ++ 188, "GPIO188", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO188"), ++ MTK_FUNCTION(1, "MIPI0_SCLK"), ++ MTK_FUNCTION(7, "DBG_MON_B32") ++ ), ++ MTK_PIN( ++ 189, "GPIO189", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO189"), ++ MTK_FUNCTION(1, "MIPI0_SDATA") ++ ), ++ MTK_PIN( ++ 190, "GPIO190", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO190"), ++ MTK_FUNCTION(1, "MIPI1_SCLK") ++ ), ++ MTK_PIN( ++ 191, "GPIO191", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO191"), ++ MTK_FUNCTION(1, "MIPI1_SDATA") ++ ), ++ MTK_PIN( ++ 192, "GPIO192", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO192"), ++ MTK_FUNCTION(1, "BPI_BUS4") ++ ), ++ MTK_PIN( ++ 193, "GPIO193", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO193"), ++ MTK_FUNCTION(1, "BPI_BUS5"), ++ MTK_FUNCTION(7, "DBG_MON_B0") ++ ), ++ MTK_PIN( ++ 194, "GPIO194", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO194"), ++ MTK_FUNCTION(1, "BPI_BUS6"), ++ MTK_FUNCTION(7, "DBG_MON_B1") ++ ), ++ MTK_PIN( ++ 195, "GPIO195", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO195"), ++ MTK_FUNCTION(1, "BPI_BUS7"), ++ MTK_FUNCTION(7, "DBG_MON_B2") ++ ), ++ MTK_PIN( ++ 196, "GPIO196", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO196"), ++ MTK_FUNCTION(1, "BPI_BUS8"), ++ MTK_FUNCTION(7, "DBG_MON_B3") ++ ), ++ MTK_PIN( ++ 197, "GPIO197", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO197"), ++ MTK_FUNCTION(1, "BPI_BUS9"), ++ MTK_FUNCTION(7, "DBG_MON_B4") ++ ), ++ MTK_PIN( ++ 198, "GPIO198", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO198"), ++ MTK_FUNCTION(1, "BPI_BUS10"), ++ MTK_FUNCTION(7, "DBG_MON_B5") ++ ), ++ MTK_PIN( ++ 199, "GPIO199", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO199"), ++ MTK_FUNCTION(1, "BPI_BUS11"), ++ MTK_FUNCTION(7, "DBG_MON_B6") ++ ), ++ MTK_PIN( ++ 200, "GPIO200", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO200"), ++ MTK_FUNCTION(1, "BPI_BUS12"), ++ MTK_FUNCTION(7, "DBG_MON_B7") ++ ), ++ MTK_PIN( ++ 201, "GPIO201", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO201"), ++ MTK_FUNCTION(1, "BPI_BUS13"), ++ MTK_FUNCTION(7, "DBG_MON_B8") ++ ), ++ MTK_PIN( ++ 202, "GPIO202", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO202"), ++ MTK_FUNCTION(1, "BPI_BUS14"), ++ MTK_FUNCTION(7, "DBG_MON_B9") ++ ), ++ MTK_PIN( ++ 203, "GPIO203", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO203"), ++ MTK_FUNCTION(1, "BPI_BUS15"), ++ MTK_FUNCTION(7, "DBG_MON_B10") ++ ), ++ MTK_PIN( ++ 204, "GPIO204", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO204"), ++ MTK_FUNCTION(1, "BPI_BUS16"), ++ MTK_FUNCTION(2, "PA_VM0"), ++ MTK_FUNCTION(7, "DBG_MON_B11") ++ ), ++ MTK_PIN( ++ 205, "GPIO205", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO205"), ++ MTK_FUNCTION(1, "BPI_BUS17"), ++ MTK_FUNCTION(2, "PA_VM1"), ++ MTK_FUNCTION(7, "DBG_MON_B12") ++ ), ++ MTK_PIN( ++ 206, "GPIO206", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO206"), ++ MTK_FUNCTION(1, "BPI_BUS18"), ++ MTK_FUNCTION(2, "TX_SWAP0"), ++ MTK_FUNCTION(7, "DBG_MON_B13") ++ ), ++ MTK_PIN( ++ 207, "GPIO207", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO207"), ++ MTK_FUNCTION(1, "BPI_BUS19"), ++ MTK_FUNCTION(2, "TX_SWAP1"), ++ MTK_FUNCTION(7, "DBG_MON_B14") ++ ), ++ MTK_PIN( ++ 208, "GPIO208", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO208"), ++ MTK_FUNCTION(1, "BPI_BUS20"), ++ MTK_FUNCTION(2, "TX_SWAP2"), ++ MTK_FUNCTION(7, "DBG_MON_B15") ++ ), ++ MTK_PIN( ++ 209, "GPIO209", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO209"), ++ MTK_FUNCTION(1, "BPI_BUS21"), ++ MTK_FUNCTION(2, "TX_SWAP3"), ++ MTK_FUNCTION(7, "DBG_MON_B16") ++ ), ++ MTK_PIN( ++ 210, "GPIO210", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO210"), ++ MTK_FUNCTION(1, "BPI_BUS22"), ++ MTK_FUNCTION(2, "DET_BPI0"), ++ MTK_FUNCTION(7, "DBG_MON_B17") ++ ), ++ MTK_PIN( ++ 211, "GPIO211", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO211"), ++ MTK_FUNCTION(1, "BPI_BUS23"), ++ MTK_FUNCTION(2, "DET_BPI1"), ++ MTK_FUNCTION(7, "DBG_MON_B18") ++ ), ++ MTK_PIN( ++ 212, "GPIO212", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO212"), ++ MTK_FUNCTION(1, "BPI_BUS0"), ++ MTK_FUNCTION(7, "DBG_MON_B19") ++ ), ++ MTK_PIN( ++ 213, "GPIO213", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO213"), ++ MTK_FUNCTION(1, "BPI_BUS1"), ++ MTK_FUNCTION(7, "DBG_MON_B20") ++ ), ++ MTK_PIN( ++ 214, "GPIO214", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO214"), ++ MTK_FUNCTION(1, "BPI_BUS2"), ++ MTK_FUNCTION(7, "DBG_MON_B21") ++ ), ++ MTK_PIN( ++ 215, "GPIO215", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO215"), ++ MTK_FUNCTION(1, "BPI_BUS3"), ++ MTK_FUNCTION(7, "DBG_MON_B22") ++ ), ++ MTK_PIN( ++ 216, "GPIO216", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO216"), ++ MTK_FUNCTION(1, "MIPI2_SCLK"), ++ MTK_FUNCTION(7, "DBG_MON_B23") ++ ), ++ MTK_PIN( ++ 217, "GPIO217", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO217"), ++ MTK_FUNCTION(1, "MIPI2_SDATA"), ++ MTK_FUNCTION(7, "DBG_MON_B24") ++ ), ++ MTK_PIN( ++ 218, "GPIO218", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO218"), ++ MTK_FUNCTION(1, "MIPI3_SCLK"), ++ MTK_FUNCTION(7, "DBG_MON_B25") ++ ), ++ MTK_PIN( ++ 219, "GPIO219", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO219"), ++ MTK_FUNCTION(1, "MIPI3_SDATA"), ++ MTK_FUNCTION(7, "DBG_MON_B26") ++ ), ++ MTK_PIN( ++ 220, "GPIO220", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO220"), ++ MTK_FUNCTION(1, "CONN_WF_IP") ++ ), ++ MTK_PIN( ++ 221, "GPIO221", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO221"), ++ MTK_FUNCTION(1, "CONN_WF_IN") ++ ), ++ MTK_PIN( ++ 222, "GPIO222", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO222"), ++ MTK_FUNCTION(1, "CONN_WF_QP") ++ ), ++ MTK_PIN( ++ 223, "GPIO223", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO223"), ++ MTK_FUNCTION(1, "CONN_WF_QN") ++ ), ++ MTK_PIN( ++ 224, "GPIO224", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO224"), ++ MTK_FUNCTION(1, "CONN_BT_IP") ++ ), ++ MTK_PIN( ++ 225, "GPIO225", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO225"), ++ MTK_FUNCTION(1, "CONN_BT_IN") ++ ), ++ MTK_PIN( ++ 226, "GPIO226", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO226"), ++ MTK_FUNCTION(1, "CONN_BT_QP") ++ ), ++ MTK_PIN( ++ 227, "GPIO227", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO227"), ++ MTK_FUNCTION(1, "CONN_BT_QN") ++ ), ++ MTK_PIN( ++ 228, "GPIO228", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO228"), ++ MTK_FUNCTION(1, "CONN_GPS_IP") ++ ), ++ MTK_PIN( ++ 229, "GPIO229", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO229"), ++ MTK_FUNCTION(1, "CONN_GPS_IN") ++ ), ++ MTK_PIN( ++ 230, "GPIO230", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO230"), ++ MTK_FUNCTION(1, "CONN_GPS_QP") ++ ), ++ MTK_PIN( ++ 231, "GPIO231", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO231"), ++ MTK_FUNCTION(1, "CONN_GPS_QN") ++ ), ++ MTK_PIN( ++ 232, "GPIO232", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO232"), ++ MTK_FUNCTION(1, "URXD1"), ++ MTK_FUNCTION(2, "UTXD1"), ++ MTK_FUNCTION(3, "MD_URXD0"), ++ MTK_FUNCTION(4, "MD_URXD1"), ++ MTK_FUNCTION(5, "MD_URXD2"), ++ MTK_FUNCTION(6, "C2K_URXD0"), ++ MTK_FUNCTION(7, "C2K_URXD1") ++ ), ++ MTK_PIN( ++ 233, "GPIO233", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO233"), ++ MTK_FUNCTION(1, "UTXD1"), ++ MTK_FUNCTION(2, "URXD1"), ++ MTK_FUNCTION(3, "MD_UTXD0"), ++ MTK_FUNCTION(4, "MD_UTXD1"), ++ MTK_FUNCTION(5, "MD_UTXD2"), ++ MTK_FUNCTION(6, "C2K_UTXD0"), ++ MTK_FUNCTION(7, "C2K_UTXD1") ++ ), ++ MTK_PIN( ++ 234, "GPIO234", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO234"), ++ MTK_FUNCTION(1, "SPI1_CLK_B"), ++ MTK_FUNCTION(2, "TP_UTXD1_AO"), ++ MTK_FUNCTION(3, "SCL4_1"), ++ MTK_FUNCTION(4, "UTXD0"), ++ MTK_FUNCTION(6, "PWM_A"), ++ MTK_FUNCTION(7, "DBG_MON_A23") ++ ), ++ MTK_PIN( ++ 235, "GPIO235", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO235"), ++ MTK_FUNCTION(1, "SPI1_MI_B"), ++ MTK_FUNCTION(2, "SPI1_MO_B"), ++ MTK_FUNCTION(3, "SDA4_1"), ++ MTK_FUNCTION(4, "URXD0"), ++ MTK_FUNCTION(6, "CLKM0"), ++ MTK_FUNCTION(7, "DBG_MON_A24") ++ ), ++ MTK_PIN( ++ 236, "GPIO236", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO236"), ++ MTK_FUNCTION(1, "SPI1_MO_B"), ++ MTK_FUNCTION(2, "SPI1_MI_B"), ++ MTK_FUNCTION(3, "SCL5_1"), ++ MTK_FUNCTION(4, "URTS0"), ++ MTK_FUNCTION(6, "PWM_B"), ++ MTK_FUNCTION(7, "DBG_MON_A25") ++ ), ++ MTK_PIN( ++ 237, "GPIO237", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO237"), ++ MTK_FUNCTION(1, "SPI1_CS_B"), ++ MTK_FUNCTION(2, "TP_URXD1_AO"), ++ MTK_FUNCTION(3, "SDA5_1"), ++ MTK_FUNCTION(4, "UCTS0"), ++ MTK_FUNCTION(6, "CLKM1"), ++ MTK_FUNCTION(7, "DBG_MON_A26") ++ ), ++ MTK_PIN( ++ 238, "GPIO238", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO238"), ++ MTK_FUNCTION(1, "SDA4_0") ++ ), ++ MTK_PIN( ++ 239, "GPIO239", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO239"), ++ MTK_FUNCTION(1, "SCL4_0") ++ ), ++ MTK_PIN( ++ 240, "GPIO240", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO240"), ++ MTK_FUNCTION(1, "SDA5_0") ++ ), ++ MTK_PIN( ++ 241, "GPIO241", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO241"), ++ MTK_FUNCTION(1, "SCL5_0") ++ ), ++ MTK_PIN( ++ 242, "GPIO242", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO242"), ++ MTK_FUNCTION(1, "SPI2_CLK_B"), ++ MTK_FUNCTION(2, "TP_UTXD2_AO"), ++ MTK_FUNCTION(3, "SCL4_2"), ++ MTK_FUNCTION(4, "UTXD1"), ++ MTK_FUNCTION(5, "URTS3"), ++ MTK_FUNCTION(6, "PWM_C"), ++ MTK_FUNCTION(7, "DBG_MON_A27") ++ ), ++ MTK_PIN( ++ 243, "GPIO243", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO243"), ++ MTK_FUNCTION(1, "SPI2_MI_B"), ++ MTK_FUNCTION(2, "SPI2_MO_B"), ++ MTK_FUNCTION(3, "SDA4_2"), ++ MTK_FUNCTION(4, "URXD1"), ++ MTK_FUNCTION(5, "UCTS3"), ++ MTK_FUNCTION(6, "CLKM2"), ++ MTK_FUNCTION(7, "DBG_MON_A28") ++ ), ++ MTK_PIN( ++ 244, "GPIO244", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO244"), ++ MTK_FUNCTION(1, "SPI2_MO_B"), ++ MTK_FUNCTION(2, "SPI2_MI_B"), ++ MTK_FUNCTION(3, "SCL5_2"), ++ MTK_FUNCTION(4, "URTS1"), ++ MTK_FUNCTION(5, "UTXD3"), ++ MTK_FUNCTION(6, "PWM_D"), ++ MTK_FUNCTION(7, "DBG_MON_A29") ++ ), ++ MTK_PIN( ++ 245, "GPIO245", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO245"), ++ MTK_FUNCTION(1, "SPI2_CS_B"), ++ MTK_FUNCTION(2, "TP_URXD2_AO"), ++ MTK_FUNCTION(3, "SDA5_2"), ++ MTK_FUNCTION(4, "UCTS1"), ++ MTK_FUNCTION(5, "URXD3"), ++ MTK_FUNCTION(6, "CLKM3"), ++ MTK_FUNCTION(7, "DBG_MON_A30") ++ ), ++ MTK_PIN( ++ 246, "GPIO246", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO246"), ++ MTK_FUNCTION(1, "I2S1_LRCK"), ++ MTK_FUNCTION(2, "I2S2_LRCK"), ++ MTK_FUNCTION(3, "I2S0_LRCK"), ++ MTK_FUNCTION(4, "I2S3_LRCK"), ++ MTK_FUNCTION(5, "PCM0_SYNC"), ++ MTK_FUNCTION(6, "SPI5_CLK_C"), ++ MTK_FUNCTION(7, "DBG_MON_A31") ++ ), ++ MTK_PIN( ++ 247, "GPIO247", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO247"), ++ MTK_FUNCTION(1, "I2S1_BCK"), ++ MTK_FUNCTION(2, "I2S2_BCK"), ++ MTK_FUNCTION(3, "I2S0_BCK"), ++ MTK_FUNCTION(4, "I2S3_BCK"), ++ MTK_FUNCTION(5, "PCM0_CLK"), ++ MTK_FUNCTION(6, "SPI5_MI_C"), ++ MTK_FUNCTION(7, "DBG_MON_A32") ++ ), ++ MTK_PIN( ++ 248, "GPIO248", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO248"), ++ MTK_FUNCTION(1, "I2S2_DI"), ++ MTK_FUNCTION(2, "I2S2_DI"), ++ MTK_FUNCTION(3, "I2S0_DI"), ++ MTK_FUNCTION(4, "I2S0_DI"), ++ MTK_FUNCTION(5, "PCM0_DI"), ++ MTK_FUNCTION(6, "SPI5_CS_C") ++ ), ++ MTK_PIN( ++ 249, "GPIO249", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO249"), ++ MTK_FUNCTION(1, "I2S1_DO"), ++ MTK_FUNCTION(2, "I2S1_DO"), ++ MTK_FUNCTION(3, "I2S3_DO"), ++ MTK_FUNCTION(4, "I2S3_DO"), ++ MTK_FUNCTION(5, "PCM0_DO"), ++ MTK_FUNCTION(6, "SPI5_MO_C"), ++ MTK_FUNCTION(7, "TRAP_SRAM_PWR_BYPASS") ++ ), ++ MTK_PIN( ++ 250, "GPIO250", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO250"), ++ MTK_FUNCTION(1, "SPI3_MI"), ++ MTK_FUNCTION(2, "SPI3_MO"), ++ MTK_FUNCTION(3, "IRTX_OUT"), ++ MTK_FUNCTION(6, "TP_URXD1_AO"), ++ MTK_FUNCTION(7, "DROP_ZONE") ++ ), ++ MTK_PIN( ++ 251, "GPIO251", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO251"), ++ MTK_FUNCTION(1, "SPI3_MO"), ++ MTK_FUNCTION(2, "SPI3_MI"), ++ MTK_FUNCTION(3, "CMFLASH"), ++ MTK_FUNCTION(6, "TP_UTXD1_AO"), ++ MTK_FUNCTION(7, "C2K_RTCK") ++ ), ++ MTK_PIN( ++ 252, "GPIO252", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO252"), ++ MTK_FUNCTION(1, "SPI3_CLK"), ++ MTK_FUNCTION(2, "SCL0_4"), ++ MTK_FUNCTION(3, "PWM_D"), ++ MTK_FUNCTION(7, "C2K_TMS") ++ ), ++ MTK_PIN( ++ 253, "GPIO253", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO253"), ++ MTK_FUNCTION(1, "SPI3_CS"), ++ MTK_FUNCTION(2, "SDA0_4"), ++ MTK_FUNCTION(3, "PWM_A"), ++ MTK_FUNCTION(7, "C2K_TCK") ++ ), ++ MTK_PIN( ++ 254, "GPIO254", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO254"), ++ MTK_FUNCTION(1, "I2S1_MCK"), ++ MTK_FUNCTION(2, "I2S2_MCK"), ++ MTK_FUNCTION(3, "I2S0_MCK"), ++ MTK_FUNCTION(4, "I2S3_MCK"), ++ MTK_FUNCTION(5, "CLKM0"), ++ MTK_FUNCTION(7, "C2K_TDI") ++ ), ++ MTK_PIN( ++ 255, "GPIO255", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO255"), ++ MTK_FUNCTION(1, "CLKM1"), ++ MTK_FUNCTION(2, "DISP_PWM"), ++ MTK_FUNCTION(3, "PWM_B"), ++ MTK_FUNCTION(6, "TP_GPIO1_AO"), ++ MTK_FUNCTION(7, "C2K_TDO") ++ ), ++ MTK_PIN( ++ 256, "GPIO256", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO256"), ++ MTK_FUNCTION(1, "CLKM2"), ++ MTK_FUNCTION(2, "IRTX_OUT"), ++ MTK_FUNCTION(3, "PWM_C"), ++ MTK_FUNCTION(6, "TP_GPIO0_AO"), ++ MTK_FUNCTION(7, "C2K_NTRST") ++ ), ++ MTK_PIN( ++ 257, "GPIO257", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO257"), ++ MTK_FUNCTION(1, "IO_JTAG_TMS"), ++ MTK_FUNCTION(2, "LTE_JTAG_TMS"), ++ MTK_FUNCTION(3, "DFD_TMS"), ++ MTK_FUNCTION(4, "DAP_SIB1_SWD"), ++ MTK_FUNCTION(5, "ANC_JTAG_TMS"), ++ MTK_FUNCTION(6, "SCP_JTAG_TMS"), ++ MTK_FUNCTION(7, "C2K_DM_OTMS") ++ ), ++ MTK_PIN( ++ 258, "GPIO258", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO258"), ++ MTK_FUNCTION(1, "IO_JTAG_TCK"), ++ MTK_FUNCTION(2, "LTE_JTAG_TCK"), ++ MTK_FUNCTION(3, "DFD_TCK_XI"), ++ MTK_FUNCTION(4, "DAP_SIB1_SWCK"), ++ MTK_FUNCTION(5, "ANC_JTAG_TCK"), ++ MTK_FUNCTION(6, "SCP_JTAG_TCK"), ++ MTK_FUNCTION(7, "C2K_DM_OTCK") ++ ), ++ MTK_PIN( ++ 259, "GPIO259", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO259"), ++ MTK_FUNCTION(1, "IO_JTAG_TDI"), ++ MTK_FUNCTION(2, "LTE_JTAG_TDI"), ++ MTK_FUNCTION(3, "DFD_TDI"), ++ MTK_FUNCTION(5, "ANC_JTAG_TDI"), ++ MTK_FUNCTION(6, "SCP_JTAG_TDI"), ++ MTK_FUNCTION(7, "C2K_DM_OTDI") ++ ), ++ MTK_PIN( ++ 260, "GPIO260", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO260"), ++ MTK_FUNCTION(1, "IO_JTAG_TDO"), ++ MTK_FUNCTION(2, "LTE_JTAG_TDO"), ++ MTK_FUNCTION(3, "DFD_TDO"), ++ MTK_FUNCTION(5, "ANC_JTAG_TDO"), ++ MTK_FUNCTION(6, "SCP_JTAG_TDO"), ++ MTK_FUNCTION(7, "C2K_DM_OTDO") ++ ), ++ MTK_PIN( ++ 261, "GPIO261", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ DRV_GRP3, ++ MTK_FUNCTION(0, "GPIO261"), ++ MTK_FUNCTION(2, "LTE_JTAG_TRSTN"), ++ MTK_FUNCTION(3, "DFD_NTRST"), ++ MTK_FUNCTION(5, "ANC_JTAG_TRSTN"), ++ MTK_FUNCTION(6, "SCP_JTAG_TRSTN"), ++ MTK_FUNCTION(7, "C2K_DM_JTINTP") ++ ), ++}; ++ ++#endif /* __PINCTRL_MTK_MT6797_H */ +diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8183.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8183.h +new file mode 100644 +index 000000000000..79adf5b8a186 +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8183.h +@@ -0,0 +1,1916 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2018 MediaTek Inc. ++ * ++ * Author: Zhiyong Tao <zhiyong.tao@mediatek.com> ++ * ++ */ ++ ++#ifndef __PINCTRL_MTK_MT8183_H ++#define __PINCTRL_MTK_MT8183_H ++ ++#include "pinctrl-paris.h" ++ ++static struct mtk_pin_desc mtk_pins_mt8183[] = { ++ MTK_PIN( ++ 0, "GPIO0", ++ MTK_EINT_FUNCTION(0, 0), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO0"), ++ MTK_FUNCTION(1, "MRG_SYNC"), ++ MTK_FUNCTION(2, "PCM0_SYNC"), ++ MTK_FUNCTION(3, "TP_GPIO0_AO"), ++ MTK_FUNCTION(4, "SRCLKENAI0"), ++ MTK_FUNCTION(5, "SCP_SPI2_CS"), ++ MTK_FUNCTION(6, "I2S3_MCK"), ++ MTK_FUNCTION(7, "SPI2_CSB") ++ ), ++ MTK_PIN( ++ 1, "GPIO1", ++ MTK_EINT_FUNCTION(0, 1), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO1"), ++ MTK_FUNCTION(1, "MRG_CLK"), ++ MTK_FUNCTION(2, "PCM0_CLK"), ++ MTK_FUNCTION(3, "TP_GPIO1_AO"), ++ MTK_FUNCTION(4, "CLKM3"), ++ MTK_FUNCTION(5, "SCP_SPI2_MO"), ++ MTK_FUNCTION(6, "I2S3_BCK"), ++ MTK_FUNCTION(7, "SPI2_MO") ++ ), ++ MTK_PIN( ++ 2, "GPIO2", ++ MTK_EINT_FUNCTION(0, 2), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO2"), ++ MTK_FUNCTION(1, "MRG_DO"), ++ MTK_FUNCTION(2, "PCM0_DO"), ++ MTK_FUNCTION(3, "TP_GPIO2_AO"), ++ MTK_FUNCTION(4, "SCL6"), ++ MTK_FUNCTION(5, "SCP_SPI2_CK"), ++ MTK_FUNCTION(6, "I2S3_LRCK"), ++ MTK_FUNCTION(7, "SPI2_CLK") ++ ), ++ MTK_PIN( ++ 3, "GPIO3", ++ MTK_EINT_FUNCTION(0, 3), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO3"), ++ MTK_FUNCTION(1, "MRG_DI"), ++ MTK_FUNCTION(2, "PCM0_DI"), ++ MTK_FUNCTION(3, "TP_GPIO3_AO"), ++ MTK_FUNCTION(4, "SDA6"), ++ MTK_FUNCTION(5, "TDM_MCK"), ++ MTK_FUNCTION(6, "I2S3_DO"), ++ MTK_FUNCTION(7, "SCP_VREQ_VAO") ++ ), ++ MTK_PIN( ++ 4, "GPIO4", ++ MTK_EINT_FUNCTION(0, 4), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO4"), ++ MTK_FUNCTION(1, "PWM_B"), ++ MTK_FUNCTION(2, "I2S0_MCK"), ++ MTK_FUNCTION(3, "SSPM_UTXD_AO"), ++ MTK_FUNCTION(4, "MD_URXD1"), ++ MTK_FUNCTION(5, "TDM_BCK"), ++ MTK_FUNCTION(6, "TP_GPIO4_AO"), ++ MTK_FUNCTION(7, "DAP_MD32_SWD") ++ ), ++ MTK_PIN( ++ 5, "GPIO5", ++ MTK_EINT_FUNCTION(0, 5), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO5"), ++ MTK_FUNCTION(1, "PWM_C"), ++ MTK_FUNCTION(2, "I2S0_BCK"), ++ MTK_FUNCTION(3, "SSPM_URXD_AO"), ++ MTK_FUNCTION(4, "MD_UTXD1"), ++ MTK_FUNCTION(5, "TDM_LRCK"), ++ MTK_FUNCTION(6, "TP_GPIO5_AO"), ++ MTK_FUNCTION(7, "DAP_MD32_SWCK") ++ ), ++ MTK_PIN( ++ 6, "GPIO6", ++ MTK_EINT_FUNCTION(0, 6), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO6"), ++ MTK_FUNCTION(1, "PWM_A"), ++ MTK_FUNCTION(2, "I2S0_LRCK"), ++ MTK_FUNCTION(3, "IDDIG"), ++ MTK_FUNCTION(4, "MD_URXD0"), ++ MTK_FUNCTION(5, "TDM_DATA0"), ++ MTK_FUNCTION(6, "TP_GPIO6_AO"), ++ MTK_FUNCTION(7, "CMFLASH") ++ ), ++ MTK_PIN( ++ 7, "GPIO7", ++ MTK_EINT_FUNCTION(0, 7), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO7"), ++ MTK_FUNCTION(1, "SPI1_B_MI"), ++ MTK_FUNCTION(2, "I2S0_DI"), ++ MTK_FUNCTION(3, "USB_DRVVBUS"), ++ MTK_FUNCTION(4, "MD_UTXD0"), ++ MTK_FUNCTION(5, "TDM_DATA1"), ++ MTK_FUNCTION(6, "TP_GPIO7_AO"), ++ MTK_FUNCTION(7, "DVFSRC_EXT_REQ") ++ ), ++ MTK_PIN( ++ 8, "GPIO8", ++ MTK_EINT_FUNCTION(0, 8), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO8"), ++ MTK_FUNCTION(1, "SPI1_B_CSB"), ++ MTK_FUNCTION(2, "ANT_SEL3"), ++ MTK_FUNCTION(3, "SCL7"), ++ MTK_FUNCTION(4, "CONN_MCU_TRST_B"), ++ MTK_FUNCTION(5, "TDM_DATA2"), ++ MTK_FUNCTION(6, "MD_INT0"), ++ MTK_FUNCTION(7, "JTRSTN_SEL1") ++ ), ++ MTK_PIN( ++ 9, "GPIO9", ++ MTK_EINT_FUNCTION(0, 9), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO9"), ++ MTK_FUNCTION(1, "SPI1_B_MO"), ++ MTK_FUNCTION(2, "ANT_SEL4"), ++ MTK_FUNCTION(3, "CMMCLK2"), ++ MTK_FUNCTION(4, "CONN_MCU_DBGACK_N"), ++ MTK_FUNCTION(5, "SSPM_JTAG_TRSTN"), ++ MTK_FUNCTION(6, "IO_JTAG_TRSTN"), ++ MTK_FUNCTION(7, "DBG_MON_B10") ++ ), ++ MTK_PIN( ++ 10, "GPIO10", ++ MTK_EINT_FUNCTION(0, 10), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO10"), ++ MTK_FUNCTION(1, "SPI1_B_CLK"), ++ MTK_FUNCTION(2, "ANT_SEL5"), ++ MTK_FUNCTION(3, "CMMCLK3"), ++ MTK_FUNCTION(4, "CONN_MCU_DBGI_N"), ++ MTK_FUNCTION(5, "TDM_DATA3"), ++ MTK_FUNCTION(6, "EXT_FRAME_SYNC"), ++ MTK_FUNCTION(7, "DBG_MON_B11") ++ ), ++ MTK_PIN( ++ 11, "GPIO11", ++ MTK_EINT_FUNCTION(0, 11), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO11"), ++ MTK_FUNCTION(1, "TP_URXD1_AO"), ++ MTK_FUNCTION(2, "IDDIG"), ++ MTK_FUNCTION(3, "SCL6"), ++ MTK_FUNCTION(4, "UCTS1"), ++ MTK_FUNCTION(5, "UCTS0"), ++ MTK_FUNCTION(6, "SRCLKENAI1"), ++ MTK_FUNCTION(7, "I2S5_MCK") ++ ), ++ MTK_PIN( ++ 12, "GPIO12", ++ MTK_EINT_FUNCTION(0, 12), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO12"), ++ MTK_FUNCTION(1, "TP_UTXD1_AO"), ++ MTK_FUNCTION(2, "USB_DRVVBUS"), ++ MTK_FUNCTION(3, "SDA6"), ++ MTK_FUNCTION(4, "URTS1"), ++ MTK_FUNCTION(5, "URTS0"), ++ MTK_FUNCTION(6, "I2S2_DI2"), ++ MTK_FUNCTION(7, "I2S5_BCK") ++ ), ++ MTK_PIN( ++ 13, "GPIO13", ++ MTK_EINT_FUNCTION(0, 13), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO13"), ++ MTK_FUNCTION(1, "DBPI_D0"), ++ MTK_FUNCTION(2, "SPI5_MI"), ++ MTK_FUNCTION(3, "PCM0_SYNC"), ++ MTK_FUNCTION(4, "MD_URXD0"), ++ MTK_FUNCTION(5, "ANT_SEL3"), ++ MTK_FUNCTION(6, "I2S0_MCK"), ++ MTK_FUNCTION(7, "DBG_MON_B15") ++ ), ++ MTK_PIN( ++ 14, "GPIO14", ++ MTK_EINT_FUNCTION(0, 14), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO14"), ++ MTK_FUNCTION(1, "DBPI_D1"), ++ MTK_FUNCTION(2, "SPI5_CSB"), ++ MTK_FUNCTION(3, "PCM0_CLK"), ++ MTK_FUNCTION(4, "MD_UTXD0"), ++ MTK_FUNCTION(5, "ANT_SEL4"), ++ MTK_FUNCTION(6, "I2S0_BCK"), ++ MTK_FUNCTION(7, "DBG_MON_B16") ++ ), ++ MTK_PIN( ++ 15, "GPIO15", ++ MTK_EINT_FUNCTION(0, 15), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO15"), ++ MTK_FUNCTION(1, "DBPI_D2"), ++ MTK_FUNCTION(2, "SPI5_MO"), ++ MTK_FUNCTION(3, "PCM0_DO"), ++ MTK_FUNCTION(4, "MD_URXD1"), ++ MTK_FUNCTION(5, "ANT_SEL5"), ++ MTK_FUNCTION(6, "I2S0_LRCK"), ++ MTK_FUNCTION(7, "DBG_MON_B17") ++ ), ++ MTK_PIN( ++ 16, "GPIO16", ++ MTK_EINT_FUNCTION(0, 16), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO16"), ++ MTK_FUNCTION(1, "DBPI_D3"), ++ MTK_FUNCTION(2, "SPI5_CLK"), ++ MTK_FUNCTION(3, "PCM0_DI"), ++ MTK_FUNCTION(4, "MD_UTXD1"), ++ MTK_FUNCTION(5, "ANT_SEL6"), ++ MTK_FUNCTION(6, "I2S0_DI"), ++ MTK_FUNCTION(7, "DBG_MON_B23") ++ ), ++ MTK_PIN( ++ 17, "GPIO17", ++ MTK_EINT_FUNCTION(0, 17), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO17"), ++ MTK_FUNCTION(1, "DBPI_D4"), ++ MTK_FUNCTION(2, "SPI4_MI"), ++ MTK_FUNCTION(3, "CONN_MCU_TRST_B"), ++ MTK_FUNCTION(4, "MD_INT0"), ++ MTK_FUNCTION(5, "ANT_SEL7"), ++ MTK_FUNCTION(6, "I2S3_MCK"), ++ MTK_FUNCTION(7, "DBG_MON_A1") ++ ), ++ MTK_PIN( ++ 18, "GPIO18", ++ MTK_EINT_FUNCTION(0, 18), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO18"), ++ MTK_FUNCTION(1, "DBPI_D5"), ++ MTK_FUNCTION(2, "SPI4_CSB"), ++ MTK_FUNCTION(3, "CONN_MCU_DBGI_N"), ++ MTK_FUNCTION(4, "MD_INT0"), ++ MTK_FUNCTION(5, "SCP_VREQ_VAO"), ++ MTK_FUNCTION(6, "I2S3_BCK"), ++ MTK_FUNCTION(7, "DBG_MON_A2") ++ ), ++ MTK_PIN( ++ 19, "GPIO19", ++ MTK_EINT_FUNCTION(0, 19), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO19"), ++ MTK_FUNCTION(1, "DBPI_D6"), ++ MTK_FUNCTION(2, "SPI4_MO"), ++ MTK_FUNCTION(3, "CONN_MCU_TDO"), ++ MTK_FUNCTION(4, "MD_INT2_C2K_UIM1_HOT_PLUG"), ++ MTK_FUNCTION(5, "URXD1"), ++ MTK_FUNCTION(6, "I2S3_LRCK"), ++ MTK_FUNCTION(7, "DBG_MON_A3") ++ ), ++ MTK_PIN( ++ 20, "GPIO20", ++ MTK_EINT_FUNCTION(0, 20), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO20"), ++ MTK_FUNCTION(1, "DBPI_D7"), ++ MTK_FUNCTION(2, "SPI4_CLK"), ++ MTK_FUNCTION(3, "CONN_MCU_DBGACK_N"), ++ MTK_FUNCTION(4, "MD_INT1_C2K_UIM0_HOT_PLUG"), ++ MTK_FUNCTION(5, "UTXD1"), ++ MTK_FUNCTION(6, "I2S3_DO"), ++ MTK_FUNCTION(7, "DBG_MON_A19") ++ ), ++ MTK_PIN( ++ 21, "GPIO21", ++ MTK_EINT_FUNCTION(0, 21), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO21"), ++ MTK_FUNCTION(1, "DBPI_D8"), ++ MTK_FUNCTION(2, "SPI3_MI"), ++ MTK_FUNCTION(3, "CONN_MCU_TMS"), ++ MTK_FUNCTION(4, "DAP_MD32_SWD"), ++ MTK_FUNCTION(5, "CONN_MCU_AICE_TMSC"), ++ MTK_FUNCTION(6, "I2S2_MCK"), ++ MTK_FUNCTION(7, "DBG_MON_B5") ++ ), ++ MTK_PIN( ++ 22, "GPIO22", ++ MTK_EINT_FUNCTION(0, 22), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO22"), ++ MTK_FUNCTION(1, "DBPI_D9"), ++ MTK_FUNCTION(2, "SPI3_CSB"), ++ MTK_FUNCTION(3, "CONN_MCU_TCK"), ++ MTK_FUNCTION(4, "DAP_MD32_SWCK"), ++ MTK_FUNCTION(5, "CONN_MCU_AICE_TCKC"), ++ MTK_FUNCTION(6, "I2S2_BCK"), ++ MTK_FUNCTION(7, "DBG_MON_B6") ++ ), ++ MTK_PIN( ++ 23, "GPIO23", ++ MTK_EINT_FUNCTION(0, 23), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO23"), ++ MTK_FUNCTION(1, "DBPI_D10"), ++ MTK_FUNCTION(2, "SPI3_MO"), ++ MTK_FUNCTION(3, "CONN_MCU_TDI"), ++ MTK_FUNCTION(4, "UCTS1"), ++ MTK_FUNCTION(5, "EXT_FRAME_SYNC"), ++ MTK_FUNCTION(6, "I2S2_LRCK"), ++ MTK_FUNCTION(7, "DBG_MON_B7") ++ ), ++ MTK_PIN( ++ 24, "GPIO24", ++ MTK_EINT_FUNCTION(0, 24), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO24"), ++ MTK_FUNCTION(1, "DBPI_D11"), ++ MTK_FUNCTION(2, "SPI3_CLK"), ++ MTK_FUNCTION(3, "SRCLKENAI0"), ++ MTK_FUNCTION(4, "URTS1"), ++ MTK_FUNCTION(5, "IO_JTAG_TCK"), ++ MTK_FUNCTION(6, "I2S2_DI"), ++ MTK_FUNCTION(7, "DBG_MON_B31") ++ ), ++ MTK_PIN( ++ 25, "GPIO25", ++ MTK_EINT_FUNCTION(0, 25), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO25"), ++ MTK_FUNCTION(1, "DBPI_HSYNC"), ++ MTK_FUNCTION(2, "ANT_SEL0"), ++ MTK_FUNCTION(3, "SCL6"), ++ MTK_FUNCTION(4, "KPCOL2"), ++ MTK_FUNCTION(5, "IO_JTAG_TMS"), ++ MTK_FUNCTION(6, "I2S1_MCK"), ++ MTK_FUNCTION(7, "DBG_MON_B0") ++ ), ++ MTK_PIN( ++ 26, "GPIO26", ++ MTK_EINT_FUNCTION(0, 26), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO26"), ++ MTK_FUNCTION(1, "DBPI_VSYNC"), ++ MTK_FUNCTION(2, "ANT_SEL1"), ++ MTK_FUNCTION(3, "SDA6"), ++ MTK_FUNCTION(4, "KPROW2"), ++ MTK_FUNCTION(5, "IO_JTAG_TDI"), ++ MTK_FUNCTION(6, "I2S1_BCK"), ++ MTK_FUNCTION(7, "DBG_MON_B1") ++ ), ++ MTK_PIN( ++ 27, "GPIO27", ++ MTK_EINT_FUNCTION(0, 27), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO27"), ++ MTK_FUNCTION(1, "DBPI_DE"), ++ MTK_FUNCTION(2, "ANT_SEL2"), ++ MTK_FUNCTION(3, "SCL7"), ++ MTK_FUNCTION(4, "DMIC_CLK"), ++ MTK_FUNCTION(5, "IO_JTAG_TDO"), ++ MTK_FUNCTION(6, "I2S1_LRCK"), ++ MTK_FUNCTION(7, "DBG_MON_B9") ++ ), ++ MTK_PIN( ++ 28, "GPIO28", ++ MTK_EINT_FUNCTION(0, 28), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO28"), ++ MTK_FUNCTION(1, "DBPI_CK"), ++ MTK_FUNCTION(2, "DVFSRC_EXT_REQ"), ++ MTK_FUNCTION(3, "SDA7"), ++ MTK_FUNCTION(4, "DMIC_DAT"), ++ MTK_FUNCTION(5, "IO_JTAG_TRSTN"), ++ MTK_FUNCTION(6, "I2S1_DO"), ++ MTK_FUNCTION(7, "DBG_MON_B32") ++ ), ++ MTK_PIN( ++ 29, "GPIO29", ++ MTK_EINT_FUNCTION(0, 29), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO29"), ++ MTK_FUNCTION(1, "MSDC1_CLK"), ++ MTK_FUNCTION(2, "IO_JTAG_TCK"), ++ MTK_FUNCTION(3, "UDI_TCK"), ++ MTK_FUNCTION(4, "CONN_DSP_JCK"), ++ MTK_FUNCTION(5, "SSPM_JTAG_TCK"), ++ MTK_FUNCTION(6, "PCM1_CLK"), ++ MTK_FUNCTION(7, "DBG_MON_A6") ++ ), ++ MTK_PIN( ++ 30, "GPIO30", ++ MTK_EINT_FUNCTION(0, 30), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO30"), ++ MTK_FUNCTION(1, "MSDC1_DAT3"), ++ MTK_FUNCTION(2, "DAP_MD32_SWD"), ++ MTK_FUNCTION(3, "CONN_MCU_AICE_TMSC"), ++ MTK_FUNCTION(4, "CONN_DSP_JINTP"), ++ MTK_FUNCTION(5, "SSPM_JTAG_TRSTN"), ++ MTK_FUNCTION(6, "PCM1_DI"), ++ MTK_FUNCTION(7, "DBG_MON_A7") ++ ), ++ MTK_PIN( ++ 31, "GPIO31", ++ MTK_EINT_FUNCTION(0, 31), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO31"), ++ MTK_FUNCTION(1, "MSDC1_CMD"), ++ MTK_FUNCTION(2, "IO_JTAG_TMS"), ++ MTK_FUNCTION(3, "UDI_TMS"), ++ MTK_FUNCTION(4, "CONN_DSP_JMS"), ++ MTK_FUNCTION(5, "SSPM_JTAG_TMS"), ++ MTK_FUNCTION(6, "PCM1_SYNC"), ++ MTK_FUNCTION(7, "DBG_MON_A8") ++ ), ++ MTK_PIN( ++ 32, "GPIO32", ++ MTK_EINT_FUNCTION(0, 32), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO32"), ++ MTK_FUNCTION(1, "MSDC1_DAT0"), ++ MTK_FUNCTION(2, "IO_JTAG_TDI"), ++ MTK_FUNCTION(3, "UDI_TDI"), ++ MTK_FUNCTION(4, "CONN_DSP_JDI"), ++ MTK_FUNCTION(5, "SSPM_JTAG_TDI"), ++ MTK_FUNCTION(6, "PCM1_DO0"), ++ MTK_FUNCTION(7, "DBG_MON_A9") ++ ), ++ MTK_PIN( ++ 33, "GPIO33", ++ MTK_EINT_FUNCTION(0, 33), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO33"), ++ MTK_FUNCTION(1, "MSDC1_DAT2"), ++ MTK_FUNCTION(2, "IO_JTAG_TRSTN"), ++ MTK_FUNCTION(3, "UDI_NTRST"), ++ MTK_FUNCTION(4, "DAP_MD32_SWCK"), ++ MTK_FUNCTION(5, "CONN_MCU_AICE_TCKC"), ++ MTK_FUNCTION(6, "PCM1_DO2"), ++ MTK_FUNCTION(7, "DBG_MON_A10") ++ ), ++ MTK_PIN( ++ 34, "GPIO34", ++ MTK_EINT_FUNCTION(0, 34), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO34"), ++ MTK_FUNCTION(1, "MSDC1_DAT1"), ++ MTK_FUNCTION(2, "IO_JTAG_TDO"), ++ MTK_FUNCTION(3, "UDI_TDO"), ++ MTK_FUNCTION(4, "CONN_DSP_JDO"), ++ MTK_FUNCTION(5, "SSPM_JTAG_TDO"), ++ MTK_FUNCTION(6, "PCM1_DO1"), ++ MTK_FUNCTION(7, "DBG_MON_A11") ++ ), ++ MTK_PIN( ++ 35, "GPIO35", ++ MTK_EINT_FUNCTION(0, 35), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO35"), ++ MTK_FUNCTION(1, "MD1_SIM2_SIO"), ++ MTK_FUNCTION(2, "CCU_JTAG_TDO"), ++ MTK_FUNCTION(3, "MD1_SIM1_SIO"), ++ MTK_FUNCTION(5, "SCP_JTAG_TDO"), ++ MTK_FUNCTION(6, "CONN_DSP_JMS"), ++ MTK_FUNCTION(7, "DBG_MON_A28") ++ ), ++ MTK_PIN( ++ 36, "GPIO36", ++ MTK_EINT_FUNCTION(0, 36), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO36"), ++ MTK_FUNCTION(1, "MD1_SIM2_SRST"), ++ MTK_FUNCTION(2, "CCU_JTAG_TMS"), ++ MTK_FUNCTION(3, "MD1_SIM1_SRST"), ++ MTK_FUNCTION(4, "CONN_MCU_AICE_TMSC"), ++ MTK_FUNCTION(5, "SCP_JTAG_TMS"), ++ MTK_FUNCTION(6, "CONN_DSP_JINTP"), ++ MTK_FUNCTION(7, "DBG_MON_A29") ++ ), ++ MTK_PIN( ++ 37, "GPIO37", ++ MTK_EINT_FUNCTION(0, 37), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO37"), ++ MTK_FUNCTION(1, "MD1_SIM2_SCLK"), ++ MTK_FUNCTION(2, "CCU_JTAG_TDI"), ++ MTK_FUNCTION(3, "MD1_SIM1_SCLK"), ++ MTK_FUNCTION(5, "SCP_JTAG_TDI"), ++ MTK_FUNCTION(6, "CONN_DSP_JDO"), ++ MTK_FUNCTION(7, "DBG_MON_A30") ++ ), ++ MTK_PIN( ++ 38, "GPIO38", ++ MTK_EINT_FUNCTION(0, 38), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO38"), ++ MTK_FUNCTION(1, "MD1_SIM1_SCLK"), ++ MTK_FUNCTION(3, "MD1_SIM2_SCLK"), ++ MTK_FUNCTION(4, "CONN_MCU_AICE_TCKC"), ++ MTK_FUNCTION(7, "DBG_MON_A20") ++ ), ++ MTK_PIN( ++ 39, "GPIO39", ++ MTK_EINT_FUNCTION(0, 39), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO39"), ++ MTK_FUNCTION(1, "MD1_SIM1_SRST"), ++ MTK_FUNCTION(2, "CCU_JTAG_TCK"), ++ MTK_FUNCTION(3, "MD1_SIM2_SRST"), ++ MTK_FUNCTION(5, "SCP_JTAG_TCK"), ++ MTK_FUNCTION(6, "CONN_DSP_JCK"), ++ MTK_FUNCTION(7, "DBG_MON_A31") ++ ), ++ MTK_PIN( ++ 40, "GPIO40", ++ MTK_EINT_FUNCTION(0, 40), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO40"), ++ MTK_FUNCTION(1, "MD1_SIM1_SIO"), ++ MTK_FUNCTION(2, "CCU_JTAG_TRST"), ++ MTK_FUNCTION(3, "MD1_SIM2_SIO"), ++ MTK_FUNCTION(5, "SCP_JTAG_TRSTN"), ++ MTK_FUNCTION(6, "CONN_DSP_JDI"), ++ MTK_FUNCTION(7, "DBG_MON_A32") ++ ), ++ MTK_PIN( ++ 41, "GPIO41", ++ MTK_EINT_FUNCTION(0, 41), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO41"), ++ MTK_FUNCTION(1, "IDDIG"), ++ MTK_FUNCTION(2, "URXD1"), ++ MTK_FUNCTION(3, "UCTS0"), ++ MTK_FUNCTION(4, "SSPM_UTXD_AO"), ++ MTK_FUNCTION(5, "EXT_FRAME_SYNC"), ++ MTK_FUNCTION(6, "DMIC_CLK") ++ ), ++ MTK_PIN( ++ 42, "GPIO42", ++ MTK_EINT_FUNCTION(0, 42), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO42"), ++ MTK_FUNCTION(1, "USB_DRVVBUS"), ++ MTK_FUNCTION(2, "UTXD1"), ++ MTK_FUNCTION(3, "URTS0"), ++ MTK_FUNCTION(4, "SSPM_URXD_AO"), ++ MTK_FUNCTION(5, "EXT_FRAME_SYNC"), ++ MTK_FUNCTION(6, "DMIC_DAT") ++ ), ++ MTK_PIN( ++ 43, "GPIO43", ++ MTK_EINT_FUNCTION(0, 43), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO43"), ++ MTK_FUNCTION(1, "DISP_PWM") ++ ), ++ MTK_PIN( ++ 44, "GPIO44", ++ MTK_EINT_FUNCTION(0, 44), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO44"), ++ MTK_FUNCTION(1, "DSI_TE") ++ ), ++ MTK_PIN( ++ 45, "GPIO45", ++ MTK_EINT_FUNCTION(0, 45), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO45"), ++ MTK_FUNCTION(1, "LCM_RST") ++ ), ++ MTK_PIN( ++ 46, "GPIO46", ++ MTK_EINT_FUNCTION(0, 46), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO46"), ++ MTK_FUNCTION(1, "MD_INT2_C2K_UIM1_HOT_PLUG"), ++ MTK_FUNCTION(2, "URXD1"), ++ MTK_FUNCTION(3, "UCTS1"), ++ MTK_FUNCTION(4, "CCU_UTXD_AO"), ++ MTK_FUNCTION(5, "TP_UCTS1_AO"), ++ MTK_FUNCTION(6, "IDDIG"), ++ MTK_FUNCTION(7, "I2S5_LRCK") ++ ), ++ MTK_PIN( ++ 47, "GPIO47", ++ MTK_EINT_FUNCTION(0, 47), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO47"), ++ MTK_FUNCTION(1, "MD_INT1_C2K_UIM0_HOT_PLUG"), ++ MTK_FUNCTION(2, "UTXD1"), ++ MTK_FUNCTION(3, "URTS1"), ++ MTK_FUNCTION(4, "CCU_URXD_AO"), ++ MTK_FUNCTION(5, "TP_URTS1_AO"), ++ MTK_FUNCTION(6, "USB_DRVVBUS"), ++ MTK_FUNCTION(7, "I2S5_DO") ++ ), ++ MTK_PIN( ++ 48, "GPIO48", ++ MTK_EINT_FUNCTION(0, 48), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO48"), ++ MTK_FUNCTION(1, "SCL5") ++ ), ++ MTK_PIN( ++ 49, "GPIO49", ++ MTK_EINT_FUNCTION(0, 49), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO49"), ++ MTK_FUNCTION(1, "SDA5") ++ ), ++ MTK_PIN( ++ 50, "GPIO50", ++ MTK_EINT_FUNCTION(0, 50), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO50"), ++ MTK_FUNCTION(1, "SCL3") ++ ), ++ MTK_PIN( ++ 51, "GPIO51", ++ MTK_EINT_FUNCTION(0, 51), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO51"), ++ MTK_FUNCTION(1, "SDA3") ++ ), ++ MTK_PIN( ++ 52, "GPIO52", ++ MTK_EINT_FUNCTION(0, 52), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO52"), ++ MTK_FUNCTION(1, "BPI_ANT2") ++ ), ++ MTK_PIN( ++ 53, "GPIO53", ++ MTK_EINT_FUNCTION(0, 53), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO53"), ++ MTK_FUNCTION(1, "BPI_ANT0") ++ ), ++ MTK_PIN( ++ 54, "GPIO54", ++ MTK_EINT_FUNCTION(0, 54), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO54"), ++ MTK_FUNCTION(1, "BPI_OLAT1") ++ ), ++ MTK_PIN( ++ 55, "GPIO55", ++ MTK_EINT_FUNCTION(0, 55), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO55"), ++ MTK_FUNCTION(1, "BPI_BUS8") ++ ), ++ MTK_PIN( ++ 56, "GPIO56", ++ MTK_EINT_FUNCTION(0, 56), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO56"), ++ MTK_FUNCTION(1, "BPI_BUS9"), ++ MTK_FUNCTION(2, "SCL_6306") ++ ), ++ MTK_PIN( ++ 57, "GPIO57", ++ MTK_EINT_FUNCTION(0, 57), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO57"), ++ MTK_FUNCTION(1, "BPI_BUS10"), ++ MTK_FUNCTION(2, "SDA_6306") ++ ), ++ MTK_PIN( ++ 58, "GPIO58", ++ MTK_EINT_FUNCTION(0, 58), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO58"), ++ MTK_FUNCTION(1, "RFIC0_BSI_D2"), ++ MTK_FUNCTION(2, "SPM_BSI_D2"), ++ MTK_FUNCTION(3, "PWM_B") ++ ), ++ MTK_PIN( ++ 59, "GPIO59", ++ MTK_EINT_FUNCTION(0, 59), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO59"), ++ MTK_FUNCTION(1, "RFIC0_BSI_D1"), ++ MTK_FUNCTION(2, "SPM_BSI_D1") ++ ), ++ MTK_PIN( ++ 60, "GPIO60", ++ MTK_EINT_FUNCTION(0, 60), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO60"), ++ MTK_FUNCTION(1, "RFIC0_BSI_D0"), ++ MTK_FUNCTION(2, "SPM_BSI_D0") ++ ), ++ MTK_PIN( ++ 61, "GPIO61", ++ MTK_EINT_FUNCTION(0, 61), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO61"), ++ MTK_FUNCTION(1, "MIPI1_SDATA") ++ ), ++ MTK_PIN( ++ 62, "GPIO62", ++ MTK_EINT_FUNCTION(0, 62), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO62"), ++ MTK_FUNCTION(1, "MIPI1_SCLK") ++ ), ++ MTK_PIN( ++ 63, "GPIO63", ++ MTK_EINT_FUNCTION(0, 63), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO63"), ++ MTK_FUNCTION(1, "MIPI0_SDATA") ++ ), ++ MTK_PIN( ++ 64, "GPIO64", ++ MTK_EINT_FUNCTION(0, 64), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO64"), ++ MTK_FUNCTION(1, "MIPI0_SCLK") ++ ), ++ MTK_PIN( ++ 65, "GPIO65", ++ MTK_EINT_FUNCTION(0, 65), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO65"), ++ MTK_FUNCTION(1, "MIPI3_SDATA"), ++ MTK_FUNCTION(2, "BPI_OLAT2") ++ ), ++ MTK_PIN( ++ 66, "GPIO66", ++ MTK_EINT_FUNCTION(0, 66), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO66"), ++ MTK_FUNCTION(1, "MIPI3_SCLK"), ++ MTK_FUNCTION(2, "BPI_OLAT3") ++ ), ++ MTK_PIN( ++ 67, "GPIO67", ++ MTK_EINT_FUNCTION(0, 67), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO67"), ++ MTK_FUNCTION(1, "MIPI2_SDATA") ++ ), ++ MTK_PIN( ++ 68, "GPIO68", ++ MTK_EINT_FUNCTION(0, 68), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO68"), ++ MTK_FUNCTION(1, "MIPI2_SCLK") ++ ), ++ MTK_PIN( ++ 69, "GPIO69", ++ MTK_EINT_FUNCTION(0, 69), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO69"), ++ MTK_FUNCTION(1, "BPI_BUS7") ++ ), ++ MTK_PIN( ++ 70, "GPIO70", ++ MTK_EINT_FUNCTION(0, 70), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO70"), ++ MTK_FUNCTION(1, "BPI_BUS6") ++ ), ++ MTK_PIN( ++ 71, "GPIO71", ++ MTK_EINT_FUNCTION(0, 71), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO71"), ++ MTK_FUNCTION(1, "BPI_BUS5") ++ ), ++ MTK_PIN( ++ 72, "GPIO72", ++ MTK_EINT_FUNCTION(0, 72), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO72"), ++ MTK_FUNCTION(1, "BPI_BUS4") ++ ), ++ MTK_PIN( ++ 73, "GPIO73", ++ MTK_EINT_FUNCTION(0, 73), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO73"), ++ MTK_FUNCTION(1, "BPI_BUS3") ++ ), ++ MTK_PIN( ++ 74, "GPIO74", ++ MTK_EINT_FUNCTION(0, 74), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO74"), ++ MTK_FUNCTION(1, "BPI_BUS2") ++ ), ++ MTK_PIN( ++ 75, "GPIO75", ++ MTK_EINT_FUNCTION(0, 75), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO75"), ++ MTK_FUNCTION(1, "BPI_BUS1") ++ ), ++ MTK_PIN( ++ 76, "GPIO76", ++ MTK_EINT_FUNCTION(0, 76), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO76"), ++ MTK_FUNCTION(1, "BPI_BUS0") ++ ), ++ MTK_PIN( ++ 77, "GPIO77", ++ MTK_EINT_FUNCTION(0, 77), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO77"), ++ MTK_FUNCTION(1, "BPI_ANT1") ++ ), ++ MTK_PIN( ++ 78, "GPIO78", ++ MTK_EINT_FUNCTION(0, 78), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO78"), ++ MTK_FUNCTION(1, "BPI_OLAT0") ++ ), ++ MTK_PIN( ++ 79, "GPIO79", ++ MTK_EINT_FUNCTION(0, 79), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO79"), ++ MTK_FUNCTION(1, "BPI_PA_VM1"), ++ MTK_FUNCTION(2, "MIPI4_SDATA") ++ ), ++ MTK_PIN( ++ 80, "GPIO80", ++ MTK_EINT_FUNCTION(0, 80), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO80"), ++ MTK_FUNCTION(1, "BPI_PA_VM0"), ++ MTK_FUNCTION(2, "MIPI4_SCLK") ++ ), ++ MTK_PIN( ++ 81, "GPIO81", ++ MTK_EINT_FUNCTION(0, 81), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO81"), ++ MTK_FUNCTION(1, "SDA1") ++ ), ++ MTK_PIN( ++ 82, "GPIO82", ++ MTK_EINT_FUNCTION(0, 82), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO82"), ++ MTK_FUNCTION(1, "SDA0") ++ ), ++ MTK_PIN( ++ 83, "GPIO83", ++ MTK_EINT_FUNCTION(0, 83), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO83"), ++ MTK_FUNCTION(1, "SCL0") ++ ), ++ MTK_PIN( ++ 84, "GPIO84", ++ MTK_EINT_FUNCTION(0, 84), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO84"), ++ MTK_FUNCTION(1, "SCL1") ++ ), ++ MTK_PIN( ++ 85, "GPIO85", ++ MTK_EINT_FUNCTION(0, 85), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO85"), ++ MTK_FUNCTION(1, "SPI0_MI"), ++ MTK_FUNCTION(2, "SCP_SPI0_MI"), ++ MTK_FUNCTION(3, "CLKM3"), ++ MTK_FUNCTION(4, "I2S1_BCK"), ++ MTK_FUNCTION(5, "MFG_DFD_JTAG_TDO"), ++ MTK_FUNCTION(6, "DFD_TDO"), ++ MTK_FUNCTION(7, "JTDO_SEL1") ++ ), ++ MTK_PIN( ++ 86, "GPIO86", ++ MTK_EINT_FUNCTION(0, 86), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO86"), ++ MTK_FUNCTION(1, "SPI0_CSB"), ++ MTK_FUNCTION(2, "SCP_SPI0_CS"), ++ MTK_FUNCTION(3, "CLKM0"), ++ MTK_FUNCTION(4, "I2S1_LRCK"), ++ MTK_FUNCTION(5, "MFG_DFD_JTAG_TMS"), ++ MTK_FUNCTION(6, "DFD_TMS"), ++ MTK_FUNCTION(7, "JTMS_SEL1") ++ ), ++ MTK_PIN( ++ 87, "GPIO87", ++ MTK_EINT_FUNCTION(0, 87), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO87"), ++ MTK_FUNCTION(1, "SPI0_MO"), ++ MTK_FUNCTION(2, "SCP_SPI0_MO"), ++ MTK_FUNCTION(3, "SDA1"), ++ MTK_FUNCTION(4, "I2S1_DO"), ++ MTK_FUNCTION(5, "MFG_DFD_JTAG_TDI"), ++ MTK_FUNCTION(6, "DFD_TDI"), ++ MTK_FUNCTION(7, "JTDI_SEL1") ++ ), ++ MTK_PIN( ++ 88, "GPIO88", ++ MTK_EINT_FUNCTION(0, 88), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO88"), ++ MTK_FUNCTION(1, "SPI0_CLK"), ++ MTK_FUNCTION(2, "SCP_SPI0_CK"), ++ MTK_FUNCTION(3, "SCL1"), ++ MTK_FUNCTION(4, "I2S1_MCK"), ++ MTK_FUNCTION(5, "MFG_DFD_JTAG_TCK"), ++ MTK_FUNCTION(6, "DFD_TCK_XI"), ++ MTK_FUNCTION(7, "JTCK_SEL1") ++ ), ++ MTK_PIN( ++ 89, "GPIO89", ++ MTK_EINT_FUNCTION(0, 89), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO89"), ++ MTK_FUNCTION(1, "SRCLKENAI0"), ++ MTK_FUNCTION(2, "PWM_C"), ++ MTK_FUNCTION(3, "I2S5_BCK"), ++ MTK_FUNCTION(4, "ANT_SEL6"), ++ MTK_FUNCTION(5, "SDA8"), ++ MTK_FUNCTION(6, "CMVREF0"), ++ MTK_FUNCTION(7, "DBG_MON_A21") ++ ), ++ MTK_PIN( ++ 90, "GPIO90", ++ MTK_EINT_FUNCTION(0, 90), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO90"), ++ MTK_FUNCTION(1, "PWM_A"), ++ MTK_FUNCTION(2, "CMMCLK2"), ++ MTK_FUNCTION(3, "I2S5_LRCK"), ++ MTK_FUNCTION(4, "SCP_VREQ_VAO"), ++ MTK_FUNCTION(5, "SCL8"), ++ MTK_FUNCTION(6, "PTA_RXD"), ++ MTK_FUNCTION(7, "DBG_MON_A22") ++ ), ++ MTK_PIN( ++ 91, "GPIO91", ++ MTK_EINT_FUNCTION(0, 91), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO91"), ++ MTK_FUNCTION(1, "KPROW1"), ++ MTK_FUNCTION(2, "PWM_B"), ++ MTK_FUNCTION(3, "I2S5_DO"), ++ MTK_FUNCTION(4, "ANT_SEL7"), ++ MTK_FUNCTION(5, "CMMCLK3"), ++ MTK_FUNCTION(6, "PTA_TXD") ++ ), ++ MTK_PIN( ++ 92, "GPIO92", ++ MTK_EINT_FUNCTION(0, 92), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO92"), ++ MTK_FUNCTION(1, "KPROW0") ++ ), ++ MTK_PIN( ++ 93, "GPIO93", ++ MTK_EINT_FUNCTION(0, 93), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO93"), ++ MTK_FUNCTION(1, "KPCOL0"), ++ MTK_FUNCTION(7, "DBG_MON_B27") ++ ), ++ MTK_PIN( ++ 94, "GPIO94", ++ MTK_EINT_FUNCTION(0, 94), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO94"), ++ MTK_FUNCTION(1, "KPCOL1"), ++ MTK_FUNCTION(2, "I2S2_DI2"), ++ MTK_FUNCTION(3, "I2S5_MCK"), ++ MTK_FUNCTION(4, "CMMCLK2"), ++ MTK_FUNCTION(5, "SCP_SPI2_MI"), ++ MTK_FUNCTION(6, "SRCLKENAI1"), ++ MTK_FUNCTION(7, "SPI2_MI") ++ ), ++ MTK_PIN( ++ 95, "GPIO95", ++ MTK_EINT_FUNCTION(0, 95), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO95"), ++ MTK_FUNCTION(1, "URXD0"), ++ MTK_FUNCTION(2, "UTXD0"), ++ MTK_FUNCTION(3, "MD_URXD0"), ++ MTK_FUNCTION(4, "MD_URXD1"), ++ MTK_FUNCTION(5, "SSPM_URXD_AO"), ++ MTK_FUNCTION(6, "CCU_URXD_AO") ++ ), ++ MTK_PIN( ++ 96, "GPIO96", ++ MTK_EINT_FUNCTION(0, 96), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO96"), ++ MTK_FUNCTION(1, "UTXD0"), ++ MTK_FUNCTION(2, "URXD0"), ++ MTK_FUNCTION(3, "MD_UTXD0"), ++ MTK_FUNCTION(4, "MD_UTXD1"), ++ MTK_FUNCTION(5, "SSPM_UTXD_AO"), ++ MTK_FUNCTION(6, "CCU_UTXD_AO"), ++ MTK_FUNCTION(7, "DBG_MON_B2") ++ ), ++ MTK_PIN( ++ 97, "GPIO97", ++ MTK_EINT_FUNCTION(0, 97), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO97"), ++ MTK_FUNCTION(1, "UCTS0"), ++ MTK_FUNCTION(2, "I2S2_MCK"), ++ MTK_FUNCTION(3, "IDDIG"), ++ MTK_FUNCTION(4, "CONN_MCU_TDO"), ++ MTK_FUNCTION(5, "SSPM_JTAG_TDO"), ++ MTK_FUNCTION(6, "IO_JTAG_TDO"), ++ MTK_FUNCTION(7, "DBG_MON_B3") ++ ), ++ MTK_PIN( ++ 98, "GPIO98", ++ MTK_EINT_FUNCTION(0, 98), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO98"), ++ MTK_FUNCTION(1, "URTS0"), ++ MTK_FUNCTION(2, "I2S2_BCK"), ++ MTK_FUNCTION(3, "USB_DRVVBUS"), ++ MTK_FUNCTION(4, "CONN_MCU_TMS"), ++ MTK_FUNCTION(5, "SSPM_JTAG_TMS"), ++ MTK_FUNCTION(6, "IO_JTAG_TMS"), ++ MTK_FUNCTION(7, "DBG_MON_B4") ++ ), ++ MTK_PIN( ++ 99, "GPIO99", ++ MTK_EINT_FUNCTION(0, 99), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO99"), ++ MTK_FUNCTION(1, "CMMCLK0"), ++ MTK_FUNCTION(4, "CONN_MCU_AICE_TMSC"), ++ MTK_FUNCTION(7, "DBG_MON_B28") ++ ), ++ MTK_PIN( ++ 100, "GPIO100", ++ MTK_EINT_FUNCTION(0, 100), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO100"), ++ MTK_FUNCTION(1, "CMMCLK1"), ++ MTK_FUNCTION(2, "PWM_C"), ++ MTK_FUNCTION(3, "MD_INT1_C2K_UIM0_HOT_PLUG"), ++ MTK_FUNCTION(4, "CONN_MCU_AICE_TCKC"), ++ MTK_FUNCTION(7, "DBG_MON_B29") ++ ), ++ MTK_PIN( ++ 101, "GPIO101", ++ MTK_EINT_FUNCTION(0, 101), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO101"), ++ MTK_FUNCTION(1, "CLKM2"), ++ MTK_FUNCTION(2, "I2S2_LRCK"), ++ MTK_FUNCTION(3, "CMVREF1"), ++ MTK_FUNCTION(4, "CONN_MCU_TCK"), ++ MTK_FUNCTION(5, "SSPM_JTAG_TCK"), ++ MTK_FUNCTION(6, "IO_JTAG_TCK") ++ ), ++ MTK_PIN( ++ 102, "GPIO102", ++ MTK_EINT_FUNCTION(0, 102), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO102"), ++ MTK_FUNCTION(1, "CLKM1"), ++ MTK_FUNCTION(2, "I2S2_DI"), ++ MTK_FUNCTION(3, "DVFSRC_EXT_REQ"), ++ MTK_FUNCTION(4, "CONN_MCU_TDI"), ++ MTK_FUNCTION(5, "SSPM_JTAG_TDI"), ++ MTK_FUNCTION(6, "IO_JTAG_TDI"), ++ MTK_FUNCTION(7, "DBG_MON_B8") ++ ), ++ MTK_PIN( ++ 103, "GPIO103", ++ MTK_EINT_FUNCTION(0, 103), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO103"), ++ MTK_FUNCTION(1, "SCL2") ++ ), ++ MTK_PIN( ++ 104, "GPIO104", ++ MTK_EINT_FUNCTION(0, 104), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO104"), ++ MTK_FUNCTION(1, "SDA2") ++ ), ++ MTK_PIN( ++ 105, "GPIO105", ++ MTK_EINT_FUNCTION(0, 105), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO105"), ++ MTK_FUNCTION(1, "SCL4") ++ ), ++ MTK_PIN( ++ 106, "GPIO106", ++ MTK_EINT_FUNCTION(0, 106), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO106"), ++ MTK_FUNCTION(1, "SDA4") ++ ), ++ MTK_PIN( ++ 107, "GPIO107", ++ MTK_EINT_FUNCTION(0, 107), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO107"), ++ MTK_FUNCTION(1, "DMIC_CLK"), ++ MTK_FUNCTION(2, "ANT_SEL0"), ++ MTK_FUNCTION(3, "CLKM0"), ++ MTK_FUNCTION(4, "SDA7"), ++ MTK_FUNCTION(5, "EXT_FRAME_SYNC"), ++ MTK_FUNCTION(6, "PWM_A"), ++ MTK_FUNCTION(7, "DBG_MON_B12") ++ ), ++ MTK_PIN( ++ 108, "GPIO108", ++ MTK_EINT_FUNCTION(0, 108), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO108"), ++ MTK_FUNCTION(1, "CMMCLK2"), ++ MTK_FUNCTION(2, "ANT_SEL1"), ++ MTK_FUNCTION(3, "CLKM1"), ++ MTK_FUNCTION(4, "SCL8"), ++ MTK_FUNCTION(5, "DAP_MD32_SWD"), ++ MTK_FUNCTION(6, "PWM_B"), ++ MTK_FUNCTION(7, "DBG_MON_B13") ++ ), ++ MTK_PIN( ++ 109, "GPIO109", ++ MTK_EINT_FUNCTION(0, 109), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO109"), ++ MTK_FUNCTION(1, "DMIC_DAT"), ++ MTK_FUNCTION(2, "ANT_SEL2"), ++ MTK_FUNCTION(3, "CLKM2"), ++ MTK_FUNCTION(4, "SDA8"), ++ MTK_FUNCTION(5, "DAP_MD32_SWCK"), ++ MTK_FUNCTION(6, "PWM_C"), ++ MTK_FUNCTION(7, "DBG_MON_B14") ++ ), ++ MTK_PIN( ++ 110, "GPIO110", ++ MTK_EINT_FUNCTION(0, 110), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO110"), ++ MTK_FUNCTION(1, "SCL7"), ++ MTK_FUNCTION(2, "ANT_SEL0"), ++ MTK_FUNCTION(3, "TP_URXD1_AO"), ++ MTK_FUNCTION(4, "USB_DRVVBUS"), ++ MTK_FUNCTION(5, "SRCLKENAI1"), ++ MTK_FUNCTION(6, "KPCOL2"), ++ MTK_FUNCTION(7, "URXD1") ++ ), ++ MTK_PIN( ++ 111, "GPIO111", ++ MTK_EINT_FUNCTION(0, 111), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO111"), ++ MTK_FUNCTION(1, "CMMCLK3"), ++ MTK_FUNCTION(2, "ANT_SEL1"), ++ MTK_FUNCTION(3, "SRCLKENAI0"), ++ MTK_FUNCTION(4, "SCP_VREQ_VAO"), ++ MTK_FUNCTION(5, "MD_INT2_C2K_UIM1_HOT_PLUG"), ++ MTK_FUNCTION(7, "DVFSRC_EXT_REQ") ++ ), ++ MTK_PIN( ++ 112, "GPIO112", ++ MTK_EINT_FUNCTION(0, 112), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO112"), ++ MTK_FUNCTION(1, "SDA7"), ++ MTK_FUNCTION(2, "ANT_SEL2"), ++ MTK_FUNCTION(3, "TP_UTXD1_AO"), ++ MTK_FUNCTION(4, "IDDIG"), ++ MTK_FUNCTION(5, "AGPS_SYNC"), ++ MTK_FUNCTION(6, "KPROW2"), ++ MTK_FUNCTION(7, "UTXD1") ++ ), ++ MTK_PIN( ++ 113, "GPIO113", ++ MTK_EINT_FUNCTION(0, 113), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO113"), ++ MTK_FUNCTION(1, "CONN_TOP_CLK"), ++ MTK_FUNCTION(3, "SCL6"), ++ MTK_FUNCTION(4, "AUXIF_CLK0"), ++ MTK_FUNCTION(6, "TP_UCTS1_AO") ++ ), ++ MTK_PIN( ++ 114, "GPIO114", ++ MTK_EINT_FUNCTION(0, 114), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO114"), ++ MTK_FUNCTION(1, "CONN_TOP_DATA"), ++ MTK_FUNCTION(3, "SDA6"), ++ MTK_FUNCTION(4, "AUXIF_ST0"), ++ MTK_FUNCTION(6, "TP_URTS1_AO") ++ ), ++ MTK_PIN( ++ 115, "GPIO115", ++ MTK_EINT_FUNCTION(0, 115), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO115"), ++ MTK_FUNCTION(1, "CONN_BT_CLK"), ++ MTK_FUNCTION(2, "UTXD1"), ++ MTK_FUNCTION(3, "PTA_TXD"), ++ MTK_FUNCTION(4, "AUXIF_CLK1"), ++ MTK_FUNCTION(5, "DAP_MD32_SWD"), ++ MTK_FUNCTION(6, "TP_UTXD1_AO") ++ ), ++ MTK_PIN( ++ 116, "GPIO116", ++ MTK_EINT_FUNCTION(0, 116), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO116"), ++ MTK_FUNCTION(1, "CONN_BT_DATA"), ++ MTK_FUNCTION(2, "IPU_JTAG_TRST"), ++ MTK_FUNCTION(4, "AUXIF_ST1"), ++ MTK_FUNCTION(5, "DAP_MD32_SWCK"), ++ MTK_FUNCTION(6, "TP_URXD2_AO"), ++ MTK_FUNCTION(7, "DBG_MON_A0") ++ ), ++ MTK_PIN( ++ 117, "GPIO117", ++ MTK_EINT_FUNCTION(0, 117), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO117"), ++ MTK_FUNCTION(1, "CONN_WF_HB0"), ++ MTK_FUNCTION(2, "IPU_JTAG_TDO"), ++ MTK_FUNCTION(6, "TP_UTXD2_AO"), ++ MTK_FUNCTION(7, "DBG_MON_A4") ++ ), ++ MTK_PIN( ++ 118, "GPIO118", ++ MTK_EINT_FUNCTION(0, 118), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO118"), ++ MTK_FUNCTION(1, "CONN_WF_HB1"), ++ MTK_FUNCTION(2, "IPU_JTAG_TDI"), ++ MTK_FUNCTION(5, "SSPM_URXD_AO"), ++ MTK_FUNCTION(6, "TP_UCTS2_AO"), ++ MTK_FUNCTION(7, "DBG_MON_A5") ++ ), ++ MTK_PIN( ++ 119, "GPIO119", ++ MTK_EINT_FUNCTION(0, 119), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO119"), ++ MTK_FUNCTION(1, "CONN_WF_HB2"), ++ MTK_FUNCTION(2, "IPU_JTAG_TCK"), ++ MTK_FUNCTION(5, "SSPM_UTXD_AO"), ++ MTK_FUNCTION(6, "TP_URTS2_AO") ++ ), ++ MTK_PIN( ++ 120, "GPIO120", ++ MTK_EINT_FUNCTION(0, 120), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO120"), ++ MTK_FUNCTION(1, "CONN_WB_PTA"), ++ MTK_FUNCTION(2, "IPU_JTAG_TMS"), ++ MTK_FUNCTION(5, "CCU_URXD_AO") ++ ), ++ MTK_PIN( ++ 121, "GPIO121", ++ MTK_EINT_FUNCTION(0, 121), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO121"), ++ MTK_FUNCTION(1, "CONN_HRST_B"), ++ MTK_FUNCTION(2, "URXD1"), ++ MTK_FUNCTION(3, "PTA_RXD"), ++ MTK_FUNCTION(5, "CCU_UTXD_AO"), ++ MTK_FUNCTION(6, "TP_URXD1_AO") ++ ), ++ MTK_PIN( ++ 122, "GPIO122", ++ MTK_EINT_FUNCTION(0, 122), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO122"), ++ MTK_FUNCTION(1, "MSDC0_CMD"), ++ MTK_FUNCTION(2, "SSPM_URXD2_AO"), ++ MTK_FUNCTION(3, "ANT_SEL1"), ++ MTK_FUNCTION(7, "DBG_MON_A12") ++ ), ++ MTK_PIN( ++ 123, "GPIO123", ++ MTK_EINT_FUNCTION(0, 123), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO123"), ++ MTK_FUNCTION(1, "MSDC0_DAT0"), ++ MTK_FUNCTION(3, "ANT_SEL0"), ++ MTK_FUNCTION(7, "DBG_MON_A13") ++ ), ++ MTK_PIN( ++ 124, "GPIO124", ++ MTK_EINT_FUNCTION(0, 124), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO124"), ++ MTK_FUNCTION(1, "MSDC0_CLK"), ++ MTK_FUNCTION(7, "DBG_MON_A14") ++ ), ++ MTK_PIN( ++ 125, "GPIO125", ++ MTK_EINT_FUNCTION(0, 125), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO125"), ++ MTK_FUNCTION(1, "MSDC0_DAT2"), ++ MTK_FUNCTION(3, "MRG_CLK"), ++ MTK_FUNCTION(7, "DBG_MON_A15") ++ ), ++ MTK_PIN( ++ 126, "GPIO126", ++ MTK_EINT_FUNCTION(0, 126), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO126"), ++ MTK_FUNCTION(1, "MSDC0_DAT4"), ++ MTK_FUNCTION(3, "ANT_SEL5"), ++ MTK_FUNCTION(6, "UFS_MPHY_SCL"), ++ MTK_FUNCTION(7, "DBG_MON_A16") ++ ), ++ MTK_PIN( ++ 127, "GPIO127", ++ MTK_EINT_FUNCTION(0, 127), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO127"), ++ MTK_FUNCTION(1, "MSDC0_DAT6"), ++ MTK_FUNCTION(3, "ANT_SEL4"), ++ MTK_FUNCTION(6, "UFS_MPHY_SDA"), ++ MTK_FUNCTION(7, "DBG_MON_A17") ++ ), ++ MTK_PIN( ++ 128, "GPIO128", ++ MTK_EINT_FUNCTION(0, 128), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO128"), ++ MTK_FUNCTION(1, "MSDC0_DAT1"), ++ MTK_FUNCTION(3, "ANT_SEL2"), ++ MTK_FUNCTION(6, "UFS_UNIPRO_SDA"), ++ MTK_FUNCTION(7, "DBG_MON_A18") ++ ), ++ MTK_PIN( ++ 129, "GPIO129", ++ MTK_EINT_FUNCTION(0, 129), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO129"), ++ MTK_FUNCTION(1, "MSDC0_DAT5"), ++ MTK_FUNCTION(3, "ANT_SEL3"), ++ MTK_FUNCTION(6, "UFS_UNIPRO_SCL"), ++ MTK_FUNCTION(7, "DBG_MON_A23") ++ ), ++ MTK_PIN( ++ 130, "GPIO130", ++ MTK_EINT_FUNCTION(0, 130), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO130"), ++ MTK_FUNCTION(1, "MSDC0_DAT7"), ++ MTK_FUNCTION(3, "MRG_DO"), ++ MTK_FUNCTION(7, "DBG_MON_A24") ++ ), ++ MTK_PIN( ++ 131, "GPIO131", ++ MTK_EINT_FUNCTION(0, 131), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO131"), ++ MTK_FUNCTION(1, "MSDC0_DSL"), ++ MTK_FUNCTION(3, "MRG_SYNC"), ++ MTK_FUNCTION(7, "DBG_MON_A25") ++ ), ++ MTK_PIN( ++ 132, "GPIO132", ++ MTK_EINT_FUNCTION(0, 132), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO132"), ++ MTK_FUNCTION(1, "MSDC0_DAT3"), ++ MTK_FUNCTION(3, "MRG_DI"), ++ MTK_FUNCTION(7, "DBG_MON_A26") ++ ), ++ MTK_PIN( ++ 133, "GPIO133", ++ MTK_EINT_FUNCTION(0, 133), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO133"), ++ MTK_FUNCTION(1, "MSDC0_RSTB"), ++ MTK_FUNCTION(3, "AGPS_SYNC"), ++ MTK_FUNCTION(7, "DBG_MON_A27") ++ ), ++ MTK_PIN( ++ 134, "GPIO134", ++ MTK_EINT_FUNCTION(0, 134), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO134"), ++ MTK_FUNCTION(1, "RTC32K_CK") ++ ), ++ MTK_PIN( ++ 135, "GPIO135", ++ MTK_EINT_FUNCTION(0, 135), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO135"), ++ MTK_FUNCTION(1, "WATCHDOG") ++ ), ++ MTK_PIN( ++ 136, "GPIO136", ++ MTK_EINT_FUNCTION(0, 136), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO136"), ++ MTK_FUNCTION(1, "AUD_CLK_MOSI"), ++ MTK_FUNCTION(2, "AUD_CLK_MISO"), ++ MTK_FUNCTION(3, "I2S1_MCK"), ++ MTK_FUNCTION(6, "UFS_UNIPRO_SCL") ++ ), ++ MTK_PIN( ++ 137, "GPIO137", ++ MTK_EINT_FUNCTION(0, 137), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO137"), ++ MTK_FUNCTION(1, "AUD_SYNC_MOSI"), ++ MTK_FUNCTION(2, "AUD_SYNC_MISO"), ++ MTK_FUNCTION(3, "I2S1_BCK") ++ ), ++ MTK_PIN( ++ 138, "GPIO138", ++ MTK_EINT_FUNCTION(0, 138), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO138"), ++ MTK_FUNCTION(1, "AUD_DAT_MOSI0"), ++ MTK_FUNCTION(2, "AUD_DAT_MISO0"), ++ MTK_FUNCTION(3, "I2S1_LRCK"), ++ MTK_FUNCTION(7, "DBG_MON_B24") ++ ), ++ MTK_PIN( ++ 139, "GPIO139", ++ MTK_EINT_FUNCTION(0, 139), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO139"), ++ MTK_FUNCTION(1, "AUD_DAT_MOSI1"), ++ MTK_FUNCTION(2, "AUD_DAT_MISO1"), ++ MTK_FUNCTION(3, "I2S1_DO"), ++ MTK_FUNCTION(6, "UFS_MPHY_SDA") ++ ), ++ MTK_PIN( ++ 140, "GPIO140", ++ MTK_EINT_FUNCTION(0, 140), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO140"), ++ MTK_FUNCTION(1, "AUD_CLK_MISO"), ++ MTK_FUNCTION(2, "AUD_CLK_MOSI"), ++ MTK_FUNCTION(3, "I2S0_MCK"), ++ MTK_FUNCTION(6, "UFS_UNIPRO_SDA") ++ ), ++ MTK_PIN( ++ 141, "GPIO141", ++ MTK_EINT_FUNCTION(0, 141), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO141"), ++ MTK_FUNCTION(1, "AUD_SYNC_MISO"), ++ MTK_FUNCTION(2, "AUD_SYNC_MOSI"), ++ MTK_FUNCTION(3, "I2S0_BCK") ++ ), ++ MTK_PIN( ++ 142, "GPIO142", ++ MTK_EINT_FUNCTION(0, 142), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO142"), ++ MTK_FUNCTION(1, "AUD_DAT_MISO0"), ++ MTK_FUNCTION(2, "AUD_DAT_MOSI0"), ++ MTK_FUNCTION(3, "I2S0_LRCK"), ++ MTK_FUNCTION(4, "VOW_DAT_MISO"), ++ MTK_FUNCTION(7, "DBG_MON_B25") ++ ), ++ MTK_PIN( ++ 143, "GPIO143", ++ MTK_EINT_FUNCTION(0, 143), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO143"), ++ MTK_FUNCTION(1, "AUD_DAT_MISO1"), ++ MTK_FUNCTION(2, "AUD_DAT_MOSI1"), ++ MTK_FUNCTION(3, "I2S0_DI"), ++ MTK_FUNCTION(4, "VOW_CLK_MISO"), ++ MTK_FUNCTION(6, "UFS_MPHY_SCL"), ++ MTK_FUNCTION(7, "DBG_MON_B26") ++ ), ++ MTK_PIN( ++ 144, "GPIO144", ++ MTK_EINT_FUNCTION(0, 144), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO144"), ++ MTK_FUNCTION(1, "PWRAP_SPI0_MI"), ++ MTK_FUNCTION(2, "PWRAP_SPI0_MO") ++ ), ++ MTK_PIN( ++ 145, "GPIO145", ++ MTK_EINT_FUNCTION(0, 145), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO145"), ++ MTK_FUNCTION(1, "PWRAP_SPI0_CSN") ++ ), ++ MTK_PIN( ++ 146, "GPIO146", ++ MTK_EINT_FUNCTION(0, 146), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO146"), ++ MTK_FUNCTION(1, "PWRAP_SPI0_MO"), ++ MTK_FUNCTION(2, "PWRAP_SPI0_MI") ++ ), ++ MTK_PIN( ++ 147, "GPIO147", ++ MTK_EINT_FUNCTION(0, 147), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO147"), ++ MTK_FUNCTION(1, "PWRAP_SPI0_CK") ++ ), ++ MTK_PIN( ++ 148, "GPIO148", ++ MTK_EINT_FUNCTION(0, 148), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO148"), ++ MTK_FUNCTION(1, "SRCLKENA0") ++ ), ++ MTK_PIN( ++ 149, "GPIO149", ++ MTK_EINT_FUNCTION(0, 149), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO149"), ++ MTK_FUNCTION(1, "SRCLKENA1") ++ ), ++ MTK_PIN( ++ 150, "GPIO150", ++ MTK_EINT_FUNCTION(0, 150), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO150"), ++ MTK_FUNCTION(1, "PWM_A"), ++ MTK_FUNCTION(2, "CMFLASH"), ++ MTK_FUNCTION(3, "CLKM0"), ++ MTK_FUNCTION(7, "DBG_MON_B30") ++ ), ++ MTK_PIN( ++ 151, "GPIO151", ++ MTK_EINT_FUNCTION(0, 151), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO151"), ++ MTK_FUNCTION(1, "PWM_B"), ++ MTK_FUNCTION(2, "CMVREF0"), ++ MTK_FUNCTION(3, "CLKM1"), ++ MTK_FUNCTION(7, "DBG_MON_B20") ++ ), ++ MTK_PIN( ++ 152, "GPIO152", ++ MTK_EINT_FUNCTION(0, 152), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO152"), ++ MTK_FUNCTION(1, "PWM_C"), ++ MTK_FUNCTION(2, "CMFLASH"), ++ MTK_FUNCTION(3, "CLKM2"), ++ MTK_FUNCTION(7, "DBG_MON_B21") ++ ), ++ MTK_PIN( ++ 153, "GPIO153", ++ MTK_EINT_FUNCTION(0, 153), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO153"), ++ MTK_FUNCTION(1, "PWM_A"), ++ MTK_FUNCTION(2, "CMVREF0"), ++ MTK_FUNCTION(3, "CLKM3"), ++ MTK_FUNCTION(7, "DBG_MON_B22") ++ ), ++ MTK_PIN( ++ 154, "GPIO154", ++ MTK_EINT_FUNCTION(0, 154), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO154"), ++ MTK_FUNCTION(1, "SCP_VREQ_VAO"), ++ MTK_FUNCTION(2, "DVFSRC_EXT_REQ"), ++ MTK_FUNCTION(7, "DBG_MON_B18") ++ ), ++ MTK_PIN( ++ 155, "GPIO155", ++ MTK_EINT_FUNCTION(0, 155), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO155"), ++ MTK_FUNCTION(1, "ANT_SEL0"), ++ MTK_FUNCTION(2, "DVFSRC_EXT_REQ"), ++ MTK_FUNCTION(3, "CMVREF1"), ++ MTK_FUNCTION(7, "SCP_JTAG_TDI") ++ ), ++ MTK_PIN( ++ 156, "GPIO156", ++ MTK_EINT_FUNCTION(0, 156), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO156"), ++ MTK_FUNCTION(1, "ANT_SEL1"), ++ MTK_FUNCTION(2, "SRCLKENAI0"), ++ MTK_FUNCTION(3, "SCL6"), ++ MTK_FUNCTION(4, "KPCOL2"), ++ MTK_FUNCTION(5, "IDDIG"), ++ MTK_FUNCTION(7, "SCP_JTAG_TCK") ++ ), ++ MTK_PIN( ++ 157, "GPIO157", ++ MTK_EINT_FUNCTION(0, 157), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO157"), ++ MTK_FUNCTION(1, "ANT_SEL2"), ++ MTK_FUNCTION(2, "SRCLKENAI1"), ++ MTK_FUNCTION(3, "SDA6"), ++ MTK_FUNCTION(4, "KPROW2"), ++ MTK_FUNCTION(5, "USB_DRVVBUS"), ++ MTK_FUNCTION(7, "SCP_JTAG_TRSTN") ++ ), ++ MTK_PIN( ++ 158, "GPIO158", ++ MTK_EINT_FUNCTION(0, 158), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO158"), ++ MTK_FUNCTION(1, "ANT_SEL3") ++ ), ++ MTK_PIN( ++ 159, "GPIO159", ++ MTK_EINT_FUNCTION(0, 159), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO159"), ++ MTK_FUNCTION(1, "ANT_SEL4") ++ ), ++ MTK_PIN( ++ 160, "GPIO160", ++ MTK_EINT_FUNCTION(0, 160), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO160"), ++ MTK_FUNCTION(1, "ANT_SEL5") ++ ), ++ MTK_PIN( ++ 161, "GPIO161", ++ MTK_EINT_FUNCTION(0, 161), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO161"), ++ MTK_FUNCTION(1, "SPI1_A_MI"), ++ MTK_FUNCTION(2, "SCP_SPI1_MI"), ++ MTK_FUNCTION(3, "IDDIG"), ++ MTK_FUNCTION(4, "ANT_SEL6"), ++ MTK_FUNCTION(5, "KPCOL2"), ++ MTK_FUNCTION(6, "PTA_RXD"), ++ MTK_FUNCTION(7, "DBG_MON_B19") ++ ), ++ MTK_PIN( ++ 162, "GPIO162", ++ MTK_EINT_FUNCTION(0, 162), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO162"), ++ MTK_FUNCTION(1, "SPI1_A_CSB"), ++ MTK_FUNCTION(2, "SCP_SPI1_CS"), ++ MTK_FUNCTION(3, "USB_DRVVBUS"), ++ MTK_FUNCTION(4, "ANT_SEL5"), ++ MTK_FUNCTION(5, "KPROW2"), ++ MTK_FUNCTION(6, "PTA_TXD") ++ ), ++ MTK_PIN( ++ 163, "GPIO163", ++ MTK_EINT_FUNCTION(0, 163), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO163"), ++ MTK_FUNCTION(1, "SPI1_A_MO"), ++ MTK_FUNCTION(2, "SCP_SPI1_MO"), ++ MTK_FUNCTION(3, "SDA1"), ++ MTK_FUNCTION(4, "ANT_SEL4"), ++ MTK_FUNCTION(5, "CMMCLK2"), ++ MTK_FUNCTION(6, "DMIC_CLK") ++ ), ++ MTK_PIN( ++ 164, "GPIO164", ++ MTK_EINT_FUNCTION(0, 164), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO164"), ++ MTK_FUNCTION(1, "SPI1_A_CLK"), ++ MTK_FUNCTION(2, "SCP_SPI1_CK"), ++ MTK_FUNCTION(3, "SCL1"), ++ MTK_FUNCTION(4, "ANT_SEL3"), ++ MTK_FUNCTION(5, "CMMCLK3"), ++ MTK_FUNCTION(6, "DMIC_DAT") ++ ), ++ MTK_PIN( ++ 165, "GPIO165", ++ MTK_EINT_FUNCTION(0, 165), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO165"), ++ MTK_FUNCTION(1, "PWM_B"), ++ MTK_FUNCTION(2, "CMMCLK2"), ++ MTK_FUNCTION(3, "SCP_VREQ_VAO"), ++ MTK_FUNCTION(6, "TDM_MCK_2ND"), ++ MTK_FUNCTION(7, "SCP_JTAG_TDO") ++ ), ++ MTK_PIN( ++ 166, "GPIO166", ++ MTK_EINT_FUNCTION(0, 166), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO166"), ++ MTK_FUNCTION(1, "ANT_SEL6") ++ ), ++ MTK_PIN( ++ 167, "GPIO167", ++ MTK_EINT_FUNCTION(0, 167), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO167"), ++ MTK_FUNCTION(1, "RFIC0_BSI_EN"), ++ MTK_FUNCTION(2, "SPM_BSI_EN") ++ ), ++ MTK_PIN( ++ 168, "GPIO168", ++ MTK_EINT_FUNCTION(0, 168), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO168"), ++ MTK_FUNCTION(1, "RFIC0_BSI_CK"), ++ MTK_FUNCTION(2, "SPM_BSI_CK") ++ ), ++ MTK_PIN( ++ 169, "GPIO169", ++ MTK_EINT_FUNCTION(0, 169), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO169"), ++ MTK_FUNCTION(1, "PWM_C"), ++ MTK_FUNCTION(2, "CMMCLK3"), ++ MTK_FUNCTION(3, "CMVREF1"), ++ MTK_FUNCTION(4, "ANT_SEL7"), ++ MTK_FUNCTION(5, "AGPS_SYNC"), ++ MTK_FUNCTION(6, "TDM_BCK_2ND"), ++ MTK_FUNCTION(7, "SCP_JTAG_TMS") ++ ), ++ MTK_PIN( ++ 170, "GPIO170", ++ MTK_EINT_FUNCTION(0, 170), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO170"), ++ MTK_FUNCTION(1, "I2S1_BCK"), ++ MTK_FUNCTION(2, "I2S3_BCK"), ++ MTK_FUNCTION(3, "SCL7"), ++ MTK_FUNCTION(4, "I2S5_BCK"), ++ MTK_FUNCTION(5, "EXT_FRAME_SYNC"), ++ MTK_FUNCTION(6, "TDM_LRCK_2ND"), ++ MTK_FUNCTION(7, "ANT_SEL3") ++ ), ++ MTK_PIN( ++ 171, "GPIO171", ++ MTK_EINT_FUNCTION(0, 184), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO171"), ++ MTK_FUNCTION(1, "I2S1_LRCK"), ++ MTK_FUNCTION(2, "I2S3_LRCK"), ++ MTK_FUNCTION(3, "SDA7"), ++ MTK_FUNCTION(4, "I2S5_LRCK"), ++ MTK_FUNCTION(5, "URXD1"), ++ MTK_FUNCTION(6, "TDM_DATA0_2ND"), ++ MTK_FUNCTION(7, "ANT_SEL4") ++ ), ++ MTK_PIN( ++ 172, "GPIO172", ++ MTK_EINT_FUNCTION(0, 185), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO172"), ++ MTK_FUNCTION(1, "I2S1_DO"), ++ MTK_FUNCTION(2, "I2S3_DO"), ++ MTK_FUNCTION(3, "SCL8"), ++ MTK_FUNCTION(4, "I2S5_DO"), ++ MTK_FUNCTION(5, "UTXD1"), ++ MTK_FUNCTION(6, "TDM_DATA1_2ND"), ++ MTK_FUNCTION(7, "ANT_SEL5") ++ ), ++ MTK_PIN( ++ 173, "GPIO173", ++ MTK_EINT_FUNCTION(0, 186), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO173"), ++ MTK_FUNCTION(1, "I2S1_MCK"), ++ MTK_FUNCTION(2, "I2S3_MCK"), ++ MTK_FUNCTION(3, "SDA8"), ++ MTK_FUNCTION(4, "I2S5_MCK"), ++ MTK_FUNCTION(5, "UCTS0"), ++ MTK_FUNCTION(6, "TDM_DATA2_2ND"), ++ MTK_FUNCTION(7, "ANT_SEL6") ++ ), ++ MTK_PIN( ++ 174, "GPIO174", ++ MTK_EINT_FUNCTION(0, 187), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO174"), ++ MTK_FUNCTION(1, "I2S2_DI"), ++ MTK_FUNCTION(2, "I2S0_DI"), ++ MTK_FUNCTION(3, "DVFSRC_EXT_REQ"), ++ MTK_FUNCTION(4, "I2S2_DI2"), ++ MTK_FUNCTION(5, "URTS0"), ++ MTK_FUNCTION(6, "TDM_DATA3_2ND"), ++ MTK_FUNCTION(7, "ANT_SEL7") ++ ), ++ MTK_PIN( ++ 175, "GPIO175", ++ MTK_EINT_FUNCTION(0, 188), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO175"), ++ MTK_FUNCTION(1, "ANT_SEL7") ++ ), ++ MTK_PIN( ++ 176, "GPIO176", ++ MTK_EINT_FUNCTION(0, 189), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO176") ++ ), ++ MTK_PIN( ++ 177, "GPIO177", ++ MTK_EINT_FUNCTION(0, 190), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO177") ++ ), ++ MTK_PIN( ++ 178, "GPIO178", ++ MTK_EINT_FUNCTION(0, 191), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO178") ++ ), ++ MTK_PIN( ++ 179, "GPIO179", ++ MTK_EINT_FUNCTION(0, 192), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO179") ++ ), ++ MTK_PIN( ++ 180, "GPIO180", ++ MTK_EINT_FUNCTION(0, 171), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO180") ++ ), ++ MTK_PIN( ++ 181, "GPIO181", ++ MTK_EINT_FUNCTION(0, 172), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO181") ++ ), ++ MTK_PIN( ++ 182, "GPIO182", ++ MTK_EINT_FUNCTION(0, 173), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO182") ++ ), ++ MTK_PIN( ++ 183, "GPIO183", ++ MTK_EINT_FUNCTION(0, 174), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO183") ++ ), ++ MTK_PIN( ++ 184, "GPIO184", ++ MTK_EINT_FUNCTION(0, 175), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO184") ++ ), ++ MTK_PIN( ++ 185, "GPIO185", ++ MTK_EINT_FUNCTION(0, 177), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO185") ++ ), ++ MTK_PIN( ++ 186, "GPIO186", ++ MTK_EINT_FUNCTION(0, 178), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO186") ++ ), ++ MTK_PIN( ++ 187, "GPIO187", ++ MTK_EINT_FUNCTION(0, 179), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO187") ++ ), ++ MTK_PIN( ++ 188, "GPIO188", ++ MTK_EINT_FUNCTION(0, 180), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO188") ++ ), ++ MTK_PIN( ++ 189, "GPIO189", ++ MTK_EINT_FUNCTION(0, 181), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO189") ++ ), ++ MTK_PIN( ++ 190, "GPIO190", ++ MTK_EINT_FUNCTION(0, 182), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO190") ++ ), ++ MTK_PIN( ++ 191, "GPIO191", ++ MTK_EINT_FUNCTION(0, 183), ++ DRV_GRP4, ++ MTK_FUNCTION(0, "GPIO191") ++ ), ++}; ++ ++#endif /* __PINCTRL_MTK_MT8183_H */ +diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h +new file mode 100644 +index 000000000000..f7a4c6e4a026 +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h +@@ -0,0 +1,1182 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2019 MediaTek Inc. ++ */ ++#ifndef __PINCTRL_MTK_MT8516_H ++#define __PINCTRL_MTK_MT8516_H ++ ++#include <linux/pinctrl/pinctrl.h> ++#include "pinctrl-mtk-common.h" ++ ++static const struct mtk_desc_pin mtk_pins_mt8516[] = { ++ MTK_PIN( ++ PINCTRL_PIN(0, "EINT0"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 0), ++ MTK_FUNCTION(0, "GPIO0"), ++ MTK_FUNCTION(1, "PWM_B"), ++ MTK_FUNCTION(3, "I2S2_BCK"), ++ MTK_FUNCTION(4, "EXT_TXD0"), ++ MTK_FUNCTION(6, "SQICS"), ++ MTK_FUNCTION(7, "DBG_MON_A[6]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(1, "EINT1"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 1), ++ MTK_FUNCTION(0, "GPIO1"), ++ MTK_FUNCTION(1, "PWM_C"), ++ MTK_FUNCTION(3, "I2S2_DI"), ++ MTK_FUNCTION(4, "EXT_TXD1"), ++ MTK_FUNCTION(5, "CONN_MCU_TDO"), ++ MTK_FUNCTION(6, "SQISO"), ++ MTK_FUNCTION(7, "DBG_MON_A[7]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(2, "EINT2"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 2), ++ MTK_FUNCTION(0, "GPIO2"), ++ MTK_FUNCTION(1, "CLKM0"), ++ MTK_FUNCTION(3, "I2S2_LRCK"), ++ MTK_FUNCTION(4, "EXT_TXD2"), ++ MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"), ++ MTK_FUNCTION(6, "SQISI"), ++ MTK_FUNCTION(7, "DBG_MON_A[8]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(3, "EINT3"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 3), ++ MTK_FUNCTION(0, "GPIO3"), ++ MTK_FUNCTION(1, "CLKM1"), ++ MTK_FUNCTION(3, "SPI_MI"), ++ MTK_FUNCTION(4, "EXT_TXD3"), ++ MTK_FUNCTION(5, "CONN_MCU_DBGI_N"), ++ MTK_FUNCTION(6, "SQIWP"), ++ MTK_FUNCTION(7, "DBG_MON_A[9]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(4, "EINT4"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 4), ++ MTK_FUNCTION(0, "GPIO4"), ++ MTK_FUNCTION(1, "CLKM2"), ++ MTK_FUNCTION(3, "SPI_MO"), ++ MTK_FUNCTION(4, "EXT_TXC"), ++ MTK_FUNCTION(5, "CONN_MCU_TCK"), ++ MTK_FUNCTION(6, "CONN_MCU_AICE_JCKC"), ++ MTK_FUNCTION(7, "DBG_MON_A[10]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(5, "EINT5"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 5), ++ MTK_FUNCTION(0, "GPIO5"), ++ MTK_FUNCTION(1, "UCTS2"), ++ MTK_FUNCTION(3, "SPI_CSB"), ++ MTK_FUNCTION(4, "EXT_RXER"), ++ MTK_FUNCTION(5, "CONN_MCU_TDI"), ++ MTK_FUNCTION(6, "CONN_TEST_CK"), ++ MTK_FUNCTION(7, "DBG_MON_A[11]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(6, "EINT6"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 6), ++ MTK_FUNCTION(0, "GPIO6"), ++ MTK_FUNCTION(1, "URTS2"), ++ MTK_FUNCTION(3, "SPI_CLK"), ++ MTK_FUNCTION(4, "EXT_RXC"), ++ MTK_FUNCTION(5, "CONN_MCU_TRST_B"), ++ MTK_FUNCTION(7, "DBG_MON_A[12]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(7, "EINT7"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 7), ++ MTK_FUNCTION(0, "GPIO7"), ++ MTK_FUNCTION(1, "SQIRST"), ++ MTK_FUNCTION(3, "SDA1_0"), ++ MTK_FUNCTION(4, "EXT_RXDV"), ++ MTK_FUNCTION(5, "CONN_MCU_TMS"), ++ MTK_FUNCTION(6, "CONN_MCU_AICE_JMSC"), ++ MTK_FUNCTION(7, "DBG_MON_A[13]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(8, "EINT8"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 8), ++ MTK_FUNCTION(0, "GPIO8"), ++ MTK_FUNCTION(1, "SQICK"), ++ MTK_FUNCTION(2, "CLKM3"), ++ MTK_FUNCTION(3, "SCL1_0"), ++ MTK_FUNCTION(4, "EXT_RXD0"), ++ MTK_FUNCTION(5, "ANT_SEL0"), ++ MTK_FUNCTION(7, "DBG_MON_A[14]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(9, "EINT9"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 9), ++ MTK_FUNCTION(0, "GPIO9"), ++ MTK_FUNCTION(1, "CLKM4"), ++ MTK_FUNCTION(2, "SDA2_0"), ++ MTK_FUNCTION(3, "EXT_FRAME_SYNC"), ++ MTK_FUNCTION(4, "EXT_RXD1"), ++ MTK_FUNCTION(5, "ANT_SEL1"), ++ MTK_FUNCTION(7, "DBG_MON_A[15]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(10, "EINT10"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 10), ++ MTK_FUNCTION(0, "GPIO10"), ++ MTK_FUNCTION(1, "CLKM5"), ++ MTK_FUNCTION(2, "SCL2_0"), ++ MTK_FUNCTION(3, "EXT_FRAME_SYNC"), ++ MTK_FUNCTION(4, "EXT_RXD2"), ++ MTK_FUNCTION(5, "ANT_SEL2"), ++ MTK_FUNCTION(7, "DBG_MON_A[16]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(11, "EINT11"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 11), ++ MTK_FUNCTION(0, "GPIO11"), ++ MTK_FUNCTION(1, "CLKM4"), ++ MTK_FUNCTION(2, "PWM_C"), ++ MTK_FUNCTION(3, "CONN_TEST_CK"), ++ MTK_FUNCTION(4, "ANT_SEL3"), ++ MTK_FUNCTION(6, "EXT_RXD3"), ++ MTK_FUNCTION(7, "DBG_MON_A[17]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(12, "EINT12"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 12), ++ MTK_FUNCTION(0, "GPIO12"), ++ MTK_FUNCTION(1, "CLKM5"), ++ MTK_FUNCTION(2, "PWM_A"), ++ MTK_FUNCTION(3, "SPDIF_OUT"), ++ MTK_FUNCTION(4, "ANT_SEL4"), ++ MTK_FUNCTION(6, "EXT_TXEN"), ++ MTK_FUNCTION(7, "DBG_MON_A[18]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(13, "EINT13"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 13), ++ MTK_FUNCTION(0, "GPIO13"), ++ MTK_FUNCTION(3, "TSF_IN"), ++ MTK_FUNCTION(4, "ANT_SEL5"), ++ MTK_FUNCTION(6, "SPDIF_IN"), ++ MTK_FUNCTION(7, "DBG_MON_A[19]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(14, "EINT14"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 14), ++ MTK_FUNCTION(0, "GPIO14"), ++ MTK_FUNCTION(2, "I2S_8CH_DO1"), ++ MTK_FUNCTION(3, "TDM_RX_MCK"), ++ MTK_FUNCTION(4, "ANT_SEL1"), ++ MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"), ++ MTK_FUNCTION(6, "NCLE"), ++ MTK_FUNCTION(7, "DBG_MON_B[8]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(15, "EINT15"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 15), ++ MTK_FUNCTION(0, "GPIO15"), ++ MTK_FUNCTION(2, "I2S_8CH_LRCK"), ++ MTK_FUNCTION(3, "TDM_RX_BCK"), ++ MTK_FUNCTION(4, "ANT_SEL2"), ++ MTK_FUNCTION(5, "CONN_MCU_DBGI_N"), ++ MTK_FUNCTION(6, "NCEB1"), ++ MTK_FUNCTION(7, "DBG_MON_B[9]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(16, "EINT16"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 16), ++ MTK_FUNCTION(0, "GPIO16"), ++ MTK_FUNCTION(2, "I2S_8CH_BCK"), ++ MTK_FUNCTION(3, "TDM_RX_LRCK"), ++ MTK_FUNCTION(4, "ANT_SEL3"), ++ MTK_FUNCTION(5, "CONN_MCU_TRST_B"), ++ MTK_FUNCTION(6, "NCEB0"), ++ MTK_FUNCTION(7, "DBG_MON_B[10]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(17, "EINT17"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 17), ++ MTK_FUNCTION(0, "GPIO17"), ++ MTK_FUNCTION(2, "I2S_8CH_MCK"), ++ MTK_FUNCTION(3, "TDM_RX_DI"), ++ MTK_FUNCTION(4, "IDDIG"), ++ MTK_FUNCTION(5, "ANT_SEL4"), ++ MTK_FUNCTION(6, "NREB"), ++ MTK_FUNCTION(7, "DBG_MON_B[11]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(18, "EINT18"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 18), ++ MTK_FUNCTION(0, "GPIO18"), ++ MTK_FUNCTION(2, "USB_DRVVBUS"), ++ MTK_FUNCTION(3, "I2S3_LRCK"), ++ MTK_FUNCTION(4, "CLKM1"), ++ MTK_FUNCTION(5, "ANT_SEL3"), ++ MTK_FUNCTION(6, "I2S2_BCK"), ++ MTK_FUNCTION(7, "DBG_MON_A[20]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(19, "EINT19"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 19), ++ MTK_FUNCTION(0, "GPIO19"), ++ MTK_FUNCTION(1, "UCTS1"), ++ MTK_FUNCTION(2, "IDDIG"), ++ MTK_FUNCTION(3, "I2S3_BCK"), ++ MTK_FUNCTION(4, "CLKM2"), ++ MTK_FUNCTION(5, "ANT_SEL4"), ++ MTK_FUNCTION(6, "I2S2_DI"), ++ MTK_FUNCTION(7, "DBG_MON_A[21]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(20, "EINT20"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 20), ++ MTK_FUNCTION(0, "GPIO20"), ++ MTK_FUNCTION(1, "URTS1"), ++ MTK_FUNCTION(3, "I2S3_DO"), ++ MTK_FUNCTION(4, "CLKM3"), ++ MTK_FUNCTION(5, "ANT_SEL5"), ++ MTK_FUNCTION(6, "I2S2_LRCK"), ++ MTK_FUNCTION(7, "DBG_MON_A[22]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(21, "EINT21"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 21), ++ MTK_FUNCTION(0, "GPIO21"), ++ MTK_FUNCTION(1, "NRNB"), ++ MTK_FUNCTION(2, "ANT_SEL0"), ++ MTK_FUNCTION(3, "I2S_8CH_DO4"), ++ MTK_FUNCTION(7, "DBG_MON_B[31]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(22, "EINT22"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 22), ++ MTK_FUNCTION(0, "GPIO22"), ++ MTK_FUNCTION(2, "I2S_8CH_DO2"), ++ MTK_FUNCTION(3, "TSF_IN"), ++ MTK_FUNCTION(4, "USB_DRVVBUS"), ++ MTK_FUNCTION(5, "SPDIF_OUT"), ++ MTK_FUNCTION(6, "NRE_C"), ++ MTK_FUNCTION(7, "DBG_MON_B[12]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(23, "EINT23"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 23), ++ MTK_FUNCTION(0, "GPIO23"), ++ MTK_FUNCTION(2, "I2S_8CH_DO3"), ++ MTK_FUNCTION(3, "CLKM0"), ++ MTK_FUNCTION(4, "IR"), ++ MTK_FUNCTION(5, "SPDIF_IN"), ++ MTK_FUNCTION(6, "NDQS_C"), ++ MTK_FUNCTION(7, "DBG_MON_B[13]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(24, "EINT24"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 24), ++ MTK_FUNCTION(0, "GPIO24"), ++ MTK_FUNCTION(3, "ANT_SEL1"), ++ MTK_FUNCTION(4, "UCTS2"), ++ MTK_FUNCTION(5, "PWM_A"), ++ MTK_FUNCTION(6, "I2S0_MCK"), ++ MTK_FUNCTION(7, "DBG_MON_A[0]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(25, "EINT25"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 25), ++ MTK_FUNCTION(0, "GPIO25"), ++ MTK_FUNCTION(3, "ANT_SEL0"), ++ MTK_FUNCTION(4, "URTS2"), ++ MTK_FUNCTION(5, "PWM_B"), ++ MTK_FUNCTION(6, "I2S_8CH_MCK"), ++ MTK_FUNCTION(7, "DBG_MON_A[1]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(26, "PWRAP_SPI0_MI"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 26), ++ MTK_FUNCTION(0, "GPIO26"), ++ MTK_FUNCTION(1, "PWRAP_SPI0_MO"), ++ MTK_FUNCTION(2, "PWRAP_SPI0_MI") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(27, "PWRAP_SPI0_MO"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 27), ++ MTK_FUNCTION(0, "GPIO27"), ++ MTK_FUNCTION(1, "PWRAP_SPI0_MI"), ++ MTK_FUNCTION(2, "PWRAP_SPI0_MO") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(28, "PWRAP_INT"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 28), ++ MTK_FUNCTION(0, "GPIO28"), ++ MTK_FUNCTION(1, "I2S0_MCK"), ++ MTK_FUNCTION(4, "I2S_8CH_MCK"), ++ MTK_FUNCTION(5, "I2S2_MCK"), ++ MTK_FUNCTION(6, "I2S3_MCK") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(29, "PWRAP_SPI0_CK"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 29), ++ MTK_FUNCTION(0, "GPIO29"), ++ MTK_FUNCTION(1, "PWRAP_SPI0_CK") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(30, "PWRAP_SPI0_CSN"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 30), ++ MTK_FUNCTION(0, "GPIO30"), ++ MTK_FUNCTION(1, "PWRAP_SPI0_CSN") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(31, "RTC32K_CK"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 31), ++ MTK_FUNCTION(0, "GPIO31"), ++ MTK_FUNCTION(1, "RTC32K_CK") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(32, "WATCHDOG"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 32), ++ MTK_FUNCTION(0, "GPIO32"), ++ MTK_FUNCTION(1, "WATCHDOG") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(33, "SRCLKENA"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 33), ++ MTK_FUNCTION(0, "GPIO33"), ++ MTK_FUNCTION(1, "SRCLKENA0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(34, "URXD2"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 34), ++ MTK_FUNCTION(0, "GPIO34"), ++ MTK_FUNCTION(1, "URXD2"), ++ MTK_FUNCTION(3, "UTXD2"), ++ MTK_FUNCTION(4, "DBG_SCL"), ++ MTK_FUNCTION(6, "I2S2_MCK"), ++ MTK_FUNCTION(7, "DBG_MON_B[0]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(35, "UTXD2"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 35), ++ MTK_FUNCTION(0, "GPIO35"), ++ MTK_FUNCTION(1, "UTXD2"), ++ MTK_FUNCTION(3, "URXD2"), ++ MTK_FUNCTION(4, "DBG_SDA"), ++ MTK_FUNCTION(6, "I2S3_MCK"), ++ MTK_FUNCTION(7, "DBG_MON_B[1]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(36, "MRG_CLK"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 36), ++ MTK_FUNCTION(0, "GPIO36"), ++ MTK_FUNCTION(1, "MRG_CLK"), ++ MTK_FUNCTION(3, "I2S0_BCK"), ++ MTK_FUNCTION(4, "I2S3_BCK"), ++ MTK_FUNCTION(5, "PCM0_CLK"), ++ MTK_FUNCTION(6, "IR"), ++ MTK_FUNCTION(7, "DBG_MON_A[2]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(37, "MRG_SYNC"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 37), ++ MTK_FUNCTION(0, "GPIO37"), ++ MTK_FUNCTION(1, "MRG_SYNC"), ++ MTK_FUNCTION(3, "I2S0_LRCK"), ++ MTK_FUNCTION(4, "I2S3_LRCK"), ++ MTK_FUNCTION(5, "PCM0_SYNC"), ++ MTK_FUNCTION(6, "EXT_COL"), ++ MTK_FUNCTION(7, "DBG_MON_A[3]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(38, "MRG_DI"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 38), ++ MTK_FUNCTION(0, "GPIO38"), ++ MTK_FUNCTION(1, "MRG_DI"), ++ MTK_FUNCTION(3, "I2S0_DI"), ++ MTK_FUNCTION(4, "I2S3_DO"), ++ MTK_FUNCTION(5, "PCM0_DI"), ++ MTK_FUNCTION(6, "EXT_MDIO"), ++ MTK_FUNCTION(7, "DBG_MON_A[4]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(39, "MRG_DO"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 39), ++ MTK_FUNCTION(0, "GPIO39"), ++ MTK_FUNCTION(1, "MRG_DO"), ++ MTK_FUNCTION(3, "I2S0_MCK"), ++ MTK_FUNCTION(4, "I2S3_MCK"), ++ MTK_FUNCTION(5, "PCM0_DO"), ++ MTK_FUNCTION(6, "EXT_MDC"), ++ MTK_FUNCTION(7, "DBG_MON_A[5]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(40, "KPROW0"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 40), ++ MTK_FUNCTION(0, "GPIO40"), ++ MTK_FUNCTION(1, "KPROW0"), ++ MTK_FUNCTION(7, "DBG_MON_B[4]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(41, "KPROW1"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 41), ++ MTK_FUNCTION(0, "GPIO41"), ++ MTK_FUNCTION(1, "KPROW1"), ++ MTK_FUNCTION(2, "IDDIG"), ++ MTK_FUNCTION(3, "EXT_FRAME_SYNC"), ++ MTK_FUNCTION(7, "DBG_MON_B[5]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(42, "KPCOL0"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 42), ++ MTK_FUNCTION(0, "GPIO42"), ++ MTK_FUNCTION(1, "KPCOL0"), ++ MTK_FUNCTION(7, "DBG_MON_B[6]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(43, "KPCOL1"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 43), ++ MTK_FUNCTION(0, "GPIO43"), ++ MTK_FUNCTION(1, "KPCOL1"), ++ MTK_FUNCTION(2, "USB_DRVVBUS"), ++ MTK_FUNCTION(3, "EXT_FRAME_SYNC"), ++ MTK_FUNCTION(4, "TSF_IN"), ++ MTK_FUNCTION(7, "DBG_MON_B[7]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(44, "JTMS"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 44), ++ MTK_FUNCTION(0, "GPIO44"), ++ MTK_FUNCTION(1, "JTMS"), ++ MTK_FUNCTION(2, "CONN_MCU_TMS"), ++ MTK_FUNCTION(3, "CONN_MCU_AICE_JMSC") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(45, "JTCK"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 45), ++ MTK_FUNCTION(0, "GPIO45"), ++ MTK_FUNCTION(1, "JTCK"), ++ MTK_FUNCTION(2, "CONN_MCU_TCK"), ++ MTK_FUNCTION(3, "CONN_MCU_AICE_JCKC") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(46, "JTDI"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 46), ++ MTK_FUNCTION(0, "GPIO46"), ++ MTK_FUNCTION(1, "JTDI"), ++ MTK_FUNCTION(2, "CONN_MCU_TDI") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(47, "JTDO"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 47), ++ MTK_FUNCTION(0, "GPIO47"), ++ MTK_FUNCTION(1, "JTDO"), ++ MTK_FUNCTION(2, "CONN_MCU_TDO") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(48, "SPI_CS"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 48), ++ MTK_FUNCTION(0, "GPIO48"), ++ MTK_FUNCTION(1, "SPI_CSB"), ++ MTK_FUNCTION(3, "I2S0_DI"), ++ MTK_FUNCTION(4, "I2S2_BCK"), ++ MTK_FUNCTION(7, "DBG_MON_A[23]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(49, "SPI_CK"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 49), ++ MTK_FUNCTION(0, "GPIO49"), ++ MTK_FUNCTION(1, "SPI_CLK"), ++ MTK_FUNCTION(3, "I2S0_LRCK"), ++ MTK_FUNCTION(4, "I2S2_DI"), ++ MTK_FUNCTION(7, "DBG_MON_A[24]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(50, "SPI_MI"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 50), ++ MTK_FUNCTION(0, "GPIO50"), ++ MTK_FUNCTION(1, "SPI_MI"), ++ MTK_FUNCTION(2, "SPI_MO"), ++ MTK_FUNCTION(3, "I2S0_BCK"), ++ MTK_FUNCTION(4, "I2S2_LRCK"), ++ MTK_FUNCTION(7, "DBG_MON_A[25]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(51, "SPI_MO"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 51), ++ MTK_FUNCTION(0, "GPIO51"), ++ MTK_FUNCTION(1, "SPI_MO"), ++ MTK_FUNCTION(2, "SPI_MI"), ++ MTK_FUNCTION(3, "I2S0_MCK"), ++ MTK_FUNCTION(4, "I2S2_MCK"), ++ MTK_FUNCTION(7, "DBG_MON_A[26]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(52, "SDA1"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 52), ++ MTK_FUNCTION(0, "GPIO52"), ++ MTK_FUNCTION(1, "SDA1_0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(53, "SCL1"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 53), ++ MTK_FUNCTION(0, "GPIO53"), ++ MTK_FUNCTION(1, "SCL1_0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(54, "GPIO54"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 54), ++ MTK_FUNCTION(0, "GPIO54"), ++ MTK_FUNCTION(2, "PWM_B"), ++ MTK_FUNCTION(7, "DBG_MON_B[2]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(55, "I2S_DATA_IN"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 55), ++ MTK_FUNCTION(0, "GPIO55"), ++ MTK_FUNCTION(1, "I2S0_DI"), ++ MTK_FUNCTION(2, "UCTS0"), ++ MTK_FUNCTION(3, "I2S3_DO"), ++ MTK_FUNCTION(4, "I2S_8CH_DO1"), ++ MTK_FUNCTION(5, "PWM_A"), ++ MTK_FUNCTION(6, "I2S2_BCK"), ++ MTK_FUNCTION(7, "DBG_MON_A[28]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(56, "I2S_LRCK"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 56), ++ MTK_FUNCTION(0, "GPIO56"), ++ MTK_FUNCTION(1, "I2S0_LRCK"), ++ MTK_FUNCTION(3, "I2S3_LRCK"), ++ MTK_FUNCTION(4, "I2S_8CH_LRCK"), ++ MTK_FUNCTION(5, "PWM_B"), ++ MTK_FUNCTION(6, "I2S2_DI"), ++ MTK_FUNCTION(7, "DBG_MON_A[29]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(57, "I2S_BCK"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 57), ++ MTK_FUNCTION(0, "GPIO57"), ++ MTK_FUNCTION(1, "I2S0_BCK"), ++ MTK_FUNCTION(2, "URTS0"), ++ MTK_FUNCTION(3, "I2S3_BCK"), ++ MTK_FUNCTION(4, "I2S_8CH_BCK"), ++ MTK_FUNCTION(5, "PWM_C"), ++ MTK_FUNCTION(6, "I2S2_LRCK"), ++ MTK_FUNCTION(7, "DBG_MON_A[30]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(58, "SDA0"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 58), ++ MTK_FUNCTION(0, "GPIO58"), ++ MTK_FUNCTION(1, "SDA0_0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(59, "SCL0"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 59), ++ MTK_FUNCTION(0, "GPIO59"), ++ MTK_FUNCTION(1, "SCL0_0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(60, "SDA2"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 60), ++ MTK_FUNCTION(0, "GPIO60"), ++ MTK_FUNCTION(1, "SDA2_0"), ++ MTK_FUNCTION(2, "PWM_B") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(61, "SCL2"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 61), ++ MTK_FUNCTION(0, "GPIO61"), ++ MTK_FUNCTION(1, "SCL2_0"), ++ MTK_FUNCTION(2, "PWM_C") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(62, "URXD0"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 62), ++ MTK_FUNCTION(0, "GPIO62"), ++ MTK_FUNCTION(1, "URXD0"), ++ MTK_FUNCTION(2, "UTXD0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(63, "UTXD0"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 63), ++ MTK_FUNCTION(0, "GPIO63"), ++ MTK_FUNCTION(1, "UTXD0"), ++ MTK_FUNCTION(2, "URXD0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(64, "URXD1"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 64), ++ MTK_FUNCTION(0, "GPIO64"), ++ MTK_FUNCTION(1, "URXD1"), ++ MTK_FUNCTION(2, "UTXD1"), ++ MTK_FUNCTION(7, "DBG_MON_A[27]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(65, "UTXD1"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 65), ++ MTK_FUNCTION(0, "GPIO65"), ++ MTK_FUNCTION(1, "UTXD1"), ++ MTK_FUNCTION(2, "URXD1"), ++ MTK_FUNCTION(7, "DBG_MON_A[31]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(66, "LCM_RST"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 66), ++ MTK_FUNCTION(0, "GPIO66"), ++ MTK_FUNCTION(1, "LCM_RST"), ++ MTK_FUNCTION(3, "I2S0_MCK"), ++ MTK_FUNCTION(7, "DBG_MON_B[3]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(67, "GPIO67"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 67), ++ MTK_FUNCTION(0, "GPIO67"), ++ MTK_FUNCTION(3, "I2S_8CH_MCK"), ++ MTK_FUNCTION(7, "DBG_MON_B[14]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(68, "MSDC2_CMD"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 68), ++ MTK_FUNCTION(0, "GPIO68"), ++ MTK_FUNCTION(1, "MSDC2_CMD"), ++ MTK_FUNCTION(2, "I2S_8CH_DO4"), ++ MTK_FUNCTION(3, "SDA1_0"), ++ MTK_FUNCTION(5, "USB_SDA"), ++ MTK_FUNCTION(6, "I2S3_BCK"), ++ MTK_FUNCTION(7, "DBG_MON_B[15]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(69, "MSDC2_CLK"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 69), ++ MTK_FUNCTION(0, "GPIO69"), ++ MTK_FUNCTION(1, "MSDC2_CLK"), ++ MTK_FUNCTION(2, "I2S_8CH_DO3"), ++ MTK_FUNCTION(3, "SCL1_0"), ++ MTK_FUNCTION(5, "USB_SCL"), ++ MTK_FUNCTION(6, "I2S3_LRCK"), ++ MTK_FUNCTION(7, "DBG_MON_B[16]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(70, "MSDC2_DAT0"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 70), ++ MTK_FUNCTION(0, "GPIO70"), ++ MTK_FUNCTION(1, "MSDC2_DAT0"), ++ MTK_FUNCTION(2, "I2S_8CH_DO2"), ++ MTK_FUNCTION(5, "UTXD0"), ++ MTK_FUNCTION(6, "I2S3_DO"), ++ MTK_FUNCTION(7, "DBG_MON_B[17]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(71, "MSDC2_DAT1"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 71), ++ MTK_FUNCTION(0, "GPIO71"), ++ MTK_FUNCTION(1, "MSDC2_DAT1"), ++ MTK_FUNCTION(2, "I2S_8CH_DO1"), ++ MTK_FUNCTION(3, "PWM_A"), ++ MTK_FUNCTION(4, "I2S3_MCK"), ++ MTK_FUNCTION(5, "URXD0"), ++ MTK_FUNCTION(6, "PWM_B"), ++ MTK_FUNCTION(7, "DBG_MON_B[18]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(72, "MSDC2_DAT2"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 72), ++ MTK_FUNCTION(0, "GPIO72"), ++ MTK_FUNCTION(1, "MSDC2_DAT2"), ++ MTK_FUNCTION(2, "I2S_8CH_LRCK"), ++ MTK_FUNCTION(3, "SDA2_0"), ++ MTK_FUNCTION(5, "UTXD1"), ++ MTK_FUNCTION(6, "PWM_C"), ++ MTK_FUNCTION(7, "DBG_MON_B[19]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(73, "MSDC2_DAT3"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 73), ++ MTK_FUNCTION(0, "GPIO73"), ++ MTK_FUNCTION(1, "MSDC2_DAT3"), ++ MTK_FUNCTION(2, "I2S_8CH_BCK"), ++ MTK_FUNCTION(3, "SCL2_0"), ++ MTK_FUNCTION(4, "EXT_FRAME_SYNC"), ++ MTK_FUNCTION(5, "URXD1"), ++ MTK_FUNCTION(6, "PWM_A"), ++ MTK_FUNCTION(7, "DBG_MON_B[20]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(74, "TDN3"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 74), ++ MTK_FUNCTION(0, "GPIO74"), ++ MTK_FUNCTION(1, "TDN3") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(75, "TDP3"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 75), ++ MTK_FUNCTION(0, "GPIO75"), ++ MTK_FUNCTION(1, "TDP3") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(76, "TDN2"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 76), ++ MTK_FUNCTION(0, "GPIO76"), ++ MTK_FUNCTION(1, "TDN2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(77, "TDP2"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 77), ++ MTK_FUNCTION(0, "GPIO77"), ++ MTK_FUNCTION(1, "TDP2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(78, "TCN"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 78), ++ MTK_FUNCTION(0, "GPIO78"), ++ MTK_FUNCTION(1, "TCN") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(79, "TCP"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 79), ++ MTK_FUNCTION(0, "GPIO79"), ++ MTK_FUNCTION(1, "TCP") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(80, "TDN1"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 80), ++ MTK_FUNCTION(0, "GPIO80"), ++ MTK_FUNCTION(1, "TDN1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(81, "TDP1"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 81), ++ MTK_FUNCTION(0, "GPIO81"), ++ MTK_FUNCTION(1, "TDP1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(82, "TDN0"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 82), ++ MTK_FUNCTION(0, "GPIO82"), ++ MTK_FUNCTION(1, "TDN0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(83, "TDP0"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 83), ++ MTK_FUNCTION(0, "GPIO83"), ++ MTK_FUNCTION(1, "TDP0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(84, "RDN0"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 84), ++ MTK_FUNCTION(0, "GPIO84"), ++ MTK_FUNCTION(1, "RDN0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(85, "RDP0"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 85), ++ MTK_FUNCTION(0, "GPIO85"), ++ MTK_FUNCTION(1, "RDP0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(86, "RDN1"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 86), ++ MTK_FUNCTION(0, "GPIO86"), ++ MTK_FUNCTION(1, "RDN1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(87, "RDP1"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 87), ++ MTK_FUNCTION(0, "GPIO87"), ++ MTK_FUNCTION(1, "RDP1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(88, "RCN"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 88), ++ MTK_FUNCTION(0, "GPIO88"), ++ MTK_FUNCTION(1, "RCN") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(89, "RCP"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 89), ++ MTK_FUNCTION(0, "GPIO89"), ++ MTK_FUNCTION(1, "RCP") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(90, "RDN2"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 90), ++ MTK_FUNCTION(0, "GPIO90"), ++ MTK_FUNCTION(1, "RDN2"), ++ MTK_FUNCTION(2, "CMDAT8") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(91, "RDP2"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 91), ++ MTK_FUNCTION(0, "GPIO91"), ++ MTK_FUNCTION(1, "RDP2"), ++ MTK_FUNCTION(2, "CMDAT9") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(92, "RDN3"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 92), ++ MTK_FUNCTION(0, "GPIO92"), ++ MTK_FUNCTION(1, "RDN3"), ++ MTK_FUNCTION(2, "CMDAT4") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(93, "RDP3"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 93), ++ MTK_FUNCTION(0, "GPIO93"), ++ MTK_FUNCTION(1, "RDP3"), ++ MTK_FUNCTION(2, "CMDAT5") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(94, "RCN_A"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 94), ++ MTK_FUNCTION(0, "GPIO94"), ++ MTK_FUNCTION(1, "RCN_A"), ++ MTK_FUNCTION(2, "CMDAT6") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(95, "RCP_A"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 95), ++ MTK_FUNCTION(0, "GPIO95"), ++ MTK_FUNCTION(1, "RCP_A"), ++ MTK_FUNCTION(2, "CMDAT7") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(96, "RDN1_A"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 96), ++ MTK_FUNCTION(0, "GPIO96"), ++ MTK_FUNCTION(1, "RDN1_A"), ++ MTK_FUNCTION(2, "CMDAT2"), ++ MTK_FUNCTION(3, "CMCSD2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(97, "RDP1_A"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 97), ++ MTK_FUNCTION(0, "GPIO97"), ++ MTK_FUNCTION(1, "RDP1_A"), ++ MTK_FUNCTION(2, "CMDAT3"), ++ MTK_FUNCTION(3, "CMCSD3") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(98, "RDN0_A"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 98), ++ MTK_FUNCTION(0, "GPIO98"), ++ MTK_FUNCTION(1, "RDN0_A"), ++ MTK_FUNCTION(2, "CMHSYNC") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(99, "RDP0_A"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 99), ++ MTK_FUNCTION(0, "GPIO99"), ++ MTK_FUNCTION(1, "RDP0_A"), ++ MTK_FUNCTION(2, "CMVSYNC") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(100, "CMDAT0"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 100), ++ MTK_FUNCTION(0, "GPIO100"), ++ MTK_FUNCTION(1, "CMDAT0"), ++ MTK_FUNCTION(2, "CMCSD0"), ++ MTK_FUNCTION(3, "ANT_SEL2"), ++ MTK_FUNCTION(5, "TDM_RX_MCK"), ++ MTK_FUNCTION(7, "DBG_MON_B[21]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(101, "CMDAT1"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 101), ++ MTK_FUNCTION(0, "GPIO101"), ++ MTK_FUNCTION(1, "CMDAT1"), ++ MTK_FUNCTION(2, "CMCSD1"), ++ MTK_FUNCTION(3, "ANT_SEL3"), ++ MTK_FUNCTION(4, "CMFLASH"), ++ MTK_FUNCTION(5, "TDM_RX_BCK"), ++ MTK_FUNCTION(7, "DBG_MON_B[22]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(102, "CMMCLK"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 102), ++ MTK_FUNCTION(0, "GPIO102"), ++ MTK_FUNCTION(1, "CMMCLK"), ++ MTK_FUNCTION(3, "ANT_SEL4"), ++ MTK_FUNCTION(5, "TDM_RX_LRCK"), ++ MTK_FUNCTION(7, "DBG_MON_B[23]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(103, "CMPCLK"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 103), ++ MTK_FUNCTION(0, "GPIO103"), ++ MTK_FUNCTION(1, "CMPCLK"), ++ MTK_FUNCTION(2, "CMCSK"), ++ MTK_FUNCTION(3, "ANT_SEL5"), ++ MTK_FUNCTION(5, " TDM_RX_DI"), ++ MTK_FUNCTION(7, "DBG_MON_B[24]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(104, "MSDC1_CMD"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 104), ++ MTK_FUNCTION(0, "GPIO104"), ++ MTK_FUNCTION(1, "MSDC1_CMD"), ++ MTK_FUNCTION(4, "SQICS"), ++ MTK_FUNCTION(7, "DBG_MON_B[25]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(105, "MSDC1_CLK"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 105), ++ MTK_FUNCTION(0, "GPIO105"), ++ MTK_FUNCTION(1, "MSDC1_CLK"), ++ MTK_FUNCTION(4, "SQISO"), ++ MTK_FUNCTION(7, "DBG_MON_B[26]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(106, "MSDC1_DAT0"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 106), ++ MTK_FUNCTION(0, "GPIO106"), ++ MTK_FUNCTION(1, "MSDC1_DAT0"), ++ MTK_FUNCTION(4, "SQISI"), ++ MTK_FUNCTION(7, "DBG_MON_B[27]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(107, "MSDC1_DAT1"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 107), ++ MTK_FUNCTION(0, "GPIO107"), ++ MTK_FUNCTION(1, "MSDC1_DAT1"), ++ MTK_FUNCTION(4, "SQIWP"), ++ MTK_FUNCTION(7, "DBG_MON_B[28]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(108, "MSDC1_DAT2"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 108), ++ MTK_FUNCTION(0, "GPIO108"), ++ MTK_FUNCTION(1, "MSDC1_DAT2"), ++ MTK_FUNCTION(4, "SQIRST"), ++ MTK_FUNCTION(7, "DBG_MON_B[29]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(109, "MSDC1_DAT3"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 109), ++ MTK_FUNCTION(0, "GPIO109"), ++ MTK_FUNCTION(1, "MSDC1_DAT3"), ++ MTK_FUNCTION(4, "SQICK"), /* WIP */ ++ MTK_FUNCTION(7, "DBG_MON_B[30]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(110, "MSDC0_DAT7"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 110), ++ MTK_FUNCTION(0, "GPIO110"), ++ MTK_FUNCTION(1, "MSDC0_DAT7"), ++ MTK_FUNCTION(4, "NLD7") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(111, "MSDC0_DAT6"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 111), ++ MTK_FUNCTION(0, "GPIO111"), ++ MTK_FUNCTION(1, "MSDC0_DAT6"), ++ MTK_FUNCTION(4, "NLD6") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(112, "MSDC0_DAT5"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 112), ++ MTK_FUNCTION(0, "GPIO112"), ++ MTK_FUNCTION(1, "MSDC0_DAT5"), ++ MTK_FUNCTION(4, "NLD4") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(113, "MSDC0_DAT4"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 113), ++ MTK_FUNCTION(0, "GPIO113"), ++ MTK_FUNCTION(1, "MSDC0_DAT4"), ++ MTK_FUNCTION(4, "NLD3") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(114, "MSDC0_RSTB"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 114), ++ MTK_FUNCTION(0, "GPIO114"), ++ MTK_FUNCTION(1, "MSDC0_RSTB"), ++ MTK_FUNCTION(4, "NLD0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(115, "MSDC0_CMD"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 115), ++ MTK_FUNCTION(0, "GPIO115"), ++ MTK_FUNCTION(1, "MSDC0_CMD"), ++ MTK_FUNCTION(4, "NALE") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(116, "MSDC0_CLK"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 116), ++ MTK_FUNCTION(0, "GPIO116"), ++ MTK_FUNCTION(1, "MSDC0_CLK"), ++ MTK_FUNCTION(4, "NWEB") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(117, "MSDC0_DAT3"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 117), ++ MTK_FUNCTION(0, "GPIO117"), ++ MTK_FUNCTION(1, "MSDC0_DAT3"), ++ MTK_FUNCTION(4, "NLD1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(118, "MSDC0_DAT2"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 118), ++ MTK_FUNCTION(0, "GPIO118"), ++ MTK_FUNCTION(1, "MSDC0_DAT2"), ++ MTK_FUNCTION(4, "NLD5") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(119, "MSDC0_DAT1"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 119), ++ MTK_FUNCTION(0, "GPIO119"), ++ MTK_FUNCTION(1, "MSDC0_DAT1"), ++ MTK_FUNCTION(4, "NLD8") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(120, "MSDC0_DAT0"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 120), ++ MTK_FUNCTION(0, "GPIO120"), ++ MTK_FUNCTION(1, "MSDC0_DAT0"), ++ MTK_FUNCTION(4, "WATCHDOG"), ++ MTK_FUNCTION(5, "NLD2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(121, "GPIO121"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 121), ++ MTK_FUNCTION(0, "GPIO121") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(122, "GPIO122"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 122), ++ MTK_FUNCTION(0, "GPIO122") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(123, "GPIO123"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 123), ++ MTK_FUNCTION(0, "GPIO123") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(124, "GPIO124"), ++ NULL, "mt8516", ++ MTK_EINT_FUNCTION(0, 124), ++ MTK_FUNCTION(0, "GPIO124") ++ ), ++}; ++ ++#endif /* __PINCTRL_MTK_MT8516_H */ +diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c +new file mode 100644 +index 000000000000..923264d0e9ef +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-paris.c +@@ -0,0 +1,947 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * MediaTek Pinctrl Paris Driver, which implement the vendor per-pin ++ * bindings for MediaTek SoC. ++ * ++ * Copyright (C) 2018 MediaTek Inc. ++ * Author: Sean Wang <sean.wang@mediatek.com> ++ * Zhiyong Tao <zhiyong.tao@mediatek.com> ++ * Hongzhou.Yang <hongzhou.yang@mediatek.com> ++ */ ++ ++#include <linux/gpio/driver.h> ++#include <dt-bindings/pinctrl/mt65xx.h> ++#include "pinctrl-paris.h" ++ ++#define PINCTRL_PINCTRL_DEV KBUILD_MODNAME ++ ++/* Custom pinconf parameters */ ++#define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1) ++#define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2) ++#define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3) ++#define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4) ++#define MTK_PIN_CONFIG_DRV_ADV (PIN_CONFIG_END + 5) ++ ++static const struct pinconf_generic_params mtk_custom_bindings[] = { ++ {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0}, ++ {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0}, ++ {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1}, ++ {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1}, ++ {"mediatek,drive-strength-adv", MTK_PIN_CONFIG_DRV_ADV, 2}, ++}; ++ ++#ifdef CONFIG_DEBUG_FS ++static const struct pin_config_item mtk_conf_items[] = { ++ PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true), ++ PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true), ++ PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true), ++ PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true), ++ PCONFDUMP(MTK_PIN_CONFIG_DRV_ADV, "drive-strength-adv", NULL, true), ++}; ++#endif ++ ++static const char * const mtk_gpio_functions[] = { ++ "func0", "func1", "func2", "func3", ++ "func4", "func5", "func6", "func7", ++ "func8", "func9", "func10", "func11", ++ "func12", "func13", "func14", "func15", ++}; ++ ++static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, ++ struct pinctrl_gpio_range *range, ++ unsigned int pin) ++{ ++ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); ++ const struct mtk_pin_desc *desc; ++ ++ desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; ++ ++ return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, ++ hw->soc->gpio_m); ++} ++ ++static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, ++ struct pinctrl_gpio_range *range, ++ unsigned int pin, bool input) ++{ ++ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); ++ const struct mtk_pin_desc *desc; ++ ++ desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; ++ ++ /* hardware would take 0 as input direction */ ++ return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input); ++} ++ ++static int mtk_pinconf_get(struct pinctrl_dev *pctldev, ++ unsigned int pin, unsigned long *config) ++{ ++ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); ++ u32 param = pinconf_to_config_param(*config); ++ int val, val2, err, reg, ret = 1; ++ const struct mtk_pin_desc *desc; ++ ++ desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; ++ ++ switch (param) { ++ case PIN_CONFIG_BIAS_DISABLE: ++ if (hw->soc->bias_disable_get) { ++ err = hw->soc->bias_disable_get(hw, desc, &ret); ++ if (err) ++ return err; ++ } else { ++ return -ENOTSUPP; ++ } ++ break; ++ case PIN_CONFIG_BIAS_PULL_UP: ++ if (hw->soc->bias_get) { ++ err = hw->soc->bias_get(hw, desc, 1, &ret); ++ if (err) ++ return err; ++ } else { ++ return -ENOTSUPP; ++ } ++ break; ++ case PIN_CONFIG_BIAS_PULL_DOWN: ++ if (hw->soc->bias_get) { ++ err = hw->soc->bias_get(hw, desc, 0, &ret); ++ if (err) ++ return err; ++ } else { ++ return -ENOTSUPP; ++ } ++ break; ++ case PIN_CONFIG_SLEW_RATE: ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &val); ++ if (err) ++ return err; ++ ++ if (!val) ++ return -EINVAL; ++ ++ break; ++ case PIN_CONFIG_INPUT_ENABLE: ++ case PIN_CONFIG_OUTPUT_ENABLE: ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val); ++ if (err) ++ return err; ++ ++ /* HW takes input mode as zero; output mode as non-zero */ ++ if ((val && param == PIN_CONFIG_INPUT_ENABLE) || ++ (!val && param == PIN_CONFIG_OUTPUT_ENABLE)) ++ return -EINVAL; ++ ++ break; ++ case PIN_CONFIG_INPUT_SCHMITT_ENABLE: ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val); ++ if (err) ++ return err; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &val2); ++ if (err) ++ return err; ++ ++ if (val || !val2) ++ return -EINVAL; ++ ++ break; ++ case PIN_CONFIG_DRIVE_STRENGTH: ++ if (hw->soc->drive_get) { ++ err = hw->soc->drive_get(hw, desc, &ret); ++ if (err) ++ return err; ++ } else { ++ err = -ENOTSUPP; ++ } ++ break; ++ case MTK_PIN_CONFIG_TDSEL: ++ case MTK_PIN_CONFIG_RDSEL: ++ reg = (param == MTK_PIN_CONFIG_TDSEL) ? ++ PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL; ++ ++ err = mtk_hw_get_value(hw, desc, reg, &val); ++ if (err) ++ return err; ++ ++ ret = val; ++ ++ break; ++ case MTK_PIN_CONFIG_PU_ADV: ++ case MTK_PIN_CONFIG_PD_ADV: ++ if (hw->soc->adv_pull_get) { ++ bool pullup; ++ ++ pullup = param == MTK_PIN_CONFIG_PU_ADV; ++ err = hw->soc->adv_pull_get(hw, desc, pullup, &ret); ++ if (err) ++ return err; ++ } else { ++ return -ENOTSUPP; ++ } ++ break; ++ case MTK_PIN_CONFIG_DRV_ADV: ++ if (hw->soc->adv_drive_get) { ++ err = hw->soc->adv_drive_get(hw, desc, &ret); ++ if (err) ++ return err; ++ } else { ++ return -ENOTSUPP; ++ } ++ break; ++ default: ++ return -ENOTSUPP; ++ } ++ ++ *config = pinconf_to_config_packed(param, ret); ++ ++ return 0; ++} ++ ++static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, ++ enum pin_config_param param, ++ enum pin_config_param arg) ++{ ++ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); ++ const struct mtk_pin_desc *desc; ++ int err = 0; ++ u32 reg; ++ ++ desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; ++ ++ switch ((u32)param) { ++ case PIN_CONFIG_BIAS_DISABLE: ++ if (hw->soc->bias_disable_set) { ++ err = hw->soc->bias_disable_set(hw, desc); ++ if (err) ++ return err; ++ } else { ++ return -ENOTSUPP; ++ } ++ break; ++ case PIN_CONFIG_BIAS_PULL_UP: ++ if (hw->soc->bias_set) { ++ err = hw->soc->bias_set(hw, desc, 1); ++ if (err) ++ return err; ++ } else { ++ return -ENOTSUPP; ++ } ++ break; ++ case PIN_CONFIG_BIAS_PULL_DOWN: ++ if (hw->soc->bias_set) { ++ err = hw->soc->bias_set(hw, desc, 0); ++ if (err) ++ return err; ++ } else { ++ return -ENOTSUPP; ++ } ++ break; ++ case PIN_CONFIG_OUTPUT_ENABLE: ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, ++ MTK_DISABLE); ++ if (err) ++ goto err; ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, ++ MTK_OUTPUT); ++ if (err) ++ goto err; ++ break; ++ case PIN_CONFIG_INPUT_ENABLE: ++ if (hw->soc->ies_present) { ++ mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, ++ MTK_ENABLE); ++ } ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, ++ MTK_INPUT); ++ if (err) ++ goto err; ++ break; ++ case PIN_CONFIG_SLEW_RATE: ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR, ++ arg); ++ if (err) ++ goto err; ++ ++ break; ++ case PIN_CONFIG_OUTPUT: ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, ++ MTK_OUTPUT); ++ if (err) ++ goto err; ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, ++ arg); ++ if (err) ++ goto err; ++ break; ++ case PIN_CONFIG_INPUT_SCHMITT_ENABLE: ++ /* arg = 1: Input mode & SMT enable ; ++ * arg = 0: Output mode & SMT disable ++ */ ++ arg = arg ? 2 : 1; ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, ++ arg & 1); ++ if (err) ++ goto err; ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, ++ !!(arg & 2)); ++ if (err) ++ goto err; ++ break; ++ case PIN_CONFIG_DRIVE_STRENGTH: ++ if (hw->soc->drive_set) { ++ err = hw->soc->drive_set(hw, desc, arg); ++ if (err) ++ return err; ++ } else { ++ return -ENOTSUPP; ++ } ++ break; ++ case MTK_PIN_CONFIG_TDSEL: ++ case MTK_PIN_CONFIG_RDSEL: ++ reg = (param == MTK_PIN_CONFIG_TDSEL) ? ++ PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL; ++ ++ err = mtk_hw_set_value(hw, desc, reg, arg); ++ if (err) ++ goto err; ++ break; ++ case MTK_PIN_CONFIG_PU_ADV: ++ case MTK_PIN_CONFIG_PD_ADV: ++ if (hw->soc->adv_pull_set) { ++ bool pullup; ++ ++ pullup = param == MTK_PIN_CONFIG_PU_ADV; ++ err = hw->soc->adv_pull_set(hw, desc, pullup, ++ arg); ++ if (err) ++ return err; ++ } else { ++ return -ENOTSUPP; ++ } ++ break; ++ case MTK_PIN_CONFIG_DRV_ADV: ++ if (hw->soc->adv_drive_set) { ++ err = hw->soc->adv_drive_set(hw, desc, arg); ++ if (err) ++ return err; ++ } else { ++ return -ENOTSUPP; ++ } ++ break; ++ default: ++ err = -ENOTSUPP; ++ } ++ ++err: ++ return err; ++} ++ ++static struct mtk_pinctrl_group * ++mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *hw, u32 pin) ++{ ++ int i; ++ ++ for (i = 0; i < hw->soc->ngrps; i++) { ++ struct mtk_pinctrl_group *grp = hw->groups + i; ++ ++ if (grp->pin == pin) ++ return grp; ++ } ++ ++ return NULL; ++} ++ ++static const struct mtk_func_desc * ++mtk_pctrl_find_function_by_pin(struct mtk_pinctrl *hw, u32 pin_num, u32 fnum) ++{ ++ const struct mtk_pin_desc *pin = hw->soc->pins + pin_num; ++ const struct mtk_func_desc *func = pin->funcs; ++ ++ while (func && func->name) { ++ if (func->muxval == fnum) ++ return func; ++ func++; ++ } ++ ++ return NULL; ++} ++ ++static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *hw, u32 pin_num, ++ u32 fnum) ++{ ++ int i; ++ ++ for (i = 0; i < hw->soc->npins; i++) { ++ const struct mtk_pin_desc *pin = hw->soc->pins + i; ++ ++ if (pin->number == pin_num) { ++ const struct mtk_func_desc *func = pin->funcs; ++ ++ while (func && func->name) { ++ if (func->muxval == fnum) ++ return true; ++ func++; ++ } ++ ++ break; ++ } ++ } ++ ++ return false; ++} ++ ++static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl, ++ u32 pin, u32 fnum, ++ struct mtk_pinctrl_group *grp, ++ struct pinctrl_map **map, ++ unsigned *reserved_maps, ++ unsigned *num_maps) ++{ ++ bool ret; ++ ++ if (*num_maps == *reserved_maps) ++ return -ENOSPC; ++ ++ (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; ++ (*map)[*num_maps].data.mux.group = grp->name; ++ ++ ret = mtk_pctrl_is_function_valid(pctl, pin, fnum); ++ if (!ret) { ++ dev_err(pctl->dev, "invalid function %d on pin %d .\n", ++ fnum, pin); ++ return -EINVAL; ++ } ++ ++ (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum]; ++ (*num_maps)++; ++ ++ return 0; ++} ++ ++static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, ++ struct device_node *node, ++ struct pinctrl_map **map, ++ unsigned *reserved_maps, ++ unsigned *num_maps) ++{ ++ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); ++ int num_pins, num_funcs, maps_per_pin, i, err; ++ struct mtk_pinctrl_group *grp; ++ unsigned int num_configs; ++ bool has_config = false; ++ unsigned long *configs; ++ u32 pinfunc, pin, func; ++ struct property *pins; ++ unsigned reserve = 0; ++ ++ pins = of_find_property(node, "pinmux", NULL); ++ if (!pins) { ++ dev_err(hw->dev, "missing pins property in node %pOFn .\n", ++ node); ++ return -EINVAL; ++ } ++ ++ err = pinconf_generic_parse_dt_config(node, pctldev, &configs, ++ &num_configs); ++ if (err) ++ return err; ++ ++ if (num_configs) ++ has_config = true; ++ ++ num_pins = pins->length / sizeof(u32); ++ num_funcs = num_pins; ++ maps_per_pin = 0; ++ if (num_funcs) ++ maps_per_pin++; ++ if (has_config && num_pins >= 1) ++ maps_per_pin++; ++ ++ if (!num_pins || !maps_per_pin) { ++ err = -EINVAL; ++ goto exit; ++ } ++ ++ reserve = num_pins * maps_per_pin; ++ ++ err = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, ++ reserve); ++ if (err < 0) ++ goto exit; ++ ++ for (i = 0; i < num_pins; i++) { ++ err = of_property_read_u32_index(node, "pinmux", i, &pinfunc); ++ if (err) ++ goto exit; ++ ++ pin = MTK_GET_PIN_NO(pinfunc); ++ func = MTK_GET_PIN_FUNC(pinfunc); ++ ++ if (pin >= hw->soc->npins || ++ func >= ARRAY_SIZE(mtk_gpio_functions)) { ++ dev_err(hw->dev, "invalid pins value.\n"); ++ err = -EINVAL; ++ goto exit; ++ } ++ ++ grp = mtk_pctrl_find_group_by_pin(hw, pin); ++ if (!grp) { ++ dev_err(hw->dev, "unable to match pin %d to group\n", ++ pin); ++ err = -EINVAL; ++ goto exit; ++ } ++ ++ err = mtk_pctrl_dt_node_to_map_func(hw, pin, func, grp, map, ++ reserved_maps, num_maps); ++ if (err < 0) ++ goto exit; ++ ++ if (has_config) { ++ err = pinctrl_utils_add_map_configs(pctldev, map, ++ reserved_maps, ++ num_maps, ++ grp->name, ++ configs, ++ num_configs, ++ PIN_MAP_TYPE_CONFIGS_GROUP); ++ if (err < 0) ++ goto exit; ++ } ++ } ++ ++ err = 0; ++ ++exit: ++ kfree(configs); ++ return err; ++} ++ ++static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, ++ struct device_node *np_config, ++ struct pinctrl_map **map, ++ unsigned *num_maps) ++{ ++ struct device_node *np; ++ unsigned reserved_maps; ++ int ret; ++ ++ *map = NULL; ++ *num_maps = 0; ++ reserved_maps = 0; ++ ++ for_each_child_of_node(np_config, np) { ++ ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map, ++ &reserved_maps, ++ num_maps); ++ if (ret < 0) { ++ pinctrl_utils_free_map(pctldev, *map, *num_maps); ++ of_node_put(np); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev) ++{ ++ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); ++ ++ return hw->soc->ngrps; ++} ++ ++static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev, ++ unsigned group) ++{ ++ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); ++ ++ return hw->groups[group].name; ++} ++ ++static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev, ++ unsigned group, const unsigned **pins, ++ unsigned *num_pins) ++{ ++ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); ++ ++ *pins = (unsigned *)&hw->groups[group].pin; ++ *num_pins = 1; ++ ++ return 0; ++} ++ ++static const struct pinctrl_ops mtk_pctlops = { ++ .dt_node_to_map = mtk_pctrl_dt_node_to_map, ++ .dt_free_map = pinctrl_utils_free_map, ++ .get_groups_count = mtk_pctrl_get_groups_count, ++ .get_group_name = mtk_pctrl_get_group_name, ++ .get_group_pins = mtk_pctrl_get_group_pins, ++}; ++ ++static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) ++{ ++ return ARRAY_SIZE(mtk_gpio_functions); ++} ++ ++static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev, ++ unsigned selector) ++{ ++ return mtk_gpio_functions[selector]; ++} ++ ++static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev, ++ unsigned function, ++ const char * const **groups, ++ unsigned * const num_groups) ++{ ++ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); ++ ++ *groups = hw->grp_names; ++ *num_groups = hw->soc->ngrps; ++ ++ return 0; ++} ++ ++static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev, ++ unsigned function, ++ unsigned group) ++{ ++ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); ++ struct mtk_pinctrl_group *grp = hw->groups + group; ++ const struct mtk_func_desc *desc_func; ++ const struct mtk_pin_desc *desc; ++ bool ret; ++ ++ ret = mtk_pctrl_is_function_valid(hw, grp->pin, function); ++ if (!ret) { ++ dev_err(hw->dev, "invalid function %d on group %d .\n", ++ function, group); ++ return -EINVAL; ++ } ++ ++ desc_func = mtk_pctrl_find_function_by_pin(hw, grp->pin, function); ++ if (!desc_func) ++ return -EINVAL; ++ ++ desc = (const struct mtk_pin_desc *)&hw->soc->pins[grp->pin]; ++ mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, desc_func->muxval); ++ ++ return 0; ++} ++ ++static const struct pinmux_ops mtk_pmxops = { ++ .get_functions_count = mtk_pmx_get_funcs_cnt, ++ .get_function_name = mtk_pmx_get_func_name, ++ .get_function_groups = mtk_pmx_get_func_groups, ++ .set_mux = mtk_pmx_set_mux, ++ .gpio_set_direction = mtk_pinmux_gpio_set_direction, ++ .gpio_request_enable = mtk_pinmux_gpio_request_enable, ++}; ++ ++static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned group, ++ unsigned long *config) ++{ ++ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); ++ ++ *config = hw->groups[group].config; ++ ++ return 0; ++} ++ ++static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, ++ unsigned long *configs, unsigned num_configs) ++{ ++ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); ++ struct mtk_pinctrl_group *grp = &hw->groups[group]; ++ int i, ret; ++ ++ for (i = 0; i < num_configs; i++) { ++ ret = mtk_pinconf_set(pctldev, grp->pin, ++ pinconf_to_config_param(configs[i]), ++ pinconf_to_config_argument(configs[i])); ++ if (ret < 0) ++ return ret; ++ ++ grp->config = configs[i]; ++ } ++ ++ return 0; ++} ++ ++static const struct pinconf_ops mtk_confops = { ++ .pin_config_get = mtk_pinconf_get, ++ .pin_config_group_get = mtk_pconf_group_get, ++ .pin_config_group_set = mtk_pconf_group_set, ++}; ++ ++static struct pinctrl_desc mtk_desc = { ++ .name = PINCTRL_PINCTRL_DEV, ++ .pctlops = &mtk_pctlops, ++ .pmxops = &mtk_pmxops, ++ .confops = &mtk_confops, ++ .owner = THIS_MODULE, ++}; ++ ++static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) ++{ ++ struct mtk_pinctrl *hw = gpiochip_get_data(chip); ++ const struct mtk_pin_desc *desc; ++ int value, err; ++ ++ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &value); ++ if (err) ++ return err; ++ ++ return !value; ++} ++ ++static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio) ++{ ++ struct mtk_pinctrl *hw = gpiochip_get_data(chip); ++ const struct mtk_pin_desc *desc; ++ int value, err; ++ ++ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value); ++ if (err) ++ return err; ++ ++ return !!value; ++} ++ ++static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) ++{ ++ struct mtk_pinctrl *hw = gpiochip_get_data(chip); ++ const struct mtk_pin_desc *desc; ++ ++ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; ++ ++ mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value); ++} ++ ++static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio) ++{ ++ return pinctrl_gpio_direction_input(chip->base + gpio); ++} ++ ++static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, ++ int value) ++{ ++ mtk_gpio_set(chip, gpio, value); ++ ++ return pinctrl_gpio_direction_output(chip->base + gpio); ++} ++ ++static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) ++{ ++ struct mtk_pinctrl *hw = gpiochip_get_data(chip); ++ const struct mtk_pin_desc *desc; ++ ++ if (!hw->eint) ++ return -ENOTSUPP; ++ ++ desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset]; ++ ++ if (desc->eint.eint_n == EINT_NA) ++ return -ENOTSUPP; ++ ++ return mtk_eint_find_irq(hw->eint, desc->eint.eint_n); ++} ++ ++static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset, ++ unsigned long config) ++{ ++ struct mtk_pinctrl *hw = gpiochip_get_data(chip); ++ const struct mtk_pin_desc *desc; ++ u32 debounce; ++ ++ desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset]; ++ ++ if (!hw->eint || ++ pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE || ++ desc->eint.eint_n == EINT_NA) ++ return -ENOTSUPP; ++ ++ debounce = pinconf_to_config_argument(config); ++ ++ return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce); ++} ++ ++static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np) ++{ ++ struct gpio_chip *chip = &hw->chip; ++ int ret; ++ ++ chip->label = PINCTRL_PINCTRL_DEV; ++ chip->parent = hw->dev; ++ chip->request = gpiochip_generic_request; ++ chip->free = gpiochip_generic_free; ++ chip->get_direction = mtk_gpio_get_direction; ++ chip->direction_input = mtk_gpio_direction_input; ++ chip->direction_output = mtk_gpio_direction_output; ++ chip->get = mtk_gpio_get; ++ chip->set = mtk_gpio_set; ++ chip->to_irq = mtk_gpio_to_irq, ++ chip->set_config = mtk_gpio_set_config, ++ chip->base = -1; ++ chip->ngpio = hw->soc->npins; ++ chip->of_node = np; ++ chip->of_gpio_n_cells = 2; ++ ++ ret = gpiochip_add_data(chip, hw); ++ if (ret < 0) ++ return ret; ++ ++ return 0; ++} ++ ++static int mtk_pctrl_build_state(struct platform_device *pdev) ++{ ++ struct mtk_pinctrl *hw = platform_get_drvdata(pdev); ++ int i; ++ ++ /* Allocate groups */ ++ hw->groups = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps, ++ sizeof(*hw->groups), GFP_KERNEL); ++ if (!hw->groups) ++ return -ENOMEM; ++ ++ /* We assume that one pin is one group, use pin name as group name. */ ++ hw->grp_names = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps, ++ sizeof(*hw->grp_names), GFP_KERNEL); ++ if (!hw->grp_names) ++ return -ENOMEM; ++ ++ for (i = 0; i < hw->soc->npins; i++) { ++ const struct mtk_pin_desc *pin = hw->soc->pins + i; ++ struct mtk_pinctrl_group *group = hw->groups + i; ++ ++ group->name = pin->name; ++ group->pin = pin->number; ++ ++ hw->grp_names[i] = pin->name; ++ } ++ ++ return 0; ++} ++ ++int mtk_paris_pinctrl_probe(struct platform_device *pdev, ++ const struct mtk_pin_soc *soc) ++{ ++ struct pinctrl_pin_desc *pins; ++ struct mtk_pinctrl *hw; ++ struct resource *res; ++ int err, i; ++ ++ hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL); ++ if (!hw) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, hw); ++ hw->soc = soc; ++ hw->dev = &pdev->dev; ++ ++ if (!hw->soc->nbase_names) { ++ dev_err(&pdev->dev, ++ "SoC should be assigned at least one register base\n"); ++ return -EINVAL; ++ } ++ ++ hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names, ++ sizeof(*hw->base), GFP_KERNEL); ++ if (!hw->base) ++ return -ENOMEM; ++ ++ for (i = 0; i < hw->soc->nbase_names; i++) { ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, ++ hw->soc->base_names[i]); ++ if (!res) { ++ dev_err(&pdev->dev, "missing IO resource\n"); ++ return -ENXIO; ++ } ++ ++ hw->base[i] = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(hw->base[i])) ++ return PTR_ERR(hw->base[i]); ++ } ++ ++ hw->nbase = hw->soc->nbase_names; ++ ++ err = mtk_pctrl_build_state(pdev); ++ if (err) { ++ dev_err(&pdev->dev, "build state failed: %d\n", err); ++ return -EINVAL; ++ } ++ ++ /* Copy from internal struct mtk_pin_desc to register to the core */ ++ pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins), ++ GFP_KERNEL); ++ if (!pins) ++ return -ENOMEM; ++ ++ for (i = 0; i < hw->soc->npins; i++) { ++ pins[i].number = hw->soc->pins[i].number; ++ pins[i].name = hw->soc->pins[i].name; ++ } ++ ++ /* Setup pins descriptions per SoC types */ ++ mtk_desc.pins = (const struct pinctrl_pin_desc *)pins; ++ mtk_desc.npins = hw->soc->npins; ++ mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings); ++ mtk_desc.custom_params = mtk_custom_bindings; ++#ifdef CONFIG_DEBUG_FS ++ mtk_desc.custom_conf_items = mtk_conf_items; ++#endif ++ ++ err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw, ++ &hw->pctrl); ++ if (err) ++ return err; ++ ++ err = pinctrl_enable(hw->pctrl); ++ if (err) ++ return err; ++ ++ err = mtk_build_eint(hw, pdev); ++ if (err) ++ dev_warn(&pdev->dev, ++ "Failed to add EINT, but pinctrl still can work\n"); ++ ++ /* Build gpiochip should be after pinctrl_enable is done */ ++ err = mtk_build_gpiochip(hw, pdev->dev.of_node); ++ if (err) { ++ dev_err(&pdev->dev, "Failed to add gpio_chip\n"); ++ return err; ++ } ++ ++ platform_set_drvdata(pdev, hw); ++ ++ return 0; ++} ++ ++static int mtk_paris_pinctrl_suspend(struct device *device) ++{ ++ struct mtk_pinctrl *pctl = dev_get_drvdata(device); ++ ++ return mtk_eint_do_suspend(pctl->eint); ++} ++ ++static int mtk_paris_pinctrl_resume(struct device *device) ++{ ++ struct mtk_pinctrl *pctl = dev_get_drvdata(device); ++ ++ return mtk_eint_do_resume(pctl->eint); ++} ++ ++const struct dev_pm_ops mtk_paris_pinctrl_pm_ops = { ++ .suspend_noirq = mtk_paris_pinctrl_suspend, ++ .resume_noirq = mtk_paris_pinctrl_resume, ++}; +diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.h b/drivers/pinctrl/mediatek/pinctrl-paris.h +new file mode 100644 +index 000000000000..3d43771074e6 +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-paris.h +@@ -0,0 +1,65 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2018 MediaTek Inc. ++ * ++ * Author: Sean Wang <sean.wang@mediatek.com> ++ * Zhiyong Tao <zhiyong.tao@mediatek.com> ++ * Hongzhou.Yang <hongzhou.yang@mediatek.com> ++ */ ++#ifndef __PINCTRL_PARIS_H ++#define __PINCTRL_PARIS_H ++ ++#include <linux/io.h> ++#include <linux/init.h> ++#include <linux/of.h> ++#include <linux/of_platform.h> ++#include <linux/platform_device.h> ++#include <linux/pinctrl/pinctrl.h> ++#include <linux/pinctrl/pinmux.h> ++#include <linux/pinctrl/pinconf.h> ++#include <linux/pinctrl/pinconf-generic.h> ++ ++#include "../core.h" ++#include "../pinconf.h" ++#include "../pinctrl-utils.h" ++#include "../pinmux.h" ++#include "mtk-eint.h" ++#include "pinctrl-mtk-common-v2.h" ++ ++#define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), } ++ ++#define MTK_EINT_FUNCTION(_eintmux, _eintnum) \ ++ { \ ++ .eint_m = _eintmux, \ ++ .eint_n = _eintnum, \ ++ } ++ ++#define MTK_FUNCTION(_val, _name) \ ++ { \ ++ .muxval = _val, \ ++ .name = _name, \ ++ } ++ ++#define MTK_PIN(_number, _name, _eint, _drv_n, ...) { \ ++ .number = _number, \ ++ .name = _name, \ ++ .eint = _eint, \ ++ .drv_n = _drv_n, \ ++ .funcs = (struct mtk_func_desc[]){ \ ++ __VA_ARGS__, { } }, \ ++ } ++ ++#define PINCTRL_PIN_GROUP(name, id) \ ++ { \ ++ name, \ ++ id##_pins, \ ++ ARRAY_SIZE(id##_pins), \ ++ id##_funcs, \ ++ } ++ ++int mtk_paris_pinctrl_probe(struct platform_device *pdev, ++ const struct mtk_pin_soc *soc); ++ ++extern const struct dev_pm_ops mtk_paris_pinctrl_pm_ops; ++ ++#endif /* __PINCTRL_PARIS_H */ diff --git a/target/linux/mediatek/patches-4.19/0006-mtd-spi-nor-mtk-quadspi-add-SNOR_HWCAPS_READ-to-spi_.patch b/target/linux/mediatek/patches-4.19/0006-mtd-spi-nor-mtk-quadspi-add-SNOR_HWCAPS_READ-to-spi_.patch new file mode 100644 index 0000000000..6164d68756 --- /dev/null +++ b/target/linux/mediatek/patches-4.19/0006-mtd-spi-nor-mtk-quadspi-add-SNOR_HWCAPS_READ-to-spi_.patch @@ -0,0 +1,34 @@ +From 9cca9b3e55989f8b227d05897877648d67910a6d Mon Sep 17 00:00:00 2001 +From: Guochun Mao <guochun.mao@mediatek.com> +Date: Wed, 16 Jan 2019 10:12:04 +0800 +Subject: [PATCH] mtd: spi-nor: mtk-quadspi: add SNOR_HWCAPS_READ to + spi_nor_hwcaps mask + +SNOR_HWCAPS_READ should be supported by this controller, so add this +flag to spi_nor_hwcaps mask. + +Signed-off-by: Guochun Mao <guochun.mao@mediatek.com> +Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> +Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> +Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> +--- + drivers/mtd/spi-nor/mtk-quadspi.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/mtd/spi-nor/mtk-quadspi.c b/drivers/mtd/spi-nor/mtk-quadspi.c +index 5442993b71ff..d9eed6844ba1 100644 +--- a/drivers/mtd/spi-nor/mtk-quadspi.c ++++ b/drivers/mtd/spi-nor/mtk-quadspi.c +@@ -431,7 +431,8 @@ static int mtk_nor_init(struct mtk_nor *mtk_nor, + struct device_node *flash_node) + { + const struct spi_nor_hwcaps hwcaps = { +- .mask = SNOR_HWCAPS_READ_FAST | ++ .mask = SNOR_HWCAPS_READ | ++ SNOR_HWCAPS_READ_FAST | + SNOR_HWCAPS_READ_1_1_2 | + SNOR_HWCAPS_PP, + }; +-- +2.21.0 + |