realtek: drop patches of upstreamed drivers from 5.15

The following drivers were upstreamed and available on 5.15, so drop
from OpenWrt tree.

- realtek-otto-gpio (5.13)
- realtek-rtl-spi (5.12)
- realtek-rtl-intc (5.12)

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>

6 files changed, 0 insertions, 1091 deletions

diff --git a/target/linux/realtek/patches-5.15/001-5.13-dt-bindings-gpio-binding-for-realtek-otto-gpio.patch b/target/linux/realtek/patches-5.15/001-5.13-dt-bindings-gpio-binding-for-realtek-otto-gpio.patch
deleted file mode 100644
index 80b806d89f..0000000000
--- a/target/linux/realtek/patches-5.15/001-5.13-dt-bindings-gpio-binding-for-realtek-otto-gpio.patch
+++ /dev/null
@@ -1,103 +0,0 @@
-From a362c0ce64866939c3daa17c76943cfed555b065 Mon Sep 17 00:00:00 2001
-From: Sander Vanheule <sander@svanheule.net>
-Date: Tue, 30 Mar 2021 19:48:42 +0200
-Subject: dt-bindings: gpio: Binding for Realtek Otto GPIO
-
-Add a binding description for Realtek's GPIO controller found on several
-of their MIPS-based SoCs (codenamed Otto), such as the RTL838x and
-RTL839x series of switch SoCs.
-
-A fallback binding 'realtek,otto-gpio' is provided for cases where the
-actual port ordering is not known yet, and enabling the interrupt
-controller may result in uncaught interrupts.
-
-Signed-off-by: Sander Vanheule <sander@svanheule.net>
-Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
----
- .../bindings/gpio/realtek,otto-gpio.yaml           | 78 ++++++++++++++++++++++
- 1 file changed, 78 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml
-@@ -0,0 +1,78 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/gpio/realtek,otto-gpio.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Realtek Otto GPIO controller
-+
-+maintainers:
-+  - Sander Vanheule <sander@svanheule.net>
-+  - Bert Vermeulen <bert@biot.com>
-+
-+description: |
-+  Realtek's GPIO controller on their MIPS switch SoCs (Otto platform) consists
-+  of two banks of 32 GPIOs. These GPIOs can generate edge-triggered interrupts.
-+  Each bank's interrupts are cascased into one interrupt line on the parent
-+  interrupt controller, if provided.
-+  This binding allows defining a single bank in the devicetree. The interrupt
-+  controller is not supported on the fallback compatible name, which only
-+  allows for GPIO port use.
-+
-+properties:
-+  $nodename:
-+    pattern: "^gpio@[0-9a-f]+$"
-+
-+  compatible:
-+    items:
-+      - enum:
-+          - realtek,rtl8380-gpio
-+          - realtek,rtl8390-gpio
-+      - const: realtek,otto-gpio
-+
-+  reg:
-+    maxItems: 1
-+
-+  "#gpio-cells":
-+    const: 2
-+
-+  gpio-controller: true
-+
-+  ngpios:
-+    minimum: 1
-+    maximum: 32
-+
-+  interrupt-controller: true
-+
-+  "#interrupt-cells":
-+    const: 2
-+
-+  interrupts:
-+    maxItems: 1
-+
-+required:
-+  - compatible
-+  - reg
-+  - "#gpio-cells"
-+  - gpio-controller
-+
-+additionalProperties: false
-+
-+dependencies:
-+  interrupt-controller: [ interrupts ]
-+
-+examples:
-+  - |
-+      gpio@3500 {
-+        compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio";
-+        reg = <0x3500 0x1c>;
-+        gpio-controller;
-+        #gpio-cells = <2>;
-+        ngpios = <24>;
-+        interrupt-controller;
-+        #interrupt-cells = <2>;
-+        interrupt-parent = <&rtlintc>;
-+        interrupts = <23>;
-+      };
-+
-+...
diff --git a/target/linux/realtek/patches-5.15/002-5.13-gpio-add-realtek-otto-gpio-support.patch b/target/linux/realtek/patches-5.15/002-5.13-gpio-add-realtek-otto-gpio-support.patch
deleted file mode 100644
index 62e4338cbb..0000000000
--- a/target/linux/realtek/patches-5.15/002-5.13-gpio-add-realtek-otto-gpio-support.patch
+++ /dev/null
@@ -1,394 +0,0 @@
-From f0f7d662e8514169c90d3d84cd6df773b2983088 Mon Sep 17 00:00:00 2001
-From: Sander Vanheule <sander@svanheule.net>
-Date: Tue, 30 Mar 2021 19:48:43 +0200
-Subject: gpio: Add Realtek Otto GPIO support
-
-Realtek MIPS SoCs (platform name Otto) have GPIO controllers with up to
-64 GPIOs, divided over two banks. Each bank has a set of registers for
-32 GPIOs, with support for edge-triggered interrupts.
-
-Each GPIO bank consists of four 8-bit GPIO ports (ABCD and EFGH). Most
-registers pack one bit per GPIO, except for the IMR register, which
-packs two bits per GPIO (AB-CD).
-
-Although the byte order is currently assumed to have port A..D at offset
-0x0..0x3, this has been observed to be reversed on other, Lexra-based,
-SoCs (e.g. RTL8196E/97D/97F).
-
-Interrupt support is disabled for the fallback devicetree-compatible
-'realtek,otto-gpio'. This allows for quick support of GPIO banks in
-which the byte order would be unknown. In this case, the port ordering
-in the IMR registers may not match the reversed order in the other
-registers (DCBA, and BA-DC or DC-BA).
-
-Signed-off-by: Sander Vanheule <sander@svanheule.net>
-Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
-Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
-Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
----
- drivers/gpio/Kconfig             |  13 ++
- drivers/gpio/Makefile            |   1 +
- drivers/gpio/gpio-realtek-otto.c | 325 +++++++++++++++++++++++++++++++++++++++
- 3 files changed, 339 insertions(+)
- create mode 100644 drivers/gpio/gpio-realtek-otto.c
-
---- a/drivers/gpio/Kconfig
-+++ b/drivers/gpio/Kconfig
-@@ -489,6 +489,19 @@ config GPIO_RDA
- 	help
- 	  Say Y here to support RDA Micro GPIO controller.
- 
-+config GPIO_REALTEK_OTTO
-+	tristate "Realtek Otto GPIO support"
-+	depends on MACH_REALTEK_RTL
-+	default MACH_REALTEK_RTL
-+	select GPIO_GENERIC
-+	select GPIOLIB_IRQCHIP
-+	help
-+	  The GPIO controller on the Otto MIPS platform supports up to two
-+	  banks of 32 GPIOs, with edge triggered interrupts. The 32 GPIOs
-+	  are grouped in four 8-bit wide ports.
-+
-+	  When built as a module, the module will be called realtek_otto_gpio.
-+
- config GPIO_REG
- 	bool
- 	help
---- a/drivers/gpio/Makefile
-+++ b/drivers/gpio/Makefile
-@@ -125,6 +125,7 @@ obj-$(CONFIG_GPIO_RC5T583)		+= gpio-rc5t
- obj-$(CONFIG_GPIO_RCAR)			+= gpio-rcar.o
- obj-$(CONFIG_GPIO_RDA)			+= gpio-rda.o
- obj-$(CONFIG_GPIO_RDC321X)		+= gpio-rdc321x.o
-+obj-$(CONFIG_GPIO_REALTEK_OTTO)		+= gpio-realtek-otto.o
- obj-$(CONFIG_GPIO_REG)			+= gpio-reg.o
- obj-$(CONFIG_ARCH_SA1100)		+= gpio-sa1100.o
- obj-$(CONFIG_GPIO_SAMA5D2_PIOBU)	+= gpio-sama5d2-piobu.o
---- /dev/null
-+++ b/drivers/gpio/gpio-realtek-otto.c
-@@ -0,0 +1,325 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+
-+#include <linux/gpio/driver.h>
-+#include <linux/irq.h>
-+#include <linux/minmax.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/property.h>
-+
-+/*
-+ * Total register block size is 0x1C for one bank of four ports (A, B, C, D).
-+ * An optional second bank, with ports E, F, G, and H, may be present, starting
-+ * at register offset 0x1C.
-+ */
-+
-+/*
-+ * Pin select: (0) "normal", (1) "dedicate peripheral"
-+ * Not used on RTL8380/RTL8390, peripheral selection is managed by control bits
-+ * in the peripheral registers.
-+ */
-+#define REALTEK_GPIO_REG_CNR		0x00
-+/* Clear bit (0) for input, set bit (1) for output */
-+#define REALTEK_GPIO_REG_DIR		0x08
-+#define REALTEK_GPIO_REG_DATA		0x0C
-+/* Read bit for IRQ status, write 1 to clear IRQ */
-+#define REALTEK_GPIO_REG_ISR		0x10
-+/* Two bits per GPIO in IMR registers */
-+#define REALTEK_GPIO_REG_IMR		0x14
-+#define REALTEK_GPIO_REG_IMR_AB		0x14
-+#define REALTEK_GPIO_REG_IMR_CD		0x18
-+#define REALTEK_GPIO_IMR_LINE_MASK	GENMASK(1, 0)
-+#define REALTEK_GPIO_IRQ_EDGE_FALLING	1
-+#define REALTEK_GPIO_IRQ_EDGE_RISING	2
-+#define REALTEK_GPIO_IRQ_EDGE_BOTH	3
-+
-+#define REALTEK_GPIO_MAX		32
-+#define REALTEK_GPIO_PORTS_PER_BANK	4
-+
-+/**
-+ * realtek_gpio_ctrl - Realtek Otto GPIO driver data
-+ *
-+ * @gc: Associated gpio_chip instance
-+ * @base: Base address of the register block for a GPIO bank
-+ * @lock: Lock for accessing the IRQ registers and values
-+ * @intr_mask: Mask for interrupts lines
-+ * @intr_type: Interrupt type selection
-+ *
-+ * Because the interrupt mask register (IMR) combines the function of IRQ type
-+ * selection and masking, two extra values are stored. @intr_mask is used to
-+ * mask/unmask the interrupts for a GPIO port, and @intr_type is used to store
-+ * the selected interrupt types. The logical AND of these values is written to
-+ * IMR on changes.
-+ */
-+struct realtek_gpio_ctrl {
-+	struct gpio_chip gc;
-+	void __iomem *base;
-+	raw_spinlock_t lock;
-+	u16 intr_mask[REALTEK_GPIO_PORTS_PER_BANK];
-+	u16 intr_type[REALTEK_GPIO_PORTS_PER_BANK];
-+};
-+
-+/* Expand with more flags as devices with other quirks are added */
-+enum realtek_gpio_flags {
-+	/*
-+	 * Allow disabling interrupts, for cases where the port order is
-+	 * unknown. This may result in a port mismatch between ISR and IMR.
-+	 * An interrupt would appear to come from a different line than the
-+	 * line the IRQ handler was assigned to, causing uncaught interrupts.
-+	 */
-+	GPIO_INTERRUPTS_DISABLED = BIT(0),
-+};
-+
-+static struct realtek_gpio_ctrl *irq_data_to_ctrl(struct irq_data *data)
-+{
-+	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
-+
-+	return container_of(gc, struct realtek_gpio_ctrl, gc);
-+}
-+
-+/*
-+ * Normal port order register access
-+ *
-+ * Port information is stored with the first port at offset 0, followed by the
-+ * second, etc. Most registers store one bit per GPIO and use a u8 value per
-+ * port. The two interrupt mask registers store two bits per GPIO, so use u16
-+ * values.
-+ */
-+static void realtek_gpio_write_imr(struct realtek_gpio_ctrl *ctrl,
-+	unsigned int port, u16 irq_type, u16 irq_mask)
-+{
-+	iowrite16(irq_type & irq_mask, ctrl->base + REALTEK_GPIO_REG_IMR + 2 * port);
-+}
-+
-+static void realtek_gpio_clear_isr(struct realtek_gpio_ctrl *ctrl,
-+	unsigned int port, u8 mask)
-+{
-+	iowrite8(mask, ctrl->base + REALTEK_GPIO_REG_ISR + port);
-+}
-+
-+static u8 realtek_gpio_read_isr(struct realtek_gpio_ctrl *ctrl, unsigned int port)
-+{
-+	return ioread8(ctrl->base + REALTEK_GPIO_REG_ISR + port);
-+}
-+
-+/* Set the rising and falling edge mask bits for a GPIO port pin */
-+static u16 realtek_gpio_imr_bits(unsigned int pin, u16 value)
-+{
-+	return (value & REALTEK_GPIO_IMR_LINE_MASK) << 2 * pin;
-+}
-+
-+static void realtek_gpio_irq_ack(struct irq_data *data)
-+{
-+	struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
-+	irq_hw_number_t line = irqd_to_hwirq(data);
-+	unsigned int port = line / 8;
-+	unsigned int port_pin = line % 8;
-+
-+	realtek_gpio_clear_isr(ctrl, port, BIT(port_pin));
-+}
-+
-+static void realtek_gpio_irq_unmask(struct irq_data *data)
-+{
-+	struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
-+	unsigned int line = irqd_to_hwirq(data);
-+	unsigned int port = line / 8;
-+	unsigned int port_pin = line % 8;
-+	unsigned long flags;
-+	u16 m;
-+
-+	raw_spin_lock_irqsave(&ctrl->lock, flags);
-+	m = ctrl->intr_mask[port];
-+	m |= realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK);
-+	ctrl->intr_mask[port] = m;
-+	realtek_gpio_write_imr(ctrl, port, ctrl->intr_type[port], m);
-+	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
-+}
-+
-+static void realtek_gpio_irq_mask(struct irq_data *data)
-+{
-+	struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
-+	unsigned int line = irqd_to_hwirq(data);
-+	unsigned int port = line / 8;
-+	unsigned int port_pin = line % 8;
-+	unsigned long flags;
-+	u16 m;
-+
-+	raw_spin_lock_irqsave(&ctrl->lock, flags);
-+	m = ctrl->intr_mask[port];
-+	m &= ~realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK);
-+	ctrl->intr_mask[port] = m;
-+	realtek_gpio_write_imr(ctrl, port, ctrl->intr_type[port], m);
-+	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
-+}
-+
-+static int realtek_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
-+{
-+	struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
-+	unsigned int line = irqd_to_hwirq(data);
-+	unsigned int port = line / 8;
-+	unsigned int port_pin = line % 8;
-+	unsigned long flags;
-+	u16 type, t;
-+
-+	switch (flow_type & IRQ_TYPE_SENSE_MASK) {
-+	case IRQ_TYPE_EDGE_FALLING:
-+		type = REALTEK_GPIO_IRQ_EDGE_FALLING;
-+		break;
-+	case IRQ_TYPE_EDGE_RISING:
-+		type = REALTEK_GPIO_IRQ_EDGE_RISING;
-+		break;
-+	case IRQ_TYPE_EDGE_BOTH:
-+		type = REALTEK_GPIO_IRQ_EDGE_BOTH;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	irq_set_handler_locked(data, handle_edge_irq);
-+
-+	raw_spin_lock_irqsave(&ctrl->lock, flags);
-+	t = ctrl->intr_type[port];
-+	t &= ~realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK);
-+	t |= realtek_gpio_imr_bits(port_pin, type);
-+	ctrl->intr_type[port] = t;
-+	realtek_gpio_write_imr(ctrl, port, t, ctrl->intr_mask[port]);
-+	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
-+
-+	return 0;
-+}
-+
-+static void realtek_gpio_irq_handler(struct irq_desc *desc)
-+{
-+	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
-+	struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc);
-+	struct irq_chip *irq_chip = irq_desc_get_chip(desc);
-+	unsigned int lines_done;
-+	unsigned int port_pin_count;
-+	unsigned int irq;
-+	unsigned long status;
-+	int offset;
-+
-+	chained_irq_enter(irq_chip, desc);
-+
-+	for (lines_done = 0; lines_done < gc->ngpio; lines_done += 8) {
-+		status = realtek_gpio_read_isr(ctrl, lines_done / 8);
-+		port_pin_count = min(gc->ngpio - lines_done, 8U);
-+		for_each_set_bit(offset, &status, port_pin_count) {
-+			irq = irq_find_mapping(gc->irq.domain, offset);
-+			generic_handle_irq(irq);
-+		}
-+	}
-+
-+	chained_irq_exit(irq_chip, desc);
-+}
-+
-+static int realtek_gpio_irq_init(struct gpio_chip *gc)
-+{
-+	struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc);
-+	unsigned int port;
-+
-+	for (port = 0; (port * 8) < gc->ngpio; port++) {
-+		realtek_gpio_write_imr(ctrl, port, 0, 0);
-+		realtek_gpio_clear_isr(ctrl, port, GENMASK(7, 0));
-+	}
-+
-+	return 0;
-+}
-+
-+static struct irq_chip realtek_gpio_irq_chip = {
-+	.name = "realtek-otto-gpio",
-+	.irq_ack = realtek_gpio_irq_ack,
-+	.irq_mask = realtek_gpio_irq_mask,
-+	.irq_unmask = realtek_gpio_irq_unmask,
-+	.irq_set_type = realtek_gpio_irq_set_type,
-+};
-+
-+static const struct of_device_id realtek_gpio_of_match[] = {
-+	{
-+		.compatible = "realtek,otto-gpio",
-+		.data = (void *)GPIO_INTERRUPTS_DISABLED,
-+	},
-+	{
-+		.compatible = "realtek,rtl8380-gpio",
-+	},
-+	{
-+		.compatible = "realtek,rtl8390-gpio",
-+	},
-+	{}
-+};
-+MODULE_DEVICE_TABLE(of, realtek_gpio_of_match);
-+
-+static int realtek_gpio_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	unsigned int dev_flags;
-+	struct gpio_irq_chip *girq;
-+	struct realtek_gpio_ctrl *ctrl;
-+	u32 ngpios;
-+	int err, irq;
-+
-+	ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
-+	if (!ctrl)
-+		return -ENOMEM;
-+
-+	dev_flags = (unsigned int) device_get_match_data(dev);
-+
-+	ngpios = REALTEK_GPIO_MAX;
-+	device_property_read_u32(dev, "ngpios", &ngpios);
-+
-+	if (ngpios > REALTEK_GPIO_MAX) {
-+		dev_err(&pdev->dev, "invalid ngpios (max. %d)\n",
-+			REALTEK_GPIO_MAX);
-+		return -EINVAL;
-+	}
-+
-+	ctrl->base = devm_platform_ioremap_resource(pdev, 0);
-+	if (IS_ERR(ctrl->base))
-+		return PTR_ERR(ctrl->base);
-+
-+	raw_spin_lock_init(&ctrl->lock);
-+
-+	err = bgpio_init(&ctrl->gc, dev, 4,
-+		ctrl->base + REALTEK_GPIO_REG_DATA, NULL, NULL,
-+		ctrl->base + REALTEK_GPIO_REG_DIR, NULL,
-+		BGPIOF_BIG_ENDIAN_BYTE_ORDER);
-+	if (err) {
-+		dev_err(dev, "unable to init generic GPIO");
-+		return err;
-+	}
-+
-+	ctrl->gc.ngpio = ngpios;
-+	ctrl->gc.owner = THIS_MODULE;
-+
-+	irq = platform_get_irq_optional(pdev, 0);
-+	if (!(dev_flags & GPIO_INTERRUPTS_DISABLED) && irq > 0) {
-+		girq = &ctrl->gc.irq;
-+		girq->chip = &realtek_gpio_irq_chip;
-+		girq->default_type = IRQ_TYPE_NONE;
-+		girq->handler = handle_bad_irq;
-+		girq->parent_handler = realtek_gpio_irq_handler;
-+		girq->num_parents = 1;
-+		girq->parents = devm_kcalloc(dev, girq->num_parents,
-+					sizeof(*girq->parents),	GFP_KERNEL);
-+		if (!girq->parents)
-+			return -ENOMEM;
-+		girq->parents[0] = irq;
-+		girq->init_hw = realtek_gpio_irq_init;
-+	}
-+
-+	return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
-+}
-+
-+static struct platform_driver realtek_gpio_driver = {
-+	.driver = {
-+		.name = "realtek-otto-gpio",
-+		.of_match_table	= realtek_gpio_of_match,
-+	},
-+	.probe = realtek_gpio_probe,
-+};
-+module_platform_driver(realtek_gpio_driver);
-+
-+MODULE_DESCRIPTION("Realtek Otto GPIO support");
-+MODULE_AUTHOR("Sander Vanheule <sander@svanheule.net>");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/realtek/patches-5.15/003-5.12-spi-realtek-rtl838x-rtl839x-spi-controller.patch b/target/linux/realtek/patches-5.15/003-5.12-spi-realtek-rtl838x-rtl839x-spi-controller.patch
deleted file mode 100644
index 325e904994..0000000000
--- a/target/linux/realtek/patches-5.15/003-5.12-spi-realtek-rtl838x-rtl839x-spi-controller.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From 6acbd614c2c8d3b8de5fb7605d6e24b9b3a8a17b Mon Sep 17 00:00:00 2001
-From: Bert Vermeulen <bert@biot.com>
-Date: Wed, 20 Jan 2021 14:59:27 +0100
-Subject: spi: Realtek RTL838x/RTL839x SPI controller
-
-Signed-off-by: Bert Vermeulen <bert@biot.com>
-Link: https://lore.kernel.org/r/20210120135928.246054-2-bert@biot.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- .../devicetree/bindings/spi/realtek,rtl-spi.yaml   | 41 ++++++++++++++++++++++
- 1 file changed, 41 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/spi/realtek,rtl-spi.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/spi/realtek,rtl-spi.yaml
-@@ -0,0 +1,41 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/spi/realtek,rtl-spi.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Realtek RTL838x/RTL839x SPI controller
-+
-+maintainers:
-+  - Bert Vermeulen <bert@biot.com>
-+  - Birger Koblitz <mail@birger-koblitz.de>
-+
-+allOf:
-+  - $ref: "spi-controller.yaml#"
-+
-+properties:
-+  compatible:
-+    oneOf:
-+      - const: realtek,rtl8380-spi
-+      - const: realtek,rtl8382-spi
-+      - const: realtek,rtl8391-spi
-+      - const: realtek,rtl8392-spi
-+      - const: realtek,rtl8393-spi
-+
-+  reg:
-+    maxItems: 1
-+
-+required:
-+  - compatible
-+  - reg
-+
-+unevaluatedProperties: false
-+
-+examples:
-+  - |
-+    spi: spi@1200 {
-+        compatible = "realtek,rtl8382-spi";
-+        reg = <0x1200 0x100>;
-+        #address-cells = <1>;
-+        #size-cells = <0>;
-+    };
diff --git a/target/linux/realtek/patches-5.15/004-5.12-spi-realtek-rtl-add-support-for-realtek-rtl838x-rtl839x-spi-controllers.patch b/target/linux/realtek/patches-5.15/004-5.12-spi-realtek-rtl-add-support-for-realtek-rtl838x-rtl839x-spi-controllers.patch
deleted file mode 100644
index 090847baad..0000000000
--- a/target/linux/realtek/patches-5.15/004-5.12-spi-realtek-rtl-add-support-for-realtek-rtl838x-rtl839x-spi-controllers.patch
+++ /dev/null
@@ -1,248 +0,0 @@
-From a8af5cc2ff1e804694629a8ef320935629dd15ba Mon Sep 17 00:00:00 2001
-From: Bert Vermeulen <bert@biot.com>
-Date: Wed, 20 Jan 2021 14:59:28 +0100
-Subject: spi: realtek-rtl: Add support for Realtek RTL838x/RTL839x SPI
- controllers
-
-This driver likely also supports earlier (RTL8196) and later (RTL93xx)
-SoCs.
-
-The SPI hardware in these SoCs is specifically intended for connecting NOR
-bootflash chips, and only used for that in dozens of examined devices.
-However boiled down to basics, it's really just a half-duplex SPI
-controller.
-
-The hardware appears to have a vestigial second chip-select control, but
-it hasn't been seen in the wild and is thus not supported.
-
-Signed-off-by: Bert Vermeulen <bert@biot.com>
-Link: https://lore.kernel.org/r/20210120135928.246054-3-bert@biot.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- drivers/spi/Makefile          |   1 +
- drivers/spi/spi-realtek-rtl.c | 209 ++++++++++++++++++++++++++++++++++++++++++
- 2 files changed, 210 insertions(+)
- create mode 100644 drivers/spi/spi-realtek-rtl.c
-
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -94,6 +94,7 @@ obj-$(CONFIG_SPI_QCOM_QSPI)		+= spi-qcom
- obj-$(CONFIG_SPI_QUP)			+= spi-qup.o
- obj-$(CONFIG_SPI_ROCKCHIP)		+= spi-rockchip.o
- obj-$(CONFIG_SPI_RB4XX)			+= spi-rb4xx.o
-+obj-$(CONFIG_MACH_REALTEK_RTL)		+= spi-realtek-rtl.o
- obj-$(CONFIG_SPI_RPCIF)			+= spi-rpc-if.o
- obj-$(CONFIG_SPI_RSPI)			+= spi-rspi.o
- obj-$(CONFIG_SPI_S3C24XX)		+= spi-s3c24xx-hw.o
---- /dev/null
-+++ b/drivers/spi/spi-realtek-rtl.c
-@@ -0,0 +1,209 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/spi/spi.h>
-+
-+struct rtspi {
-+	void __iomem *base;
-+};
-+
-+/* SPI Flash Configuration Register */
-+#define RTL_SPI_SFCR			0x00
-+#define RTL_SPI_SFCR_RBO		BIT(28)
-+#define RTL_SPI_SFCR_WBO		BIT(27)
-+
-+/* SPI Flash Control and Status Register */
-+#define RTL_SPI_SFCSR			0x08
-+#define RTL_SPI_SFCSR_CSB0		BIT(31)
-+#define RTL_SPI_SFCSR_CSB1		BIT(30)
-+#define RTL_SPI_SFCSR_RDY		BIT(27)
-+#define RTL_SPI_SFCSR_CS		BIT(24)
-+#define RTL_SPI_SFCSR_LEN_MASK		~(0x03 << 28)
-+#define RTL_SPI_SFCSR_LEN1		(0x00 << 28)
-+#define RTL_SPI_SFCSR_LEN4		(0x03 << 28)
-+
-+/* SPI Flash Data Register */
-+#define RTL_SPI_SFDR			0x0c
-+
-+#define REG(x)		(rtspi->base + x)
-+
-+
-+static void rt_set_cs(struct spi_device *spi, bool active)
-+{
-+	struct rtspi *rtspi = spi_controller_get_devdata(spi->controller);
-+	u32 value;
-+
-+	/* CS0 bit is active low */
-+	value = readl(REG(RTL_SPI_SFCSR));
-+	if (active)
-+		value |= RTL_SPI_SFCSR_CSB0;
-+	else
-+		value &= ~RTL_SPI_SFCSR_CSB0;
-+	writel(value, REG(RTL_SPI_SFCSR));
-+}
-+
-+static void set_size(struct rtspi *rtspi, int size)
-+{
-+	u32 value;
-+
-+	value = readl(REG(RTL_SPI_SFCSR));
-+	value &= RTL_SPI_SFCSR_LEN_MASK;
-+	if (size == 4)
-+		value |= RTL_SPI_SFCSR_LEN4;
-+	else if (size == 1)
-+		value |= RTL_SPI_SFCSR_LEN1;
-+	writel(value, REG(RTL_SPI_SFCSR));
-+}
-+
-+static inline void wait_ready(struct rtspi *rtspi)
-+{
-+	while (!(readl(REG(RTL_SPI_SFCSR)) & RTL_SPI_SFCSR_RDY))
-+		cpu_relax();
-+}
-+static void send4(struct rtspi *rtspi, const u32 *buf)
-+{
-+	wait_ready(rtspi);
-+	set_size(rtspi, 4);
-+	writel(*buf, REG(RTL_SPI_SFDR));
-+}
-+
-+static void send1(struct rtspi *rtspi, const u8 *buf)
-+{
-+	wait_ready(rtspi);
-+	set_size(rtspi, 1);
-+	writel(buf[0] << 24, REG(RTL_SPI_SFDR));
-+}
-+
-+static void rcv4(struct rtspi *rtspi, u32 *buf)
-+{
-+	wait_ready(rtspi);
-+	set_size(rtspi, 4);
-+	*buf = readl(REG(RTL_SPI_SFDR));
-+}
-+
-+static void rcv1(struct rtspi *rtspi, u8 *buf)
-+{
-+	wait_ready(rtspi);
-+	set_size(rtspi, 1);
-+	*buf = readl(REG(RTL_SPI_SFDR)) >> 24;
-+}
-+
-+static int transfer_one(struct spi_controller *ctrl, struct spi_device *spi,
-+			struct spi_transfer *xfer)
-+{
-+	struct rtspi *rtspi = spi_controller_get_devdata(ctrl);
-+	void *rx_buf;
-+	const void *tx_buf;
-+	int cnt;
-+
-+	tx_buf = xfer->tx_buf;
-+	rx_buf = xfer->rx_buf;
-+	cnt = xfer->len;
-+	if (tx_buf) {
-+		while (cnt >= 4) {
-+			send4(rtspi, tx_buf);
-+			tx_buf += 4;
-+			cnt -= 4;
-+		}
-+		while (cnt) {
-+			send1(rtspi, tx_buf);
-+			tx_buf++;
-+			cnt--;
-+		}
-+	} else if (rx_buf) {
-+		while (cnt >= 4) {
-+			rcv4(rtspi, rx_buf);
-+			rx_buf += 4;
-+			cnt -= 4;
-+		}
-+		while (cnt) {
-+			rcv1(rtspi, rx_buf);
-+			rx_buf++;
-+			cnt--;
-+		}
-+	}
-+
-+	spi_finalize_current_transfer(ctrl);
-+
-+	return 0;
-+}
-+
-+static void init_hw(struct rtspi *rtspi)
-+{
-+	u32 value;
-+
-+	/* Turn on big-endian byte ordering */
-+	value = readl(REG(RTL_SPI_SFCR));
-+	value |= RTL_SPI_SFCR_RBO | RTL_SPI_SFCR_WBO;
-+	writel(value, REG(RTL_SPI_SFCR));
-+
-+	value = readl(REG(RTL_SPI_SFCSR));
-+	/* Permanently disable CS1, since it's never used */
-+	value |= RTL_SPI_SFCSR_CSB1;
-+	/* Select CS0 for use */
-+	value &= RTL_SPI_SFCSR_CS;
-+	writel(value, REG(RTL_SPI_SFCSR));
-+}
-+
-+static int realtek_rtl_spi_probe(struct platform_device *pdev)
-+{
-+	struct spi_controller *ctrl;
-+	struct rtspi *rtspi;
-+	int err;
-+
-+	ctrl = devm_spi_alloc_master(&pdev->dev, sizeof(*rtspi));
-+	if (!ctrl) {
-+		dev_err(&pdev->dev, "Error allocating SPI controller\n");
-+		return -ENOMEM;
-+	}
-+	platform_set_drvdata(pdev, ctrl);
-+	rtspi = spi_controller_get_devdata(ctrl);
-+
-+	rtspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
-+	if (IS_ERR(rtspi->base)) {
-+		dev_err(&pdev->dev, "Could not map SPI register address");
-+		return -ENOMEM;
-+	}
-+
-+	init_hw(rtspi);
-+
-+	ctrl->dev.of_node = pdev->dev.of_node;
-+	ctrl->flags = SPI_CONTROLLER_HALF_DUPLEX;
-+	ctrl->set_cs = rt_set_cs;
-+	ctrl->transfer_one = transfer_one;
-+
-+	err = devm_spi_register_controller(&pdev->dev, ctrl);
-+	if (err) {
-+		dev_err(&pdev->dev, "Could not register SPI controller\n");
-+		return -ENODEV;
-+	}
-+
-+	return 0;
-+}
-+
-+
-+static const struct of_device_id realtek_rtl_spi_of_ids[] = {
-+	{ .compatible = "realtek,rtl8380-spi" },
-+	{ .compatible = "realtek,rtl8382-spi" },
-+	{ .compatible = "realtek,rtl8391-spi" },
-+	{ .compatible = "realtek,rtl8392-spi" },
-+	{ .compatible = "realtek,rtl8393-spi" },
-+	{ /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, realtek_rtl_spi_of_ids);
-+
-+static struct platform_driver realtek_rtl_spi_driver = {
-+	.probe = realtek_rtl_spi_probe,
-+	.driver = {
-+		.name = "realtek-rtl-spi",
-+		.of_match_table = realtek_rtl_spi_of_ids,
-+	},
-+};
-+
-+module_platform_driver(realtek_rtl_spi_driver);
-+
-+MODULE_LICENSE("GPL v2");
-+MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
-+MODULE_DESCRIPTION("Realtek RTL SPI driver");
diff --git a/target/linux/realtek/patches-5.15/005-5.12-dt-bindings-interrupt-controller-add-realtek-rtl838x-rtl839x-support.patch b/target/linux/realtek/patches-5.15/005-5.12-dt-bindings-interrupt-controller-add-realtek-rtl838x-rtl839x-support.patch
deleted file mode 100644
index 165545a220..0000000000
--- a/target/linux/realtek/patches-5.15/005-5.12-dt-bindings-interrupt-controller-add-realtek-rtl838x-rtl839x-support.patch
+++ /dev/null
@@ -1,78 +0,0 @@
-From 4a2b92a5d3519fc2c1edda4d4aa0e05bff41e8de Mon Sep 17 00:00:00 2001
-From: Bert Vermeulen <bert@biot.com>
-Date: Fri, 22 Jan 2021 21:42:23 +0100
-Subject: dt-bindings: interrupt-controller: Add Realtek RTL838x/RTL839x
- support
-
-Document the binding for the Realtek RTL838x/RTL839x interrupt controller.
-
-Reviewed-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Bert Vermeulen <bert@biot.com>
-[maz: Add a commit message, as the author couldn't be bothered...]
-Signed-off-by: Marc Zyngier <maz@kernel.org>
-Link: https://lore.kernel.org/r/20210122204224.509124-2-bert@biot.com
----
- .../interrupt-controller/realtek,rtl-intc.yaml     | 57 ++++++++++++++++++++++
- 1 file changed, 57 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml
-@@ -0,0 +1,57 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/interrupt-controller/realtek,rtl-intc.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Realtek RTL SoC interrupt controller devicetree bindings
-+
-+maintainers:
-+  - Birger Koblitz <mail@birger-koblitz.de>
-+  - Bert Vermeulen <bert@biot.com>
-+  - John Crispin <john@phrozen.org>
-+
-+properties:
-+  compatible:
-+    const: realtek,rtl-intc
-+
-+  "#interrupt-cells":
-+    const: 1
-+
-+  reg:
-+    maxItems: 1
-+
-+  interrupts:
-+    maxItems: 1
-+
-+  interrupt-controller: true
-+
-+  "#address-cells":
-+    const: 0
-+
-+  interrupt-map:
-+    description: Describes mapping from SoC interrupts to CPU interrupts
-+
-+required:
-+  - compatible
-+  - reg
-+  - "#interrupt-cells"
-+  - interrupt-controller
-+  - "#address-cells"
-+  - interrupt-map
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    intc: interrupt-controller@3000 {
-+      compatible = "realtek,rtl-intc";
-+      #interrupt-cells = <1>;
-+      interrupt-controller;
-+      reg = <0x3000 0x20>;
-+      #address-cells = <0>;
-+      interrupt-map =
-+              <31 &cpuintc 2>,
-+              <30 &cpuintc 1>,
-+              <29 &cpuintc 5>;
-+    };
diff --git a/target/linux/realtek/patches-5.15/006-5.12-irqchip-add-support-for-realtek-rtl838x-rtl839x-interrupt-controller.patch b/target/linux/realtek/patches-5.15/006-5.12-irqchip-add-support-for-realtek-rtl838x-rtl839x-interrupt-controller.patch
deleted file mode 100644
index 753c41eb2f..0000000000
--- a/target/linux/realtek/patches-5.15/006-5.12-irqchip-add-support-for-realtek-rtl838x-rtl839x-interrupt-controller.patch
+++ /dev/null
@@ -1,211 +0,0 @@
-From 9f3a0f34b84ad1b9a8f2bdae44b66f16685b2143 Mon Sep 17 00:00:00 2001
-From: Bert Vermeulen <bert@biot.com>
-Date: Fri, 22 Jan 2021 21:42:24 +0100
-Subject: irqchip: Add support for Realtek RTL838x/RTL839x interrupt controller
-
-This is a standard IRQ driver with only status and mask registers.
-
-The mapping from SoC interrupts (18-31) to MIPS core interrupts is
-done via an interrupt-map in device tree.
-
-Signed-off-by: Bert Vermeulen <bert@biot.com>
-Signed-off-by: Birger Koblitz <mail@birger-koblitz.de>
-Acked-by: John Crispin <john@phrozen.org>
-Signed-off-by: Marc Zyngier <maz@kernel.org>
-Link: https://lore.kernel.org/r/20210122204224.509124-3-bert@biot.com
----
- drivers/irqchip/Makefile          |   1 +
- drivers/irqchip/irq-realtek-rtl.c | 180 ++++++++++++++++++++++++++++++++++++++
- 2 files changed, 181 insertions(+)
- create mode 100644 drivers/irqchip/irq-realtek-rtl.c
-
---- a/drivers/irqchip/Makefile
-+++ b/drivers/irqchip/Makefile
-@@ -114,3 +114,4 @@ obj-$(CONFIG_LOONGSON_PCH_PIC)		+= irq-l
- obj-$(CONFIG_LOONGSON_PCH_MSI)		+= irq-loongson-pch-msi.o
- obj-$(CONFIG_MST_IRQ)			+= irq-mst-intc.o
- obj-$(CONFIG_SL28CPLD_INTC)		+= irq-sl28cpld.o
-+obj-$(CONFIG_MACH_REALTEK_RTL)		+= irq-realtek-rtl.o
---- /dev/null
-+++ b/drivers/irqchip/irq-realtek-rtl.c
-@@ -0,0 +1,180 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * Copyright (C) 2020 Birger Koblitz <mail@birger-koblitz.de>
-+ * Copyright (C) 2020 Bert Vermeulen <bert@biot.com>
-+ * Copyright (C) 2020 John Crispin <john@phrozen.org>
-+ */
-+
-+#include <linux/of_irq.h>
-+#include <linux/irqchip.h>
-+#include <linux/spinlock.h>
-+#include <linux/of_address.h>
-+#include <linux/irqchip/chained_irq.h>
-+
-+/* Global Interrupt Mask Register */
-+#define RTL_ICTL_GIMR		0x00
-+/* Global Interrupt Status Register */
-+#define RTL_ICTL_GISR		0x04
-+/* Interrupt Routing Registers */
-+#define RTL_ICTL_IRR0		0x08
-+#define RTL_ICTL_IRR1		0x0c
-+#define RTL_ICTL_IRR2		0x10
-+#define RTL_ICTL_IRR3		0x14
-+
-+#define REG(x)		(realtek_ictl_base + x)
-+
-+static DEFINE_RAW_SPINLOCK(irq_lock);
-+static void __iomem *realtek_ictl_base;
-+
-+static void realtek_ictl_unmask_irq(struct irq_data *i)
-+{
-+	unsigned long flags;
-+	u32 value;
-+
-+	raw_spin_lock_irqsave(&irq_lock, flags);
-+
-+	value = readl(REG(RTL_ICTL_GIMR));
-+	value |= BIT(i->hwirq);
-+	writel(value, REG(RTL_ICTL_GIMR));
-+
-+	raw_spin_unlock_irqrestore(&irq_lock, flags);
-+}
-+
-+static void realtek_ictl_mask_irq(struct irq_data *i)
-+{
-+	unsigned long flags;
-+	u32 value;
-+
-+	raw_spin_lock_irqsave(&irq_lock, flags);
-+
-+	value = readl(REG(RTL_ICTL_GIMR));
-+	value &= ~BIT(i->hwirq);
-+	writel(value, REG(RTL_ICTL_GIMR));
-+
-+	raw_spin_unlock_irqrestore(&irq_lock, flags);
-+}
-+
-+static struct irq_chip realtek_ictl_irq = {
-+	.name = "realtek-rtl-intc",
-+	.irq_mask = realtek_ictl_mask_irq,
-+	.irq_unmask = realtek_ictl_unmask_irq,
-+};
-+
-+static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
-+{
-+	irq_set_chip_and_handler(hw, &realtek_ictl_irq, handle_level_irq);
-+
-+	return 0;
-+}
-+
-+static const struct irq_domain_ops irq_domain_ops = {
-+	.map = intc_map,
-+	.xlate = irq_domain_xlate_onecell,
-+};
-+
-+static void realtek_irq_dispatch(struct irq_desc *desc)
-+{
-+	struct irq_chip *chip = irq_desc_get_chip(desc);
-+	struct irq_domain *domain;
-+	unsigned int pending;
-+
-+	chained_irq_enter(chip, desc);
-+	pending = readl(REG(RTL_ICTL_GIMR)) & readl(REG(RTL_ICTL_GISR));
-+	if (unlikely(!pending)) {
-+		spurious_interrupt();
-+		goto out;
-+	}
-+	domain = irq_desc_get_handler_data(desc);
-+	generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
-+
-+out:
-+	chained_irq_exit(chip, desc);
-+}
-+
-+/*
-+ * SoC interrupts are cascaded to MIPS CPU interrupts according to the
-+ * interrupt-map in the device tree. Each SoC interrupt gets 4 bits for
-+ * the CPU interrupt in an Interrupt Routing Register. Max 32 SoC interrupts
-+ * thus go into 4 IRRs.
-+ */
-+static int __init map_interrupts(struct device_node *node, struct irq_domain *domain)
-+{
-+	struct device_node *cpu_ictl;
-+	const __be32 *imap;
-+	u32 imaplen, soc_int, cpu_int, tmp, regs[4];
-+	int ret, i, irr_regs[] = {
-+		RTL_ICTL_IRR3,
-+		RTL_ICTL_IRR2,
-+		RTL_ICTL_IRR1,
-+		RTL_ICTL_IRR0,
-+	};
-+	u8 mips_irqs_set;
-+
-+	ret = of_property_read_u32(node, "#address-cells", &tmp);
-+	if (ret || tmp)
-+		return -EINVAL;
-+
-+	imap = of_get_property(node, "interrupt-map", &imaplen);
-+	if (!imap || imaplen % 3)
-+		return -EINVAL;
-+
-+	mips_irqs_set = 0;
-+	memset(regs, 0, sizeof(regs));
-+	for (i = 0; i < imaplen; i += 3 * sizeof(u32)) {
-+		soc_int = be32_to_cpup(imap);
-+		if (soc_int > 31)
-+			return -EINVAL;
-+
-+		cpu_ictl = of_find_node_by_phandle(be32_to_cpup(imap + 1));
-+		if (!cpu_ictl)
-+			return -EINVAL;
-+		ret = of_property_read_u32(cpu_ictl, "#interrupt-cells", &tmp);
-+		if (ret || tmp != 1)
-+			return -EINVAL;
-+		of_node_put(cpu_ictl);
-+
-+		cpu_int = be32_to_cpup(imap + 2);
-+		if (cpu_int > 7)
-+			return -EINVAL;
-+
-+		if (!(mips_irqs_set & BIT(cpu_int))) {
-+			irq_set_chained_handler_and_data(cpu_int, realtek_irq_dispatch,
-+							 domain);
-+			mips_irqs_set |= BIT(cpu_int);
-+		}
-+
-+		regs[(soc_int * 4) / 32] |= cpu_int << (soc_int * 4) % 32;
-+		imap += 3;
-+	}
-+
-+	for (i = 0; i < 4; i++)
-+		writel(regs[i], REG(irr_regs[i]));
-+
-+	return 0;
-+}
-+
-+static int __init realtek_rtl_of_init(struct device_node *node, struct device_node *parent)
-+{
-+	struct irq_domain *domain;
-+	int ret;
-+
-+	realtek_ictl_base = of_iomap(node, 0);
-+	if (!realtek_ictl_base)
-+		return -ENXIO;
-+
-+	/* Disable all cascaded interrupts */
-+	writel(0, REG(RTL_ICTL_GIMR));
-+
-+	domain = irq_domain_add_simple(node, 32, 0,
-+				       &irq_domain_ops, NULL);
-+
-+	ret = map_interrupts(node, domain);
-+	if (ret) {
-+		pr_err("invalid interrupt map\n");
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+IRQCHIP_DECLARE(realtek_rtl_intc, "realtek,rtl-intc", realtek_rtl_of_init);