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author | Roman Yeryomin <roman@advem.lv> | 2018-01-17 00:07:58 +0200 |
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committer | John Crispin <john@phrozen.org> | 2018-02-15 10:46:39 +0100 |
commit | f4e5880d0f3496a3151fe24d87ca2d08d3403a83 (patch) | |
tree | b2a3f276e4786d7eed8d928cd8984975334556cf /target/linux/ramips/patches-4.14/100-mt7621-core-detect-hack.patch | |
parent | a3b9cbafc33a94606368226020e7b69ff85f1115 (diff) | |
download | upstream-f4e5880d0f3496a3151fe24d87ca2d08d3403a83.tar.gz upstream-f4e5880d0f3496a3151fe24d87ca2d08d3403a83.tar.bz2 upstream-f4e5880d0f3496a3151fe24d87ca2d08d3403a83.zip |
ramips: preliminary support for 4.14
- removed upstreamed patches
- 0901-spansion_nand_id_fix.patch is disabled, not clear if it's needed
Signed-off-by: Roman Yeryomin <roman@advem.lv>
Signed-off-by: John Crispin <john@phrozen.org>
Diffstat (limited to 'target/linux/ramips/patches-4.14/100-mt7621-core-detect-hack.patch')
-rw-r--r-- | target/linux/ramips/patches-4.14/100-mt7621-core-detect-hack.patch | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-4.14/100-mt7621-core-detect-hack.patch b/target/linux/ramips/patches-4.14/100-mt7621-core-detect-hack.patch new file mode 100644 index 0000000000..991e19b6df --- /dev/null +++ b/target/linux/ramips/patches-4.14/100-mt7621-core-detect-hack.patch @@ -0,0 +1,61 @@ +There is a variant of MT7621 which contains only one CPU core instead of 2. +This is not reflected in the config register, so the kernel detects more +physical cores, which leads to a hang on SMP bringup. +Add a hack to detect missing cores. + +Signed-off-by: Felix Fietkau <nbd@nbd.name> + +--- a/arch/mips/kernel/smp-cps.c ++++ b/arch/mips/kernel/smp-cps.c +@@ -47,6 +47,11 @@ static unsigned core_vpe_count(unsigned + return mips_cps_numvps(cluster, core); + } + ++bool __weak plat_cpu_core_present(int core) ++{ ++ return true; ++} ++ + static void __init cps_smp_setup(void) + { + unsigned int nclusters, ncores, nvpes, core_vpes; +@@ -64,6 +69,8 @@ static void __init cps_smp_setup(void) + + ncores = mips_cps_numcores(cl); + for (c = 0; c < ncores; c++) { ++ if (!plat_cpu_core_present(c)) ++ continue; + core_vpes = core_vpe_count(cl, c); + + if (c > 0) +--- a/arch/mips/ralink/mt7621.c ++++ b/arch/mips/ralink/mt7621.c +@@ -15,6 +15,7 @@ + #include <asm/mips-cps.h> + #include <asm/mach-ralink/ralink_regs.h> + #include <asm/mach-ralink/mt7621.h> ++#include <asm/mips-boards/launch.h> + + #include <pinmux.h> + +@@ -162,6 +163,20 @@ void __init ralink_of_remap(void) + panic("Failed to remap core resources"); + } + ++bool plat_cpu_core_present(int core) ++{ ++ struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); ++ ++ if (!core) ++ return true; ++ launch += core * 2; /* 2 VPEs per core */ ++ if (!(launch->flags & LAUNCH_FREADY)) ++ return false; ++ if (launch->flags & (LAUNCH_FGO | LAUNCH_FGONE)) ++ return false; ++ return true; ++} ++ + void prom_soc_init(struct ralink_soc_info *soc_info) + { + void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE); |