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| author | John Crispin <blogic@openwrt.org> | 2013-07-14 18:00:34 +0000 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2013-07-14 18:00:34 +0000 |
| commit | d4b8b8d62fcb34be61c325efa6f91d937d19a616 (patch) | |
| tree | 29b48b2691fa9b9bb934598aab3dd09bb8562f6e /target/linux/ramips/patches-3.8/0055-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch | |
| parent | 6bcbd536ed1e845dce59f5a063bbce293740c26e (diff) | |
| download | upstream-d4b8b8d62fcb34be61c325efa6f91d937d19a616.tar.gz upstream-d4b8b8d62fcb34be61c325efa6f91d937d19a616.tar.bz2 upstream-d4b8b8d62fcb34be61c325efa6f91d937d19a616.zip | |
ralink: drop v3.8 support
Signed-off-by: John Crispin <blogic@opewnrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@37311 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips/patches-3.8/0055-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch')
| -rw-r--r-- | target/linux/ramips/patches-3.8/0055-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch | 25 |
1 files changed, 0 insertions, 25 deletions
diff --git a/target/linux/ramips/patches-3.8/0055-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch b/target/linux/ramips/patches-3.8/0055-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch deleted file mode 100644 index b6d91eb66f..0000000000 --- a/target/linux/ramips/patches-3.8/0055-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 148d428995c21cc95350937d42ffd3b13e36daa5 Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Thu, 23 May 2013 18:46:25 +0200 -Subject: [PATCH 55/79] MIPS: ralink: add spi clock definition to mt7620a - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - arch/mips/ralink/mt7620.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c -index 69729a5..08c96db6 100644 ---- a/arch/mips/ralink/mt7620.c -+++ b/arch/mips/ralink/mt7620.c -@@ -183,6 +183,7 @@ void __init ralink_clk_init(void) - ralink_clk_add("cpu", cpu_rate); - ralink_clk_add("10000100.timer", 40000000); - ralink_clk_add("10000500.uart", 40000000); -+ ralink_clk_add("10000b00.spi", 40000000); - ralink_clk_add("10000c00.uartlite", 40000000); - } - --- -1.7.10.4 - |