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author | John Crispin <blogic@openwrt.org> | 2014-03-18 19:21:56 +0000 |
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committer | John Crispin <blogic@openwrt.org> | 2014-03-18 19:21:56 +0000 |
commit | de51ae36beb618be705b292e32610a2e3efae330 (patch) | |
tree | 5bd54a4e1462f1d3bd187b2af9d1f2d1d4f00d55 /target/linux/ramips/patches-3.10/0107-MIPS-ralink-allow-manual-memory-override.patch | |
parent | 694bc2270f53c34cdf86d5067040481f37e44e00 (diff) | |
download | upstream-de51ae36beb618be705b292e32610a2e3efae330.tar.gz upstream-de51ae36beb618be705b292e32610a2e3efae330.tar.bz2 upstream-de51ae36beb618be705b292e32610a2e3efae330.zip |
ralink: refresh patches
Signed-off-by: John Crispin <blogic@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39949 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips/patches-3.10/0107-MIPS-ralink-allow-manual-memory-override.patch')
-rw-r--r-- | target/linux/ramips/patches-3.10/0107-MIPS-ralink-allow-manual-memory-override.patch | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-3.10/0107-MIPS-ralink-allow-manual-memory-override.patch b/target/linux/ramips/patches-3.10/0107-MIPS-ralink-allow-manual-memory-override.patch new file mode 100644 index 0000000000..4fb2b2be37 --- /dev/null +++ b/target/linux/ramips/patches-3.10/0107-MIPS-ralink-allow-manual-memory-override.patch @@ -0,0 +1,45 @@ +From ee46d05eefefb0fb40b5682b4f6f3876b496044b Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Sun, 16 Mar 2014 04:40:48 +0000 +Subject: [PATCH 107/133] MIPS: ralink: allow manual memory override + +RT5350 relies on the bootloader setting up the memc correctly. +On sme boards the setup is incorrect leading to 32 MB being available but only 16 being recognized. Allow these boards to manually override the memory range +. +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/ralink/of.c | 16 +++++++++++++++- + 1 file changed, 15 insertions(+), 1 deletion(-) + +--- a/arch/mips/ralink/of.c ++++ b/arch/mips/ralink/of.c +@@ -77,6 +77,17 @@ void __init device_tree_init(void) + //free_bootmem(base, size); + } + ++static int memory_dtb; ++ ++static int __init early_init_dt_find_memory(unsigned long node, const char *uname, ++ int depth, void *data) ++{ ++ if (depth == 1 && !strcmp(uname, "memory@0")) ++ memory_dtb = 1; ++ ++ return 0; ++} ++ + void __init plat_mem_setup(void) + { + set_io_port_base(KSEG1); +@@ -87,7 +98,10 @@ void __init plat_mem_setup(void) + */ + __dt_setup_arch(&__dtb_start); + +- if (soc_info.mem_size) ++ of_scan_flat_dt(early_init_dt_find_memory, NULL); ++ if (memory_dtb) ++ of_scan_flat_dt(early_init_dt_scan_memory, NULL); ++ else if (soc_info.mem_size) + add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M, + BOOT_MEM_RAM); + else |