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| author | Jonathan A. Kollasch <jakllsch@kollasch.net> | 2020-09-11 14:33:39 -0500 |
|---|---|---|
| committer | Adrian Schmutzler <freifunk@adrianschmutzler.de> | 2021-06-12 11:01:43 +0200 |
| commit | 0794a784e905e14f673fee6120e86be67bb4862d (patch) | |
| tree | 1b9c7738bf1f1d0420bd9271761602a554f604c0 /target/linux/ramips/dts/rt3052_tenda_3g300m.dts | |
| parent | 1a8de9cbf91fe1f2550140f4254bc310a99ccd39 (diff) | |
| download | upstream-0794a784e905e14f673fee6120e86be67bb4862d.tar.gz upstream-0794a784e905e14f673fee6120e86be67bb4862d.tar.bz2 upstream-0794a784e905e14f673fee6120e86be67bb4862d.zip | |
ath79: fix eth0 PLL registers on WD My Net Wi-Fi Range Extender
This replaces the register bits for RGMII delay on the MAC side in favor
of having the RGMII delay on the PHY side by setting the phy-mode
property to rgmii-id (RGMII internal delay), which is supported by the
at803x driver. Speed 1000 is fixed as a result, so now all ethernet
speeds function.
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-by: Michael Pratt <mcpratt@pm.me>
(cherry picked from commit f36990eae77c3a22842a2c418378c5dd40dec366)
Diffstat (limited to 'target/linux/ramips/dts/rt3052_tenda_3g300m.dts')
0 files changed, 0 insertions, 0 deletions