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author | Adrian Schmutzler <freifunk@adrianschmutzler.de> | 2019-07-03 23:22:25 +0200 |
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committer | Daniel Golle <daniel@makrotopia.org> | 2019-07-10 17:36:29 +0200 |
commit | 48047b3a5c6aa9fff89a7a9c7ec76d8335b1a8e7 (patch) | |
tree | 6f48a2118b5ab45dcb88ab7dab0b18a6feccb619 /target/linux/ramips/dts/mt7620a_hiwifi_hc5761.dts | |
parent | 402138d12dca1a24d2837145c8d31c9d35769b9d (diff) | |
download | upstream-48047b3a5c6aa9fff89a7a9c7ec76d8335b1a8e7.tar.gz upstream-48047b3a5c6aa9fff89a7a9c7ec76d8335b1a8e7.tar.bz2 upstream-48047b3a5c6aa9fff89a7a9c7ec76d8335b1a8e7.zip |
ramips/mt7620: Name DTS files based on scheme
As introduced with ath79, DTS files for ramips will now be labelled
soc_vendor_device.dts(i). With this change, DTS files can be
selected automatically without further manual links.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Diffstat (limited to 'target/linux/ramips/dts/mt7620a_hiwifi_hc5761.dts')
-rw-r--r-- | target/linux/ramips/dts/mt7620a_hiwifi_hc5761.dts | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/target/linux/ramips/dts/mt7620a_hiwifi_hc5761.dts b/target/linux/ramips/dts/mt7620a_hiwifi_hc5761.dts new file mode 100644 index 0000000000..265f7d9bb1 --- /dev/null +++ b/target/linux/ramips/dts/mt7620a_hiwifi_hc5761.dts @@ -0,0 +1,59 @@ +/dts-v1/; + +#include "mt7620a_hiwifi_hc5x61.dtsi" + +/ { + compatible = "hiwifi,hc5761", "hiwifi,hc5x61", "ralink,mt7620a-soc"; + model = "HiWiFi HC5761"; + + aliases { + led-boot = &led_system; + led-failsafe = &led_system; + led-running = &led_system; + led-upgrade = &led_system; + }; + + leds { + compatible = "gpio-leds"; + + led_system: system { + label = "hc5761:blue:system"; + gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + }; + + internet { + label = "hc5761:blue:internet"; + gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; + }; + + wlan2g { + label = "hc5761:blue:wlan2g"; + gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + }; + + wlan5g { + label = "hc5761:blue:wlan5g"; + gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&pcie0 { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x8000>; + ieee80211-freq-limit = <5000000 6000000>; + }; +}; |