ipq806x: fix wireless regression

In current state there's huge regression on ipq806x target that causes the device to transmit broken/malformed frames that are not corrected/detected by error control mechanisms and other less severe issues.
https://bugs.lede-project.org/index.php?do=details&task_id=1197

This finally had been narrowed down to patch 0071-pcie-qcom-fixes.patch

Meanwhile QSDK contains a handful of commits that add support for ipq806x to upstream qcom pcie driver
https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-msm/log/drivers/pci/host/pcie-qcom.c?h=eggplant
Unfortunately qca developers do not bother to push it upstream.

Using those commits instead of lede 0071 patch fixes mentioned issue and probably many others as it seems that corrupted data has been originating within pcie misconfiguration.

Fixes: FS#1197 and probably others
Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>

1 files changed, 85 insertions, 0 deletions

diff --git a/target/linux/ipq806x/patches-4.9/0071-2-PCI-qcom-Fixed-IPQ806x-PCIE-reset-changes.patch b/target/linux/ipq806x/patches-4.9/0071-2-PCI-qcom-Fixed-IPQ806x-PCIE-reset-changes.patch
new file mode 100644
index 0000000000..aab4f364e6
--- /dev/null
+++ b/target/linux/ipq806x/patches-4.9/0071-2-PCI-qcom-Fixed-IPQ806x-PCIE-reset-changes.patch
@@ -0,0 +1,85 @@
+From 490d103232287eb51c92c49a4ef8865fd0a9d59e Mon Sep 17 00:00:00 2001
+From: Sham Muthayyan <smuthayy@codeaurora.org>
+Date: Tue, 19 Jul 2016 18:58:18 +0530
+Subject: PCI: qcom: Fixed IPQ806x PCIE reset changes
+
+Change-Id: Ia6590e960b9754b1e8b7a51f318788cd63e9e321
+Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
+---
+ drivers/pci/host/pcie-qcom.c | 24 +++++++++++++++++++-----
+ 1 file changed, 19 insertions(+), 5 deletions(-)
+
+--- a/drivers/pci/host/pcie-qcom.c
++++ b/drivers/pci/host/pcie-qcom.c
+@@ -60,6 +60,7 @@ struct qcom_pcie_resources_v0 {
+ 	struct reset_control *ahb_reset;
+ 	struct reset_control *por_reset;
+ 	struct reset_control *phy_reset;
++	struct reset_control *ext_reset;
+ 	struct regulator *vdda;
+ 	struct regulator *vdda_phy;
+ 	struct regulator *vdda_refclk;
+@@ -190,6 +191,10 @@ static int qcom_pcie_get_resources_v0(st
+ 	if (IS_ERR(res->phy_reset))
+ 		return PTR_ERR(res->phy_reset);
+ 
++	res->ext_reset = devm_reset_control_get(dev, "ext");
++	if (IS_ERR(res->ext_reset))
++		return PTR_ERR(res->ext_reset);
++
+ 	return 0;
+ }
+ 
+@@ -234,6 +239,7 @@ static void qcom_pcie_deinit_v0(struct q
+ 	reset_control_assert(res->ahb_reset);
+ 	reset_control_assert(res->por_reset);
+ 	reset_control_assert(res->pci_reset);
++	reset_control_assert(res->ext_reset);
+ 	clk_disable_unprepare(res->iface_clk);
+ 	clk_disable_unprepare(res->core_clk);
+ 	clk_disable_unprepare(res->phy_clk);
+@@ -251,6 +257,12 @@ static int qcom_pcie_init_v0(struct qcom
+ 	u32 val;
+ 	int ret;
+ 
++	ret = reset_control_assert(res->ahb_reset);
++	if (ret) {
++		dev_err(dev, "cannot assert ahb reset\n");
++		return ret;
++	}
++
+ 	ret = regulator_enable(res->vdda);
+ 	if (ret) {
+ 		dev_err(dev, "cannot enable vdda regulator\n");
+@@ -269,16 +281,16 @@ static int qcom_pcie_init_v0(struct qcom
+ 		goto err_vdda_phy;
+ 	}
+ 
+-	ret = reset_control_assert(res->ahb_reset);
++	ret = reset_control_deassert(res->ext_reset);
+ 	if (ret) {
+-		dev_err(dev, "cannot assert ahb reset\n");
+-		goto err_assert_ahb;
++		dev_err(dev, "cannot assert ext reset\n");
++		goto err_reset_ext;
+ 	}
+ 
+ 	ret = clk_prepare_enable(res->iface_clk);
+ 	if (ret) {
+ 		dev_err(dev, "cannot prepare/enable iface clock\n");
+-		goto err_assert_ahb;
++		goto err_iface;
+ 	}
+ 
+ 	ret = clk_prepare_enable(res->core_clk);
+@@ -360,7 +372,9 @@ err_clk_phy:
+ 	clk_disable_unprepare(res->core_clk);
+ err_clk_core:
+ 	clk_disable_unprepare(res->iface_clk);
+-err_assert_ahb:
++err_iface:
++	reset_control_assert(res->ext_reset);
++err_reset_ext:
+ 	regulator_disable(res->vdda_phy);
+ err_vdda_phy:
+ 	regulator_disable(res->vdda_refclk);