imx6: add flexcan support

backport upstream changes to 3.10:
 - 0060-flexcan.patch:
   - add flexcan pinctrl and devicetree config
 - 0061-can-flexcan-use-correct-clock-as-base-for-bit-rate-c.patch
   - fix a clock issue
 - 0062-ARM-i.MX6q-fix-the-wrong-parent-of-can_root-clock.patch
   - fix a clock issue

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

SVN-Revision: 39033

1 files changed, 25 insertions, 0 deletions

diff --git a/target/linux/imx6/patches-3.10/0062-ARM-i.MX6q-fix-the-wrong-parent-of-can_root-clock.patch b/target/linux/imx6/patches-3.10/0062-ARM-i.MX6q-fix-the-wrong-parent-of-can_root-clock.patch
new file mode 100644
index 0000000000..8ea02f6dc6
--- /dev/null
+++ b/target/linux/imx6/patches-3.10/0062-ARM-i.MX6q-fix-the-wrong-parent-of-can_root-clock.patch
@@ -0,0 +1,25 @@
+From 9b3d423707c3b1f6633be1be7e959623e10c596b Mon Sep 17 00:00:00 2001
+From: Jiada Wang <jiada_wang@mentor.com>
+Date: Wed, 30 Oct 2013 04:25:51 -0700
+Subject: [PATCH] ARM: i.MX6q: fix the wrong parent of can_root clock
+
+instead of pll3_usb_otg the parent of can_root clock
+should be pll3_60m.
+
+Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
+Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
+---
+ arch/arm/mach-imx/clk-imx6q.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/mach-imx/clk-imx6q.c
++++ b/arch/arm/mach-imx/clk-imx6q.c
+@@ -442,7 +442,7 @@ int __init mx6q_clocks_init(void)
+ 	clk[asrc_podf]        = imx_clk_divider("asrc_podf",        "asrc_pred",         base + 0x30, 9,  3);
+ 	clk[spdif_pred]       = imx_clk_divider("spdif_pred",       "spdif_sel",         base + 0x30, 25, 3);
+ 	clk[spdif_podf]       = imx_clk_divider("spdif_podf",       "spdif_pred",        base + 0x30, 22, 3);
+-	clk[can_root]         = imx_clk_divider("can_root",         "pll3_usb_otg",      base + 0x20, 2,  6);
++	clk[can_root]         = imx_clk_divider("can_root",         "pll3_60m",          base + 0x20, 2,  6);
+ 	clk[ecspi_root]       = imx_clk_divider("ecspi_root",       "pll3_60m",          base + 0x38, 19, 6);
+ 	clk[gpu2d_core_podf]  = imx_clk_divider("gpu2d_core_podf",  "gpu2d_core_sel",    base + 0x18, 23, 3);
+ 	clk[gpu3d_core_podf]  = imx_clk_divider("gpu3d_core_podf",  "gpu3d_core_sel",    base + 0x18, 26, 3);