diff options
author | Christian Lamparter <chunkeey@gmail.com> | 2020-09-12 22:28:38 +0200 |
---|---|---|
committer | Christian Lamparter <chunkeey@gmail.com> | 2021-10-30 15:00:22 +0200 |
commit | 6102f883ce7f32988d22b7fc5b79356e3d06c1dc (patch) | |
tree | 74d0327a355a6374a594ce0333001b3d22757fea /target/linux/bcm53xx/patches-5.10 | |
parent | f5d071a508b3e3d218b8ed6f6f5a999384bb7f6d (diff) | |
download | upstream-6102f883ce7f32988d22b7fc5b79356e3d06c1dc.tar.gz upstream-6102f883ce7f32988d22b7fc5b79356e3d06c1dc.tar.bz2 upstream-6102f883ce7f32988d22b7fc5b79356e3d06c1dc.zip |
bcm53xx: MR32: replace i2c-gpio with SoC's i2c
During review of the MR32, Florian Fainelli pointed out that the
SoC has a real I2C-controller. Furthermore, the connected pins
(SDA and SCL) would line up perfectly for use. This patch swaps
out the the bitbanged i2c-gpio with the real deal.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Diffstat (limited to 'target/linux/bcm53xx/patches-5.10')
-rw-r--r-- | target/linux/bcm53xx/patches-5.10/040-v5.16-ARM-dts-BCM5301X-Fix-I2C-controller-interrupt.patch | 32 | ||||
-rw-r--r-- | target/linux/bcm53xx/patches-5.10/332-Meraki-MR32-use-hw-i2c.patch | 85 |
2 files changed, 117 insertions, 0 deletions
diff --git a/target/linux/bcm53xx/patches-5.10/040-v5.16-ARM-dts-BCM5301X-Fix-I2C-controller-interrupt.patch b/target/linux/bcm53xx/patches-5.10/040-v5.16-ARM-dts-BCM5301X-Fix-I2C-controller-interrupt.patch new file mode 100644 index 0000000000..628569eca9 --- /dev/null +++ b/target/linux/bcm53xx/patches-5.10/040-v5.16-ARM-dts-BCM5301X-Fix-I2C-controller-interrupt.patch @@ -0,0 +1,32 @@ +From beda1bbdb19baa8319ed81fa370fe0c5b91d05df Mon Sep 17 00:00:00 2001 +From: Florian Fainelli <f.fainelli@gmail.com> +Date: Tue, 26 Oct 2021 11:36:22 -0700 +Subject: [PATCH] ARM: dts: BCM5301X: Fix I2C controller interrupt + +The I2C interrupt controller line is off by 32 because the datasheet +describes interrupt inputs into the GIC which are for Shared Peripheral +Interrupts and are starting at offset 32. The ARM GIC binding expects +the SPI interrupts to be numbered from 0 relative to the SPI base. + +Fixes: bb097e3e0045 ("ARM: dts: BCM5301X: Add I2C support to the DT") +Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> +--- + arch/arm/boot/dts/bcm5301x.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi +index f92089290ccd..ec5de636796e 100644 +--- a/arch/arm/boot/dts/bcm5301x.dtsi ++++ b/arch/arm/boot/dts/bcm5301x.dtsi +@@ -408,7 +408,7 @@ uart2: serial@18008000 { + i2c0: i2c@18009000 { + compatible = "brcm,iproc-i2c"; + reg = <0x18009000 0x50>; +- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; ++ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; +-- +2.25.1 + diff --git a/target/linux/bcm53xx/patches-5.10/332-Meraki-MR32-use-hw-i2c.patch b/target/linux/bcm53xx/patches-5.10/332-Meraki-MR32-use-hw-i2c.patch new file mode 100644 index 0000000000..acd69edaab --- /dev/null +++ b/target/linux/bcm53xx/patches-5.10/332-Meraki-MR32-use-hw-i2c.patch @@ -0,0 +1,85 @@ +From: Christian Lamparter <chunkeey@gmail.com> +Date: Sat, 12 Sep 2020 22:11:12 +0200 +Subject: bcm53xx: Meraki MR32 use hw i2c + +replace the i2c-gpio provided i2c functionality with the +hardware in the SoC. This can be activated once the +internal i2c works as well as the bit-banged i2c-gpio. + +Signed-off-by: Christian Lamparter <chunkeey@gmail.com> + +--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts ++++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +@@ -85,40 +85,6 @@ + max-brightness = <255>; + }; + }; +- +- i2c { +- /* +- * The platform provided I2C does not budge. +- * This is a replacement until I can figure +- * out what are the missing bits... +- */ +- +- compatible = "i2c-gpio"; +- sda-gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; +- i2c-gpio,delay-us = <10>; /* close to 100 kHz */ +- #address-cells = <1>; +- #size-cells = <0>; +- +- current_sense: ina219@45 { +- compatible = "ti,ina219"; +- reg = <0x45>; +- shunt-resistor = <60000>; /* = 60 mOhms */ +- }; +- +- eeprom: eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- pagesize = <32>; +- read-only; +- #address-cells = <1>; +- #size-cells = <1>; +- +- mac_address: mac-address@66 { +- reg = <0x66 0x6>; +- }; +- }; +- }; + }; + + &uart0 { +@@ -196,3 +168,31 @@ + }; + }; + }; ++ ++&i2c0 { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinmux_i2c>; ++ ++ clock-frequency = <100000>; ++ ++ current_sense: ina219@45 { ++ compatible = "ti,ina219"; ++ reg = <0x45>; ++ shunt-resistor = <60000>; /* = 60 mOhms */ ++ }; ++ ++ eeprom: eeprom@50 { ++ compatible = "atmel,24c64"; ++ reg = <0x50>; ++ pagesize = <32>; ++ read-only; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ mac_address: mac-address@66 { ++ reg = <0x66 0x6>; ++ }; ++ }; ++}; |