brcm2708: rename target to bcm27xx

This change makes the names of Broadcom targets consistent by using
the common notation based on SoC/CPU ID (which is used internally
anyway), bcmXXXX instead of brcmXXXX.
This is even used for target TITLE in make menuconfig already,
only the short target name used brcm so far.

Despite, since subtargets range from bcm2708 to bcm2711, it seems
appropriate to use bcm27xx instead of bcm2708 (again, as already done
for BOARDNAME).

This also renames the packages brcm2708-userland and brcm2708-gpu-fw.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Acked-by: Álvaro Fernández Rojas <noltari@gmail.com>

1 files changed, 43 insertions, 0 deletions

diff --git a/target/linux/bcm27xx/patches-4.19/950-0495-drm-v3d-Don-t-bother-flushing-L1TD-at-job-start.patch b/target/linux/bcm27xx/patches-4.19/950-0495-drm-v3d-Don-t-bother-flushing-L1TD-at-job-start.patch
new file mode 100644
index 0000000000..164e29f673
--- /dev/null
+++ b/target/linux/bcm27xx/patches-4.19/950-0495-drm-v3d-Don-t-bother-flushing-L1TD-at-job-start.patch
@@ -0,0 +1,43 @@
+From 4a6410a53059d6505680b70fc438b7cfbf8939ca Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Mon, 3 Dec 2018 14:24:35 -0800
+Subject: [PATCH] drm/v3d: Don't bother flushing L1TD at job start.
+
+This is the write combiner for TMU writes.  You're supposed to flush
+that at job end if you had dirtied any cachelines.  Flushing it at job
+start then doesn't make any sense.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Fixes: 57692c94dcbe ("drm/v3d: Introduce a new DRM driver for Broadcom V3D V3.x+")
+Reviewed-by: Dave Emett <david.emett@broadcom.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20181203222438.25417-3-eric@anholt.net
+(cherry picked from commit 2e6dc3bd80478212e84addf1cafd6ec60674b884)
+---
+ drivers/gpu/drm/v3d/v3d_gem.c | 12 ------------
+ 1 file changed, 12 deletions(-)
+
+--- a/drivers/gpu/drm/v3d/v3d_gem.c
++++ b/drivers/gpu/drm/v3d/v3d_gem.c
+@@ -139,22 +139,10 @@ v3d_invalidate_l2(struct v3d_dev *v3d, i
+ 		       V3D_L2CACTL_L2CENA);
+ }
+ 
+-static void
+-v3d_invalidate_l1td(struct v3d_dev *v3d, int core)
+-{
+-	V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF);
+-	if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
+-		       V3D_L2TCACTL_L2TFLS), 100)) {
+-		DRM_ERROR("Timeout waiting for L1T write combiner flush\n");
+-	}
+-}
+-
+ /* Invalidates texture L2 cachelines */
+ static void
+ v3d_flush_l2t(struct v3d_dev *v3d, int core)
+ {
+-	v3d_invalidate_l1td(v3d, core);
+-
+ 	V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL,
+ 		       V3D_L2TCACTL_L2TFLS |
+ 		       V3D_SET_FIELD(V3D_L2TCACTL_FLM_FLUSH, V3D_L2TCACTL_FLM));