ar71xx: drop kernel 4.4 support

Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>

1 files changed, 0 insertions, 696 deletions

diff --git a/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
deleted file mode 100644
index fcaff77619..0000000000
--- a/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
+++ /dev/null
@@ -1,696 +0,0 @@
-From 5300a7cd7ed2f88488ddba62947b9c6bb9663777 Mon Sep 17 00:00:00 2001
-Message-Id: <5300a7cd7ed2f88488ddba62947b9c6bb9663777.1396122227.git.mschiffer@universe-factory.net>
-From: Matthias Schiffer <mschiffer@universe-factory.net>
-Date: Sat, 29 Mar 2014 20:26:08 +0100
-Subject: [PATCH 1/2] MIPS: ath79: add support for QCA953x SoC
-
-Note that the clock calculation looks very similar to the QCA955x, but the
-meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
----
- arch/mips/ath79/Kconfig                        |  6 +-
- arch/mips/ath79/clock.c                        | 78 ++++++++++++++++++++++++++
- arch/mips/ath79/common.c                       |  4 ++
- arch/mips/ath79/dev-common.c                   |  1 +
- arch/mips/ath79/dev-wmac.c                     | 20 +++++++
- arch/mips/ath79/early_printk.c                 |  1 +
- arch/mips/ath79/gpio.c                         |  4 +-
- arch/mips/ath79/irq.c                          |  4 ++
- arch/mips/ath79/setup.c                        |  8 ++-
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 48 ++++++++++++++++
- arch/mips/include/asm/mach-ath79/ath79.h       | 11 ++++
- 11 files changed, 182 insertions(+), 3 deletions(-)
-
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -116,6 +116,10 @@ config SOC_AR934X
- 	select PCI_AR724X if PCI
- 	def_bool n
- 
-+config SOC_QCA953X
-+	select USB_ARCH_HAS_EHCI
-+	def_bool n
-+
- config SOC_QCA955X
- 	select HW_HAS_PCI
- 	select PCI_AR724X if PCI
-@@ -155,7 +159,7 @@ config ATH79_DEV_USB
- 	def_bool n
- 
- config ATH79_DEV_WMAC
--	depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
-+	depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
- 	def_bool n
- 
- config ATH79_NVRAM
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -354,6 +354,87 @@ static void __init ar934x_clocks_init(vo
- 	iounmap(dpll_base);
- }
- 
-+static void __init qca953x_clocks_init(void)
-+{
-+	unsigned long ref_rate;
-+	unsigned long cpu_rate;
-+	unsigned long ddr_rate;
-+	unsigned long ahb_rate;
-+	u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
-+	u32 cpu_pll, ddr_pll;
-+
-+	/* QCA953X only supports 25MHz ref_clk */
-+	ref_rate = 25 * 1000 * 1000;
-+
-+	pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
-+	out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
-+		  QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
-+	ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
-+		  QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
-+	nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
-+	       QCA953X_PLL_CPU_CONFIG_NINT_MASK;
-+	frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
-+	       QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
-+
-+	cpu_pll = nint * ref_rate / ref_div;
-+	cpu_pll += frac * (ref_rate >> 6) / ref_div;
-+	cpu_pll /= (1 << out_div);
-+
-+	pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
-+	out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
-+		  QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
-+	ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
-+		  QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
-+	nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
-+	       QCA953X_PLL_DDR_CONFIG_NINT_MASK;
-+	frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
-+	       QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
-+
-+	ddr_pll = nint * ref_rate / ref_div;
-+	ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
-+	ddr_pll /= (1 << out_div);
-+
-+	clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
-+
-+	postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
-+		  QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
-+
-+	if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
-+		cpu_rate = ref_rate;
-+	else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
-+		cpu_rate = cpu_pll / (postdiv + 1);
-+	else
-+		cpu_rate = ddr_pll / (postdiv + 1);
-+
-+	postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
-+		  QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
-+
-+	if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
-+		ddr_rate = ref_rate;
-+	else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
-+		ddr_rate = ddr_pll / (postdiv + 1);
-+	else
-+		ddr_rate = cpu_pll / (postdiv + 1);
-+
-+	postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
-+		  QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
-+
-+	if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
-+		ahb_rate = ref_rate;
-+	else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
-+		ahb_rate = ddr_pll / (postdiv + 1);
-+	else
-+		ahb_rate = cpu_pll / (postdiv + 1);
-+
-+	ath79_add_sys_clkdev("ref", ref_rate);
-+	ath79_add_sys_clkdev("cpu", cpu_rate);
-+	ath79_add_sys_clkdev("ddr", ddr_rate);
-+	ath79_add_sys_clkdev("ahb", ahb_rate);
-+
-+	clk_add_alias("wdt", NULL, "ref", NULL);
-+	clk_add_alias("uart", NULL, "ref", NULL);
-+}
-+
- static void __init qca955x_clocks_init(void)
- {
- 	unsigned long ref_rate;
-@@ -451,6 +532,8 @@ void __init ath79_clocks_init(void)
- 		ar933x_clocks_init();
- 	else if (soc_is_ar934x())
- 		ar934x_clocks_init();
-+	else if (soc_is_qca953x())
-+		qca953x_clocks_init();
- 	else if (soc_is_qca955x())
- 		qca955x_clocks_init();
- 	else
---- a/arch/mips/ath79/common.c
-+++ b/arch/mips/ath79/common.c
-@@ -103,6 +103,8 @@ void ath79_device_reset_set(u32 mask)
- 		reg = AR933X_RESET_REG_RESET_MODULE;
- 	else if (soc_is_ar934x())
- 		reg = AR934X_RESET_REG_RESET_MODULE;
-+	else if (soc_is_qca953x())
-+		reg = QCA953X_RESET_REG_RESET_MODULE;
- 	else if (soc_is_qca955x())
- 		reg = QCA955X_RESET_REG_RESET_MODULE;
- 	else
-@@ -131,6 +133,8 @@ void ath79_device_reset_clear(u32 mask)
- 		reg = AR933X_RESET_REG_RESET_MODULE;
- 	else if (soc_is_ar934x())
- 		reg = AR934X_RESET_REG_RESET_MODULE;
-+	else if (soc_is_qca953x())
-+		reg = QCA953X_RESET_REG_RESET_MODULE;
- 	else if (soc_is_qca955x())
- 		reg = QCA955X_RESET_REG_RESET_MODULE;
- 	else
---- a/arch/mips/ath79/dev-common.c
-+++ b/arch/mips/ath79/dev-common.c
-@@ -94,6 +94,7 @@ void __init ath79_register_uart(void)
- 	    soc_is_ar724x() ||
- 	    soc_is_ar913x() ||
- 	    soc_is_ar934x() ||
-+	    soc_is_qca953x() ||
- 	    soc_is_qca955x()) {
- 		ath79_uart_data[0].uartclk = uart_clk_rate;
- 		platform_device_register(&ath79_uart_device);
-@@ -157,6 +158,9 @@ void __init ath79_gpio_init(void)
- 	} else if (soc_is_ar934x()) {
- 		ath79_gpio_pdata.ngpios = AR934X_GPIO_COUNT;
- 		ath79_gpio_pdata.oe_inverted = 1;
-+	} else if (soc_is_qca953x()) {
-+		ath79_gpio_pdata.ngpios = QCA953X_GPIO_COUNT;
-+		ath79_gpio_pdata.oe_inverted = 1;
- 	} else if (soc_is_qca955x()) {
- 		ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT;
- 		ath79_gpio_pdata.oe_inverted = 1;
---- a/arch/mips/ath79/dev-usb.c
-+++ b/arch/mips/ath79/dev-usb.c
-@@ -236,6 +236,30 @@ static void __init ar934x_usb_setup(void
- 			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
- }
- 
-+static void __init qca953x_usb_setup(void)
-+{
-+	u32 bootstrap;
-+
-+	bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
-+
-+	ath79_device_reset_set(QCA953X_RESET_USBSUS_OVERRIDE);
-+	udelay(1000);
-+
-+	ath79_device_reset_clear(QCA953X_RESET_USB_PHY);
-+	udelay(1000);
-+
-+	ath79_device_reset_clear(QCA953X_RESET_USB_PHY_ANALOG);
-+	udelay(1000);
-+
-+	ath79_device_reset_clear(QCA953X_RESET_USB_HOST);
-+	udelay(1000);
-+
-+	ath79_usb_register("ehci-platform", -1,
-+			   QCA953X_EHCI_BASE, QCA953X_EHCI_SIZE,
-+			   ATH79_CPU_IRQ(3),
-+			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
-+}
-+
- static void qca955x_usb_reset_notifier(struct platform_device *pdev)
- {
- 	u32 base;
-@@ -286,6 +310,8 @@ void __init ath79_register_usb(void)
- 		ar933x_usb_setup();
- 	else if (soc_is_ar934x())
- 		ar934x_usb_setup();
-+	else if (soc_is_qca953x())
-+		qca953x_usb_setup();
- 	else if (soc_is_qca955x())
- 		qca955x_usb_setup();
- 	else
---- a/arch/mips/ath79/dev-wmac.c
-+++ b/arch/mips/ath79/dev-wmac.c
-@@ -100,7 +100,7 @@ static int ar933x_wmac_reset(void)
- 	return -ETIMEDOUT;
- }
- 
--static int ar933x_r1_get_wmac_revision(void)
-+static int ar93xx_get_soc_revision(void)
- {
- 	return ath79_soc_rev;
- }
-@@ -125,7 +125,7 @@ static void __init ar933x_wmac_setup(voi
- 		ath79_wmac_data.is_clk_25mhz = true;
- 
- 	if (ath79_soc_rev == 1)
--		ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
-+		ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
- 
- 	ath79_wmac_data.external_reset = ar933x_wmac_reset;
- }
-@@ -150,6 +150,21 @@ static void ar934x_wmac_setup(void)
- 	ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
- }
- 
-+static void qca953x_wmac_setup(void)
-+{
-+	ath79_wmac_device.name = "qca953x_wmac";
-+
-+	ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
-+	ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1;
-+	ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
-+	ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
-+
-+	/* QCA953X only supports 25MHz ref_clk */
-+	ath79_wmac_data.is_clk_25mhz = true;
-+
-+	ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
-+}
-+
- static void qca955x_wmac_setup(void)
- {
- 	u32 t;
-@@ -379,6 +394,8 @@ void __init ath79_register_wmac(u8 *cal_
- 		ar933x_wmac_setup();
- 	else if (soc_is_ar934x())
- 		ar934x_wmac_setup();
-+	else if (soc_is_qca953x())
-+		qca953x_wmac_setup();
- 	else if (soc_is_qca955x())
- 		qca955x_wmac_setup();
- 	else
---- a/arch/mips/ath79/early_printk.c
-+++ b/arch/mips/ath79/early_printk.c
-@@ -116,6 +116,8 @@ static void prom_putchar_init(void)
- 	case REV_ID_MAJOR_AR9341:
- 	case REV_ID_MAJOR_AR9342:
- 	case REV_ID_MAJOR_AR9344:
-+	case REV_ID_MAJOR_QCA9533:
-+	case REV_ID_MAJOR_QCA9533_V2:
- 	case REV_ID_MAJOR_QCA9556:
- 	case REV_ID_MAJOR_QCA9558:
- 		_prom_putchar = prom_putchar_ar71xx;
---- a/arch/mips/ath79/gpio.c
-+++ b/arch/mips/ath79/gpio.c
-@@ -31,7 +31,7 @@ static void __iomem *ath79_gpio_get_func
- 	    soc_is_ar913x() ||
- 	    soc_is_ar933x())
- 		reg = AR71XX_GPIO_REG_FUNC;
--	else if (soc_is_ar934x())
-+	else if (soc_is_ar934x() || soc_is_qca953x())
- 		reg = AR934X_GPIO_REG_FUNC;
- 	else
- 		BUG();
-@@ -64,7 +64,7 @@ void __init ath79_gpio_output_select(uns
- 	unsigned int reg;
- 	u32 t, s;
- 
--	BUG_ON(!soc_is_ar934x());
-+	BUG_ON(!soc_is_ar934x() && !soc_is_qca953x());
- 
- 	if (gpio >= AR934X_GPIO_COUNT)
- 		return;
---- a/arch/mips/ath79/irq.c
-+++ b/arch/mips/ath79/irq.c
-@@ -105,6 +105,7 @@ static void __init ath79_misc_irq_init(v
- 	else if (soc_is_ar724x() ||
- 		 soc_is_ar933x() ||
- 		 soc_is_ar934x() ||
-+		 soc_is_qca953x() ||
- 		 soc_is_qca955x())
- 		ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
- 	else
-@@ -148,6 +149,34 @@ static void ar934x_ip2_irq_init(void)
- 	irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
- }
- 
-+static void qca953x_ip2_irq_dispatch(struct irq_desc *desc)
-+{
-+	u32 status;
-+
-+	status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
-+
-+	if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
-+		ath79_ddr_wb_flush(3);
-+		generic_handle_irq(ATH79_IP2_IRQ(0));
-+	} else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
-+		ath79_ddr_wb_flush(4);
-+		generic_handle_irq(ATH79_IP2_IRQ(1));
-+	} else {
-+		spurious_interrupt();
-+	}
-+}
-+
-+static void qca953x_irq_init(void)
-+{
-+	int i;
-+
-+	for (i = ATH79_IP2_IRQ_BASE;
-+	     i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
-+		irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
-+
-+	irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
-+}
-+
- static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
- {
- 	u32 status;
-@@ -362,7 +391,7 @@ void __init arch_init_irq(void)
- 	    soc_is_ar913x() || soc_is_ar933x()) {
- 		irq_wb_chan[2] = 3;
- 		irq_wb_chan[3] = 2;
--	} else if (soc_is_ar934x()) {
-+	} else if (soc_is_ar934x() || soc_is_qca953x()) {
- 		irq_wb_chan[3] = 2;
- 	}
- 
-@@ -371,6 +400,8 @@ void __init arch_init_irq(void)
- 
- 	if (soc_is_ar934x())
- 		ar934x_ip2_irq_init();
-+	else if (soc_is_qca953x())
-+		qca953x_irq_init();
- 	else if (soc_is_qca955x())
- 		qca955x_irq_init();
- }
---- a/arch/mips/ath79/setup.c
-+++ b/arch/mips/ath79/setup.c
-@@ -64,6 +64,7 @@ static void __init ath79_detect_sys_type
- 	u32 major;
- 	u32 minor;
- 	u32 rev = 0;
-+	u32 ver = 1;
- 
- 	id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
- 	major = id & REV_ID_MAJOR_MASK;
-@@ -156,6 +157,17 @@ static void __init ath79_detect_sys_type
- 		rev = id & AR934X_REV_ID_REVISION_MASK;
- 		break;
- 
-+	case REV_ID_MAJOR_QCA9533_V2:
-+		ver = 2;
-+		ath79_soc_rev = 2;
-+		/* drop through */
-+
-+	case REV_ID_MAJOR_QCA9533:
-+		ath79_soc = ATH79_SOC_QCA9533;
-+		chip = "9533";
-+		rev = id & QCA953X_REV_ID_REVISION_MASK;
-+		break;
-+
- 	case REV_ID_MAJOR_QCA9556:
- 		ath79_soc = ATH79_SOC_QCA9556;
- 		chip = "9556";
-@@ -172,11 +184,12 @@ static void __init ath79_detect_sys_type
- 		panic("ath79: unknown SoC, id:0x%08x", id);
- 	}
- 
--	ath79_soc_rev = rev;
-+	if (ver == 1)
-+		ath79_soc_rev = rev;
- 
--	if (soc_is_qca955x())
--		sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
--			chip, rev);
-+	if (soc_is_qca953x() || soc_is_qca955x())
-+		sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
-+			chip, ver, rev);
- 	else
- 		sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
- 	pr_info("SoC: %s\n", ath79_sys_type);
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -105,6 +105,21 @@
- #define AR934X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
- #define AR934X_SRIF_SIZE	0x1000
- 
-+#define QCA953X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
-+#define QCA953X_GMAC_SIZE	0x14
-+#define QCA953X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
-+#define QCA953X_WMAC_SIZE	0x20000
-+#define QCA953X_EHCI_BASE	0x1b000000
-+#define QCA953X_EHCI_SIZE	0x200
-+#define QCA953X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
-+#define QCA953X_SRIF_SIZE	0x1000
-+
-+#define QCA953X_PCI_CFG_BASE0	0x14000000
-+#define QCA953X_PCI_CTRL_BASE0	(AR71XX_APB_BASE + 0x000f0000)
-+#define QCA953X_PCI_CRP_BASE0	(AR71XX_APB_BASE + 0x000c0000)
-+#define QCA953X_PCI_MEM_BASE0	0x10000000
-+#define QCA953X_PCI_MEM_SIZE	0x02000000
-+
- #define QCA955X_PCI_MEM_BASE0	0x10000000
- #define QCA955X_PCI_MEM_BASE1	0x12000000
- #define QCA955X_PCI_MEM_SIZE	0x02000000
-@@ -180,6 +195,12 @@
- #define AR934X_OTP_INTF3_ADDRESS			0x3100c
- #define AR934X_OTP_PGENB_SETUP_HOLD_TIME_ADDRESS	0x31034
- 
-+#define QCA953X_DDR_REG_FLUSH_GE0	0x9c
-+#define QCA953X_DDR_REG_FLUSH_GE1	0xa0
-+#define QCA953X_DDR_REG_FLUSH_USB	0xa4
-+#define QCA953X_DDR_REG_FLUSH_PCIE	0xa8
-+#define QCA953X_DDR_REG_FLUSH_WMAC	0xac
-+
- /*
-  * PLL block
-  */
-@@ -289,6 +310,44 @@
- 
- #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL	BIT(6)
- 
-+#define QCA953X_PLL_CPU_CONFIG_REG		0x00
-+#define QCA953X_PLL_DDR_CONFIG_REG		0x04
-+#define QCA953X_PLL_CLK_CTRL_REG		0x08
-+#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG	0x24
-+#define QCA953X_PLL_ETH_XMII_CONTROL_REG	0x2c
-+#define QCA953X_PLL_ETH_SGMII_CONTROL_REG	0x48
-+
-+#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
-+#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
-+#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT	6
-+#define QCA953X_PLL_CPU_CONFIG_NINT_MASK	0x3f
-+#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT	12
-+#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
-+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT	19
-+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK	0x7
-+
-+#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT	0
-+#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK	0x3ff
-+#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT	10
-+#define QCA953X_PLL_DDR_CONFIG_NINT_MASK	0x3f
-+#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT	16
-+#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK	0x1f
-+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT	23
-+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK	0x7
-+
-+#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
-+#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
-+#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS		BIT(4)
-+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
-+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x1f
-+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
-+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x1f
-+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
-+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x1f
-+#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL		BIT(20)
-+#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL		BIT(21)
-+#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)
-+
- #define QCA955X_PLL_CPU_CONFIG_REG		0x00
- #define QCA955X_PLL_DDR_CONFIG_REG		0x04
- #define QCA955X_PLL_CLK_CTRL_REG		0x08
-@@ -365,6 +424,10 @@
- #define AR934X_RESET_REG_BOOTSTRAP		0xb0
- #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS	0xac
- 
-+#define QCA953X_RESET_REG_RESET_MODULE		0x1c
-+#define QCA953X_RESET_REG_BOOTSTRAP		0xb0
-+#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS	0xac
-+
- #define QCA955X_RESET_REG_RESET_MODULE		0x1c
- #define QCA955X_RESET_REG_BOOTSTRAP		0xb0
- #define QCA955X_RESET_REG_EXT_INT_STATUS	0xac
-@@ -460,6 +523,27 @@
- #define AR934X_RESET_MBOX		BIT(1)
- #define AR934X_RESET_I2S		BIT(0)
- 
-+#define QCA953X_RESET_USB_EXT_PWR	BIT(29)
-+#define QCA953X_RESET_EXTERNAL		BIT(28)
-+#define QCA953X_RESET_RTC		BIT(27)
-+#define QCA953X_RESET_FULL_CHIP		BIT(24)
-+#define QCA953X_RESET_GE1_MDIO		BIT(23)
-+#define QCA953X_RESET_GE0_MDIO		BIT(22)
-+#define QCA953X_RESET_CPU_NMI		BIT(21)
-+#define QCA953X_RESET_CPU_COLD		BIT(20)
-+#define QCA953X_RESET_DDR		BIT(16)
-+#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
-+#define QCA953X_RESET_GE1_MAC		BIT(13)
-+#define QCA953X_RESET_ETH_SWITCH_ANALOG	BIT(12)
-+#define QCA953X_RESET_USB_PHY_ANALOG	BIT(11)
-+#define QCA953X_RESET_GE0_MAC		BIT(9)
-+#define QCA953X_RESET_ETH_SWITCH	BIT(8)
-+#define QCA953X_RESET_PCIE_PHY		BIT(7)
-+#define QCA953X_RESET_PCIE		BIT(6)
-+#define QCA953X_RESET_USB_HOST		BIT(5)
-+#define QCA953X_RESET_USB_PHY		BIT(4)
-+#define QCA953X_RESET_USBSUS_OVERRIDE	BIT(3)
-+
- #define QCA955X_RESET_HOST		BIT(31)
- #define QCA955X_RESET_SLIC		BIT(30)
- #define QCA955X_RESET_HDMA		BIT(29)
-@@ -513,6 +597,13 @@
- #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
- #define AR934X_BOOTSTRAP_DDR1		BIT(0)
- 
-+#define QCA953X_BOOTSTRAP_SW_OPTION2	BIT(12)
-+#define QCA953X_BOOTSTRAP_SW_OPTION1	BIT(11)
-+#define QCA953X_BOOTSTRAP_EJTAG_MODE	BIT(5)
-+#define QCA953X_BOOTSTRAP_REF_CLK	BIT(4)
-+#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
-+#define QCA953X_BOOTSTRAP_DDR1		BIT(0)
-+
- #define QCA955X_BOOTSTRAP_REF_CLK_40	BIT(4)
- 
- #define AR934X_PCIE_WMAC_INT_WMAC_MISC		BIT(0)
-@@ -533,6 +624,24 @@
- 	 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
- 	 AR934X_PCIE_WMAC_INT_PCIE_RC3)
- 
-+#define QCA953X_PCIE_WMAC_INT_WMAC_MISC		BIT(0)
-+#define QCA953X_PCIE_WMAC_INT_WMAC_TX		BIT(1)
-+#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP		BIT(2)
-+#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP		BIT(3)
-+#define QCA953X_PCIE_WMAC_INT_PCIE_RC		BIT(4)
-+#define QCA953X_PCIE_WMAC_INT_PCIE_RC0		BIT(5)
-+#define QCA953X_PCIE_WMAC_INT_PCIE_RC1		BIT(6)
-+#define QCA953X_PCIE_WMAC_INT_PCIE_RC2		BIT(7)
-+#define QCA953X_PCIE_WMAC_INT_PCIE_RC3		BIT(8)
-+#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
-+	(QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
-+	 QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
-+
-+#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
-+	(QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
-+	 QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
-+	 QCA953X_PCIE_WMAC_INT_PCIE_RC3)
-+
- #define QCA955X_EXT_INT_WMAC_MISC		BIT(0)
- #define QCA955X_EXT_INT_WMAC_TX			BIT(1)
- #define QCA955X_EXT_INT_WMAC_RXLP		BIT(2)
-@@ -575,6 +684,8 @@
- #define REV_ID_MAJOR_AR9341		0x0120
- #define REV_ID_MAJOR_AR9342		0x1120
- #define REV_ID_MAJOR_AR9344		0x2120
-+#define REV_ID_MAJOR_QCA9533		0x0140
-+#define REV_ID_MAJOR_QCA9533_V2		0x0160
- #define REV_ID_MAJOR_QCA9556		0x0130
- #define REV_ID_MAJOR_QCA9558		0x1130
- 
-@@ -597,6 +708,8 @@
- 
- #define AR934X_REV_ID_REVISION_MASK	0xf
- 
-+#define QCA953X_REV_ID_REVISION_MASK	0xf
-+
- #define QCA955X_REV_ID_REVISION_MASK	0xf
- 
- /*
-@@ -644,6 +757,25 @@
- #define AR934X_GPIO_REG_OUT_FUNC5	0x40
- #define AR934X_GPIO_REG_FUNC		0x6c
- 
-+#define QCA953X_GPIO_REG_OUT_FUNC0	0x2c
-+#define QCA953X_GPIO_REG_OUT_FUNC1	0x30
-+#define QCA953X_GPIO_REG_OUT_FUNC2	0x34
-+#define QCA953X_GPIO_REG_OUT_FUNC3	0x38
-+#define QCA953X_GPIO_REG_OUT_FUNC4	0x3c
-+#define QCA953X_GPIO_REG_IN_ENABLE0	0x44
-+#define QCA953X_GPIO_REG_FUNC		0x6c
-+
-+#define QCA953X_GPIO_OUT_MUX_SPI_CS1		10
-+#define QCA953X_GPIO_OUT_MUX_SPI_CS2		11
-+#define QCA953X_GPIO_OUT_MUX_SPI_CS0		9
-+#define QCA953X_GPIO_OUT_MUX_SPI_CLK		8
-+#define QCA953X_GPIO_OUT_MUX_SPI_MOSI		12
-+#define QCA953X_GPIO_OUT_MUX_LED_LINK1		41
-+#define QCA953X_GPIO_OUT_MUX_LED_LINK2		42
-+#define QCA953X_GPIO_OUT_MUX_LED_LINK3		43
-+#define QCA953X_GPIO_OUT_MUX_LED_LINK4		44
-+#define QCA953X_GPIO_OUT_MUX_LED_LINK5		45
-+
- #define QCA955X_GPIO_REG_OUT_FUNC0	0x2c
- #define QCA955X_GPIO_REG_OUT_FUNC1	0x30
- #define QCA955X_GPIO_REG_OUT_FUNC2	0x34
-@@ -658,6 +790,7 @@
- #define AR913X_GPIO_COUNT		22
- #define AR933X_GPIO_COUNT		30
- #define AR934X_GPIO_COUNT		23
-+#define QCA953X_GPIO_COUNT		18
- #define QCA955X_GPIO_COUNT		24
- 
- /*
-@@ -681,6 +814,24 @@
- #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT	13
- #define AR934X_SRIF_DPLL2_OUTDIV_MASK	0x7
- 
-+#define QCA953X_SRIF_CPU_DPLL1_REG	0x1c0
-+#define QCA953X_SRIF_CPU_DPLL2_REG	0x1c4
-+#define QCA953X_SRIF_CPU_DPLL3_REG	0x1c8
-+
-+#define QCA953X_SRIF_DDR_DPLL1_REG	0x240
-+#define QCA953X_SRIF_DDR_DPLL2_REG	0x244
-+#define QCA953X_SRIF_DDR_DPLL3_REG	0x248
-+
-+#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT	27
-+#define QCA953X_SRIF_DPLL1_REFDIV_MASK	0x1f
-+#define QCA953X_SRIF_DPLL1_NINT_SHIFT	18
-+#define QCA953X_SRIF_DPLL1_NINT_MASK	0x1ff
-+#define QCA953X_SRIF_DPLL1_NFRAC_MASK	0x0003ffff
-+
-+#define QCA953X_SRIF_DPLL2_LOCAL_PLL	BIT(30)
-+#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT	13
-+#define QCA953X_SRIF_DPLL2_OUTDIV_MASK	0x7
-+
- #define AR71XX_GPIO_FUNC_STEREO_EN		BIT(17)
- #define AR71XX_GPIO_FUNC_SLIC_EN		BIT(16)
- #define AR71XX_GPIO_FUNC_SPI_CS2_EN		BIT(13)
-@@ -887,6 +1038,16 @@
- #define AR934X_ETH_CFG_RDV_DELAY_SHIFT  16
- 
- /*
-+ * QCA953X GMAC Interface
-+ */
-+#define QCA953X_GMAC_REG_ETH_CFG		0x00
-+
-+#define QCA953X_ETH_CFG_SW_ONLY_MODE		BIT(6)
-+#define QCA953X_ETH_CFG_SW_PHY_SWAP		BIT(7)
-+#define QCA953X_ETH_CFG_SW_APB_ACCESS		BIT(9)
-+#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST	BIT(13)
-+
-+/*
-  * QCA955X GMAC Interface
-  */
- 
---- a/arch/mips/include/asm/mach-ath79/ath79.h
-+++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -32,6 +32,7 @@ enum ath79_soc_type {
- 	ATH79_SOC_AR9341,
- 	ATH79_SOC_AR9342,
- 	ATH79_SOC_AR9344,
-+	ATH79_SOC_QCA9533,
- 	ATH79_SOC_QCA9556,
- 	ATH79_SOC_QCA9558,
- };
-@@ -100,6 +101,16 @@ static inline int soc_is_ar934x(void)
- 	return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
- }
- 
-+static inline int soc_is_qca9533(void)
-+{
-+	return ath79_soc == ATH79_SOC_QCA9533;
-+}
-+
-+static inline int soc_is_qca953x(void)
-+{
-+	return soc_is_qca9533();
-+}
-+
- static inline int soc_is_qca9556(void)
- {
- 	return ath79_soc == ATH79_SOC_QCA9556;