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| author | Felix Fietkau <nbd@openwrt.org> | 2015-07-07 08:05:55 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2015-07-07 08:05:55 +0000 |
| commit | c9e433206f3440e683fbf7a2334bcd32e8daba1d (patch) | |
| tree | f19472fee99d4dfaf4fe9faabcdde8dd074b6a6c /target/linux/ar71xx/patches-3.18/736-MIPS-ath79-fix-chained-irq-disable.patch | |
| parent | 7acbd52055067c246a9f87b62b4df5f74293204b (diff) | |
| download | upstream-c9e433206f3440e683fbf7a2334bcd32e8daba1d.tar.gz upstream-c9e433206f3440e683fbf7a2334bcd32e8daba1d.tar.bz2 upstream-c9e433206f3440e683fbf7a2334bcd32e8daba1d.zip | |
ar71xx: rework patch for qca953x/956x
Patch cherry-picked from the following location:
https://www.codeaurora.org/cgit/quic/qsdk/oss/system/openwrt/commit/?h=release/coconut_ioe4531_2.0&id=5c357bf6c763e4140dddcc9a3bc5f005525a9c0e
Changelist,
- add more register defines
- add EHCI support
- fix GPIO pin count to 18
- fix chained irq disabled
- fix GMAC0/GMAC1 initial
- fix WMAC irq number to 47
- merge the changes of dev-eth.c from the patch to file.
Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
SVN-Revision: 46207
Diffstat (limited to 'target/linux/ar71xx/patches-3.18/736-MIPS-ath79-fix-chained-irq-disable.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-3.18/736-MIPS-ath79-fix-chained-irq-disable.patch | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/target/linux/ar71xx/patches-3.18/736-MIPS-ath79-fix-chained-irq-disable.patch b/target/linux/ar71xx/patches-3.18/736-MIPS-ath79-fix-chained-irq-disable.patch index 8cb38d3971..8c0cc95384 100644 --- a/target/linux/ar71xx/patches-3.18/736-MIPS-ath79-fix-chained-irq-disable.patch +++ b/target/linux/ar71xx/patches-3.18/736-MIPS-ath79-fix-chained-irq-disable.patch @@ -19,7 +19,16 @@ irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); } -@@ -224,15 +225,13 @@ static void qca955x_irq_init(void) +@@ -182,7 +183,7 @@ static void qca953x_irq_init(void) + + for (i = ATH79_IP2_IRQ_BASE; + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) +- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); ++ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch); + } +@@ -256,15 +257,13 @@ static void qca955x_irq_init(void) for (i = ATH79_IP2_IRQ_BASE; i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) @@ -37,25 +46,23 @@ irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch); } -@@ -313,15 +312,13 @@ static void qca956x_irq_init(void) +@@ -345,13 +344,13 @@ static void qca956x_irq_init(void) for (i = ATH79_IP2_IRQ_BASE; i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) -- irq_set_chip_and_handler(i, &dummy_irq_chip, -- handle_level_irq); +- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch); for (i = ATH79_IP3_IRQ_BASE; i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) -- irq_set_chip_and_handler(i, &dummy_irq_chip, -- handle_level_irq); +- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); + irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq); irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch); -@@ -430,8 +427,35 @@ static void ar934x_ip3_handler(void) +@@ -466,8 +465,35 @@ static void qca953x_ip3_handler(void) do_IRQ(ATH79_CPU_IRQ(3)); } |