ar71xx: add support for YunCore CPE870

YunCore CPE870 is an outdoor CPE/AP based on Atheros AR9341.
Short specification:

- 535/400/200 MHz (CPU/DDR/AHB)
- 2x 10/100 Mbps Ethernet, passive PoE support
- 64/128 MB of RAM (DDR2)
- 8 MB of FLASH
- 2T2R 2.4 GHz with external PA (SKY65174-21), up to 30 dBm
- internal 14 dBi panel antenna
- 8x LED, 1x button
- UART (JP1) header on PCB

Flash instruction (do it under U-Boot, using UART):

1. tftp 0x80060000 lede-ar71xx-generic-cpe870-squashfs-sysupgrade.bin
2. erase 0x9f020000 +$filesize
3. cp.b $fileaddr 0x9f020000 $filesize
4. setenv bootcmd "bootm 0x9f020000"
5. saveenv && reset

Vendor firmware access (login/password): Admin/5up

Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>

4 files changed, 163 insertions, 0 deletions

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt b/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt
index e9431f139e..6daa093a01 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt
+++ b/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt
@@ -1211,6 +1211,15 @@ config ATH79_MACH_CPE510
 	select ATH79_DEV_M25P80
 	select ATH79_DEV_WMAC
 
+config ATH79_MACH_CPE870
+	bool "YunCore CPE870 support"
+	select SOC_AR934X
+	select ATH79_DEV_ETH
+	select ATH79_DEV_GPIO_BUTTONS
+	select ATH79_DEV_LEDS_GPIO
+	select ATH79_DEV_M25P80
+	select ATH79_DEV_WMAC
+
 config ATH79_MACH_TL_MR11U
 	bool "TP-LINK TL-MR11U/TL-MR3040 support"
 	select SOC_AR933X
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/Makefile b/target/linux/ar71xx/files/arch/mips/ath79/Makefile
index c0caccdb23..b718d6bfd3 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/Makefile
+++ b/target/linux/ar71xx/files/arch/mips/ath79/Makefile
@@ -75,6 +75,7 @@ obj-$(CONFIG_ATH79_MACH_CF_E380AC_V2)		+= mach-cf-e316n-v2.o
 obj-$(CONFIG_ATH79_MACH_CF_E520N)		+= mach-cf-e316n-v2.o
 obj-$(CONFIG_ATH79_MACH_CF_E530N)		+= mach-cf-e316n-v2.o
 obj-$(CONFIG_ATH79_MACH_CPE510)			+= mach-cpe510.o
+obj-$(CONFIG_ATH79_MACH_CPE870)			+= mach-cpe870.o
 obj-$(CONFIG_ATH79_MACH_CR3000)			+= mach-cr3000.o
 obj-$(CONFIG_ATH79_MACH_CR5000)			+= mach-cr5000.o
 obj-$(CONFIG_ATH79_MACH_DAP_2695_A1)		+= mach-dap-2695-a1.o
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-cpe870.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-cpe870.c
new file mode 100644
index 0000000000..284cdc71c2
--- /dev/null
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-cpe870.c
@@ -0,0 +1,152 @@
+/*
+ * YunCore CPE870 board support
+ *
+ * Copyright (C) 2016 Piotr Dymacz <pepe2k@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-ath79/ath79.h>
+#include <asm/mach-ath79/ar71xx_regs.h>
+
+#include "common.h"
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+#include "dev-wmac.h"
+#include "machtypes.h"
+
+#define CPE870_GPIO_LED_LINK1	0
+#define CPE870_GPIO_LED_LINK2	1
+#define CPE870_GPIO_LED_LINK3	2
+#define CPE870_GPIO_LED_LINK4	3
+#define CPE870_GPIO_LED_WLAN	13
+#define CPE870_GPIO_LED_WAN	19
+#define CPE870_GPIO_LED_LAN	20
+
+#define CPE870_GPIO_BTN_RESET	16
+
+#define CPE870_KEYS_POLL_INTERVAL	20
+#define CPE870_KEYS_DEBOUNCE_INTERVAL	(3 * CPE870_KEYS_POLL_INTERVAL)
+
+static struct gpio_led cpe870_leds_gpio[] __initdata = {
+	{
+		.name		= "cpe870:green:lan",
+		.gpio		= CPE870_GPIO_LED_LAN,
+		.active_low	= 1,
+	},
+	{
+		.name		= "cpe870:green:wan",
+		.gpio		= CPE870_GPIO_LED_WAN,
+		.active_low	= 1,
+	},
+	{
+		.name		= "cpe870:green:wlan",
+		.gpio		= CPE870_GPIO_LED_WLAN,
+		.active_low	= 1,
+	},
+	{
+		.name		= "cpe870:green:link1",
+		.gpio		= CPE870_GPIO_LED_LINK1,
+		.active_low	= 1,
+	},
+	{
+		.name		= "cpe870:green:link2",
+		.gpio		= CPE870_GPIO_LED_LINK2,
+		.active_low	= 1,
+	},
+	{
+		.name		= "cpe870:green:link3",
+		.gpio		= CPE870_GPIO_LED_LINK3,
+		.active_low	= 1,
+	},
+	{
+		.name		= "cpe870:green:link4",
+		.gpio		= CPE870_GPIO_LED_LINK4,
+		.active_low	= 1,
+	},
+};
+
+static struct gpio_keys_button cpe870_gpio_keys[] __initdata = {
+	{
+		.desc		= "reset",
+		.type		= EV_KEY,
+		.code		= KEY_RESTART,
+		.debounce_interval = CPE870_KEYS_DEBOUNCE_INTERVAL,
+		.gpio		= CPE870_GPIO_BTN_RESET,
+		.active_low	= 1,
+	},
+};
+
+static void __init cpe870_gpio_setup(void)
+{
+	/* Disable JTAG (enables GPIO0-3) */
+	ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
+
+	ath79_gpio_direction_select(CPE870_GPIO_LED_LINK1, true);
+	ath79_gpio_direction_select(CPE870_GPIO_LED_LINK2, true);
+	ath79_gpio_direction_select(CPE870_GPIO_LED_LINK3, true);
+	ath79_gpio_direction_select(CPE870_GPIO_LED_LINK4, true);
+
+	/* Mute LEDs on boot */
+	gpio_set_value(CPE870_GPIO_LED_LAN, 1);
+	gpio_set_value(CPE870_GPIO_LED_WAN, 1);
+	gpio_set_value(CPE870_GPIO_LED_LINK1, 1);
+	gpio_set_value(CPE870_GPIO_LED_LINK2, 1);
+	gpio_set_value(CPE870_GPIO_LED_LINK3, 1);
+	gpio_set_value(CPE870_GPIO_LED_LINK4, 1);
+
+	ath79_gpio_output_select(CPE870_GPIO_LED_LINK1, 0);
+	ath79_gpio_output_select(CPE870_GPIO_LED_LINK2, 0);
+	ath79_gpio_output_select(CPE870_GPIO_LED_LINK3, 0);
+	ath79_gpio_output_select(CPE870_GPIO_LED_LINK4, 0);
+
+	ath79_register_leds_gpio(-1, ARRAY_SIZE(cpe870_leds_gpio),
+				 cpe870_leds_gpio);
+
+	ath79_register_gpio_keys_polled(-1, CPE870_KEYS_POLL_INTERVAL,
+					ARRAY_SIZE(cpe870_gpio_keys),
+					cpe870_gpio_keys);
+}
+
+static void __init cpe870_setup(void)
+{
+	u8 *art = (u8 *) KSEG1ADDR(0x1fff1000);
+	u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000);
+
+	ath79_register_m25p80(NULL);
+
+	cpe870_gpio_setup();
+
+	ath79_register_mdio(1, 0x0);
+
+	ath79_switch_data.phy4_mii_en = 1;
+	ath79_switch_data.phy_poll_mask = BIT(4);
+
+	/* LAN */
+	ath79_eth1_data.duplex = DUPLEX_FULL;
+	ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
+	ath79_eth1_data.speed = SPEED_1000;
+	ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
+	ath79_register_eth(1);
+
+	/* WAN */
+	ath79_eth0_data.duplex = DUPLEX_FULL;
+	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+	ath79_eth0_data.speed = SPEED_100;
+	ath79_eth0_data.phy_mask = BIT(4);
+	ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
+	ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
+	ath79_register_eth(0);
+
+	ath79_register_wmac(art, NULL);
+}
+
+MIPS_MACHINE(ATH79_MACH_CPE870, "CPE870", "YunCore CPE870", cpe870_setup);
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h b/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h
index e69cf3bece..50ecff46f5 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h
+++ b/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h
@@ -61,6 +61,7 @@ enum ath79_mach_type {
 	ATH79_MACH_CF_E530N,			/* COMFAST CF-E530N */
 	ATH79_MACH_CPE210,			/* TP-LINK CPE210 */
 	ATH79_MACH_CPE510,			/* TP-LINK CPE510 */
+	ATH79_MACH_CPE870,			/* YunCore CPE870 */
 	ATH79_MACH_CR3000,			/* PowerCloud CR3000 */
 	ATH79_MACH_CR5000,			/* PowerCloud CR5000 */
 	ATH79_MACH_DAP_2695_A1,			/* D-Link DAP-2695 rev. A1 */