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| author | Gabor Juhos <juhosg@openwrt.org> | 2008-09-17 13:29:47 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2008-09-17 13:29:47 +0000 |
| commit | 71164d3a814bd27d08dc90d96533c63e00955fdb (patch) | |
| tree | fcc9d53fb57bb9f9312d38372c453201d88b6024 /target/linux/ar71xx/files/arch/mips | |
| parent | a7fb86ba05d78034be1e46a2cbcd99c12f581dfe (diff) | |
| download | upstream-71164d3a814bd27d08dc90d96533c63e00955fdb.tar.gz upstream-71164d3a814bd27d08dc90d96533c63e00955fdb.tar.bz2 upstream-71164d3a814bd27d08dc90d96533c63e00955fdb.zip | |
[ar71xx] fix the PCI byte lane enable generation code, based on a patch by Chris Dearman
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@12617 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/files/arch/mips')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c index e3e80a9014..f27c171a63 100644 --- a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c +++ b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c @@ -59,17 +59,18 @@ static inline void ar71xx_pcicfg_wr(unsigned int reg, u32 val) /* Byte lane enable bits */ static u8 ble_table[4][4] = { - {0xf, 0xe, 0xd, 0xc}, - {0xc, 0x9, 0x3, 0x1}, - {0x0, 0x0, 0x0, 0x0}, - {0x0, 0x0, 0x0, 0x0}, + {0x0, 0xf, 0xf, 0xf}, + {0xe, 0xd, 0xb, 0x7}, + {0xc, 0xf, 0x3, 0xf}, + {0xf, 0xf, 0xf, 0xf}, }; static inline u32 ar71xx_pci_get_ble(int where, int size, int local) { u32 t; - t = ble_table[size][where & 3]; + t = ble_table[size & 3][where & 3]; + BUG_ON(t == 0xf); t <<= (local) ? 20 : 4; return t; } |