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| author | Gabor Juhos <juhosg@openwrt.org> | 2012-01-22 22:38:19 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2012-01-22 22:38:19 +0000 |
| commit | af015f956c35717909247a5732f6862d3de1476f (patch) | |
| tree | c72d67ef23e35b8dd3e8177c4811773ed6eed759 /target/linux/ar71xx/files-3.2/arch/mips/ath79/dev-eth.h | |
| parent | 386cbfe45bc521baa889a8c261b2c77e69fc956f (diff) | |
| download | upstream-af015f956c35717909247a5732f6862d3de1476f.tar.gz upstream-af015f956c35717909247a5732f6862d3de1476f.tar.bz2 upstream-af015f956c35717909247a5732f6862d3de1476f.zip | |
ar71xx: add initial support for 3.2
Tested on the following boards:
ALFA AP96
TL-MR3220 v1
TL-WR1043ND v1
TL-WR2543ND v1
TL-WR703N v1
TL-WR741ND v1
TL-WR741ND v4
WNDR3700 v1
WZR-HP-G300NH
SVN-Revision: 29868
Diffstat (limited to 'target/linux/ar71xx/files-3.2/arch/mips/ath79/dev-eth.h')
| -rw-r--r-- | target/linux/ar71xx/files-3.2/arch/mips/ath79/dev-eth.h | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files-3.2/arch/mips/ath79/dev-eth.h b/target/linux/ar71xx/files-3.2/arch/mips/ath79/dev-eth.h new file mode 100644 index 0000000000..4c010ef74e --- /dev/null +++ b/target/linux/ar71xx/files-3.2/arch/mips/ath79/dev-eth.h @@ -0,0 +1,46 @@ +/* + * Atheros AR71xx SoC device definitions + * + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_ETH_H +#define _ATH79_DEV_ETH_H + +#include <asm/mach-ath79/ag71xx_platform.h> + +struct platform_device; + +extern unsigned char ath79_mac_base[] __initdata; +void ath79_parse_mac_addr(char *mac_str); +void ath79_init_mac(unsigned char *dst, const unsigned char *src, + int offset); +void ath79_init_local_mac(unsigned char *dst, const unsigned char *src); + +struct ath79_eth_pll_data { + u32 pll_10; + u32 pll_100; + u32 pll_1000; +}; + +extern struct ath79_eth_pll_data ath79_eth0_pll_data; +extern struct ath79_eth_pll_data ath79_eth1_pll_data; + +extern struct ag71xx_platform_data ath79_eth0_data; +extern struct ag71xx_platform_data ath79_eth1_data; +extern struct platform_device ath79_eth0_device; +extern struct platform_device ath79_eth1_device; +void ath79_register_eth(unsigned int id); + +extern struct ag71xx_switch_platform_data ath79_switch_data; + +extern struct platform_device ath79_mdio0_device; +extern struct platform_device ath79_mdio1_device; +void ath79_register_mdio(unsigned int id, u32 phy_mask); + +#endif /* _ATH79_DEV_ETH_H */ |