mpc85xx: add support for Aerohive BR200-WP

The following adds the Aerohive BR200-WP router to OpenWrt under
the mpc85xx/p1010 subtarget.

Hardware:
- SoC: Freescale P1011
- NOR: Intel JS28F512M29EWH 64MB
- Memory: 2x Nanya NT5TU64M16GG-AC 128MB (Total of 256MB)
- 2.4GHz WiFi: Atheros AR9390-AL1A
- Eth1: Atheros AR8035-A PoE
- 2x LEDs
- 1x Button
- PoE PSE

Flashing:
1. Hook into UART (9600 baud) and enter U-Boot. You may need to enter a
password of administrator or AhNf?d@ta06 if prompted.
2. Once in U-Boot, tftp boot the initramfs image:
   dhcp; setenv serverip 192.168.1.3;
   tftpboot 0x2004000 openwrt-mpc85xx-p1010-aerohive_br200-wp-initramfs-kernel.bin;
   bootm 0x2004000;
3. Once booted, scp over the sysupgrade file and sysupgrade the device
to flash LEDE to the NOR.

Note:

MAC assigns are taken from stock firmware:

Name        MAC addr      Mode       State Chan(Width) VLAN   Radio      Hive       SSID
-------- -------------- --------     ----- ----------- ---- ---------- ---------- ---------
Mgt0     08ea:44XX:XXc0    -           U     -            1     -        hive0        -
Eth0     08ea:44XX:XXc0 wan            U     -            -     -          -          -
Eth1     08ea:44XX:XXc2 access         D     -            -     -        hive0        -
Eth2     08ea:44XX:XXc3 access         D     -            -     -        hive0        -
Eth3     08ea:44XX:XXc4 access         D     -            -     -        hive0        -
Eth4     08ea:44XX:XXc5 access         D     -            -     -        hive0        -
Wifi0    08ea:44XX:XXd0 access         U     1(20MHz)     -  radio_ng0     -          -
Wifi0.1  08ea:44XX:XXd4 access         D     1(20MHz)     -  radio_ng0   hive0        -

Note2:
PoE PSE could be managed with `realtek-poe` package. Example port
config:

config port
        option enable   '1'
        option id       '4'
        option name     'lan2'
        option poe_plus '0'
        option priority '2'
config port
        option enable   '1'
        option id       '3'
        option name     'lan1'
        option poe_plus '0'
        option priority '1'

Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
(switch@0 -> switch@10, Device's quickstart says LEDs are
amber and white => add function+color properties but keep
labels around, use pr_info)
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>

9 files changed, 544 insertions, 5 deletions

diff --git a/target/linux/mpc85xx/base-files/etc/board.d/02_network b/target/linux/mpc85xx/base-files/etc/board.d/02_network
index 04c27769a9..41859362b5 100644
--- a/target/linux/mpc85xx/base-files/etc/board.d/02_network
+++ b/target/linux/mpc85xx/base-files/etc/board.d/02_network
@@ -9,6 +9,9 @@ board_config_update
 board=$(board_name)
 
 case "$board" in
+aerohive,br200-wp)
+	ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
+	;;
 aerohive,hiveap-330|\
 enterasys,ws-ap3715i)
 	ucidef_set_interfaces_lan_wan "eth1" "eth0"
diff --git a/target/linux/mpc85xx/config-5.15 b/target/linux/mpc85xx/config-5.15
index 9c051e63c1..6f7db117d4 100644
--- a/target/linux/mpc85xx/config-5.15
+++ b/target/linux/mpc85xx/config-5.15
@@ -20,6 +20,7 @@ CONFIG_AUDIT_ARCH=y
 CONFIG_BLK_MQ_PCI=y
 CONFIG_BOOKE=y
 CONFIG_BOOKE_WDT=y
+# CONFIG_BR200_WP is not set
 # CONFIG_BSC9131_RDB is not set
 # CONFIG_BSC9132_QDS is not set
 # CONFIG_C293_PCIE is not set
@@ -58,6 +59,7 @@ CONFIG_EDAC_ATOMIC_SCRUB=y
 CONFIG_EDAC_LEGACY_SYSFS=y
 CONFIG_EDAC_MPC85XX=y
 CONFIG_EDAC_SUPPORT=y
+# CONFIG_FIREBOX_T10 is not set
 CONFIG_FIXED_PHY=y
 CONFIG_FSL_BOOKE=y
 # CONFIG_FSL_DPAA2_SWITCH is not set
@@ -265,4 +267,3 @@ CONFIG_WATCHDOG_CORE=y
 # CONFIG_XES_MPC85xx is not set
 CONFIG_XZ_DEC_BCJ=y
 CONFIG_XZ_DEC_POWERPC=y
-# CONFIG_FIREBOX_T10 is not set
diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/br200-wp.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/br200-wp.dts
new file mode 100644
index 0000000000..a4bc10ff38
--- /dev/null
+++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/br200-wp.dts
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Aerohive BR200-WP Device Tree Source
+ *
+ * Based on: Aerohive HiveAP-330 Device Tree Source
+ *
+ * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
+ * Copyright (C) 2023 Pawel Dembicki <paweldembicki@gmail.com>
+ */
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/include/ "fsl/p1020si-pre.dtsi"
+
+/ {
+	model = "Aerohive BR200-WP";
+	compatible = "aerohive,br200-wp";
+
+	chosen {
+		bootargs = "console=ttyS0,9600";
+		bootargs-override = "console=ttyS0,9600 noinitrd";
+	};
+
+	aliases {
+		led-boot = &led_attention;
+		led-failsafe = &led_attention;
+		led-running = &led_status;
+		led-upgrade = &led_status;
+		label-mac-device = &enet0;
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	cpus {
+		/delete-property/ PowerPC,P1020@1; /* P1011 have one core only */
+	};
+
+	board_lbc: lbc: localbus@ffe05000 {
+		reg = <0 0xffe05000 0 0x1000>;
+		ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
+
+		nor@0,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x0 0x0 0x4000000>;
+			bank-width = <2>;
+			device-width = <1>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					reg = <0x0 0x40000>;
+					label = "dtb";
+				};
+
+				partition@40000 {
+					reg = <0x40000 0x40000>;
+					label = "initramfs";
+				};
+
+				partition@80000 {
+					reg = <0x80000 0x27c0000>;
+					label = "rootfs";
+				};
+
+				partition@2840000 {
+					reg = <0x2840000 0x800000>;
+					label = "kernel";
+				};
+
+				partition@3040000 {
+					reg = <0x3040000 0xec0000>;
+					label = "stock-jffs2";
+					read-only;
+				};
+
+				partition@3f00000 {
+					reg = <0x3f00000 0x20000>;
+					label = "hw-info";
+					read-only;
+
+					compatible = "nvmem-cells";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_hwinfo_0: macaddr@0 {
+						reg = <0x0 0x6>;
+					};
+				};
+
+				partition@3f20000 {
+					reg = <0x3f20000 0x20000>;
+					label = "boot-info";
+					read-only;
+				};
+
+				partition@3f40000 {
+					reg = <0x3f40000 0x20000>;
+					label = "boot-info-backup";
+					read-only;
+				};
+
+				partition@3f60000 {
+					reg = <0x3f60000 0x20000>;
+					label = "u-boot-env";
+				};
+
+				partition@3f80000 {
+					reg = <0x3f80000 0x80000>;
+					label = "u-boot";
+					read-only;
+				};
+
+				firmware@0 {
+					reg = <0x0 0x3040000>;
+					label = "firmware";
+				};
+			};
+		};
+	};
+
+	board_soc: soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		mdio@24000 {
+
+			phy_port1: phy@0 {
+				reg = <0>;
+			};
+
+			phy_port2: phy@1 {
+				reg = <1>;
+			};
+
+			phy_port3: phy@2 {
+				reg = <2>;
+			};
+
+			phy_port4: phy@3 {
+				reg = <3>;
+			};
+
+			phy_port5: phy@4 {
+				reg = <4>;
+			};
+
+			switch@10 {
+				compatible = "qca,qca8327";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x10>;
+				reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@1 {
+						reg = <1>;
+						label = "lan1";
+						phy-handle = <&phy_port1>;
+						nvmem-cells = <&macaddr_hwinfo_0>;
+						nvmem-cell-names = "mac-address";
+						mac-address-increment = <2>;
+					};
+
+					port@2 {
+						reg = <2>;
+						label = "lan2";
+						phy-handle = <&phy_port2>;
+						nvmem-cells = <&macaddr_hwinfo_0>;
+						nvmem-cell-names = "mac-address";
+						mac-address-increment = <3>;
+					};
+
+					port@3 {
+						reg = <3>;
+						label = "lan3";
+						phy-handle = <&phy_port3>;
+						nvmem-cells = <&macaddr_hwinfo_0>;
+						nvmem-cell-names = "mac-address";
+						mac-address-increment = <4>;
+					};
+
+					port@4 {
+						reg = <4>;
+						label = "lan4";
+						phy-handle = <&phy_port4>;
+						nvmem-cells = <&macaddr_hwinfo_0>;
+						nvmem-cell-names = "mac-address";
+						mac-address-increment = <5>;
+					};
+
+					port@5 {
+						reg = <5>;
+						label = "wan";
+						phy-handle = <&phy_port5>;
+						nvmem-cells = <&macaddr_hwinfo_0>;
+						nvmem-cell-names = "mac-address";
+					};
+
+					port@6 {
+						reg = <6>;
+						ethernet = <&enet0>;
+						phy-mode = "rgmii-id";
+
+						fixed-link {
+							speed = <1000>;
+							full-duplex;
+						};
+					};
+				};
+			};
+		};
+
+		mdio@25000 {
+			status = "disabled";
+		};
+
+		mdio@26000 {
+			status = "disabled";
+		};
+
+		enet0: ethernet@b0000 {
+			status = "okay";
+			phy-connection-type = "rgmii-id";
+			nvmem-cells = <&macaddr_hwinfo_0>;
+			nvmem-cell-names = "mac-address";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+
+		enet1: ethernet@b1000 {
+			status = "disabled";
+		};
+
+		enet2: ethernet@b2000 {
+			status = "disabled";
+		};
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		usb@22000 {
+			phy_type = "ulpi";
+			dr_mode = "host";
+		};
+
+		usb@23000 {
+			status = "disabled";
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		status = "disabled";
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0x0 0xffe0a000 0x0 0x1000>;
+		ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000
+				  0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
+
+		reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
+
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xc0000000
+				  0x2000000 0x0 0xc0000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+
+			ath9k: wifi@0,0 {
+				reg = <0x0000 0 0 0 0>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				nvmem-cells = <&macaddr_hwinfo_0>;
+				nvmem-cell-names = "mac-address";
+				mac-address-increment = <16>;
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_attention: led-0 {
+			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
+			label = "amber:status";
+			color = <LED_COLOR_ID_AMBER>;
+			function = LED_FUNCTION_STATUS;
+		};
+
+		led_status: led-1 {
+			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+			label = "white:status";
+			color = <LED_COLOR_ID_WHITE>;
+			function = LED_FUNCTION_STATUS;
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "Reset button";
+			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+};
+
+/include/ "fsl/p1020si-post.dtsi"
+
+/ {
+	chosen {
+		linux,stdout-path = "/soc@ffe00000/serial@4500";
+	};
+
+	cpus {
+		PowerPC,P1020@0 {
+			i-cache-sets = <0x80>;
+			i-cache-size = <0x8000>;
+			i-cache-block-size = <0x20>;
+			d-cache-sets = <0x80>;
+			d-cache-size = <0x8000>;
+			d-cache-block-size = <0x20>;
+			clock-frequency = <0x2756cd00>;
+			bus-frequency = <0x13ab6680>;
+			timebase-frequency = <0x2756cd0>;
+		};
+	};
+
+	memory {
+		reg = <0x00 0x00 0x00 0x10000000>;
+	};
+
+	localbus@ffe05000 {
+		bus-frequency = <0x13ab668>;
+	};
+
+	soc@ffe00000 {
+		bus-frequency = <0x13ab6680>;
+
+		serial@4500 {
+			clock-frequency = <0x13ab6680>;
+		};
+
+		serial@4600 {
+			clock-frequency = <0x13ab6680>;
+		};
+	};
+
+	pcie@ffe09000 {
+		clock-frequency = <0x1fca055>;
+	};
+
+	pcie@ffe0a000 {
+		clock-frequency = <0x1fca055>;
+	};
+};
diff --git a/target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/br200-wp.c b/target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/br200-wp.c
new file mode 100644
index 0000000000..23fd11a5c6
--- /dev/null
+++ b/target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/br200-wp.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Aerohive BR200-WP Board Setup
+ * Copyright (C) 2023 Pawel Dembicki <paweldembicki@gmail.com>
+ *
+ * Based on:
+ *   hiveap-330.c:
+ *      Aerohive HiveAP-330 Board Setup
+ *      Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include "smp.h"
+
+#include "mpc85xx.h"
+
+void __init br200_wp_pic_init(void)
+{
+	struct mpic *mpic;
+
+	mpic = mpic_alloc(NULL, 0,
+	  MPIC_BIG_ENDIAN |
+	  MPIC_SINGLE_DEST_CPU,
+	  0, 256, " OpenPIC  ");
+
+	BUG_ON(mpic == NULL);
+	mpic_init(mpic);
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init br200_wp_setup_arch(void)
+{
+	if (ppc_md.progress)
+		ppc_md.progress("br200_wp_setup_arch()", 0);
+
+	fsl_pci_assign_primary();
+
+	pr_info("br200-wp board from Aerohive\n");
+}
+
+machine_arch_initcall(br200_wp, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init br200_wp_probe(void)
+{
+	if (of_machine_is_compatible("aerohive,br200-wp"))
+		return 1;
+	return 0;
+}
+
+define_machine(br200_wp) {
+	.name			= "P1020 RDB",
+	.probe			= br200_wp_probe,
+	.setup_arch		= br200_wp_setup_arch,
+	.init_IRQ		= br200_wp_pic_init,
+#ifdef CONFIG_PCI
+	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
+	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
+#endif
+	.get_irq		= mpic_get_irq,
+	.calibrate_decr		= generic_calibrate_decr,
+	.progress		= udbg_progress,
+};
diff --git a/target/linux/mpc85xx/image/p1010.mk b/target/linux/mpc85xx/image/p1010.mk
index 034f6abc40..c0de19f6c6 100644
--- a/target/linux/mpc85xx/image/p1010.mk
+++ b/target/linux/mpc85xx/image/p1010.mk
@@ -14,6 +14,26 @@ define Build/spi-loader-okli
 	mv "$@.new" "$@"
 endef
 
+define Device/aerohive_br200-wp
+  DEVICE_VENDOR := Aerohive
+  DEVICE_MODEL := BR200-WP
+  BLOCKSIZE := 128k
+  KERNEL_NAME := simpleImage.br200-wp
+  KERNEL := kernel-bin | uImage none
+  KERNEL_INITRAMFS := kernel-bin | uImage none
+  KERNEL_ENTRY := 0x1000000
+  KERNEL_LOADADDR := 0x1000000
+  KERNEL_SIZE := 8m
+  IMAGES := fdt.bin sysupgrade.bin
+  IMAGE/fdt.bin := append-dtb
+  IMAGE/sysupgrade.bin := append-dtb | pad-to 256k | check-size 256k | \
+	append-uImage-fakehdr ramdisk | pad-to 256k | check-size 512k | \
+	append-rootfs | pad-rootfs $$(BLOCKSIZE) | pad-to 41216k | check-size 41216k | \
+	append-kernel | append-metadata
+  IMAGE_SIZE = 63m
+endef
+TARGET_DEVICES += aerohive_br200-wp
+
 define Device/enterasys_ws-ap3715i
   DEVICE_VENDOR := Enterasys
   DEVICE_MODEL := WS-AP3715i
diff --git a/target/linux/mpc85xx/p1010/config-default b/target/linux/mpc85xx/p1010/config-default
index 6af6b8e097..b6d483cd80 100644
--- a/target/linux/mpc85xx/p1010/config-default
+++ b/target/linux/mpc85xx/p1010/config-default
@@ -1,8 +1,12 @@
 CONFIG_AT803X_PHY=y
+CONFIG_BR200_WP=y
 CONFIG_CMDLINE_OVERRIDE=y
+CONFIG_FIREBOX_T10=y
 # CONFIG_FSL_CORENET_CF is not set
 CONFIG_GPIO_74X164=y
+CONFIG_MTD_CFI=y
 CONFIG_MTD_NAND_FSL_IFC=y
+CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_SPLIT_FIRMWARE=y
 CONFIG_MTD_SPLIT_TPLINK_FW=y
 CONFIG_MTD_SPLIT_UIMAGE_FW=y
@@ -24,4 +28,3 @@ CONFIG_SPI_GPIO=y
 CONFIG_TL_WDR4900_V1=y
 CONFIG_UBIFS_FS=y
 CONFIG_WS_AP3715I=y
-CONFIG_FIREBOX_T10=y
\ No newline at end of file
diff --git a/target/linux/mpc85xx/p1010/target.mk b/target/linux/mpc85xx/p1010/target.mk
index fa1bb7542d..6b54390863 100644
--- a/target/linux/mpc85xx/p1010/target.mk
+++ b/target/linux/mpc85xx/p1010/target.mk
@@ -1,5 +1,5 @@
 BOARDNAME:=P1010
-KERNEL_IMAGES:=simpleImage.tl-wdr4900-v1 simpleImage.ws-ap3715i
+KERNEL_IMAGES:=simpleImage.br200-wp simpleImage.tl-wdr4900-v1 simpleImage.ws-ap3715i
 
 define Target/Description
 	Build firmware images for P1010 based boards.
diff --git a/target/linux/mpc85xx/patches-5.15/110-powerpc-85xx-br200-wp-support.patch b/target/linux/mpc85xx/patches-5.15/110-powerpc-85xx-br200-wp-support.patch
new file mode 100644
index 0000000000..8d510759dc
--- /dev/null
+++ b/target/linux/mpc85xx/patches-5.15/110-powerpc-85xx-br200-wp-support.patch
@@ -0,0 +1,57 @@
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -49,6 +49,16 @@ config BSC9132_QDS
+ 	  and dual StarCore SC3850 DSP cores.
+ 	  Manufacturer : Freescale Semiconductor, Inc
+ 
++config BR200_WP
++    bool "Aerohive BR200-WP"
++    select DEFAULT_UIMAGE
++    select ARCH_REQUIRE_GPIOLIB
++    select GPIO_MPC8XXX
++    help
++      This option enables support for the Aerohive BR200-WP board.
++
++      This board is a wireless router with a Freescale P1011 SoC.
++
+ config HIVEAP_330
+     bool "Aerohive HiveAP-330"
+     select DEFAULT_UIMAGE
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -12,6 +12,7 @@ obj-y += common.o
+ obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o
+ obj-$(CONFIG_BSC9132_QDS) += bsc913x_qds.o
+ obj-$(CONFIG_C293_PCIE)   += c293pcie.o
++obj-$(CONFIG_BR200_WP) += br200-wp.o
+ obj-$(CONFIG_HIVEAP_330) += hiveap-330.o
+ obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
+ obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -163,6 +163,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie
+ src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
+ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
+ src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
++src-plat-$(CONFIG_BR200_WP) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
+ 
+@@ -345,6 +346,7 @@ image-$(CONFIG_TQM8548)			+= cuImage.tqm
+ image-$(CONFIG_TQM8555)			+= cuImage.tqm8555
+ image-$(CONFIG_TQM8560)			+= cuImage.tqm8560
+ image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
++image-$(CONFIG_BR200_WP)		+= simpleImage.br200-wp
+ image-$(CONFIG_TL_WDR4900_V1)		+= simpleImage.tl-wdr4900-v1
+ image-$(CONFIG_WS_AP3715I)		+= simpleImage.ws-ap3715i
+ image-$(CONFIG_WS_AP3825I)		+= simpleImage.ws-ap3825i
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -326,6 +326,7 @@ adder875-redboot)
+     platformo="$object/fixed-head.o $object/redboot-8xx.o"
+     binary=y
+     ;;
++simpleboot-br200-wp|\
+ simpleboot-ws-ap3715i|\
+ simpleboot-ws-ap3825i|\
+ simpleboot-tl-wdr4900-v1)
diff --git a/target/linux/mpc85xx/patches-5.15/900-powerpc-bootwrapper-disable-uImage-generation.patch b/target/linux/mpc85xx/patches-5.15/900-powerpc-bootwrapper-disable-uImage-generation.patch
index 66935c04b7..1af5aefe0b 100644
--- a/target/linux/mpc85xx/patches-5.15/900-powerpc-bootwrapper-disable-uImage-generation.patch
+++ b/target/linux/mpc85xx/patches-5.15/900-powerpc-bootwrapper-disable-uImage-generation.patch
@@ -16,7 +16,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
 
 --- a/arch/powerpc/boot/Makefile
 +++ b/arch/powerpc/boot/Makefile
-@@ -273,7 +273,6 @@ image-$(CONFIG_PPC_CHRP)		+= zImage.chrp
+@@ -274,7 +274,6 @@ image-$(CONFIG_PPC_CHRP)		+= zImage.chrp
  image-$(CONFIG_PPC_EFIKA)		+= zImage.chrp
  image-$(CONFIG_PPC_PMAC)		+= zImage.pmac
  image-$(CONFIG_PPC_HOLLY)		+= dtbImage.holly
@@ -24,7 +24,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
  image-$(CONFIG_EPAPR_BOOT)		+= zImage.epapr
  
  #
-@@ -407,15 +406,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
+@@ -409,15 +408,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
  $(obj)/vmlinux.strip: vmlinux
  	$(STRIP) -s -R .comment $< -o $@