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author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2022-06-16 21:43:48 +0200 |
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committer | Christian Lamparter <chunkeey@gmail.com> | 2022-06-19 12:31:02 +0200 |
commit | 087f2cba26faf085f825128b78ba2e662a66cbbd (patch) | |
tree | 24ddb3adc81ea6aba2f9fd0423b8dc30ece3fbff | |
parent | 00f64ed6601f3cc67b70777e5eec994d297bd5e4 (diff) | |
download | upstream-087f2cba26faf085f825128b78ba2e662a66cbbd.tar.gz upstream-087f2cba26faf085f825128b78ba2e662a66cbbd.tar.bz2 upstream-087f2cba26faf085f825128b78ba2e662a66cbbd.zip |
lantiq: dts: Add the reset line for the PCI controller
The PCI controller has it's reset line wired up to bit 13 of RCU.
Describe this in our .dtsi files.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
3 files changed, 6 insertions, 0 deletions
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9.dtsi index 61283f5621..98aca38fe2 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9.dtsi +++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9.dtsi @@ -415,6 +415,8 @@ req-mask = <0x1>; device_type = "pci"; + + resets = <&reset0 13 13>; }; }; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube.dtsi index a18183a2de..9d9946fbb5 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube.dtsi +++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube.dtsi @@ -328,6 +328,8 @@ req-mask = <0x1>; /* GNT1 */ device_type = "pci"; + + resets = <&reset0 13 13>; }; }; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi index 27858be28f..1089cdc80c 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi +++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi @@ -555,6 +555,8 @@ req-mask = <0x1>; /* GNT1 */ device_type = "pci"; + + resets = <&reset0 13 13>; }; }; |