diff options
Diffstat (limited to 'target/linux/generic/patches-3.3/025-bcma_backport.patch')
| -rw-r--r-- | target/linux/generic/patches-3.3/025-bcma_backport.patch | 4901 |
1 files changed, 4901 insertions, 0 deletions
diff --git a/target/linux/generic/patches-3.3/025-bcma_backport.patch b/target/linux/generic/patches-3.3/025-bcma_backport.patch new file mode 100644 index 0000000..a00bec3 --- /dev/null +++ b/target/linux/generic/patches-3.3/025-bcma_backport.patch @@ -0,0 +1,4901 @@ +--- a/drivers/bcma/Kconfig ++++ b/drivers/bcma/Kconfig +@@ -29,7 +29,7 @@ config BCMA_HOST_PCI + + config BCMA_DRIVER_PCI_HOSTMODE + bool "Driver for PCI core working in hostmode" +- depends on BCMA && MIPS ++ depends on BCMA && MIPS && BCMA_HOST_PCI + help + PCI core hostmode operation (external PCI bus). + +@@ -46,6 +46,33 @@ config BCMA_DRIVER_MIPS + + If unsure, say N + ++config BCMA_SFLASH ++ bool ++ depends on BCMA_DRIVER_MIPS ++ default y ++ ++config BCMA_NFLASH ++ bool ++ depends on BCMA_DRIVER_MIPS ++ default y ++ ++config BCMA_DRIVER_GMAC_CMN ++ bool "BCMA Broadcom GBIT MAC COMMON core driver" ++ depends on BCMA ++ help ++ Driver for the Broadcom GBIT MAC COMMON core attached to Broadcom ++ specific Advanced Microcontroller Bus. ++ ++ If unsure, say N ++ ++config BCMA_DRIVER_GPIO ++ bool "BCMA GPIO driver" ++ depends on BCMA && GPIOLIB ++ help ++ Driver to provide access to the GPIO pins of the bcma bus. ++ ++ If unsure, say N ++ + config BCMA_DEBUG + bool "BCMA debugging" + depends on BCMA +--- a/drivers/bcma/Makefile ++++ b/drivers/bcma/Makefile +@@ -1,8 +1,12 @@ + bcma-y += main.o scan.o core.o sprom.o + bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o ++bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o ++bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o + bcma-y += driver_pci.o + bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o + bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o ++bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o ++bcma-$(CONFIG_BCMA_DRIVER_GPIO) += driver_gpio.o + bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o + bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o + obj-$(CONFIG_BCMA) += bcma.o +--- a/drivers/bcma/bcma_private.h ++++ b/drivers/bcma/bcma_private.h +@@ -10,10 +10,19 @@ + + #define BCMA_CORE_SIZE 0x1000 + ++#define bcma_err(bus, fmt, ...) \ ++ pr_err("bus%d: " fmt, (bus)->num, ##__VA_ARGS__) ++#define bcma_warn(bus, fmt, ...) \ ++ pr_warn("bus%d: " fmt, (bus)->num, ##__VA_ARGS__) ++#define bcma_info(bus, fmt, ...) \ ++ pr_info("bus%d: " fmt, (bus)->num, ##__VA_ARGS__) ++#define bcma_debug(bus, fmt, ...) \ ++ pr_debug("bus%d: " fmt, (bus)->num, ##__VA_ARGS__) ++ + struct bcma_bus; + + /* main.c */ +-int bcma_bus_register(struct bcma_bus *bus); ++int __devinit bcma_bus_register(struct bcma_bus *bus); + void bcma_bus_unregister(struct bcma_bus *bus); + int __init bcma_bus_early_register(struct bcma_bus *bus, + struct bcma_device *core_cc, +@@ -22,6 +31,8 @@ int __init bcma_bus_early_register(struc + int bcma_bus_suspend(struct bcma_bus *bus); + int bcma_bus_resume(struct bcma_bus *bus); + #endif ++struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, ++ u8 unit); + + /* scan.c */ + int bcma_bus_scan(struct bcma_bus *bus); +@@ -39,8 +50,32 @@ void bcma_chipco_serial_init(struct bcma + #endif /* CONFIG_BCMA_DRIVER_MIPS */ + + /* driver_chipcommon_pmu.c */ +-u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc); +-u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc); ++u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc); ++u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc); ++ ++#ifdef CONFIG_BCMA_SFLASH ++/* driver_chipcommon_sflash.c */ ++int bcma_sflash_init(struct bcma_drv_cc *cc); ++extern struct platform_device bcma_sflash_dev; ++#else ++static inline int bcma_sflash_init(struct bcma_drv_cc *cc) ++{ ++ bcma_err(cc->core->bus, "Serial flash not supported\n"); ++ return 0; ++} ++#endif /* CONFIG_BCMA_SFLASH */ ++ ++#ifdef CONFIG_BCMA_NFLASH ++/* driver_chipcommon_nflash.c */ ++int bcma_nflash_init(struct bcma_drv_cc *cc); ++extern struct platform_device bcma_nflash_dev; ++#else ++static inline int bcma_nflash_init(struct bcma_drv_cc *cc) ++{ ++ bcma_err(cc->core->bus, "NAND flash not supported\n"); ++ return 0; ++} ++#endif /* CONFIG_BCMA_NFLASH */ + + #ifdef CONFIG_BCMA_HOST_PCI + /* host_pci.c */ +@@ -48,8 +83,24 @@ extern int __init bcma_host_pci_init(voi + extern void __exit bcma_host_pci_exit(void); + #endif /* CONFIG_BCMA_HOST_PCI */ + ++/* driver_pci.c */ ++u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address); ++ ++extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc); ++ + #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE +-void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc); ++bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc); ++void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc); + #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ + ++#ifdef CONFIG_BCMA_DRIVER_GPIO ++/* driver_gpio.c */ ++int bcma_gpio_init(struct bcma_drv_cc *cc); ++#else ++static inline int bcma_gpio_init(struct bcma_drv_cc *cc) ++{ ++ return -ENOTSUPP; ++} ++#endif /* CONFIG_BCMA_DRIVER_GPIO */ ++ + #endif +--- a/drivers/bcma/core.c ++++ b/drivers/bcma/core.c +@@ -30,6 +30,7 @@ void bcma_core_disable(struct bcma_devic + udelay(10); + + bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET); ++ bcma_aread32(core, BCMA_RESET_CTL); + udelay(1); + } + EXPORT_SYMBOL_GPL(bcma_core_disable); +@@ -64,7 +65,7 @@ void bcma_core_set_clockmode(struct bcma + switch (clkmode) { + case BCMA_CLKMODE_FAST: + bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT); +- udelay(64); ++ usleep_range(64, 300); + for (i = 0; i < 1500; i++) { + if (bcma_read32(core, BCMA_CLKCTLST) & + BCMA_CLKCTLST_HAVEHT) { +@@ -74,10 +75,10 @@ void bcma_core_set_clockmode(struct bcma + udelay(10); + } + if (i) +- pr_err("HT force timeout\n"); ++ bcma_err(core->bus, "HT force timeout\n"); + break; + case BCMA_CLKMODE_DYNAMIC: +- pr_warn("Dynamic clockmode not supported yet!\n"); ++ bcma_set32(core, BCMA_CLKCTLST, ~BCMA_CLKCTLST_FORCEHT); + break; + } + } +@@ -101,9 +102,9 @@ void bcma_core_pll_ctl(struct bcma_devic + udelay(10); + } + if (i) +- pr_err("PLL enable timeout\n"); ++ bcma_err(core->bus, "PLL enable timeout\n"); + } else { +- pr_warn("Disabling PLL not supported yet!\n"); ++ bcma_warn(core->bus, "Disabling PLL not supported yet!\n"); + } + } + EXPORT_SYMBOL_GPL(bcma_core_pll_ctl); +@@ -119,8 +120,8 @@ u32 bcma_core_dma_translation(struct bcm + else + return BCMA_DMA_TRANSLATION_DMA32_CMT; + default: +- pr_err("DMA translation unknown for host %d\n", +- core->bus->hosttype); ++ bcma_err(core->bus, "DMA translation unknown for host %d\n", ++ core->bus->hosttype); + } + return BCMA_DMA_TRANSLATION_NONE; + } +--- a/drivers/bcma/driver_chipcommon.c ++++ b/drivers/bcma/driver_chipcommon.c +@@ -4,12 +4,15 @@ + * + * Copyright 2005, Broadcom Corporation + * Copyright 2006, 2007, Michael Buesch <m@bues.ch> ++ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + + #include "bcma_private.h" ++#include <linux/bcm47xx_wdt.h> + #include <linux/export.h> ++#include <linux/platform_device.h> + #include <linux/bcma/bcma.h> + + static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, +@@ -22,20 +25,119 @@ static inline u32 bcma_cc_write32_masked + return value; + } + +-void bcma_core_chipcommon_init(struct bcma_drv_cc *cc) ++static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) + { +- u32 leddc_on = 10; +- u32 leddc_off = 90; ++ if (cc->capabilities & BCMA_CC_CAP_PMU) ++ return bcma_pmu_get_alp_clock(cc); + +- if (cc->setup_done) ++ return 20000000; ++} ++ ++static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc) ++{ ++ struct bcma_bus *bus = cc->core->bus; ++ u32 nb; ++ ++ if (cc->capabilities & BCMA_CC_CAP_PMU) { ++ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) ++ nb = 32; ++ else if (cc->core->id.rev < 26) ++ nb = 16; ++ else ++ nb = (cc->core->id.rev >= 37) ? 32 : 24; ++ } else { ++ nb = 28; ++ } ++ if (nb == 32) ++ return 0xffffffff; ++ else ++ return (1 << nb) - 1; ++} ++ ++static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, ++ u32 ticks) ++{ ++ struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt); ++ ++ return bcma_chipco_watchdog_timer_set(cc, ticks); ++} ++ ++static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt, ++ u32 ms) ++{ ++ struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt); ++ u32 ticks; ++ ++ ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms); ++ return ticks / cc->ticks_per_ms; ++} ++ ++static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc) ++{ ++ struct bcma_bus *bus = cc->core->bus; ++ ++ if (cc->capabilities & BCMA_CC_CAP_PMU) { ++ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) ++ /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */ ++ return bcma_chipco_get_alp_clock(cc) / 4000; ++ else ++ /* based on 32KHz ILP clock */ ++ return 32; ++ } else { ++ return bcma_chipco_get_alp_clock(cc) / 1000; ++ } ++} ++ ++int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc) ++{ ++ struct bcm47xx_wdt wdt = {}; ++ struct platform_device *pdev; ++ ++ wdt.driver_data = cc; ++ wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt; ++ wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt; ++ wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms; ++ ++ pdev = platform_device_register_data(NULL, "bcm47xx-wdt", ++ cc->core->bus->num, &wdt, ++ sizeof(wdt)); ++ if (IS_ERR(pdev)) ++ return PTR_ERR(pdev); ++ ++ cc->watchdog = pdev; ++ ++ return 0; ++} ++ ++void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc) ++{ ++ if (cc->early_setup_done) + return; + ++ spin_lock_init(&cc->gpio_lock); ++ + if (cc->core->id.rev >= 11) + cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); + cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP); + if (cc->core->id.rev >= 35) + cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT); + ++ if (cc->capabilities & BCMA_CC_CAP_PMU) ++ bcma_pmu_early_init(cc); ++ ++ cc->early_setup_done = true; ++} ++ ++void bcma_core_chipcommon_init(struct bcma_drv_cc *cc) ++{ ++ u32 leddc_on = 10; ++ u32 leddc_off = 90; ++ ++ if (cc->setup_done) ++ return; ++ ++ bcma_core_chipcommon_early_init(cc); ++ + if (cc->core->id.rev >= 20) { + bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0); + bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0); +@@ -44,7 +146,7 @@ void bcma_core_chipcommon_init(struct bc + if (cc->capabilities & BCMA_CC_CAP_PMU) + bcma_pmu_init(cc); + if (cc->capabilities & BCMA_CC_CAP_PCTL) +- pr_err("Power control not implemented!\n"); ++ bcma_err(cc->core->bus, "Power control not implemented!\n"); + + if (cc->core->id.rev >= 16) { + if (cc->core->bus->sprom.leddc_on_time && +@@ -56,15 +158,33 @@ void bcma_core_chipcommon_init(struct bc + ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) | + (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT))); + } ++ cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc); + + cc->setup_done = true; + } + + /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ +-void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks) ++u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks) + { +- /* instant NMI */ +- bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks); ++ u32 maxt; ++ enum bcma_clkmode clkmode; ++ ++ maxt = bcma_chipco_watchdog_get_max_timer(cc); ++ if (cc->capabilities & BCMA_CC_CAP_PMU) { ++ if (ticks == 1) ++ ticks = 2; ++ else if (ticks > maxt) ++ ticks = maxt; ++ bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks); ++ } else { ++ clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC; ++ bcma_core_set_clockmode(cc->core, clkmode); ++ if (ticks > maxt) ++ ticks = maxt; ++ /* instant NMI */ ++ bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks); ++ } ++ return ticks; + } + + void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value) +@@ -84,28 +204,97 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_ + + u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); ++ unsigned long flags; ++ u32 res; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); ++ unsigned long flags; ++ u32 res; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + ++/* ++ * If the bit is set to 0, chipcommon controlls this GPIO, ++ * if the bit is set to 1, it is used by some part of the chip and not our code. ++ */ + u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); ++ unsigned long flags; ++ u32 res; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control); + + u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); ++ unsigned long flags; ++ u32 res; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); ++ unsigned long flags; ++ u32 res; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; ++} ++ ++u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value) ++{ ++ unsigned long flags; ++ u32 res; ++ ++ if (cc->core->id.rev < 20) ++ return 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; ++} ++ ++u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value) ++{ ++ unsigned long flags; ++ u32 res; ++ ++ if (cc->core->id.rev < 20) ++ return 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + #ifdef CONFIG_BCMA_DRIVER_MIPS +@@ -118,8 +307,7 @@ void bcma_chipco_serial_init(struct bcma + struct bcma_serial_port *ports = cc->serial_ports; + + if (ccrev >= 11 && ccrev != 15) { +- /* Fixed ALP clock */ +- baud_base = bcma_pmu_alp_clock(cc); ++ baud_base = bcma_chipco_get_alp_clock(cc); + if (ccrev >= 21) { + /* Turn off UART clock before switching clocksource. */ + bcma_cc_write32(cc, BCMA_CC_CORECTL, +@@ -137,8 +325,7 @@ void bcma_chipco_serial_init(struct bcma + | BCMA_CC_CORECTL_UARTCLKEN); + } + } else { +- pr_err("serial not supported on this device ccrev: 0x%x\n", +- ccrev); ++ bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ccrev); + return; + } + +--- /dev/null ++++ b/drivers/bcma/driver_chipcommon_nflash.c +@@ -0,0 +1,44 @@ ++/* ++ * Broadcom specific AMBA ++ * ChipCommon NAND flash interface ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++#include <linux/platform_device.h> ++#include <linux/bcma/bcma.h> ++ ++#include "bcma_private.h" ++ ++struct platform_device bcma_nflash_dev = { ++ .name = "bcma_nflash", ++ .num_resources = 0, ++}; ++ ++/* Initialize NAND flash access */ ++int bcma_nflash_init(struct bcma_drv_cc *cc) ++{ ++ struct bcma_bus *bus = cc->core->bus; ++ ++ if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 && ++ cc->core->id.rev != 0x38) { ++ bcma_err(bus, "NAND flash on unsupported board!\n"); ++ return -ENOTSUPP; ++ } ++ ++ if (!(cc->capabilities & BCMA_CC_CAP_NFLASH)) { ++ bcma_err(bus, "NAND flash not present according to ChipCommon\n"); ++ return -ENODEV; ++ } ++ ++ cc->nflash.present = true; ++ if (cc->core->id.rev == 38 && ++ (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)) ++ cc->nflash.boot = true; ++ ++ /* Prepare platform device, but don't register it yet. It's too early, ++ * malloc (required by device_private_init) is not available yet. */ ++ bcma_nflash_dev.dev.platform_data = &cc->nflash; ++ ++ return 0; ++} +--- a/drivers/bcma/driver_chipcommon_pmu.c ++++ b/drivers/bcma/driver_chipcommon_pmu.c +@@ -3,7 +3,8 @@ + * ChipCommon Power Management Unit driver + * + * Copyright 2009, Michael Buesch <m@bues.ch> +- * Copyright 2007, Broadcom Corporation ++ * Copyright 2007, 2011, Broadcom Corporation ++ * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ +@@ -12,12 +13,13 @@ + #include <linux/export.h> + #include <linux/bcma/bcma.h> + +-static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset) ++u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset) + { + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); + bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR); + return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA); + } ++EXPORT_SYMBOL_GPL(bcma_chipco_pll_read); + + void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value) + { +@@ -54,38 +56,19 @@ void bcma_chipco_regctl_maskset(struct b + } + EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset); + +-static void bcma_pmu_pll_init(struct bcma_drv_cc *cc) +-{ +- struct bcma_bus *bus = cc->core->bus; +- +- switch (bus->chipinfo.id) { +- case 0x4313: +- case 0x4331: +- case 43224: +- case 43225: +- break; +- default: +- pr_err("PLL init unknown for device 0x%04X\n", +- bus->chipinfo.id); +- } +-} +- + static void bcma_pmu_resources_init(struct bcma_drv_cc *cc) + { + struct bcma_bus *bus = cc->core->bus; + u32 min_msk = 0, max_msk = 0; + + switch (bus->chipinfo.id) { +- case 0x4313: ++ case BCMA_CHIP_ID_BCM4313: + min_msk = 0x200D; + max_msk = 0xFFFF; + break; +- case 43224: +- case 43225: +- break; + default: +- pr_err("PMU resource config unknown for device 0x%04X\n", +- bus->chipinfo.id); ++ bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n", ++ bus->chipinfo.id); + } + + /* Set the resource masks. */ +@@ -93,22 +76,12 @@ static void bcma_pmu_resources_init(stru + bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk); + if (max_msk) + bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk); +-} +- +-void bcma_pmu_swreg_init(struct bcma_drv_cc *cc) +-{ +- struct bcma_bus *bus = cc->core->bus; + +- switch (bus->chipinfo.id) { +- case 0x4313: +- case 0x4331: +- case 43224: +- case 43225: +- break; +- default: +- pr_err("PMU switch/regulators init unknown for device " +- "0x%04X\n", bus->chipinfo.id); +- } ++ /* ++ * Add some delay; allow resources to come up and settle. ++ * Delay is required for SoC (early init). ++ */ ++ mdelay(2); + } + + /* Disable to allow reading SPROM. Don't know the adventages of enabling it. */ +@@ -122,51 +95,69 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct + val |= BCMA_CHIPCTL_4331_EXTPA_EN; + if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11) + val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5; ++ else if (bus->chipinfo.rev > 0) ++ val |= BCMA_CHIPCTL_4331_EXTPA_EN2; + } else { + val &= ~BCMA_CHIPCTL_4331_EXTPA_EN; ++ val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2; + val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5; + } + bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val); + } + +-void bcma_pmu_workarounds(struct bcma_drv_cc *cc) ++static void bcma_pmu_workarounds(struct bcma_drv_cc *cc) + { + struct bcma_bus *bus = cc->core->bus; + + switch (bus->chipinfo.id) { +- case 0x4313: +- bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7); ++ case BCMA_CHIP_ID_BCM4313: ++ /* enable 12 mA drive strenth for 4313 and set chipControl ++ register bit 1 */ ++ bcma_chipco_chipctl_maskset(cc, 0, ++ ~BCMA_CCTRL_4313_12MA_LED_DRIVE, ++ BCMA_CCTRL_4313_12MA_LED_DRIVE); + break; +- case 0x4331: +- /* BCM4331 workaround is SPROM-related, we put it in sprom.c */ ++ case BCMA_CHIP_ID_BCM4331: ++ case BCMA_CHIP_ID_BCM43431: ++ /* Ext PA lines must be enabled for tx on BCM4331 */ ++ bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true); + break; +- case 43224: ++ case BCMA_CHIP_ID_BCM43224: ++ case BCMA_CHIP_ID_BCM43421: ++ /* enable 12 mA drive strenth for 43224 and set chipControl ++ register bit 15 */ + if (bus->chipinfo.rev == 0) { +- pr_err("Workarounds for 43224 rev 0 not fully " +- "implemented\n"); +- bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0); ++ bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL, ++ ~BCMA_CCTRL_43224_GPIO_TOGGLE, ++ BCMA_CCTRL_43224_GPIO_TOGGLE); ++ bcma_chipco_chipctl_maskset(cc, 0, ++ ~BCMA_CCTRL_43224A0_12MA_LED_DRIVE, ++ BCMA_CCTRL_43224A0_12MA_LED_DRIVE); + } else { +- bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0); ++ bcma_chipco_chipctl_maskset(cc, 0, ++ ~BCMA_CCTRL_43224B0_12MA_LED_DRIVE, ++ BCMA_CCTRL_43224B0_12MA_LED_DRIVE); + } + break; +- case 43225: +- break; + default: +- pr_err("Workarounds unknown for device 0x%04X\n", +- bus->chipinfo.id); ++ bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n", ++ bus->chipinfo.id); + } + } + +-void bcma_pmu_init(struct bcma_drv_cc *cc) ++void bcma_pmu_early_init(struct bcma_drv_cc *cc) + { + u32 pmucap; + + pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP); + cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION); + +- pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev, +- pmucap); ++ bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n", ++ cc->pmu.rev, pmucap); ++} + ++void bcma_pmu_init(struct bcma_drv_cc *cc) ++{ + if (cc->pmu.rev == 1) + bcma_cc_mask32(cc, BCMA_CC_PMU_CTL, + ~BCMA_CC_PMU_CTL_NOILPONW); +@@ -174,37 +165,31 @@ void bcma_pmu_init(struct bcma_drv_cc *c + bcma_cc_set32(cc, BCMA_CC_PMU_CTL, + BCMA_CC_PMU_CTL_NOILPONW); + +- if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2) +- pr_err("Fix for 4329b0 bad LPOM state not implemented!\n"); +- +- bcma_pmu_pll_init(cc); + bcma_pmu_resources_init(cc); +- bcma_pmu_swreg_init(cc); + bcma_pmu_workarounds(cc); + } + +-u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc) ++u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc) + { + struct bcma_bus *bus = cc->core->bus; + + switch (bus->chipinfo.id) { +- case 0x4716: +- case 0x4748: +- case 47162: +- case 0x4313: +- case 0x5357: +- case 0x4749: +- case 53572: ++ case BCMA_CHIP_ID_BCM4716: ++ case BCMA_CHIP_ID_BCM4748: ++ case BCMA_CHIP_ID_BCM47162: ++ case BCMA_CHIP_ID_BCM4313: ++ case BCMA_CHIP_ID_BCM5357: ++ case BCMA_CHIP_ID_BCM4749: ++ case BCMA_CHIP_ID_BCM53572: + /* always 20Mhz */ + return 20000 * 1000; +- case 0x5356: +- case 0x5300: ++ case BCMA_CHIP_ID_BCM5356: ++ case BCMA_CHIP_ID_BCM4706: + /* always 25Mhz */ + return 25000 * 1000; + default: +- pr_warn("No ALP clock specified for %04X device, " +- "pmu rev. %d, using default %d Hz\n", +- bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK); ++ bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n", ++ bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK); + } + return BCMA_CC_PMU_ALP_CLOCK; + } +@@ -212,7 +197,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c + /* Find the output of the "m" pll divider given pll controls that start with + * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc. + */ +-static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) ++static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) + { + u32 tmp, div, ndiv, p1, p2, fc; + struct bcma_bus *bus = cc->core->bus; +@@ -221,7 +206,8 @@ static u32 bcma_pmu_clock(struct bcma_dr + + BUG_ON(!m || m > 4); + +- if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) { ++ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 || ++ bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) { + /* Detect failure in clock setting */ + tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); + if (tmp & 0x40000) +@@ -240,60 +226,95 @@ static u32 bcma_pmu_clock(struct bcma_dr + ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT; + + /* Do calculation in Mhz */ +- fc = bcma_pmu_alp_clock(cc) / 1000000; ++ fc = bcma_pmu_get_alp_clock(cc) / 1000000; + fc = (p1 * ndiv * fc) / p2; + + /* Return clock in Hertz */ + return (fc / div) * 1000000; + } + ++static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m) ++{ ++ u32 tmp, ndiv, p1div, p2div; ++ u32 clock; ++ ++ BUG_ON(!m || m > 4); ++ ++ /* Get N, P1 and P2 dividers to determine CPU clock */ ++ tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF); ++ ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK) ++ >> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT; ++ p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK) ++ >> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT; ++ p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK) ++ >> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT; ++ ++ tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); ++ if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION) ++ /* Low cost bonding: Fixed reference clock 25MHz and m = 4 */ ++ clock = (25000000 / 4) * ndiv * p2div / p1div; ++ else ++ /* Fixed reference clock 25MHz and m = 2 */ ++ clock = (25000000 / 2) * ndiv * p2div / p1div; ++ ++ if (m == BCMA_CC_PMU5_MAINPLL_SSB) ++ clock = clock / 4; ++ ++ return clock; ++} ++ + /* query bus clock frequency for PMU-enabled chipcommon */ +-u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc) ++static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc) + { + struct bcma_bus *bus = cc->core->bus; + + switch (bus->chipinfo.id) { +- case 0x4716: +- case 0x4748: +- case 47162: +- return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0, +- BCMA_CC_PMU5_MAINPLL_SSB); +- case 0x5356: +- return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0, +- BCMA_CC_PMU5_MAINPLL_SSB); +- case 0x5357: +- case 0x4749: +- return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0, +- BCMA_CC_PMU5_MAINPLL_SSB); +- case 0x5300: +- return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0, +- BCMA_CC_PMU5_MAINPLL_SSB); +- case 53572: ++ case BCMA_CHIP_ID_BCM4716: ++ case BCMA_CHIP_ID_BCM4748: ++ case BCMA_CHIP_ID_BCM47162: ++ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0, ++ BCMA_CC_PMU5_MAINPLL_SSB); ++ case BCMA_CHIP_ID_BCM5356: ++ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0, ++ BCMA_CC_PMU5_MAINPLL_SSB); ++ case BCMA_CHIP_ID_BCM5357: ++ case BCMA_CHIP_ID_BCM4749: ++ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0, ++ BCMA_CC_PMU5_MAINPLL_SSB); ++ case BCMA_CHIP_ID_BCM4706: ++ return bcma_pmu_pll_clock_bcm4706(cc, ++ BCMA_CC_PMU4706_MAINPLL_PLL0, ++ BCMA_CC_PMU5_MAINPLL_SSB); ++ case BCMA_CHIP_ID_BCM53572: + return 75000000; + default: +- pr_warn("No backplane clock specified for %04X device, " +- "pmu rev. %d, using default %d Hz\n", +- bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK); ++ bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n", ++ bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK); + } + return BCMA_CC_PMU_HT_CLOCK; + } + + /* query cpu clock frequency for PMU-enabled chipcommon */ +-u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc) ++u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc) + { + struct bcma_bus *bus = cc->core->bus; + +- if (bus->chipinfo.id == 53572) ++ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) + return 300000000; + ++ /* New PMUs can have different clock for bus and CPU */ + if (cc->pmu.rev >= 5) { + u32 pll; + switch (bus->chipinfo.id) { +- case 0x5356: ++ case BCMA_CHIP_ID_BCM4706: ++ return bcma_pmu_pll_clock_bcm4706(cc, ++ BCMA_CC_PMU4706_MAINPLL_PLL0, ++ BCMA_CC_PMU5_MAINPLL_CPU); ++ case BCMA_CHIP_ID_BCM5356: + pll = BCMA_CC_PMU5356_MAINPLL_PLL0; + break; +- case 0x5357: +- case 0x4749: ++ case BCMA_CHIP_ID_BCM5357: ++ case BCMA_CHIP_ID_BCM4749: + pll = BCMA_CC_PMU5357_MAINPLL_PLL0; + break; + default: +@@ -301,10 +322,189 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr + break; + } + +- /* TODO: if (bus->chipinfo.id == 0x5300) +- return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */ +- return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU); ++ return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU); ++ } ++ ++ /* On old PMUs CPU has the same clock as the bus */ ++ return bcma_pmu_get_bus_clock(cc); ++} ++ ++static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset, ++ u32 value) ++{ ++ bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); ++ bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value); ++} ++ ++void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid) ++{ ++ u32 tmp = 0; ++ u8 phypll_offset = 0; ++ u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5}; ++ u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc}; ++ struct bcma_bus *bus = cc->core->bus; ++ ++ switch (bus->chipinfo.id) { ++ case BCMA_CHIP_ID_BCM5357: ++ case BCMA_CHIP_ID_BCM4749: ++ case BCMA_CHIP_ID_BCM53572: ++ /* 5357[ab]0, 43236[ab]0, and 6362b0 */ ++ ++ /* BCM5357 needs to touch PLL1_PLLCTL[02], ++ so offset PLL0_PLLCTL[02] by 6 */ ++ phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 || ++ bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 || ++ bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0; ++ ++ /* RMW only the P1 divider */ ++ bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, ++ BCMA_CC_PMU_PLL_CTL0 + phypll_offset); ++ tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA); ++ tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK)); ++ tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT); ++ bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); ++ ++ /* RMW only the int feedback divider */ ++ bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, ++ BCMA_CC_PMU_PLL_CTL2 + phypll_offset); ++ tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA); ++ tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK); ++ tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT; ++ bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); ++ ++ tmp = 1 << 10; ++ break; ++ ++ case BCMA_CHIP_ID_BCM4331: ++ case BCMA_CHIP_ID_BCM43431: ++ if (spuravoid == 2) { ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, ++ 0x11500014); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, ++ 0x0FC00a08); ++ } else if (spuravoid == 1) { ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, ++ 0x11500014); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, ++ 0x0F600a08); ++ } else { ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, ++ 0x11100014); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, ++ 0x03000a08); ++ } ++ tmp = 1 << 10; ++ break; ++ ++ case BCMA_CHIP_ID_BCM43224: ++ case BCMA_CHIP_ID_BCM43225: ++ case BCMA_CHIP_ID_BCM43421: ++ if (spuravoid == 1) { ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, ++ 0x11500010); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1, ++ 0x000C0C06); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, ++ 0x0F600a08); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3, ++ 0x00000000); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4, ++ 0x2001E920); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, ++ 0x88888815); ++ } else { ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, ++ 0x11100010); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1, ++ 0x000c0c06); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, ++ 0x03000a08); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3, ++ 0x00000000); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4, ++ 0x200005c0); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, ++ 0x88888815); ++ } ++ tmp = 1 << 10; ++ break; ++ ++ case BCMA_CHIP_ID_BCM4716: ++ case BCMA_CHIP_ID_BCM4748: ++ case BCMA_CHIP_ID_BCM47162: ++ if (spuravoid == 1) { ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, ++ 0x11500060); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1, ++ 0x080C0C06); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, ++ 0x0F600000); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3, ++ 0x00000000); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4, ++ 0x2001E924); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, ++ 0x88888815); ++ } else { ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, ++ 0x11100060); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1, ++ 0x080c0c06); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, ++ 0x03000000); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3, ++ 0x00000000); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4, ++ 0x200005c0); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, ++ 0x88888815); ++ } ++ ++ tmp = 3 << 9; ++ break; ++ ++ case BCMA_CHIP_ID_BCM43227: ++ case BCMA_CHIP_ID_BCM43228: ++ case BCMA_CHIP_ID_BCM43428: ++ /* LCNXN */ ++ /* PLL Settings for spur avoidance on/off mode, ++ no on2 support for 43228A0 */ ++ if (spuravoid == 1) { ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, ++ 0x01100014); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1, ++ 0x040C0C06); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, ++ 0x03140A08); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3, ++ 0x00333333); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4, ++ 0x202C2820); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, ++ 0x88888815); ++ } else { ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, ++ 0x11100014); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1, ++ 0x040c0c06); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, ++ 0x03000a08); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3, ++ 0x00000000); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4, ++ 0x200005c0); ++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, ++ 0x88888815); ++ } ++ tmp = 1 << 10; ++ break; ++ default: ++ bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", ++ bus->chipinfo.id); ++ break; + } + +- return bcma_pmu_get_clockcontrol(cc); ++ tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL); ++ bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp); + } ++EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate); +--- /dev/null ++++ b/drivers/bcma/driver_chipcommon_sflash.c +@@ -0,0 +1,165 @@ ++/* ++ * Broadcom specific AMBA ++ * ChipCommon serial flash interface ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++#include <linux/platform_device.h> ++#include <linux/bcma/bcma.h> ++ ++#include "bcma_private.h" ++ ++static struct resource bcma_sflash_resource = { ++ .name = "bcma_sflash", ++ .start = BCMA_SOC_FLASH2, ++ .end = 0, ++ .flags = IORESOURCE_MEM | IORESOURCE_READONLY, ++}; ++ ++struct platform_device bcma_sflash_dev = { ++ .name = "bcma_sflash", ++ .resource = &bcma_sflash_resource, ++ .num_resources = 1, ++}; ++ ++struct bcma_sflash_tbl_e { ++ char *name; ++ u32 id; ++ u32 blocksize; ++ u16 numblocks; ++}; ++ ++static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = { ++ { "M25P20", 0x11, 0x10000, 4, }, ++ { "M25P40", 0x12, 0x10000, 8, }, ++ ++ { "M25P16", 0x14, 0x10000, 32, }, ++ { "M25P32", 0x15, 0x10000, 64, }, ++ { "M25P64", 0x16, 0x10000, 128, }, ++ { "M25FL128", 0x17, 0x10000, 256, }, ++ { 0 }, ++}; ++ ++static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = { ++ { "SST25WF512", 1, 0x1000, 16, }, ++ { "SST25VF512", 0x48, 0x1000, 16, }, ++ { "SST25WF010", 2, 0x1000, 32, }, ++ { "SST25VF010", 0x49, 0x1000, 32, }, ++ { "SST25WF020", 3, 0x1000, 64, }, ++ { "SST25VF020", 0x43, 0x1000, 64, }, ++ { "SST25WF040", 4, 0x1000, 128, }, ++ { "SST25VF040", 0x44, 0x1000, 128, }, ++ { "SST25VF040B", 0x8d, 0x1000, 128, }, ++ { "SST25WF080", 5, 0x1000, 256, }, ++ { "SST25VF080B", 0x8e, 0x1000, 256, }, ++ { "SST25VF016", 0x41, 0x1000, 512, }, ++ { "SST25VF032", 0x4a, 0x1000, 1024, }, ++ { "SST25VF064", 0x4b, 0x1000, 2048, }, ++ { 0 }, ++}; ++ ++static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = { ++ { "AT45DB011", 0xc, 256, 512, }, ++ { "AT45DB021", 0x14, 256, 1024, }, ++ { "AT45DB041", 0x1c, 256, 2048, }, ++ { "AT45DB081", 0x24, 256, 4096, }, ++ { "AT45DB161", 0x2c, 512, 4096, }, ++ { "AT45DB321", 0x34, 512, 8192, }, ++ { "AT45DB642", 0x3c, 1024, 8192, }, ++ { 0 }, ++}; ++ ++static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode) ++{ ++ int i; ++ bcma_cc_write32(cc, BCMA_CC_FLASHCTL, ++ BCMA_CC_FLASHCTL_START | opcode); ++ for (i = 0; i < 1000; i++) { ++ if (!(bcma_cc_read32(cc, BCMA_CC_FLASHCTL) & ++ BCMA_CC_FLASHCTL_BUSY)) ++ return; ++ cpu_relax(); ++ } ++ bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n"); ++} ++ ++/* Initialize serial flash access */ ++int bcma_sflash_init(struct bcma_drv_cc *cc) ++{ ++ struct bcma_bus *bus = cc->core->bus; ++ struct bcma_sflash *sflash = &cc->sflash; ++ struct bcma_sflash_tbl_e *e; ++ u32 id, id2; ++ ++ switch (cc->capabilities & BCMA_CC_CAP_FLASHT) { ++ case BCMA_CC_FLASHT_STSER: ++ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_DP); ++ ++ bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 0); ++ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES); ++ id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA); ++ ++ bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 1); ++ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES); ++ id2 = bcma_cc_read32(cc, BCMA_CC_FLASHDATA); ++ ++ switch (id) { ++ case 0xbf: ++ for (e = bcma_sflash_sst_tbl; e->name; e++) { ++ if (e->id == id2) ++ break; ++ } ++ break; ++ case 0x13: ++ return -ENOTSUPP; ++ default: ++ for (e = bcma_sflash_st_tbl; e->name; e++) { ++ if (e->id == id) ++ break; ++ } ++ break; ++ } ++ if (!e->name) { ++ bcma_err(bus, "Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n", id, id2); ++ return -ENOTSUPP; ++ } ++ ++ break; ++ case BCMA_CC_FLASHT_ATSER: ++ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_STATUS); ++ id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA) & 0x3c; ++ ++ for (e = bcma_sflash_at_tbl; e->name; e++) { ++ if (e->id == id) ++ break; ++ } ++ if (!e->name) { ++ bcma_err(bus, "Unsupported Atmel serial flash (id: 0x%X)\n", id); ++ return -ENOTSUPP; ++ } ++ ++ break; ++ default: ++ bcma_err(bus, "Unsupported flash type\n"); ++ return -ENOTSUPP; ++ } ++ ++ sflash->window = BCMA_SOC_FLASH2; ++ sflash->blocksize = e->blocksize; ++ sflash->numblocks = e->numblocks; ++ sflash->size = sflash->blocksize * sflash->numblocks; ++ sflash->present = true; ++ ++ bcma_info(bus, "Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n", ++ e->name, sflash->size / 1024, sflash->blocksize, ++ sflash->numblocks); ++ ++ /* Prepare platform device, but don't register it yet. It's too early, ++ * malloc (required by device_private_init) is not available yet. */ ++ bcma_sflash_dev.resource[0].end = bcma_sflash_dev.resource[0].start + ++ sflash->size; ++ bcma_sflash_dev.dev.platform_data = sflash; ++ ++ return 0; ++} +--- /dev/null ++++ b/drivers/bcma/driver_gmac_cmn.c +@@ -0,0 +1,14 @@ ++/* ++ * Broadcom specific AMBA ++ * GBIT MAC COMMON Core ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++#include "bcma_private.h" ++#include <linux/bcma/bcma.h> ++ ++void __devinit bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc) ++{ ++ mutex_init(&gc->phy_mutex); ++} +--- /dev/null ++++ b/drivers/bcma/driver_gpio.c +@@ -0,0 +1,98 @@ ++/* ++ * Broadcom specific AMBA ++ * GPIO driver ++ * ++ * Copyright 2011, Broadcom Corporation ++ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de> ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++#include <linux/gpio.h> ++#include <linux/export.h> ++#include <linux/bcma/bcma.h> ++ ++#include "bcma_private.h" ++ ++static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip) ++{ ++ return container_of(chip, struct bcma_drv_cc, gpio); ++} ++ ++static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ return !!bcma_chipco_gpio_in(cc, 1 << gpio); ++} ++ ++static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio, ++ int value) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0); ++} ++ ++static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ bcma_chipco_gpio_outen(cc, 1 << gpio, 0); ++ return 0; ++} ++ ++static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, ++ int value) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio); ++ bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0); ++ return 0; ++} ++ ++static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ bcma_chipco_gpio_control(cc, 1 << gpio, 0); ++ /* clear pulldown */ ++ bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0); ++ /* Set pullup */ ++ bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio); ++ ++ return 0; ++} ++ ++static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ /* clear pullup */ ++ bcma_chipco_gpio_pullup(cc, 1 << gpio, 0); ++} ++ ++int bcma_gpio_init(struct bcma_drv_cc *cc) ++{ ++ struct gpio_chip *chip = &cc->gpio; ++ ++ chip->label = "bcma_gpio"; ++ chip->owner = THIS_MODULE; ++ chip->request = bcma_gpio_request; ++ chip->free = bcma_gpio_free; ++ chip->get = bcma_gpio_get_value; ++ chip->set = bcma_gpio_set_value; ++ chip->direction_input = bcma_gpio_direction_input; ++ chip->direction_output = bcma_gpio_direction_output; ++ chip->ngpio = 16; ++ /* There is just one SoC in one device and its GPIO addresses should be ++ * deterministic to address them more easily. The other buses could get ++ * a random base number. */ ++ if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC) ++ chip->base = 0; ++ else ++ chip->base = -1; ++ ++ return gpiochip_add(chip); ++} +--- a/drivers/bcma/driver_mips.c ++++ b/drivers/bcma/driver_mips.c +@@ -22,15 +22,15 @@ + /* The 47162a0 hangs when reading MIPS DMP registers registers */ + static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev) + { +- return dev->bus->chipinfo.id == 47162 && dev->bus->chipinfo.rev == 0 && +- dev->id.id == BCMA_CORE_MIPS_74K; ++ return dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM47162 && ++ dev->bus->chipinfo.rev == 0 && dev->id.id == BCMA_CORE_MIPS_74K; + } + + /* The 5357b0 hangs when reading USB20H DMP registers */ + static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev) + { +- return (dev->bus->chipinfo.id == 0x5357 || +- dev->bus->chipinfo.id == 0x4749) && ++ return (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 || ++ dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) && + dev->bus->chipinfo.pkg == 11 && + dev->id.id == BCMA_CORE_USB20_HOST; + } +@@ -74,11 +74,16 @@ static u32 bcma_core_mips_irqflag(struct + return dev->core_index; + flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30); + +- return flag & 0x1F; ++ if (flag) ++ return flag & 0x1F; ++ else ++ return 0x3f; + } + + /* Get the MIPS IRQ assignment for a specified device. + * If unassigned, 0 is returned. ++ * If disabled, 5 is returned. ++ * If not supported, 6 is returned. + */ + unsigned int bcma_core_mips_irq(struct bcma_device *dev) + { +@@ -87,13 +92,15 @@ unsigned int bcma_core_mips_irq(struct b + unsigned int irq; + + irqflag = bcma_core_mips_irqflag(dev); ++ if (irqflag == 0x3f) ++ return 6; + +- for (irq = 1; irq <= 4; irq++) ++ for (irq = 0; irq <= 4; irq++) + if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) & + (1 << irqflag)) + return irq; + +- return 0; ++ return 5; + } + EXPORT_SYMBOL(bcma_core_mips_irq); + +@@ -114,8 +121,8 @@ static void bcma_core_mips_set_irq(struc + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0), + bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) & + ~(1 << irqflag)); +- else +- bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0); ++ else if (oldirq != 5) ++ bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0); + + /* assign the new one */ + if (irq == 0) { +@@ -123,17 +130,17 @@ static void bcma_core_mips_set_irq(struc + bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) | + (1 << irqflag)); + } else { +- u32 oldirqflag = bcma_read32(mdev, +- BCMA_MIPS_MIPS74K_INTMASK(irq)); +- if (oldirqflag) { ++ u32 irqinitmask = bcma_read32(mdev, ++ BCMA_MIPS_MIPS74K_INTMASK(irq)); ++ if (irqinitmask) { + struct bcma_device *core; + + /* backplane irq line is in use, find out who uses + * it and set user to irq 0 + */ +- list_for_each_entry_reverse(core, &bus->cores, list) { ++ list_for_each_entry(core, &bus->cores, list) { + if ((1 << bcma_core_mips_irqflag(core)) == +- oldirqflag) { ++ irqinitmask) { + bcma_core_mips_set_irq(core, 0); + break; + } +@@ -143,15 +150,31 @@ static void bcma_core_mips_set_irq(struc + 1 << irqflag); + } + +- pr_info("set_irq: core 0x%04x, irq %d => %d\n", +- dev->id.id, oldirq + 2, irq + 2); ++ bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n", ++ dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2); ++} ++ ++static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq, ++ u16 coreid, u8 unit) ++{ ++ struct bcma_device *core; ++ ++ core = bcma_find_core_unit(bus, coreid, unit); ++ if (!core) { ++ bcma_warn(bus, ++ "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n", ++ coreid, unit); ++ return; ++ } ++ ++ bcma_core_mips_set_irq(core, irq); + } + + static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq) + { + int i; + static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"}; +- printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id); ++ printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id); + for (i = 0; i <= 6; i++) + printk(" %s%s", irq_name[i], i == irq ? "*" : " "); + printk("\n"); +@@ -161,7 +184,7 @@ static void bcma_core_mips_dump_irq(stru + { + struct bcma_device *core; + +- list_for_each_entry_reverse(core, &bus->cores, list) { ++ list_for_each_entry(core, &bus->cores, list) { + bcma_core_mips_print_irq(core, bcma_core_mips_irq(core)); + } + } +@@ -171,9 +194,9 @@ u32 bcma_cpu_clock(struct bcma_drv_mips + struct bcma_bus *bus = mcore->core->bus; + + if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU) +- return bcma_pmu_get_clockcpu(&bus->drv_cc); ++ return bcma_pmu_get_cpu_clock(&bus->drv_cc); + +- pr_err("No PMU available, need this to get the cpu clock\n"); ++ bcma_err(bus, "No PMU available, need this to get the cpu clock\n"); + return 0; + } + EXPORT_SYMBOL(bcma_cpu_clock); +@@ -181,76 +204,109 @@ EXPORT_SYMBOL(bcma_cpu_clock); + static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore) + { + struct bcma_bus *bus = mcore->core->bus; ++ struct bcma_drv_cc *cc = &bus->drv_cc; + +- switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) { ++ switch (cc->capabilities & BCMA_CC_CAP_FLASHT) { + case BCMA_CC_FLASHT_STSER: + case BCMA_CC_FLASHT_ATSER: +- pr_err("Serial flash not supported.\n"); ++ bcma_debug(bus, "Found serial flash\n"); ++ bcma_sflash_init(cc); + break; + case BCMA_CC_FLASHT_PARA: +- pr_info("found parallel flash.\n"); +- bus->drv_cc.pflash.window = 0x1c000000; +- bus->drv_cc.pflash.window_size = 0x02000000; ++ bcma_debug(bus, "Found parallel flash\n"); ++ cc->pflash.present = true; ++ cc->pflash.window = BCMA_SOC_FLASH2; ++ cc->pflash.window_size = BCMA_SOC_FLASH2_SZ; + +- if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) & ++ if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) & + BCMA_CC_FLASH_CFG_DS) == 0) +- bus->drv_cc.pflash.buswidth = 1; ++ cc->pflash.buswidth = 1; + else +- bus->drv_cc.pflash.buswidth = 2; ++ cc->pflash.buswidth = 2; + break; + default: +- pr_err("flash not supported.\n"); ++ bcma_err(bus, "Flash type not supported\n"); ++ } ++ ++ if (cc->core->id.rev == 38 || ++ bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) { ++ if (cc->capabilities & BCMA_CC_CAP_NFLASH) { ++ bcma_debug(bus, "Found NAND flash\n"); ++ bcma_nflash_init(cc); ++ } + } + } + ++void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) ++{ ++ struct bcma_bus *bus = mcore->core->bus; ++ ++ if (mcore->early_setup_done) ++ return; ++ ++ bcma_chipco_serial_init(&bus->drv_cc); ++ bcma_core_mips_flash_detect(mcore); ++ ++ mcore->early_setup_done = true; ++} ++ + void bcma_core_mips_init(struct bcma_drv_mips *mcore) + { + struct bcma_bus *bus; + struct bcma_device *core; + bus = mcore->core->bus; + +- pr_info("Initializing MIPS core...\n"); ++ if (mcore->setup_done) ++ return; ++ ++ bcma_debug(bus, "Initializing MIPS core...\n"); + +- if (!mcore->setup_done) +- mcore->assigned_irqs = 1; ++ bcma_core_mips_early_init(mcore); + +- /* Assign IRQs to all cores on the bus */ +- list_for_each_entry_reverse(core, &bus->cores, list) { +- int mips_irq; +- if (core->irq) +- continue; +- +- mips_irq = bcma_core_mips_irq(core); +- if (mips_irq > 4) +- core->irq = 0; +- else +- core->irq = mips_irq + 2; +- if (core->irq > 5) +- continue; +- switch (core->id.id) { +- case BCMA_CORE_PCI: +- case BCMA_CORE_PCIE: +- case BCMA_CORE_ETHERNET: +- case BCMA_CORE_ETHERNET_GBIT: +- case BCMA_CORE_MAC_GBIT: +- case BCMA_CORE_80211: +- case BCMA_CORE_USB20_HOST: +- /* These devices get their own IRQ line if available, +- * the rest goes on IRQ0 +- */ +- if (mcore->assigned_irqs <= 4) +- bcma_core_mips_set_irq(core, +- mcore->assigned_irqs++); +- break; ++ switch (bus->chipinfo.id) { ++ case BCMA_CHIP_ID_BCM4716: ++ case BCMA_CHIP_ID_BCM4748: ++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); ++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); ++ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0); ++ bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0); ++ break; ++ case BCMA_CHIP_ID_BCM5356: ++ case BCMA_CHIP_ID_BCM47162: ++ case BCMA_CHIP_ID_BCM53572: ++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); ++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); ++ break; ++ case BCMA_CHIP_ID_BCM5357: ++ case BCMA_CHIP_ID_BCM4749: ++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); ++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); ++ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0); ++ break; ++ case BCMA_CHIP_ID_BCM4706: ++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0); ++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT, ++ 0); ++ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1); ++ bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON, ++ 0); ++ break; ++ default: ++ list_for_each_entry(core, &bus->cores, list) { ++ core->irq = bcma_core_mips_irq(core) + 2; + } ++ bcma_err(bus, ++ "Unknown device (0x%x) found, can not configure IRQs\n", ++ bus->chipinfo.id); + } +- pr_info("IRQ reconfiguration done\n"); ++ bcma_debug(bus, "IRQ reconfiguration done\n"); + bcma_core_mips_dump_irq(bus); + +- if (mcore->setup_done) +- return; +- +- bcma_chipco_serial_init(&bus->drv_cc); +- bcma_core_mips_flash_detect(mcore); + mcore->setup_done = true; + } +--- a/drivers/bcma/driver_pci.c ++++ b/drivers/bcma/driver_pci.c +@@ -2,8 +2,9 @@ + * Broadcom specific AMBA + * PCI Core + * +- * Copyright 2005, Broadcom Corporation ++ * Copyright 2005, 2011, Broadcom Corporation + * Copyright 2006, 2007, Michael Buesch <m@bues.ch> ++ * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ +@@ -16,120 +17,124 @@ + * R/W ops. + **************************************************/ + +-static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address) ++u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address) + { +- pcicore_write32(pc, 0x130, address); +- pcicore_read32(pc, 0x130); +- return pcicore_read32(pc, 0x134); ++ pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address); ++ pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR); ++ return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA); + } + +-#if 0 + static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data) + { +- pcicore_write32(pc, 0x130, address); +- pcicore_read32(pc, 0x130); +- pcicore_write32(pc, 0x134, data); ++ pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address); ++ pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR); ++ pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data); + } +-#endif + + static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy) + { +- const u16 mdio_control = 0x128; +- const u16 mdio_data = 0x12C; + u32 v; + int i; + +- v = (1 << 30); /* Start of Transaction */ +- v |= (1 << 28); /* Write Transaction */ +- v |= (1 << 17); /* Turnaround */ +- v |= (0x1F << 18); ++ v = BCMA_CORE_PCI_MDIODATA_START; ++ v |= BCMA_CORE_PCI_MDIODATA_WRITE; ++ v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR << ++ BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF); ++ v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR << ++ BCMA_CORE_PCI_MDIODATA_REGADDR_SHF); ++ v |= BCMA_CORE_PCI_MDIODATA_TA; + v |= (phy << 4); +- pcicore_write32(pc, mdio_data, v); ++ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v); + + udelay(10); + for (i = 0; i < 200; i++) { +- v = pcicore_read32(pc, mdio_control); +- if (v & 0x100 /* Trans complete */) ++ v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); ++ if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) + break; +- msleep(1); ++ usleep_range(1000, 2000); + } + } + + static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address) + { +- const u16 mdio_control = 0x128; +- const u16 mdio_data = 0x12C; + int max_retries = 10; + u16 ret = 0; + u32 v; + int i; + +- v = 0x80; /* Enable Preamble Sequence */ +- v |= 0x2; /* MDIO Clock Divisor */ +- pcicore_write32(pc, mdio_control, v); ++ /* enable mdio access to SERDES */ ++ v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN; ++ v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL; ++ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v); + + if (pc->core->id.rev >= 10) { + max_retries = 200; + bcma_pcie_mdio_set_phy(pc, device); ++ v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR << ++ BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF); ++ v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF); ++ } else { ++ v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD); ++ v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD); + } + +- v = (1 << 30); /* Start of Transaction */ +- v |= (1 << 29); /* Read Transaction */ +- v |= (1 << 17); /* Turnaround */ +- if (pc->core->id.rev < 10) +- v |= (u32)device << 22; +- v |= (u32)address << 18; +- pcicore_write32(pc, mdio_data, v); ++ v = BCMA_CORE_PCI_MDIODATA_START; ++ v |= BCMA_CORE_PCI_MDIODATA_READ; ++ v |= BCMA_CORE_PCI_MDIODATA_TA; ++ ++ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v); + /* Wait for the device to complete the transaction */ + udelay(10); + for (i = 0; i < max_retries; i++) { +- v = pcicore_read32(pc, mdio_control); +- if (v & 0x100 /* Trans complete */) { ++ v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); ++ if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) { + udelay(10); +- ret = pcicore_read32(pc, mdio_data); ++ ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA); + break; + } +- msleep(1); ++ usleep_range(1000, 2000); + } +- pcicore_write32(pc, mdio_control, 0); ++ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0); + return ret; + } + + static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device, + u8 address, u16 data) + { +- const u16 mdio_control = 0x128; +- const u16 mdio_data = 0x12C; + int max_retries = 10; + u32 v; + int i; + +- v = 0x80; /* Enable Preamble Sequence */ +- v |= 0x2; /* MDIO Clock Divisor */ +- pcicore_write32(pc, mdio_control, v); ++ /* enable mdio access to SERDES */ ++ v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN; ++ v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL; ++ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v); + + if (pc->core->id.rev >= 10) { + max_retries = 200; + bcma_pcie_mdio_set_phy(pc, device); ++ v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR << ++ BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF); ++ v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF); ++ } else { ++ v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD); ++ v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD); + } + +- v = (1 << 30); /* Start of Transaction */ +- v |= (1 << 28); /* Write Transaction */ +- v |= (1 << 17); /* Turnaround */ +- if (pc->core->id.rev < 10) +- v |= (u32)device << 22; +- v |= (u32)address << 18; ++ v = BCMA_CORE_PCI_MDIODATA_START; ++ v |= BCMA_CORE_PCI_MDIODATA_WRITE; ++ v |= BCMA_CORE_PCI_MDIODATA_TA; + v |= data; +- pcicore_write32(pc, mdio_data, v); ++ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v); + /* Wait for the device to complete the transaction */ + udelay(10); + for (i = 0; i < max_retries; i++) { +- v = pcicore_read32(pc, mdio_control); +- if (v & 0x100 /* Trans complete */) ++ v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); ++ if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) + break; +- msleep(1); ++ usleep_range(1000, 2000); + } +- pcicore_write32(pc, mdio_control, 0); ++ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0); + } + + /************************************************** +@@ -138,88 +143,108 @@ static void bcma_pcie_mdio_write(struct + + static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc) + { +- return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80; ++ u32 tmp; ++ ++ tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG); ++ if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT) ++ return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE | ++ BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY; ++ else ++ return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE; + } + + static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc) + { +- const u8 serdes_pll_device = 0x1D; +- const u8 serdes_rx_device = 0x1F; + u16 tmp; + +- bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */, +- bcma_pcicore_polarity_workaround(pc)); +- tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */); +- if (tmp & 0x4000) +- bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000); ++ bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX, ++ BCMA_CORE_PCI_SERDES_RX_CTRL, ++ bcma_pcicore_polarity_workaround(pc)); ++ tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL, ++ BCMA_CORE_PCI_SERDES_PLL_CTRL); ++ if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN) ++ bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL, ++ BCMA_CORE_PCI_SERDES_PLL_CTRL, ++ tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN); ++} ++ ++static void bcma_core_pci_fixcfg(struct bcma_drv_pci *pc) ++{ ++ struct bcma_device *core = pc->core; ++ u16 val16, core_index; ++ uint regoff; ++ ++ regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_PI_OFFSET); ++ core_index = (u16)core->core_index; ++ ++ val16 = pcicore_read16(pc, regoff); ++ if (((val16 & BCMA_CORE_PCI_SPROM_PI_MASK) >> BCMA_CORE_PCI_SPROM_PI_SHIFT) ++ != core_index) { ++ val16 = (core_index << BCMA_CORE_PCI_SPROM_PI_SHIFT) | ++ (val16 & ~BCMA_CORE_PCI_SPROM_PI_MASK); ++ pcicore_write16(pc, regoff, val16); ++ } ++} ++ ++/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */ ++/* Needs to happen when coming out of 'standby'/'hibernate' */ ++static void bcma_core_pci_config_fixup(struct bcma_drv_pci *pc) ++{ ++ u16 val16; ++ uint regoff; ++ ++ regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_MISC_CONFIG); ++ ++ val16 = pcicore_read16(pc, regoff); ++ ++ if (!(val16 & BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST)) { ++ val16 |= BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST; ++ pcicore_write16(pc, regoff, val16); ++ } + } + + /************************************************** + * Init. + **************************************************/ + +-static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc) ++static void __devinit bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc) + { ++ bcma_core_pci_fixcfg(pc); + bcma_pcicore_serdes_workaround(pc); ++ bcma_core_pci_config_fixup(pc); + } + +-static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc) +-{ +- struct bcma_bus *bus = pc->core->bus; +- u16 chipid_top; +- +- chipid_top = (bus->chipinfo.id & 0xFF00); +- if (chipid_top != 0x4700 && +- chipid_top != 0x5300) +- return false; +- +-#ifdef CONFIG_SSB_DRIVER_PCICORE +- if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI) +- return false; +-#endif /* CONFIG_SSB_DRIVER_PCICORE */ +- +-#if 0 +- /* TODO: on BCMA we use address from EROM instead of magic formula */ +- u32 tmp; +- return !mips_busprobe32(tmp, (bus->mmio + +- (pc->core->core_index * BCMA_CORE_SIZE))); +-#endif +- +- return true; +-} +- +-void bcma_core_pci_init(struct bcma_drv_pci *pc) ++void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc) + { + if (pc->setup_done) + return; + +- if (bcma_core_pci_is_in_hostmode(pc)) { + #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE ++ pc->hostmode = bcma_core_pci_is_in_hostmode(pc); ++ if (pc->hostmode) + bcma_core_pci_hostmode_init(pc); +-#else +- pr_err("Driver compiled without support for hostmode PCI\n"); + #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ +- } else { +- bcma_core_pci_clientmode_init(pc); +- } + +- pc->setup_done = true; ++ if (!pc->hostmode) ++ bcma_core_pci_clientmode_init(pc); + } + + int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core, + bool enable) + { +- struct pci_dev *pdev = pc->core->bus->host_pci; ++ struct pci_dev *pdev; + u32 coremask, tmp; + int err = 0; + +- if (core->bus->hosttype != BCMA_HOSTTYPE_PCI) { ++ if (!pc || core->bus->hosttype != BCMA_HOSTTYPE_PCI) { + /* This bcma device is not on a PCI host-bus. So the IRQs are + * not routed through the PCI core. + * So we must not enable routing through the PCI core. */ + goto out; + } + ++ pdev = pc->core->bus->host_pci; ++ + err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp); + if (err) + goto out; +@@ -236,3 +261,17 @@ out: + return err; + } + EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl); ++ ++void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend) ++{ ++ u32 w; ++ ++ w = bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG); ++ if (extend) ++ w |= BCMA_CORE_PCI_ASPMTIMER_EXTEND; ++ else ++ w &= ~BCMA_CORE_PCI_ASPMTIMER_EXTEND; ++ bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w); ++ bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG); ++} ++EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer); +--- a/drivers/bcma/driver_pci_host.c ++++ b/drivers/bcma/driver_pci_host.c +@@ -2,13 +2,600 @@ + * Broadcom specific AMBA + * PCI Core in hostmode + * ++ * Copyright 2005 - 2011, Broadcom Corporation ++ * Copyright 2006, 2007, Michael Buesch <m@bues.ch> ++ * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de> ++ * + * Licensed under the GNU/GPL. See COPYING for details. + */ + + #include "bcma_private.h" ++#include <linux/pci.h> ++#include <linux/export.h> + #include <linux/bcma/bcma.h> ++#include <asm/paccess.h> ++ ++/* Probe a 32bit value on the bus and catch bus exceptions. ++ * Returns nonzero on a bus exception. ++ * This is MIPS specific */ ++#define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr))) ++ ++/* Assume one-hot slot wiring */ ++#define BCMA_PCI_SLOT_MAX 16 ++#define PCI_CONFIG_SPACE_SIZE 256 ++ ++bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc) ++{ ++ struct bcma_bus *bus = pc->core->bus; ++ u16 chipid_top; ++ u32 tmp; ++ ++ chipid_top = (bus->chipinfo.id & 0xFF00); ++ if (chipid_top != 0x4700 && ++ chipid_top != 0x5300) ++ return false; ++ ++ bcma_core_enable(pc->core, 0); ++ ++ return !mips_busprobe32(tmp, pc->core->io_addr); ++} ++ ++static u32 bcma_pcie_read_config(struct bcma_drv_pci *pc, u32 address) ++{ ++ pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address); ++ pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR); ++ return pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_DATA); ++} ++ ++static void bcma_pcie_write_config(struct bcma_drv_pci *pc, u32 address, ++ u32 data) ++{ ++ pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address); ++ pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR); ++ pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_DATA, data); ++} ++ ++static u32 bcma_get_cfgspace_addr(struct bcma_drv_pci *pc, unsigned int dev, ++ unsigned int func, unsigned int off) ++{ ++ u32 addr = 0; ++ ++ /* Issue config commands only when the data link is up (atleast ++ * one external pcie device is present). ++ */ ++ if (dev >= 2 || !(bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_LSREG) ++ & BCMA_CORE_PCI_DLLP_LSREG_LINKUP)) ++ goto out; ++ ++ /* Type 0 transaction */ ++ /* Slide the PCI window to the appropriate slot */ ++ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0); ++ /* Calculate the address */ ++ addr = pc->host_controller->host_cfg_addr; ++ addr |= (dev << BCMA_CORE_PCI_CFG_SLOT_SHIFT); ++ addr |= (func << BCMA_CORE_PCI_CFG_FUN_SHIFT); ++ addr |= (off & ~3); ++ ++out: ++ return addr; ++} + +-void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc) ++static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev, ++ unsigned int func, unsigned int off, ++ void *buf, int len) + { +- pr_err("No support for PCI core in hostmode yet\n"); ++ int err = -EINVAL; ++ u32 addr, val; ++ void __iomem *mmio = 0; ++ ++ WARN_ON(!pc->hostmode); ++ if (unlikely(len != 1 && len != 2 && len != 4)) ++ goto out; ++ if (dev == 0) { ++ /* we support only two functions on device 0 */ ++ if (func > 1) ++ return -EINVAL; ++ ++ /* accesses to config registers with offsets >= 256 ++ * requires indirect access. ++ */ ++ if (off >= PCI_CONFIG_SPACE_SIZE) { ++ addr = (func << 12); ++ addr |= (off & 0x0FFF); ++ val = bcma_pcie_read_config(pc, addr); ++ } else { ++ addr = BCMA_CORE_PCI_PCICFG0; ++ addr |= (func << 8); ++ addr |= (off & 0xfc); ++ val = pcicore_read32(pc, addr); ++ } ++ } else { ++ addr = bcma_get_cfgspace_addr(pc, dev, func, off); ++ if (unlikely(!addr)) ++ goto out; ++ err = -ENOMEM; ++ mmio = ioremap_nocache(addr, sizeof(val)); ++ if (!mmio) ++ goto out; ++ ++ if (mips_busprobe32(val, mmio)) { ++ val = 0xffffffff; ++ goto unmap; ++ } ++ ++ val = readl(mmio); ++ } ++ val >>= (8 * (off & 3)); ++ ++ switch (len) { ++ case 1: ++ *((u8 *)buf) = (u8)val; ++ break; ++ case 2: ++ *((u16 *)buf) = (u16)val; ++ break; ++ case 4: ++ *((u32 *)buf) = (u32)val; ++ break; ++ } ++ err = 0; ++unmap: ++ if (mmio) ++ iounmap(mmio); ++out: ++ return err; ++} ++ ++static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev, ++ unsigned int func, unsigned int off, ++ const void *buf, int len) ++{ ++ int err = -EINVAL; ++ u32 addr = 0, val = 0; ++ void __iomem *mmio = 0; ++ u16 chipid = pc->core->bus->chipinfo.id; ++ ++ WARN_ON(!pc->hostmode); ++ if (unlikely(len != 1 && len != 2 && len != 4)) ++ goto out; ++ if (dev == 0) { ++ /* accesses to config registers with offsets >= 256 ++ * requires indirect access. ++ */ ++ if (off < PCI_CONFIG_SPACE_SIZE) { ++ addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0; ++ addr |= (func << 8); ++ addr |= (off & 0xfc); ++ mmio = ioremap_nocache(addr, sizeof(val)); ++ if (!mmio) ++ goto out; ++ } ++ } else { ++ addr = bcma_get_cfgspace_addr(pc, dev, func, off); ++ if (unlikely(!addr)) ++ goto out; ++ err = -ENOMEM; ++ mmio = ioremap_nocache(addr, sizeof(val)); ++ if (!mmio) ++ goto out; ++ ++ if (mips_busprobe32(val, mmio)) { ++ val = 0xffffffff; ++ goto unmap; ++ } ++ } ++ ++ switch (len) { ++ case 1: ++ val = readl(mmio); ++ val &= ~(0xFF << (8 * (off & 3))); ++ val |= *((const u8 *)buf) << (8 * (off & 3)); ++ break; ++ case 2: ++ val = readl(mmio); ++ val &= ~(0xFFFF << (8 * (off & 3))); ++ val |= *((const u16 *)buf) << (8 * (off & 3)); ++ break; ++ case 4: ++ val = *((const u32 *)buf); ++ break; ++ } ++ if (dev == 0 && !addr) { ++ /* accesses to config registers with offsets >= 256 ++ * requires indirect access. ++ */ ++ addr = (func << 12); ++ addr |= (off & 0x0FFF); ++ bcma_pcie_write_config(pc, addr, val); ++ } else { ++ writel(val, mmio); ++ ++ if (chipid == BCMA_CHIP_ID_BCM4716 || ++ chipid == BCMA_CHIP_ID_BCM4748) ++ readl(mmio); ++ } ++ ++ err = 0; ++unmap: ++ if (mmio) ++ iounmap(mmio); ++out: ++ return err; ++} ++ ++static int bcma_core_pci_hostmode_read_config(struct pci_bus *bus, ++ unsigned int devfn, ++ int reg, int size, u32 *val) ++{ ++ unsigned long flags; ++ int err; ++ struct bcma_drv_pci *pc; ++ struct bcma_drv_pci_host *pc_host; ++ ++ pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops); ++ pc = pc_host->pdev; ++ ++ spin_lock_irqsave(&pc_host->cfgspace_lock, flags); ++ err = bcma_extpci_read_config(pc, PCI_SLOT(devfn), ++ PCI_FUNC(devfn), reg, val, size); ++ spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags); ++ ++ return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; ++} ++ ++static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus, ++ unsigned int devfn, ++ int reg, int size, u32 val) ++{ ++ unsigned long flags; ++ int err; ++ struct bcma_drv_pci *pc; ++ struct bcma_drv_pci_host *pc_host; ++ ++ pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops); ++ pc = pc_host->pdev; ++ ++ spin_lock_irqsave(&pc_host->cfgspace_lock, flags); ++ err = bcma_extpci_write_config(pc, PCI_SLOT(devfn), ++ PCI_FUNC(devfn), reg, &val, size); ++ spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags); ++ ++ return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; ++} ++ ++/* return cap_offset if requested capability exists in the PCI config space */ ++static u8 __devinit bcma_find_pci_capability(struct bcma_drv_pci *pc, ++ unsigned int dev, ++ unsigned int func, u8 req_cap_id, ++ unsigned char *buf, u32 *buflen) ++{ ++ u8 cap_id; ++ u8 cap_ptr = 0; ++ u32 bufsize; ++ u8 byte_val; ++ ++ /* check for Header type 0 */ ++ bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val, ++ sizeof(u8)); ++ if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL) ++ return cap_ptr; ++ ++ /* check if the capability pointer field exists */ ++ bcma_extpci_read_config(pc, dev, func, PCI_STATUS, &byte_val, ++ sizeof(u8)); ++ if (!(byte_val & PCI_STATUS_CAP_LIST)) ++ return cap_ptr; ++ ++ /* check if the capability pointer is 0x00 */ ++ bcma_extpci_read_config(pc, dev, func, PCI_CAPABILITY_LIST, &cap_ptr, ++ sizeof(u8)); ++ if (cap_ptr == 0x00) ++ return cap_ptr; ++ ++ /* loop thr'u the capability list and see if the requested capabilty ++ * exists */ ++ bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, sizeof(u8)); ++ while (cap_id != req_cap_id) { ++ bcma_extpci_read_config(pc, dev, func, cap_ptr + 1, &cap_ptr, ++ sizeof(u8)); ++ if (cap_ptr == 0x00) ++ return cap_ptr; ++ bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, ++ sizeof(u8)); ++ } ++ ++ /* found the caller requested capability */ ++ if ((buf != NULL) && (buflen != NULL)) { ++ u8 cap_data; ++ ++ bufsize = *buflen; ++ if (!bufsize) ++ return cap_ptr; ++ ++ *buflen = 0; ++ ++ /* copy the cpability data excluding cap ID and next ptr */ ++ cap_data = cap_ptr + 2; ++ if ((bufsize + cap_data) > PCI_CONFIG_SPACE_SIZE) ++ bufsize = PCI_CONFIG_SPACE_SIZE - cap_data; ++ *buflen = bufsize; ++ while (bufsize--) { ++ bcma_extpci_read_config(pc, dev, func, cap_data, buf, ++ sizeof(u8)); ++ cap_data++; ++ buf++; ++ } ++ } ++ ++ return cap_ptr; ++} ++ ++/* If the root port is capable of returning Config Request ++ * Retry Status (CRS) Completion Status to software then ++ * enable the feature. ++ */ ++static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc) ++{ ++ struct bcma_bus *bus = pc->core->bus; ++ u8 cap_ptr, root_ctrl, root_cap, dev; ++ u16 val16; ++ int i; ++ ++ cap_ptr = bcma_find_pci_capability(pc, 0, 0, PCI_CAP_ID_EXP, NULL, ++ NULL); ++ root_cap = cap_ptr + PCI_EXP_RTCAP; ++ bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16)); ++ if (val16 & BCMA_CORE_PCI_RC_CRS_VISIBILITY) { ++ /* Enable CRS software visibility */ ++ root_ctrl = cap_ptr + PCI_EXP_RTCTL; ++ val16 = PCI_EXP_RTCTL_CRSSVE; ++ bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16, ++ sizeof(u16)); ++ ++ /* Initiate a configuration request to read the vendor id ++ * field of the device function's config space header after ++ * 100 ms wait time from the end of Reset. If the device is ++ * not done with its internal initialization, it must at ++ * least return a completion TLP, with a completion status ++ * of "Configuration Request Retry Status (CRS)". The root ++ * complex must complete the request to the host by returning ++ * a read-data value of 0001h for the Vendor ID field and ++ * all 1s for any additional bytes included in the request. ++ * Poll using the config reads for max wait time of 1 sec or ++ * until we receive the successful completion status. Repeat ++ * the procedure for all the devices. ++ */ ++ for (dev = 1; dev < BCMA_PCI_SLOT_MAX; dev++) { ++ for (i = 0; i < 100000; i++) { ++ bcma_extpci_read_config(pc, dev, 0, ++ PCI_VENDOR_ID, &val16, ++ sizeof(val16)); ++ if (val16 != 0x1) ++ break; ++ udelay(10); ++ } ++ if (val16 == 0x1) ++ bcma_err(bus, "PCI: Broken device in slot %d\n", ++ dev); ++ } ++ } ++} ++ ++void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc) ++{ ++ struct bcma_bus *bus = pc->core->bus; ++ struct bcma_drv_pci_host *pc_host; ++ u32 tmp; ++ u32 pci_membase_1G; ++ unsigned long io_map_base; ++ ++ bcma_info(bus, "PCIEcore in host mode found\n"); ++ ++ if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) { ++ bcma_info(bus, "This PCIE core is disabled and not working\n"); ++ return; ++ } ++ ++ pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL); ++ if (!pc_host) { ++ bcma_err(bus, "can not allocate memory"); ++ return; ++ } ++ ++ pc->host_controller = pc_host; ++ pc_host->pci_controller.io_resource = &pc_host->io_resource; ++ pc_host->pci_controller.mem_resource = &pc_host->mem_resource; ++ pc_host->pci_controller.pci_ops = &pc_host->pci_ops; ++ pc_host->pdev = pc; ++ ++ pci_membase_1G = BCMA_SOC_PCI_DMA; ++ pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG; ++ ++ pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config; ++ pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config; ++ ++ pc_host->mem_resource.name = "BCMA PCIcore external memory", ++ pc_host->mem_resource.start = BCMA_SOC_PCI_DMA; ++ pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1; ++ pc_host->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED; ++ ++ pc_host->io_resource.name = "BCMA PCIcore external I/O", ++ pc_host->io_resource.start = 0x100; ++ pc_host->io_resource.end = 0x7FF; ++ pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED; ++ ++ /* Reset RC */ ++ usleep_range(3000, 5000); ++ pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE); ++ usleep_range(1000, 2000); ++ pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST | ++ BCMA_CORE_PCI_CTL_RST_OE); ++ ++ /* 64 MB I/O access window. On 4716, use ++ * sbtopcie0 to access the device registers. We ++ * can't use address match 2 (1 GB window) region ++ * as mips can't generate 64-bit address on the ++ * backplane. ++ */ ++ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4716 || ++ bus->chipinfo.id == BCMA_CHIP_ID_BCM4748) { ++ pc_host->mem_resource.start = BCMA_SOC_PCI_MEM; ++ pc_host->mem_resource.end = BCMA_SOC_PCI_MEM + ++ BCMA_SOC_PCI_MEM_SZ - 1; ++ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, ++ BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM); ++ } else if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) { ++ tmp = BCMA_CORE_PCI_SBTOPCI_MEM; ++ tmp |= BCMA_CORE_PCI_SBTOPCI_PREF; ++ tmp |= BCMA_CORE_PCI_SBTOPCI_BURST; ++ if (pc->core->core_unit == 0) { ++ pc_host->mem_resource.start = BCMA_SOC_PCI_MEM; ++ pc_host->mem_resource.end = BCMA_SOC_PCI_MEM + ++ BCMA_SOC_PCI_MEM_SZ - 1; ++ pc_host->io_resource.start = 0x100; ++ pc_host->io_resource.end = 0x47F; ++ pci_membase_1G = BCMA_SOC_PCIE_DMA_H32; ++ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, ++ tmp | BCMA_SOC_PCI_MEM); ++ } else if (pc->core->core_unit == 1) { ++ pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM; ++ pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM + ++ BCMA_SOC_PCI_MEM_SZ - 1; ++ pc_host->io_resource.start = 0x480; ++ pc_host->io_resource.end = 0x7FF; ++ pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32; ++ pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG; ++ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, ++ tmp | BCMA_SOC_PCI1_MEM); ++ } ++ } else ++ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, ++ BCMA_CORE_PCI_SBTOPCI_IO); ++ ++ /* 64 MB configuration access window */ ++ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0); ++ ++ /* 1 GB memory access window */ ++ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2, ++ BCMA_CORE_PCI_SBTOPCI_MEM | pci_membase_1G); ++ ++ ++ /* As per PCI Express Base Spec 1.1 we need to wait for ++ * at least 100 ms from the end of a reset (cold/warm/hot) ++ * before issuing configuration requests to PCI Express ++ * devices. ++ */ ++ msleep(100); ++ ++ bcma_core_pci_enable_crs(pc); ++ ++ /* Enable PCI bridge BAR0 memory & master access */ ++ tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; ++ bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp)); ++ ++ /* Enable PCI interrupts */ ++ pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA); ++ ++ /* Ok, ready to run, register it to the system. ++ * The following needs change, if we want to port hostmode ++ * to non-MIPS platform. */ ++ io_map_base = (unsigned long)ioremap_nocache(pc_host->mem_resource.start, ++ resource_size(&pc_host->mem_resource)); ++ pc_host->pci_controller.io_map_base = io_map_base; ++ set_io_port_base(pc_host->pci_controller.io_map_base); ++ /* Give some time to the PCI controller to configure itself with the new ++ * values. Not waiting at this point causes crashes of the machine. */ ++ usleep_range(10000, 15000); ++ register_pci_controller(&pc_host->pci_controller); ++ return; ++} ++ ++/* Early PCI fixup for a device on the PCI-core bridge. */ ++static void bcma_core_pci_fixup_pcibridge(struct pci_dev *dev) ++{ ++ if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { ++ /* This is not a device on the PCI-core bridge. */ ++ return; ++ } ++ if (PCI_SLOT(dev->devfn) != 0) ++ return; ++ ++ pr_info("PCI: Fixing up bridge %s\n", pci_name(dev)); ++ ++ /* Enable PCI bridge bus mastering and memory space */ ++ pci_set_master(dev); ++ if (pcibios_enable_device(dev, ~0) < 0) { ++ pr_err("PCI: BCMA bridge enable failed\n"); ++ return; ++ } ++ ++ /* Enable PCI bridge BAR1 prefetch and burst */ ++ pci_write_config_dword(dev, BCMA_PCI_BAR1_CONTROL, 3); ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge); ++ ++/* Early PCI fixup for all PCI-cores to set the correct memory address. */ ++static void bcma_core_pci_fixup_addresses(struct pci_dev *dev) ++{ ++ struct resource *res; ++ int pos, err; ++ ++ if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { ++ /* This is not a device on the PCI-core bridge. */ ++ return; ++ } ++ if (PCI_SLOT(dev->devfn) == 0) ++ return; ++ ++ pr_info("PCI: Fixing up addresses %s\n", pci_name(dev)); ++ ++ for (pos = 0; pos < 6; pos++) { ++ res = &dev->resource[pos]; ++ if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) { ++ err = pci_assign_resource(dev, pos); ++ if (err) ++ pr_err("PCI: Problem fixing up the addresses on %s\n", ++ pci_name(dev)); ++ } ++ } ++} ++DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses); ++ ++/* This function is called when doing a pci_enable_device(). ++ * We must first check if the device is a device on the PCI-core bridge. */ ++int bcma_core_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ struct bcma_drv_pci_host *pc_host; ++ ++ if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { ++ /* This is not a device on the PCI-core bridge. */ ++ return -ENODEV; ++ } ++ pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host, ++ pci_ops); ++ ++ pr_info("PCI: Fixing up device %s\n", pci_name(dev)); ++ ++ /* Fix up interrupt lines */ ++ dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2; ++ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); ++ ++ return 0; ++} ++EXPORT_SYMBOL(bcma_core_pci_plat_dev_init); ++ ++/* PCI device IRQ mapping. */ ++int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev) ++{ ++ struct bcma_drv_pci_host *pc_host; ++ ++ if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { ++ /* This is not a device on the PCI-core bridge. */ ++ return -ENODEV; ++ } ++ ++ pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host, ++ pci_ops); ++ return bcma_core_mips_irq(pc_host->pdev->core) + 2; + } ++EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq); +--- a/drivers/bcma/host_pci.c ++++ b/drivers/bcma/host_pci.c +@@ -18,7 +18,7 @@ static void bcma_host_pci_switch_core(st + pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN2, + core->wrap); + core->bus->mapped_core = core; +- pr_debug("Switched to core: 0x%X\n", core->id.id); ++ bcma_debug(core->bus, "Switched to core: 0x%X\n", core->id.id); + } + + /* Provides access to the requested core. Returns base offset that has to be +@@ -77,8 +77,8 @@ static void bcma_host_pci_write32(struct + } + + #ifdef CONFIG_BCMA_BLOCKIO +-void bcma_host_pci_block_read(struct bcma_device *core, void *buffer, +- size_t count, u16 offset, u8 reg_width) ++static void bcma_host_pci_block_read(struct bcma_device *core, void *buffer, ++ size_t count, u16 offset, u8 reg_width) + { + void __iomem *addr = core->bus->mmio + offset; + if (core->bus->mapped_core != core) +@@ -100,8 +100,9 @@ void bcma_host_pci_block_read(struct bcm + } + } + +-void bcma_host_pci_block_write(struct bcma_device *core, const void *buffer, +- size_t count, u16 offset, u8 reg_width) ++static void bcma_host_pci_block_write(struct bcma_device *core, ++ const void *buffer, size_t count, ++ u16 offset, u8 reg_width) + { + void __iomem *addr = core->bus->mmio + offset; + if (core->bus->mapped_core != core) +@@ -139,7 +140,7 @@ static void bcma_host_pci_awrite32(struc + iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset); + } + +-const struct bcma_host_ops bcma_host_pci_ops = { ++static const struct bcma_host_ops bcma_host_pci_ops = { + .read8 = bcma_host_pci_read8, + .read16 = bcma_host_pci_read16, + .read32 = bcma_host_pci_read32, +@@ -154,8 +155,8 @@ const struct bcma_host_ops bcma_host_pci + .awrite32 = bcma_host_pci_awrite32, + }; + +-static int bcma_host_pci_probe(struct pci_dev *dev, +- const struct pci_device_id *id) ++static int __devinit bcma_host_pci_probe(struct pci_dev *dev, ++ const struct pci_device_id *id) + { + struct bcma_bus *bus; + int err = -ENOMEM; +@@ -188,7 +189,7 @@ static int bcma_host_pci_probe(struct pc + + /* SSB needed additional powering up, do we have any AMBA PCI cards? */ + if (!pci_is_pcie(dev)) +- pr_err("PCI card detected, report problems.\n"); ++ bcma_err(bus, "PCI card detected, report problems.\n"); + + /* Map MMIO */ + err = -ENOMEM; +@@ -201,6 +202,9 @@ static int bcma_host_pci_probe(struct pc + bus->hosttype = BCMA_HOSTTYPE_PCI; + bus->ops = &bcma_host_pci_ops; + ++ bus->boardinfo.vendor = bus->host_pci->subsystem_vendor; ++ bus->boardinfo.type = bus->host_pci->subsystem_device; ++ + /* Register */ + err = bcma_bus_register(bus); + if (err) +@@ -222,7 +226,7 @@ err_kfree_bus: + return err; + } + +-static void bcma_host_pci_remove(struct pci_dev *dev) ++static void __devexit bcma_host_pci_remove(struct pci_dev *dev) + { + struct bcma_bus *bus = pci_get_drvdata(dev); + +@@ -234,7 +238,7 @@ static void bcma_host_pci_remove(struct + pci_set_drvdata(dev, NULL); + } + +-#ifdef CONFIG_PM ++#ifdef CONFIG_PM_SLEEP + static int bcma_host_pci_suspend(struct device *dev) + { + struct pci_dev *pdev = to_pci_dev(dev); +@@ -257,17 +261,20 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc + bcma_host_pci_resume); + #define BCMA_PM_OPS (&bcma_pm_ops) + +-#else /* CONFIG_PM */ ++#else /* CONFIG_PM_SLEEP */ + + #define BCMA_PM_OPS NULL + +-#endif /* CONFIG_PM */ ++#endif /* CONFIG_PM_SLEEP */ + + static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = { + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) }, ++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) }, ++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) }, ++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) }, + { 0, }, + }; +@@ -277,7 +284,7 @@ static struct pci_driver bcma_pci_bridge + .name = "bcma-pci-bridge", + .id_table = bcma_pci_bridge_tbl, + .probe = bcma_host_pci_probe, +- .remove = bcma_host_pci_remove, ++ .remove = __devexit_p(bcma_host_pci_remove), + .driver.pm = BCMA_PM_OPS, + }; + +--- a/drivers/bcma/host_soc.c ++++ b/drivers/bcma/host_soc.c +@@ -143,7 +143,7 @@ static void bcma_host_soc_awrite32(struc + writel(value, core->io_wrap + offset); + } + +-const struct bcma_host_ops bcma_host_soc_ops = { ++static const struct bcma_host_ops bcma_host_soc_ops = { + .read8 = bcma_host_soc_read8, + .read16 = bcma_host_soc_read16, + .read32 = bcma_host_soc_read32, +--- a/drivers/bcma/main.c ++++ b/drivers/bcma/main.c +@@ -7,12 +7,19 @@ + + #include "bcma_private.h" + #include <linux/module.h> ++#include <linux/platform_device.h> + #include <linux/bcma/bcma.h> + #include <linux/slab.h> + + MODULE_DESCRIPTION("Broadcom's specific AMBA driver"); + MODULE_LICENSE("GPL"); + ++/* contains the number the next bus should get. */ ++static unsigned int bcma_bus_next_num = 0; ++ ++/* bcma_buses_mutex locks the bcma_bus_next_num */ ++static DEFINE_MUTEX(bcma_buses_mutex); ++ + static int bcma_bus_match(struct device *dev, struct device_driver *drv); + static int bcma_device_probe(struct device *dev); + static int bcma_device_remove(struct device *dev); +@@ -55,7 +62,14 @@ static struct bus_type bcma_bus_type = { + .dev_attrs = bcma_device_attrs, + }; + +-static struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid) ++static u16 bcma_cc_core_id(struct bcma_bus *bus) ++{ ++ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) ++ return BCMA_CORE_4706_CHIPCOMMON; ++ return BCMA_CORE_CHIPCOMMON; ++} ++ ++struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid) + { + struct bcma_device *core; + +@@ -65,6 +79,19 @@ static struct bcma_device *bcma_find_cor + } + return NULL; + } ++EXPORT_SYMBOL_GPL(bcma_find_core); ++ ++struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, ++ u8 unit) ++{ ++ struct bcma_device *core; ++ ++ list_for_each_entry(core, &bus->cores, list) { ++ if (core->id.id == coreid && core->core_unit == unit) ++ return core; ++ } ++ return NULL; ++} + + static void bcma_release_core_dev(struct device *dev) + { +@@ -84,16 +111,18 @@ static int bcma_register_cores(struct bc + list_for_each_entry(core, &bus->cores, list) { + /* We support that cores ourself */ + switch (core->id.id) { ++ case BCMA_CORE_4706_CHIPCOMMON: + case BCMA_CORE_CHIPCOMMON: + case BCMA_CORE_PCI: + case BCMA_CORE_PCIE: + case BCMA_CORE_MIPS_74K: ++ case BCMA_CORE_4706_MAC_GBIT_COMMON: + continue; + } + + core->dev.release = bcma_release_core_dev; + core->dev.bus = &bcma_bus_type; +- dev_set_name(&core->dev, "bcma%d:%d", 0/*bus->num*/, dev_id); ++ dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id); + + switch (bus->hosttype) { + case BCMA_HOSTTYPE_PCI: +@@ -111,41 +140,90 @@ static int bcma_register_cores(struct bc + + err = device_register(&core->dev); + if (err) { +- pr_err("Could not register dev for core 0x%03X\n", +- core->id.id); ++ bcma_err(bus, ++ "Could not register dev for core 0x%03X\n", ++ core->id.id); + continue; + } + core->dev_registered = true; + dev_id++; + } + ++#ifdef CONFIG_BCMA_SFLASH ++ if (bus->drv_cc.sflash.present) { ++ err = platform_device_register(&bcma_sflash_dev); ++ if (err) ++ bcma_err(bus, "Error registering serial flash\n"); ++ } ++#endif ++ ++#ifdef CONFIG_BCMA_NFLASH ++ if (bus->drv_cc.nflash.present) { ++ err = platform_device_register(&bcma_nflash_dev); ++ if (err) ++ bcma_err(bus, "Error registering NAND flash\n"); ++ } ++#endif ++ err = bcma_gpio_init(&bus->drv_cc); ++ if (err == -ENOTSUPP) ++ bcma_debug(bus, "GPIO driver not activated\n"); ++ else if (err) ++ bcma_err(bus, "Error registering GPIO driver: %i\n", err); ++ ++ if (bus->hosttype == BCMA_HOSTTYPE_SOC) { ++ err = bcma_chipco_watchdog_register(&bus->drv_cc); ++ if (err) ++ bcma_err(bus, "Error registering watchdog driver\n"); ++ } ++ + return 0; + } + + static void bcma_unregister_cores(struct bcma_bus *bus) + { +- struct bcma_device *core; ++ struct bcma_device *core, *tmp; + +- list_for_each_entry(core, &bus->cores, list) { ++ list_for_each_entry_safe(core, tmp, &bus->cores, list) { ++ list_del(&core->list); + if (core->dev_registered) + device_unregister(&core->dev); + } ++ if (bus->hosttype == BCMA_HOSTTYPE_SOC) ++ platform_device_unregister(bus->drv_cc.watchdog); + } + +-int bcma_bus_register(struct bcma_bus *bus) ++int __devinit bcma_bus_register(struct bcma_bus *bus) + { + int err; + struct bcma_device *core; + ++ mutex_lock(&bcma_buses_mutex); ++ bus->num = bcma_bus_next_num++; ++ mutex_unlock(&bcma_buses_mutex); ++ + /* Scan for devices (cores) */ + err = bcma_bus_scan(bus); + if (err) { +- pr_err("Failed to scan: %d\n", err); ++ bcma_err(bus, "Failed to scan: %d\n", err); + return -1; + } + ++ /* Early init CC core */ ++ core = bcma_find_core(bus, bcma_cc_core_id(bus)); ++ if (core) { ++ bus->drv_cc.core = core; ++ bcma_core_chipcommon_early_init(&bus->drv_cc); ++ } ++ ++ /* Try to get SPROM */ ++ err = bcma_sprom_get(bus); ++ if (err == -ENOENT) { ++ bcma_err(bus, "No SPROM available\n"); ++ } else if (err) ++ bcma_err(bus, "Failed to get SPROM: %d\n", err); ++ + /* Init CC core */ +- core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON); ++ core = bcma_find_core(bus, bcma_cc_core_id(bus)); + if (core) { + bus->drv_cc.core = core; + bcma_core_chipcommon_init(&bus->drv_cc); +@@ -159,30 +237,47 @@ int bcma_bus_register(struct bcma_bus *b + } + + /* Init PCIE core */ +- core = bcma_find_core(bus, BCMA_CORE_PCIE); ++ core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0); + if (core) { +- bus->drv_pci.core = core; +- bcma_core_pci_init(&bus->drv_pci); ++ bus->drv_pci[0].core = core; ++ bcma_core_pci_init(&bus->drv_pci[0]); + } + +- /* Try to get SPROM */ +- err = bcma_sprom_get(bus); +- if (err == -ENOENT) { +- pr_err("No SPROM available\n"); +- } else if (err) +- pr_err("Failed to get SPROM: %d\n", err); ++ /* Init PCIE core */ ++ core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1); ++ if (core) { ++ bus->drv_pci[1].core = core; ++ bcma_core_pci_init(&bus->drv_pci[1]); ++ } ++ ++ /* Init GBIT MAC COMMON core */ ++ core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON); ++ if (core) { ++ bus->drv_gmac_cmn.core = core; ++ bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn); ++ } + + /* Register found cores */ + bcma_register_cores(bus); + +- pr_info("Bus registered\n"); ++ bcma_info(bus, "Bus registered\n"); + + return 0; + } + + void bcma_bus_unregister(struct bcma_bus *bus) + { ++ struct bcma_device *cores[3]; ++ ++ cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K); ++ cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE); ++ cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON); ++ + bcma_unregister_cores(bus); ++ ++ kfree(cores[2]); ++ kfree(cores[1]); ++ kfree(cores[0]); + } + + int __init bcma_bus_early_register(struct bcma_bus *bus, +@@ -196,14 +291,14 @@ int __init bcma_bus_early_register(struc + bcma_init_bus(bus); + + match.manuf = BCMA_MANUF_BCM; +- match.id = BCMA_CORE_CHIPCOMMON; ++ match.id = bcma_cc_core_id(bus); + match.class = BCMA_CL_SIM; + match.rev = BCMA_ANY_REV; + + /* Scan for chip common core */ + err = bcma_bus_scan_early(bus, &match, core_cc); + if (err) { +- pr_err("Failed to scan for common core: %d\n", err); ++ bcma_err(bus, "Failed to scan for common core: %d\n", err); + return -1; + } + +@@ -215,25 +310,25 @@ int __init bcma_bus_early_register(struc + /* Scan for mips core */ + err = bcma_bus_scan_early(bus, &match, core_mips); + if (err) { +- pr_err("Failed to scan for mips core: %d\n", err); ++ bcma_err(bus, "Failed to scan for mips core: %d\n", err); + return -1; + } + +- /* Init CC core */ +- core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON); ++ /* Early init CC core */ ++ core = bcma_find_core(bus, bcma_cc_core_id(bus)); + if (core) { + bus->drv_cc.core = core; +- bcma_core_chipcommon_init(&bus->drv_cc); ++ bcma_core_chipcommon_early_init(&bus->drv_cc); + } + +- /* Init MIPS core */ ++ /* Early init MIPS core */ + core = bcma_find_core(bus, BCMA_CORE_MIPS_74K); + if (core) { + bus->drv_mips.core = core; +- bcma_core_mips_init(&bus->drv_mips); ++ bcma_core_mips_early_init(&bus->drv_mips); + } + +- pr_info("Early bus registered\n"); ++ bcma_info(bus, "Early bus registered\n"); + + return 0; + } +@@ -259,8 +354,7 @@ int bcma_bus_resume(struct bcma_bus *bus + struct bcma_device *core; + + /* Init CC core */ +- core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON); +- if (core) { ++ if (bus->drv_cc.core) { + bus->drv_cc.setup_done = false; + bcma_core_chipcommon_init(&bus->drv_cc); + } +--- a/drivers/bcma/scan.c ++++ b/drivers/bcma/scan.c +@@ -19,15 +19,27 @@ struct bcma_device_id_name { + u16 id; + const char *name; + }; +-struct bcma_device_id_name bcma_device_names[] = { ++ ++static const struct bcma_device_id_name bcma_arm_device_names[] = { ++ { BCMA_CORE_4706_MAC_GBIT_COMMON, "BCM4706 GBit MAC Common" }, ++ { BCMA_CORE_ARM_1176, "ARM 1176" }, ++ { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" }, ++ { BCMA_CORE_ARM_CM3, "ARM CM3" }, ++}; ++ ++static const struct bcma_device_id_name bcma_bcm_device_names[] = { + { BCMA_CORE_OOB_ROUTER, "OOB Router" }, ++ { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" }, ++ { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" }, ++ { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" }, ++ { BCMA_CORE_AMEMC, "AMEMC (DDR)" }, ++ { BCMA_CORE_ALTA, "ALTA (I2S)" }, + { BCMA_CORE_INVALID, "Invalid" }, + { BCMA_CORE_CHIPCOMMON, "ChipCommon" }, + { BCMA_CORE_ILINE20, "ILine 20" }, + { BCMA_CORE_SRAM, "SRAM" }, + { BCMA_CORE_SDRAM, "SDRAM" }, + { BCMA_CORE_PCI, "PCI" }, +- { BCMA_CORE_MIPS, "MIPS" }, + { BCMA_CORE_ETHERNET, "Fast Ethernet" }, + { BCMA_CORE_V90, "V90" }, + { BCMA_CORE_USB11_HOSTDEV, "USB 1.1 Hostdev" }, +@@ -44,7 +56,6 @@ struct bcma_device_id_name bcma_device_n + { BCMA_CORE_PHY_A, "PHY A" }, + { BCMA_CORE_PHY_B, "PHY B" }, + { BCMA_CORE_PHY_G, "PHY G" }, +- { BCMA_CORE_MIPS_3302, "MIPS 3302" }, + { BCMA_CORE_USB11_HOST, "USB 1.1 Host" }, + { BCMA_CORE_USB11_DEV, "USB 1.1 Device" }, + { BCMA_CORE_USB20_HOST, "USB 2.0 Host" }, +@@ -58,15 +69,11 @@ struct bcma_device_id_name bcma_device_n + { BCMA_CORE_PHY_N, "PHY N" }, + { BCMA_CORE_SRAM_CTL, "SRAM Controller" }, + { BCMA_CORE_MINI_MACPHY, "Mini MACPHY" }, +- { BCMA_CORE_ARM_1176, "ARM 1176" }, +- { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" }, + { BCMA_CORE_PHY_LP, "PHY LP" }, + { BCMA_CORE_PMU, "PMU" }, + { BCMA_CORE_PHY_SSN, "PHY SSN" }, + { BCMA_CORE_SDIO_DEV, "SDIO Device" }, +- { BCMA_CORE_ARM_CM3, "ARM CM3" }, + { BCMA_CORE_PHY_HT, "PHY HT" }, +- { BCMA_CORE_MIPS_74K, "MIPS 74K" }, + { BCMA_CORE_MAC_GBIT, "GBit MAC" }, + { BCMA_CORE_DDR12_MEM_CTL, "DDR1/DDR2 Memory Controller" }, + { BCMA_CORE_PCIE_RC, "PCIe Root Complex" }, +@@ -79,16 +86,41 @@ struct bcma_device_id_name bcma_device_n + { BCMA_CORE_SHIM, "SHIM" }, + { BCMA_CORE_DEFAULT, "Default" }, + }; +-const char *bcma_device_name(struct bcma_device_id *id) ++ ++static const struct bcma_device_id_name bcma_mips_device_names[] = { ++ { BCMA_CORE_MIPS, "MIPS" }, ++ { BCMA_CORE_MIPS_3302, "MIPS 3302" }, ++ { BCMA_CORE_MIPS_74K, "MIPS 74K" }, ++}; ++ ++static const char *bcma_device_name(const struct bcma_device_id *id) + { +- int i; ++ const struct bcma_device_id_name *names; ++ int size, i; + +- if (id->manuf == BCMA_MANUF_BCM) { +- for (i = 0; i < ARRAY_SIZE(bcma_device_names); i++) { +- if (bcma_device_names[i].id == id->id) +- return bcma_device_names[i].name; +- } ++ /* search manufacturer specific names */ ++ switch (id->manuf) { ++ case BCMA_MANUF_ARM: ++ names = bcma_arm_device_names; ++ size = ARRAY_SIZE(bcma_arm_device_names); ++ break; ++ case BCMA_MANUF_BCM: ++ names = bcma_bcm_device_names; ++ size = ARRAY_SIZE(bcma_bcm_device_names); ++ break; ++ case BCMA_MANUF_MIPS: ++ names = bcma_mips_device_names; ++ size = ARRAY_SIZE(bcma_mips_device_names); ++ break; ++ default: ++ return "UNKNOWN"; + } ++ ++ for (i = 0; i < size; i++) { ++ if (names[i].id == id->id) ++ return names[i].name; ++ } ++ + return "UNKNOWN"; + } + +@@ -212,6 +244,17 @@ static struct bcma_device *bcma_find_cor + return NULL; + } + ++static struct bcma_device *bcma_find_core_reverse(struct bcma_bus *bus, u16 coreid) ++{ ++ struct bcma_device *core; ++ ++ list_for_each_entry_reverse(core, &bus->cores, list) { ++ if (core->id.id == coreid) ++ return core; ++ } ++ return NULL; ++} ++ + static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr, + struct bcma_device_id *match, int core_num, + struct bcma_device *core) +@@ -252,11 +295,15 @@ static int bcma_get_next_core(struct bcm + + /* check if component is a core at all */ + if (wrappers[0] + wrappers[1] == 0) { +- /* we could save addrl of the router +- if (cid == BCMA_CORE_OOB_ROUTER) +- */ +- bcma_erom_skip_component(bus, eromptr); +- return -ENXIO; ++ /* Some specific cores don't need wrappers */ ++ switch (core->id.id) { ++ case BCMA_CORE_4706_MAC_GBIT_COMMON: ++ /* Not used yet: case BCMA_CORE_OOB_ROUTER: */ ++ break; ++ default: ++ bcma_erom_skip_component(bus, eromptr); ++ return -ENXIO; ++ } + } + + if (bcma_erom_is_bridge(bus, eromptr)) { +@@ -286,6 +333,23 @@ static int bcma_get_next_core(struct bcm + return -EILSEQ; + } + ++ /* First Slave Address Descriptor should be port 0: ++ * the main register space for the core ++ */ ++ tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0); ++ if (tmp <= 0) { ++ /* Try again to see if it is a bridge */ ++ tmp = bcma_erom_get_addr_desc(bus, eromptr, ++ SCAN_ADDR_TYPE_BRIDGE, 0); ++ if (tmp <= 0) { ++ return -EILSEQ; ++ } else { ++ bcma_info(bus, "Bridge found\n"); ++ return -ENXIO; ++ } ++ } ++ core->addr = tmp; ++ + /* get & parse slave ports */ + for (i = 0; i < ports[1]; i++) { + for (j = 0; ; j++) { +@@ -298,7 +362,7 @@ static int bcma_get_next_core(struct bcm + break; + } else { + if (i == 0 && j == 0) +- core->addr = tmp; ++ core->addr1 = tmp; + } + } + } +@@ -353,6 +417,7 @@ static int bcma_get_next_core(struct bcm + void bcma_init_bus(struct bcma_bus *bus) + { + s32 tmp; ++ struct bcma_chipinfo *chipinfo = &(bus->chipinfo); + + if (bus->init_done) + return; +@@ -363,9 +428,12 @@ void bcma_init_bus(struct bcma_bus *bus) + bcma_scan_switch_core(bus, BCMA_ADDR_BASE); + + tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID); +- bus->chipinfo.id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT; +- bus->chipinfo.rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT; +- bus->chipinfo.pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT; ++ chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT; ++ chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT; ++ chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT; ++ bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n", ++ chipinfo->id, chipinfo->rev, chipinfo->pkg); ++ + bus->init_done = true; + } + +@@ -392,9 +460,12 @@ int bcma_bus_scan(struct bcma_bus *bus) + bcma_scan_switch_core(bus, erombase); + + while (eromptr < eromend) { ++ struct bcma_device *other_core; + struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL); +- if (!core) +- return -ENOMEM; ++ if (!core) { ++ err = -ENOMEM; ++ goto out; ++ } + INIT_LIST_HEAD(&core->list); + core->bus = bus; + +@@ -409,25 +480,28 @@ int bcma_bus_scan(struct bcma_bus *bus) + } else if (err == -ESPIPE) { + break; + } +- return err; ++ goto out; + } + + core->core_index = core_num++; + bus->nr_cores++; ++ other_core = bcma_find_core_reverse(bus, core->id.id); ++ core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1; + +- pr_info("Core %d found: %s " +- "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n", +- core->core_index, bcma_device_name(&core->id), +- core->id.manuf, core->id.id, core->id.rev, +- core->id.class); ++ bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n", ++ core->core_index, bcma_device_name(&core->id), ++ core->id.manuf, core->id.id, core->id.rev, ++ core->id.class); + +- list_add(&core->list, &bus->cores); ++ list_add_tail(&core->list, &bus->cores); + } + ++ err = 0; ++out: + if (bus->hosttype == BCMA_HOSTTYPE_SOC) + iounmap(eromptr); + +- return 0; ++ return err; + } + + int __init bcma_bus_scan_early(struct bcma_bus *bus, +@@ -467,21 +541,21 @@ int __init bcma_bus_scan_early(struct bc + else if (err == -ESPIPE) + break; + else if (err < 0) +- return err; ++ goto out; + + core->core_index = core_num++; + bus->nr_cores++; +- pr_info("Core %d found: %s " +- "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n", +- core->core_index, bcma_device_name(&core->id), +- core->id.manuf, core->id.id, core->id.rev, +- core->id.class); ++ bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n", ++ core->core_index, bcma_device_name(&core->id), ++ core->id.manuf, core->id.id, core->id.rev, ++ core->id.class); + +- list_add(&core->list, &bus->cores); ++ list_add_tail(&core->list, &bus->cores); + err = 0; + break; + } + ++out: + if (bus->hosttype == BCMA_HOSTTYPE_SOC) + iounmap(eromptr); + +--- a/drivers/bcma/scan.h ++++ b/drivers/bcma/scan.h +@@ -27,7 +27,7 @@ + #define SCAN_CIB_NMW 0x0007C000 + #define SCAN_CIB_NMW_SHIFT 14 + #define SCAN_CIB_NSW 0x00F80000 +-#define SCAN_CIB_NSW_SHIFT 17 ++#define SCAN_CIB_NSW_SHIFT 19 + #define SCAN_CIB_REV 0xFF000000 + #define SCAN_CIB_REV_SHIFT 24 + +--- a/drivers/bcma/sprom.c ++++ b/drivers/bcma/sprom.c +@@ -2,6 +2,8 @@ + * Broadcom specific AMBA + * SPROM reading + * ++ * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de> ++ * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +@@ -14,7 +16,57 @@ + #include <linux/dma-mapping.h> + #include <linux/slab.h> + +-#define SPOFF(offset) ((offset) / sizeof(u16)) ++static int(*get_fallback_sprom)(struct bcma_bus *dev, struct ssb_sprom *out); ++ ++/** ++ * bcma_arch_register_fallback_sprom - Registers a method providing a ++ * fallback SPROM if no SPROM is found. ++ * ++ * @sprom_callback: The callback function. ++ * ++ * With this function the architecture implementation may register a ++ * callback handler which fills the SPROM data structure. The fallback is ++ * used for PCI based BCMA devices, where no valid SPROM can be found ++ * in the shadow registers and to provide the SPROM for SoCs where BCMA is ++ * to controll the system bus. ++ * ++ * This function is useful for weird architectures that have a half-assed ++ * BCMA device hardwired to their PCI bus. ++ * ++ * This function is available for architecture code, only. So it is not ++ * exported. ++ */ ++int bcma_arch_register_fallback_sprom(int (*sprom_callback)(struct bcma_bus *bus, ++ struct ssb_sprom *out)) ++{ ++ if (get_fallback_sprom) ++ return -EEXIST; ++ get_fallback_sprom = sprom_callback; ++ ++ return 0; ++} ++ ++static int bcma_fill_sprom_with_fallback(struct bcma_bus *bus, ++ struct ssb_sprom *out) ++{ ++ int err; ++ ++ if (!get_fallback_sprom) { ++ err = -ENOENT; ++ goto fail; ++ } ++ ++ err = get_fallback_sprom(bus, out); ++ if (err) ++ goto fail; ++ ++ bcma_debug(bus, "Using SPROM revision %d provided by platform.\n", ++ bus->sprom.revision); ++ return 0; ++fail: ++ bcma_warn(bus, "Using fallback SPROM failed (err %d)\n", err); ++ return err; ++} + + /************************************************** + * R/W ops. +@@ -124,10 +176,37 @@ static int bcma_sprom_valid(const u16 *s + * SPROM extraction. + **************************************************/ + ++#define SPOFF(offset) ((offset) / sizeof(u16)) ++ ++#define SPEX(_field, _offset, _mask, _shift) \ ++ bus->sprom._field = ((sprom[SPOFF(_offset)] & (_mask)) >> (_shift)) ++ ++#define SPEX32(_field, _offset, _mask, _shift) \ ++ bus->sprom._field = ((((u32)sprom[SPOFF((_offset)+2)] << 16 | \ ++ sprom[SPOFF(_offset)]) & (_mask)) >> (_shift)) ++ ++#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ ++ do { \ ++ SPEX(_field[0], _offset + 0, _mask, _shift); \ ++ SPEX(_field[1], _offset + 2, _mask, _shift); \ ++ SPEX(_field[2], _offset + 4, _mask, _shift); \ ++ SPEX(_field[3], _offset + 6, _mask, _shift); \ ++ SPEX(_field[4], _offset + 8, _mask, _shift); \ ++ SPEX(_field[5], _offset + 10, _mask, _shift); \ ++ SPEX(_field[6], _offset + 12, _mask, _shift); \ ++ SPEX(_field[7], _offset + 14, _mask, _shift); \ ++ } while (0) ++ + static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom) + { +- u16 v; ++ u16 v, o; + int i; ++ u16 pwr_info_offset[] = { ++ SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1, ++ SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3 ++ }; ++ BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) != ++ ARRAY_SIZE(bus->sprom.core_pwr_info)); + + bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & + SSB_SPROM_REVISION_REV; +@@ -137,107 +216,390 @@ static void bcma_sprom_extract_r8(struct + *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v); + } + +- bus->sprom.board_rev = sprom[SPOFF(SSB_SPROM8_BOARDREV)]; ++ SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0); ++ ++ SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0, ++ SSB_SPROM4_TXPID2G0_SHIFT); ++ SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G1, ++ SSB_SPROM4_TXPID2G1_SHIFT); ++ SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G2, ++ SSB_SPROM4_TXPID2G2_SHIFT); ++ SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G3, ++ SSB_SPROM4_TXPID2G3_SHIFT); ++ ++ SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL0, ++ SSB_SPROM4_TXPID5GL0_SHIFT); ++ SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL1, ++ SSB_SPROM4_TXPID5GL1_SHIFT); ++ SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL2, ++ SSB_SPROM4_TXPID5GL2_SHIFT); ++ SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL3, ++ SSB_SPROM4_TXPID5GL3_SHIFT); ++ ++ SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G0, ++ SSB_SPROM4_TXPID5G0_SHIFT); ++ SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G1, ++ SSB_SPROM4_TXPID5G1_SHIFT); ++ SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G2, ++ SSB_SPROM4_TXPID5G2_SHIFT); ++ SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G3, ++ SSB_SPROM4_TXPID5G3_SHIFT); ++ ++ SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH0, ++ SSB_SPROM4_TXPID5GH0_SHIFT); ++ SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH1, ++ SSB_SPROM4_TXPID5GH1_SHIFT); ++ SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH2, ++ SSB_SPROM4_TXPID5GH2_SHIFT); ++ SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH3, ++ SSB_SPROM4_TXPID5GH3_SHIFT); ++ ++ SPEX(boardflags_lo, SSB_SPROM8_BFLLO, ~0, 0); ++ SPEX(boardflags_hi, SSB_SPROM8_BFLHI, ~0, 0); ++ SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, ~0, 0); ++ SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, ~0, 0); ++ ++ SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8); ++ SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0); ++ ++ /* Extract cores power info info */ ++ for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) { ++ o = pwr_info_offset[i]; ++ SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI, ++ SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT); ++ SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI, ++ SSB_SPROM8_2G_MAXP, 0); ++ ++ SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0); ++ SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0); ++ SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0); ++ ++ SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI, ++ SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT); ++ SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI, ++ SSB_SPROM8_5G_MAXP, 0); ++ SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP, ++ SSB_SPROM8_5GH_MAXP, 0); ++ SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP, ++ SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT); ++ ++ SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0); ++ } + +- bus->sprom.txpid2g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] & +- SSB_SPROM4_TXPID2G0) >> SSB_SPROM4_TXPID2G0_SHIFT; +- bus->sprom.txpid2g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] & +- SSB_SPROM4_TXPID2G1) >> SSB_SPROM4_TXPID2G1_SHIFT; +- bus->sprom.txpid2g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] & +- SSB_SPROM4_TXPID2G2) >> SSB_SPROM4_TXPID2G2_SHIFT; +- bus->sprom.txpid2g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] & +- SSB_SPROM4_TXPID2G3) >> SSB_SPROM4_TXPID2G3_SHIFT; +- +- bus->sprom.txpid5gl[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] & +- SSB_SPROM4_TXPID5GL0) >> SSB_SPROM4_TXPID5GL0_SHIFT; +- bus->sprom.txpid5gl[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] & +- SSB_SPROM4_TXPID5GL1) >> SSB_SPROM4_TXPID5GL1_SHIFT; +- bus->sprom.txpid5gl[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] & +- SSB_SPROM4_TXPID5GL2) >> SSB_SPROM4_TXPID5GL2_SHIFT; +- bus->sprom.txpid5gl[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] & +- SSB_SPROM4_TXPID5GL3) >> SSB_SPROM4_TXPID5GL3_SHIFT; +- +- bus->sprom.txpid5g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] & +- SSB_SPROM4_TXPID5G0) >> SSB_SPROM4_TXPID5G0_SHIFT; +- bus->sprom.txpid5g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] & +- SSB_SPROM4_TXPID5G1) >> SSB_SPROM4_TXPID5G1_SHIFT; +- bus->sprom.txpid5g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] & +- SSB_SPROM4_TXPID5G2) >> SSB_SPROM4_TXPID5G2_SHIFT; +- bus->sprom.txpid5g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] & +- SSB_SPROM4_TXPID5G3) >> SSB_SPROM4_TXPID5G3_SHIFT; +- +- bus->sprom.txpid5gh[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] & +- SSB_SPROM4_TXPID5GH0) >> SSB_SPROM4_TXPID5GH0_SHIFT; +- bus->sprom.txpid5gh[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] & +- SSB_SPROM4_TXPID5GH1) >> SSB_SPROM4_TXPID5GH1_SHIFT; +- bus->sprom.txpid5gh[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] & +- SSB_SPROM4_TXPID5GH2) >> SSB_SPROM4_TXPID5GH2_SHIFT; +- bus->sprom.txpid5gh[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] & +- SSB_SPROM4_TXPID5GH3) >> SSB_SPROM4_TXPID5GH3_SHIFT; +- +- bus->sprom.boardflags_lo = sprom[SPOFF(SSB_SPROM8_BFLLO)]; +- bus->sprom.boardflags_hi = sprom[SPOFF(SSB_SPROM8_BFLHI)]; +- bus->sprom.boardflags2_lo = sprom[SPOFF(SSB_SPROM8_BFL2LO)]; +- bus->sprom.boardflags2_hi = sprom[SPOFF(SSB_SPROM8_BFL2HI)]; +- +- bus->sprom.country_code = sprom[SPOFF(SSB_SPROM8_CCODE)]; +- +- bus->sprom.fem.ghz2.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM2G)] & +- SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT; +- bus->sprom.fem.ghz2.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM2G)] & +- SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT; +- bus->sprom.fem.ghz2.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM2G)] & +- SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT; +- bus->sprom.fem.ghz2.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM2G)] & +- SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT; +- bus->sprom.fem.ghz2.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM2G)] & +- SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT; +- +- bus->sprom.fem.ghz5.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM5G)] & +- SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT; +- bus->sprom.fem.ghz5.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM5G)] & +- SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT; +- bus->sprom.fem.ghz5.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM5G)] & +- SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT; +- bus->sprom.fem.ghz5.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM5G)] & +- SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT; +- bus->sprom.fem.ghz5.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM5G)] & +- SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT; ++ SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TSSIPOS, ++ SSB_SROM8_FEM_TSSIPOS_SHIFT); ++ SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_EXTPA_GAIN, ++ SSB_SROM8_FEM_EXTPA_GAIN_SHIFT); ++ SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_PDET_RANGE, ++ SSB_SROM8_FEM_PDET_RANGE_SHIFT); ++ SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TR_ISO, ++ SSB_SROM8_FEM_TR_ISO_SHIFT); ++ SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_ANTSWLUT, ++ SSB_SROM8_FEM_ANTSWLUT_SHIFT); ++ ++ SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TSSIPOS, ++ SSB_SROM8_FEM_TSSIPOS_SHIFT); ++ SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_EXTPA_GAIN, ++ SSB_SROM8_FEM_EXTPA_GAIN_SHIFT); ++ SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_PDET_RANGE, ++ SSB_SROM8_FEM_PDET_RANGE_SHIFT); ++ SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TR_ISO, ++ SSB_SROM8_FEM_TR_ISO_SHIFT); ++ SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_ANTSWLUT, ++ SSB_SROM8_FEM_ANTSWLUT_SHIFT); ++ ++ SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A, ++ SSB_SPROM8_ANTAVAIL_A_SHIFT); ++ SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG, ++ SSB_SPROM8_ANTAVAIL_BG_SHIFT); ++ SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0); ++ SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG, ++ SSB_SPROM8_ITSSI_BG_SHIFT); ++ SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0); ++ SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A, ++ SSB_SPROM8_ITSSI_A_SHIFT); ++ SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0); ++ SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK, ++ SSB_SPROM8_MAXP_AL_SHIFT); ++ SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0); ++ SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1, ++ SSB_SPROM8_GPIOA_P1_SHIFT); ++ SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0); ++ SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3, ++ SSB_SPROM8_GPIOB_P3_SHIFT); ++ SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0); ++ SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G, ++ SSB_SPROM8_TRI5G_SHIFT); ++ SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0); ++ SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH, ++ SSB_SPROM8_TRI5GH_SHIFT); ++ SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, ++ SSB_SPROM8_RXPO2G_SHIFT); ++ SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G, ++ SSB_SPROM8_RXPO5G_SHIFT); ++ SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0); ++ SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G, ++ SSB_SPROM8_RSSISMC2G_SHIFT); ++ SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G, ++ SSB_SPROM8_RSSISAV2G_SHIFT); ++ SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G, ++ SSB_SPROM8_BXA2G_SHIFT); ++ SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0); ++ SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G, ++ SSB_SPROM8_RSSISMC5G_SHIFT); ++ SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G, ++ SSB_SPROM8_RSSISAV5G_SHIFT); ++ SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G, ++ SSB_SPROM8_BXA5G_SHIFT); ++ ++ SPEX(pa0b0, SSB_SPROM8_PA0B0, ~0, 0); ++ SPEX(pa0b1, SSB_SPROM8_PA0B1, ~0, 0); ++ SPEX(pa0b2, SSB_SPROM8_PA0B2, ~0, 0); ++ SPEX(pa1b0, SSB_SPROM8_PA1B0, ~0, 0); ++ SPEX(pa1b1, SSB_SPROM8_PA1B1, ~0, 0); ++ SPEX(pa1b2, SSB_SPROM8_PA1B2, ~0, 0); ++ SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, ~0, 0); ++ SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, ~0, 0); ++ SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, ~0, 0); ++ SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, ~0, 0); ++ SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, ~0, 0); ++ SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, ~0, 0); ++ SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, ~0, 0); ++ SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, ~0, 0); ++ SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, ~0, 0); ++ SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, ~0, 0); ++ SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0); ++ ++ /* Extract the antenna gain values. */ ++ SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01, ++ SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT); ++ SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01, ++ SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT); ++ SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23, ++ SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT); ++ SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23, ++ SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT); ++ ++ SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON, ++ SSB_SPROM8_LEDDC_ON_SHIFT); ++ SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF, ++ SSB_SPROM8_LEDDC_OFF_SHIFT); ++ ++ SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN, ++ SSB_SPROM8_TXRXC_TXCHAIN_SHIFT); ++ SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN, ++ SSB_SPROM8_TXRXC_RXCHAIN_SHIFT); ++ SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH, ++ SSB_SPROM8_TXRXC_SWITCH_SHIFT); ++ ++ SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0); ++ ++ SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0); ++ SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0); ++ SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0); ++ SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0); ++ ++ SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP, ++ SSB_SPROM8_RAWTS_RAWTEMP_SHIFT); ++ SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER, ++ SSB_SPROM8_RAWTS_MEASPOWER_SHIFT); ++ SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX, ++ SSB_SPROM8_OPT_CORRX_TEMP_SLOPE, ++ SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT); ++ SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX, ++ SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT); ++ SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX, ++ SSB_SPROM8_OPT_CORRX_TEMP_OPTION, ++ SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT); ++ SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP, ++ SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR, ++ SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT); ++ SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP, ++ SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP, ++ SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT); ++ SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL, ++ SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT); ++ ++ SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0); ++ SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0); ++ SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0); ++ SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0); ++ ++ SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH, ++ SSB_SPROM8_THERMAL_TRESH_SHIFT); ++ SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET, ++ SSB_SPROM8_THERMAL_OFFSET_SHIFT); ++ SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA, ++ SSB_SPROM8_TEMPDELTA_PHYCAL, ++ SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT); ++ SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD, ++ SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT); ++ SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA, ++ SSB_SPROM8_TEMPDELTA_HYSTERESIS, ++ SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT); ++} ++ ++/* ++ * Indicates the presence of external SPROM. ++ */ ++static bool bcma_sprom_ext_available(struct bcma_bus *bus) ++{ ++ u32 chip_status; ++ u32 srom_control; ++ u32 present_mask; ++ ++ if (bus->drv_cc.core->id.rev >= 31) { ++ if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM)) ++ return false; ++ ++ srom_control = bcma_read32(bus->drv_cc.core, ++ BCMA_CC_SROM_CONTROL); ++ return srom_control & BCMA_CC_SROM_CONTROL_PRESENT; ++ } ++ ++ /* older chipcommon revisions use chip status register */ ++ chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT); ++ switch (bus->chipinfo.id) { ++ case BCMA_CHIP_ID_BCM4313: ++ present_mask = BCMA_CC_CHIPST_4313_SPROM_PRESENT; ++ break; ++ ++ case BCMA_CHIP_ID_BCM4331: ++ present_mask = BCMA_CC_CHIPST_4331_SPROM_PRESENT; ++ break; ++ ++ default: ++ return true; ++ } ++ ++ return chip_status & present_mask; ++} ++ ++/* ++ * Indicates that on-chip OTP memory is present and enabled. ++ */ ++static bool bcma_sprom_onchip_available(struct bcma_bus *bus) ++{ ++ u32 chip_status; ++ u32 otpsize = 0; ++ bool present; ++ ++ chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT); ++ switch (bus->chipinfo.id) { ++ case BCMA_CHIP_ID_BCM4313: ++ present = chip_status & BCMA_CC_CHIPST_4313_OTP_PRESENT; ++ break; ++ ++ case BCMA_CHIP_ID_BCM4331: ++ present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT; ++ break; ++ ++ case BCMA_CHIP_ID_BCM43224: ++ case BCMA_CHIP_ID_BCM43225: ++ /* for these chips OTP is always available */ ++ present = true; ++ break; ++ case BCMA_CHIP_ID_BCM43227: ++ case BCMA_CHIP_ID_BCM43228: ++ case BCMA_CHIP_ID_BCM43428: ++ present = chip_status & BCMA_CC_CHIPST_43228_OTP_PRESENT; ++ break; ++ default: ++ present = false; ++ break; ++ } ++ ++ if (present) { ++ otpsize = bus->drv_cc.capabilities & BCMA_CC_CAP_OTPS; ++ otpsize >>= BCMA_CC_CAP_OTPS_SHIFT; ++ } ++ ++ return otpsize != 0; ++} ++ ++/* ++ * Verify OTP is filled and determine the byte ++ * offset where SPROM data is located. ++ * ++ * On error, returns 0; byte offset otherwise. ++ */ ++static int bcma_sprom_onchip_offset(struct bcma_bus *bus) ++{ ++ struct bcma_device *cc = bus->drv_cc.core; ++ u32 offset; ++ ++ /* verify OTP status */ ++ if ((bcma_read32(cc, BCMA_CC_OTPS) & BCMA_CC_OTPS_GU_PROG_HW) == 0) ++ return 0; ++ ++ /* obtain bit offset from otplayout register */ ++ offset = (bcma_read32(cc, BCMA_CC_OTPL) & BCMA_CC_OTPL_GURGN_OFFSET); ++ return BCMA_CC_SPROM + (offset >> 3); + } + + int bcma_sprom_get(struct bcma_bus *bus) + { +- u16 offset; ++ u16 offset = BCMA_CC_SPROM; + u16 *sprom; + int err = 0; + + if (!bus->drv_cc.core) + return -EOPNOTSUPP; + +- if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM)) +- return -ENOENT; ++ if (!bcma_sprom_ext_available(bus)) { ++ bool sprom_onchip; ++ ++ /* ++ * External SPROM takes precedence so check ++ * on-chip OTP only when no external SPROM ++ * is present. ++ */ ++ sprom_onchip = bcma_sprom_onchip_available(bus); ++ if (sprom_onchip) { ++ /* determine offset */ ++ offset = bcma_sprom_onchip_offset(bus); ++ } ++ if (!offset || !sprom_onchip) { ++ /* ++ * Maybe there is no SPROM on the device? ++ * Now we ask the arch code if there is some sprom ++ * available for this device in some other storage. ++ */ ++ err = bcma_fill_sprom_with_fallback(bus, &bus->sprom); ++ return err; ++ } ++ } + + sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16), + GFP_KERNEL); + if (!sprom) + return -ENOMEM; + +- if (bus->chipinfo.id == 0x4331) ++ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 || ++ bus->chipinfo.id == BCMA_CHIP_ID_BCM43431) + bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false); + +- /* Most cards have SPROM moved by additional offset 0x30 (48 dwords). +- * According to brcm80211 this applies to cards with PCIe rev >= 6 +- * TODO: understand this condition and use it */ +- offset = (bus->chipinfo.id == 0x4331) ? BCMA_CC_SPROM : +- BCMA_CC_SPROM_PCIE6; ++ bcma_debug(bus, "SPROM offset 0x%x\n", offset); + bcma_sprom_read(bus, offset, sprom); + +- if (bus->chipinfo.id == 0x4331) ++ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 || ++ bus->chipinfo.id == BCMA_CHIP_ID_BCM43431) + bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true); + + err = bcma_sprom_valid(sprom); +- if (err) ++ if (err) { ++ bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n"); ++ err = bcma_fill_sprom_with_fallback(bus, &bus->sprom); + goto out; ++ } + + bcma_sprom_extract_r8(bus, sprom); + +--- a/include/linux/bcma/bcma.h ++++ b/include/linux/bcma/bcma.h +@@ -7,9 +7,10 @@ + #include <linux/bcma/bcma_driver_chipcommon.h> + #include <linux/bcma/bcma_driver_pci.h> + #include <linux/bcma/bcma_driver_mips.h> ++#include <linux/bcma/bcma_driver_gmac_cmn.h> + #include <linux/ssb/ssb.h> /* SPROM sharing */ + +-#include "bcma_regs.h" ++#include <linux/bcma/bcma_regs.h> + + struct bcma_device; + struct bcma_bus; +@@ -26,6 +27,11 @@ struct bcma_chipinfo { + u8 pkg; + }; + ++struct bcma_boardinfo { ++ u16 vendor; ++ u16 type; ++}; ++ + enum bcma_clkmode { + BCMA_CLKMODE_FAST, + BCMA_CLKMODE_DYNAMIC, +@@ -65,6 +71,13 @@ struct bcma_host_ops { + + /* Core-ID values. */ + #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */ ++#define BCMA_CORE_4706_CHIPCOMMON 0x500 ++#define BCMA_CORE_4706_SOC_RAM 0x50E ++#define BCMA_CORE_4706_MAC_GBIT 0x52D ++#define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */ ++#define BCMA_CORE_ALTA 0x534 /* I2S core */ ++#define BCMA_CORE_4706_MAC_GBIT_COMMON 0x5DC ++#define BCMA_CORE_DDR23_PHY 0x5DD + #define BCMA_CORE_INVALID 0x700 + #define BCMA_CORE_CHIPCOMMON 0x800 + #define BCMA_CORE_ILINE20 0x801 +@@ -125,6 +138,41 @@ struct bcma_host_ops { + + #define BCMA_MAX_NR_CORES 16 + ++/* Chip IDs of PCIe devices */ ++#define BCMA_CHIP_ID_BCM4313 0x4313 ++#define BCMA_CHIP_ID_BCM43224 43224 ++#define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8 ++#define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa ++#define BCMA_CHIP_ID_BCM43225 43225 ++#define BCMA_CHIP_ID_BCM43227 43227 ++#define BCMA_CHIP_ID_BCM43228 43228 ++#define BCMA_CHIP_ID_BCM43421 43421 ++#define BCMA_CHIP_ID_BCM43428 43428 ++#define BCMA_CHIP_ID_BCM43431 43431 ++#define BCMA_CHIP_ID_BCM43460 43460 ++#define BCMA_CHIP_ID_BCM4331 0x4331 ++#define BCMA_CHIP_ID_BCM6362 0x6362 ++#define BCMA_CHIP_ID_BCM4360 0x4360 ++#define BCMA_CHIP_ID_BCM4352 0x4352 ++ ++/* Chip IDs of SoCs */ ++#define BCMA_CHIP_ID_BCM4706 0x5300 ++#define BCMA_PKG_ID_BCM4706L 1 ++#define BCMA_CHIP_ID_BCM4716 0x4716 ++#define BCMA_PKG_ID_BCM4716 8 ++#define BCMA_PKG_ID_BCM4717 9 ++#define BCMA_PKG_ID_BCM4718 10 ++#define BCMA_CHIP_ID_BCM47162 47162 ++#define BCMA_CHIP_ID_BCM4748 0x4748 ++#define BCMA_CHIP_ID_BCM4749 0x4749 ++#define BCMA_CHIP_ID_BCM5356 0x5356 ++#define BCMA_CHIP_ID_BCM5357 0x5357 ++#define BCMA_PKG_ID_BCM5358 9 ++#define BCMA_PKG_ID_BCM47186 10 ++#define BCMA_PKG_ID_BCM5357 11 ++#define BCMA_CHIP_ID_BCM53572 53572 ++#define BCMA_PKG_ID_BCM47188 9 ++ + struct bcma_device { + struct bcma_bus *bus; + struct bcma_device_id id; +@@ -136,8 +184,10 @@ struct bcma_device { + bool dev_registered; + + u8 core_index; ++ u8 core_unit; + + u32 addr; ++ u32 addr1; + u32 wrap; + + void __iomem *io_addr; +@@ -175,6 +225,12 @@ int __bcma_driver_register(struct bcma_d + + extern void bcma_driver_unregister(struct bcma_driver *drv); + ++/* Set a fallback SPROM. ++ * See kdoc at the function definition for complete documentation. */ ++extern int bcma_arch_register_fallback_sprom( ++ int (*sprom_callback)(struct bcma_bus *bus, ++ struct ssb_sprom *out)); ++ + struct bcma_bus { + /* The MMIO area. */ + void __iomem *mmio; +@@ -191,14 +247,18 @@ struct bcma_bus { + + struct bcma_chipinfo chipinfo; + ++ struct bcma_boardinfo boardinfo; ++ + struct bcma_device *mapped_core; + struct list_head cores; + u8 nr_cores; + u8 init_done:1; ++ u8 num; + + struct bcma_drv_cc drv_cc; +- struct bcma_drv_pci drv_pci; ++ struct bcma_drv_pci drv_pci[2]; + struct bcma_drv_mips drv_mips; ++ struct bcma_drv_gmac_cmn drv_gmac_cmn; + + /* We decided to share SPROM struct with SSB as long as we do not need + * any hacks for BCMA. This simplifies drivers code. */ +@@ -282,6 +342,7 @@ static inline void bcma_maskset16(struct + bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set); + } + ++extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid); + extern bool bcma_core_is_enabled(struct bcma_device *core); + extern void bcma_core_disable(struct bcma_device *core, u32 flags); + extern int bcma_core_enable(struct bcma_device *core, u32 flags); +@@ -289,6 +350,7 @@ extern void bcma_core_set_clockmode(stru + enum bcma_clkmode clkmode); + extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status, + bool on); ++extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset); + #define BCMA_DMA_TRANSLATION_MASK 0xC0000000 + #define BCMA_DMA_TRANSLATION_NONE 0x00000000 + #define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */ +--- a/include/linux/bcma/bcma_driver_chipcommon.h ++++ b/include/linux/bcma/bcma_driver_chipcommon.h +@@ -1,6 +1,9 @@ + #ifndef LINUX_BCMA_DRIVER_CC_H_ + #define LINUX_BCMA_DRIVER_CC_H_ + ++#include <linux/platform_device.h> ++#include <linux/gpio.h> ++ + /** ChipCommon core registers. **/ + #define BCMA_CC_ID 0x0000 + #define BCMA_CC_ID_ID 0x0000FFFF +@@ -24,7 +27,7 @@ + #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */ + #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */ + #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */ +-#define BCMA_CC_FLASHT_NFLASH 0x00000200 ++#define BCMA_CC_FLASHT_NFLASH 0x00000200 /* NAND flash */ + #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */ + #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */ + #define BCMA_PLLTYPE_NONE 0x00000000 +@@ -45,6 +48,7 @@ + #define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */ + #define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */ + #define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */ ++#define BCMA_CC_CAP_NFLASH 0x80000000 /* NAND flash present (rev >= 35 or BCM4706?) */ + #define BCMA_CC_CORECTL 0x0008 + #define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */ + #define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ +@@ -56,6 +60,9 @@ + #define BCMA_CC_OTPS_HW_PROTECT 0x00000001 + #define BCMA_CC_OTPS_SW_PROTECT 0x00000002 + #define BCMA_CC_OTPS_CID_PROTECT 0x00000004 ++#define BCMA_CC_OTPS_GU_PROG_IND 0x00000F00 /* General Use programmed indication */ ++#define BCMA_CC_OTPS_GU_PROG_IND_SHIFT 8 ++#define BCMA_CC_OTPS_GU_PROG_HW 0x00000100 /* HW region programmed */ + #define BCMA_CC_OTPC 0x0014 /* OTP control */ + #define BCMA_CC_OTPC_RECWAIT 0xFF000000 + #define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00 +@@ -72,6 +79,8 @@ + #define BCMA_CC_OTPP_READ 0x40000000 + #define BCMA_CC_OTPP_START 0x80000000 + #define BCMA_CC_OTPP_BUSY 0x80000000 ++#define BCMA_CC_OTPL 0x001C /* OTP layout */ ++#define BCMA_CC_OTPL_GURGN_OFFSET 0x00000FFF /* offset of general use region */ + #define BCMA_CC_IRQSTAT 0x0020 + #define BCMA_CC_IRQMASK 0x0024 + #define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */ +@@ -79,6 +88,22 @@ + #define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */ + #define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */ + #define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */ ++#define BCMA_CC_CHIPST_4313_SPROM_PRESENT 1 ++#define BCMA_CC_CHIPST_4313_OTP_PRESENT 2 ++#define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2 ++#define BCMA_CC_CHIPST_4331_OTP_PRESENT 4 ++#define BCMA_CC_CHIPST_43228_ILP_DIV_EN 0x00000001 ++#define BCMA_CC_CHIPST_43228_OTP_PRESENT 0x00000002 ++#define BCMA_CC_CHIPST_43228_SERDES_REFCLK_PADSEL 0x00000004 ++#define BCMA_CC_CHIPST_43228_SDIO_MODE 0x00000008 ++#define BCMA_CC_CHIPST_43228_SDIO_OTP_PRESENT 0x00000010 ++#define BCMA_CC_CHIPST_43228_SDIO_RESET 0x00000020 ++#define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */ ++#define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */ ++#define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */ ++#define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */ ++#define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */ ++#define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */ + #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */ + #define BCMA_CC_JCMD_START 0x80000000 + #define BCMA_CC_JCMD_BUSY 0x80000000 +@@ -108,10 +133,58 @@ + #define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */ + #define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */ + #define BCMA_CC_FLASHCTL 0x0040 ++/* Start/busy bit in flashcontrol */ ++#define BCMA_CC_FLASHCTL_OPCODE 0x000000ff ++#define BCMA_CC_FLASHCTL_ACTION 0x00000700 ++#define BCMA_CC_FLASHCTL_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */ + #define BCMA_CC_FLASHCTL_START 0x80000000 + #define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START ++/* Flashcontrol action + opcodes for ST flashes */ ++#define BCMA_CC_FLASHCTL_ST_WREN 0x0006 /* Write Enable */ ++#define BCMA_CC_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */ ++#define BCMA_CC_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */ ++#define BCMA_CC_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */ ++#define BCMA_CC_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */ ++#define BCMA_CC_FLASHCTL_ST_PP 0x0302 /* Page Program */ ++#define BCMA_CC_FLASHCTL_ST_SE 0x02d8 /* Sector Erase */ ++#define BCMA_CC_FLASHCTL_ST_BE 0x00c7 /* Bulk Erase */ ++#define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */ ++#define BCMA_CC_FLASHCTL_ST_RES 0x03ab /* Read Electronic Signature */ ++#define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */ ++#define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */ ++/* Flashcontrol action + opcodes for Atmel flashes */ ++#define BCMA_CC_FLASHCTL_AT_READ 0x07e8 ++#define BCMA_CC_FLASHCTL_AT_PAGE_READ 0x07d2 ++#define BCMA_CC_FLASHCTL_AT_STATUS 0x01d7 ++#define BCMA_CC_FLASHCTL_AT_BUF1_WRITE 0x0384 ++#define BCMA_CC_FLASHCTL_AT_BUF2_WRITE 0x0387 ++#define BCMA_CC_FLASHCTL_AT_BUF1_ERASE_PROGRAM 0x0283 ++#define BCMA_CC_FLASHCTL_AT_BUF2_ERASE_PROGRAM 0x0286 ++#define BCMA_CC_FLASHCTL_AT_BUF1_PROGRAM 0x0288 ++#define BCMA_CC_FLASHCTL_AT_BUF2_PROGRAM 0x0289 ++#define BCMA_CC_FLASHCTL_AT_PAGE_ERASE 0x0281 ++#define BCMA_CC_FLASHCTL_AT_BLOCK_ERASE 0x0250 ++#define BCMA_CC_FLASHCTL_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382 ++#define BCMA_CC_FLASHCTL_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385 ++#define BCMA_CC_FLASHCTL_AT_BUF1_LOAD 0x0253 ++#define BCMA_CC_FLASHCTL_AT_BUF2_LOAD 0x0255 ++#define BCMA_CC_FLASHCTL_AT_BUF1_COMPARE 0x0260 ++#define BCMA_CC_FLASHCTL_AT_BUF2_COMPARE 0x0261 ++#define BCMA_CC_FLASHCTL_AT_BUF1_REPROGRAM 0x0258 ++#define BCMA_CC_FLASHCTL_AT_BUF2_REPROGRAM 0x0259 + #define BCMA_CC_FLASHADDR 0x0044 + #define BCMA_CC_FLASHDATA 0x0048 ++/* Status register bits for ST flashes */ ++#define BCMA_CC_FLASHDATA_ST_WIP 0x01 /* Write In Progress */ ++#define BCMA_CC_FLASHDATA_ST_WEL 0x02 /* Write Enable Latch */ ++#define BCMA_CC_FLASHDATA_ST_BP_MASK 0x1c /* Block Protect */ ++#define BCMA_CC_FLASHDATA_ST_BP_SHIFT 2 ++#define BCMA_CC_FLASHDATA_ST_SRWD 0x80 /* Status Register Write Disable */ ++/* Status register bits for Atmel flashes */ ++#define BCMA_CC_FLASHDATA_AT_READY 0x80 ++#define BCMA_CC_FLASHDATA_AT_MISMATCH 0x40 ++#define BCMA_CC_FLASHDATA_AT_ID_MASK 0x38 ++#define BCMA_CC_FLASHDATA_AT_ID_SHIFT 3 + #define BCMA_CC_BCAST_ADDR 0x0050 + #define BCMA_CC_BCAST_DATA 0x0054 + #define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */ +@@ -181,6 +254,45 @@ + #define BCMA_CC_FLASH_CFG 0x0128 + #define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */ + #define BCMA_CC_FLASH_WAITCNT 0x012C ++#define BCMA_CC_SROM_CONTROL 0x0190 ++#define BCMA_CC_SROM_CONTROL_START 0x80000000 ++#define BCMA_CC_SROM_CONTROL_BUSY 0x80000000 ++#define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000 ++#define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000 ++#define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000 ++#define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000 ++#define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000 ++#define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010 ++#define BCMA_CC_SROM_CONTROL_LOCK 0x00000008 ++#define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006 ++#define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000 ++#define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002 ++#define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004 ++#define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1 ++#define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001 ++/* Block 0x140 - 0x190 registers are chipset specific */ ++#define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */ ++#define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff ++#define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */ ++#define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */ ++#define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */ ++#define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */ ++#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0 ++#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */ ++#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */ ++#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */ ++#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */ ++#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */ ++#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */ ++#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */ ++/* NAND flash registers for BCM4706 (corerev = 31) */ ++#define BCMA_CC_NFLASH_CTL 0x01A0 ++#define BCMA_CC_NFLASH_CTL_ERR 0x08000000 ++#define BCMA_CC_NFLASH_CONF 0x01A4 ++#define BCMA_CC_NFLASH_COL_ADDR 0x01A8 ++#define BCMA_CC_NFLASH_ROW_ADDR 0x01AC ++#define BCMA_CC_NFLASH_DATA 0x01B0 ++#define BCMA_CC_NFLASH_WAITCNT0 0x01B4 + /* 0x1E0 is defined as shared BCMA_CLKCTLST */ + #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */ + #define BCMA_CC_UART0_DATA 0x0300 +@@ -240,7 +352,60 @@ + #define BCMA_CC_PLLCTL_ADDR 0x0660 + #define BCMA_CC_PLLCTL_DATA 0x0664 + #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */ +-#define BCMA_CC_SPROM_PCIE6 0x0830 /* SPROM beginning on PCIe rev >= 6 */ ++/* NAND flash MLC controller registers (corerev >= 38) */ ++#define BCMA_CC_NAND_REVISION 0x0C00 ++#define BCMA_CC_NAND_CMD_START 0x0C04 ++#define BCMA_CC_NAND_CMD_ADDR_X 0x0C08 ++#define BCMA_CC_NAND_CMD_ADDR 0x0C0C ++#define BCMA_CC_NAND_CMD_END_ADDR 0x0C10 ++#define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14 ++#define BCMA_CC_NAND_CS_NAND_XOR 0x0C18 ++#define BCMA_CC_NAND_SPARE_RD0 0x0C20 ++#define BCMA_CC_NAND_SPARE_RD4 0x0C24 ++#define BCMA_CC_NAND_SPARE_RD8 0x0C28 ++#define BCMA_CC_NAND_SPARE_RD12 0x0C2C ++#define BCMA_CC_NAND_SPARE_WR0 0x0C30 ++#define BCMA_CC_NAND_SPARE_WR4 0x0C34 ++#define BCMA_CC_NAND_SPARE_WR8 0x0C38 ++#define BCMA_CC_NAND_SPARE_WR12 0x0C3C ++#define BCMA_CC_NAND_ACC_CONTROL 0x0C40 ++#define BCMA_CC_NAND_CONFIG 0x0C48 ++#define BCMA_CC_NAND_TIMING_1 0x0C50 ++#define BCMA_CC_NAND_TIMING_2 0x0C54 ++#define BCMA_CC_NAND_SEMAPHORE 0x0C58 ++#define BCMA_CC_NAND_DEVID 0x0C60 ++#define BCMA_CC_NAND_DEVID_X 0x0C64 ++#define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68 ++#define BCMA_CC_NAND_INTFC_STATUS 0x0C6C ++#define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70 ++#define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74 ++#define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78 ++#define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C ++#define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80 ++#define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84 ++#define BCMA_CC_NAND_READ_ADDR_X 0x0C90 ++#define BCMA_CC_NAND_READ_ADDR 0x0C94 ++#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98 ++#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C ++#define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0 ++#define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4 ++#define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8 ++#define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC ++#define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0 ++#define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4 ++#define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0 ++#define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0 ++#define BCMA_CC_NAND_CONFIG_CS1 0x0CD4 ++#define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8 ++#define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC ++#define BCMA_CC_NAND_SPARE_RD16 0x0D30 ++#define BCMA_CC_NAND_SPARE_RD20 0x0D34 ++#define BCMA_CC_NAND_SPARE_RD24 0x0D38 ++#define BCMA_CC_NAND_SPARE_RD28 0x0D3C ++#define BCMA_CC_NAND_CACHE_ADDR 0x0D40 ++#define BCMA_CC_NAND_CACHE_DATA 0x0D44 ++#define BCMA_CC_NAND_CTRL_CONFIG 0x0D48 ++#define BCMA_CC_NAND_CTRL_STATUS 0x0D4C + + /* Divider allocation in 4716/47162/5356 */ + #define BCMA_CC_PMU5_MAINPLL_CPU 1 +@@ -256,6 +421,15 @@ + + /* 4706 PMU */ + #define BCMA_CC_PMU4706_MAINPLL_PLL0 0 ++#define BCMA_CC_PMU6_4706_PROCPLL_OFF 4 /* The CPU PLL */ ++#define BCMA_CC_PMU6_4706_PROC_P2DIV_MASK 0x000f0000 ++#define BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT 16 ++#define BCMA_CC_PMU6_4706_PROC_P1DIV_MASK 0x0000f000 ++#define BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT 12 ++#define BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8 ++#define BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT 3 ++#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007 ++#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0 + + /* ALP clock on pre-PMU chips */ + #define BCMA_CC_PMU_ALP_CLOCK 20000000 +@@ -284,6 +458,19 @@ + #define BCMA_CC_PPL_PCHI_OFF 5 + #define BCMA_CC_PPL_PCHI_MASK 0x0000003f + ++#define BCMA_CC_PMU_PLL_CTL0 0 ++#define BCMA_CC_PMU_PLL_CTL1 1 ++#define BCMA_CC_PMU_PLL_CTL2 2 ++#define BCMA_CC_PMU_PLL_CTL3 3 ++#define BCMA_CC_PMU_PLL_CTL4 4 ++#define BCMA_CC_PMU_PLL_CTL5 5 ++ ++#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 ++#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT 20 ++ ++#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 ++#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 ++ + /* BCM4331 ChipControl numbers. */ + #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */ + #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */ +@@ -297,9 +484,25 @@ + #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */ + #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */ + #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */ ++#define BCMA_CHIPCTL_4331_EXTPA_EN2 BIT(12) /* 0 ext pa disable, 1 ext pa enabled */ + #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */ + #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */ + ++/* 43224 chip-specific ChipControl register bits */ ++#define BCMA_CCTRL_43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */ ++#define BCMA_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */ ++#define BCMA_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */ ++ ++/* 4313 Chip specific ChipControl register bits */ ++#define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ ++ ++/* BCM5357 ChipControl register bits */ ++#define BCMA_CHIPCTL_5357_EXTPA BIT(14) ++#define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15) ++#define BCMA_CHIPCTL_5357_NFLASH BIT(16) ++#define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18) ++#define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19) ++ + /* Data for the PMU, if available. + * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU) + */ +@@ -310,11 +513,35 @@ struct bcma_chipcommon_pmu { + + #ifdef CONFIG_BCMA_DRIVER_MIPS + struct bcma_pflash { ++ bool present; + u8 buswidth; + u32 window; + u32 window_size; + }; + ++#ifdef CONFIG_BCMA_SFLASH ++struct bcma_sflash { ++ bool present; ++ u32 window; ++ u32 blocksize; ++ u16 numblocks; ++ u32 size; ++ ++ struct mtd_info *mtd; ++}; ++#endif ++ ++#ifdef CONFIG_BCMA_NFLASH ++struct mtd_info; ++ ++struct bcma_nflash { ++ bool present; ++ bool boot; /* This is the flash the SoC boots from */ ++ ++ struct mtd_info *mtd; ++}; ++#endif ++ + struct bcma_serial_port { + void *regs; + unsigned long clockspeed; +@@ -330,15 +557,30 @@ struct bcma_drv_cc { + u32 capabilities; + u32 capabilities_ext; + u8 setup_done:1; ++ u8 early_setup_done:1; + /* Fast Powerup Delay constant */ + u16 fast_pwrup_delay; + struct bcma_chipcommon_pmu pmu; + #ifdef CONFIG_BCMA_DRIVER_MIPS + struct bcma_pflash pflash; ++#ifdef CONFIG_BCMA_SFLASH ++ struct bcma_sflash sflash; ++#endif ++#ifdef CONFIG_BCMA_NFLASH ++ struct bcma_nflash nflash; ++#endif + + int nr_serial_ports; + struct bcma_serial_port serial_ports[4]; + #endif /* CONFIG_BCMA_DRIVER_MIPS */ ++ u32 ticks_per_ms; ++ struct platform_device *watchdog; ++ ++ /* Lock for GPIO register access. */ ++ spinlock_t gpio_lock; ++#ifdef CONFIG_BCMA_DRIVER_GPIO ++ struct gpio_chip gpio; ++#endif + }; + + /* Register access */ +@@ -355,14 +597,14 @@ struct bcma_drv_cc { + bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set)) + + extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc); ++extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc); + + extern void bcma_chipco_suspend(struct bcma_drv_cc *cc); + extern void bcma_chipco_resume(struct bcma_drv_cc *cc); + + void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable); + +-extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, +- u32 ticks); ++extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks); + + void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); + +@@ -375,9 +617,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d + u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value); + u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value); + u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value); ++u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value); ++u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value); + + /* PMU support */ + extern void bcma_pmu_init(struct bcma_drv_cc *cc); ++extern void bcma_pmu_early_init(struct bcma_drv_cc *cc); + + extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, + u32 value); +@@ -387,5 +632,6 @@ extern void bcma_chipco_chipctl_maskset( + u32 offset, u32 mask, u32 set); + extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, + u32 offset, u32 mask, u32 set); ++extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid); + + #endif /* LINUX_BCMA_DRIVER_CC_H_ */ +--- /dev/null ++++ b/include/linux/bcma/bcma_driver_gmac_cmn.h +@@ -0,0 +1,100 @@ ++#ifndef LINUX_BCMA_DRIVER_GMAC_CMN_H_ ++#define LINUX_BCMA_DRIVER_GMAC_CMN_H_ ++ ++#include <linux/types.h> ++ ++#define BCMA_GMAC_CMN_STAG0 0x000 ++#define BCMA_GMAC_CMN_STAG1 0x004 ++#define BCMA_GMAC_CMN_STAG2 0x008 ++#define BCMA_GMAC_CMN_STAG3 0x00C ++#define BCMA_GMAC_CMN_PARSER_CTL 0x020 ++#define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024 ++#define BCMA_GMAC_CMN_PHY_ACCESS 0x100 ++#define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff ++#define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000 ++#define BCMA_GMAC_CMN_PA_ADDR_SHIFT 16 ++#define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000 ++#define BCMA_GMAC_CMN_PA_REG_SHIFT 24 ++#define BCMA_GMAC_CMN_PA_WRITE 0x20000000 ++#define BCMA_GMAC_CMN_PA_START 0x40000000 ++#define BCMA_GMAC_CMN_PHY_CTL 0x104 ++#define BCMA_GMAC_CMN_PC_EPA_MASK 0x0000001f ++#define BCMA_GMAC_CMN_PC_MCT_MASK 0x007f0000 ++#define BCMA_GMAC_CMN_PC_MCT_SHIFT 16 ++#define BCMA_GMAC_CMN_PC_MTE 0x00800000 ++#define BCMA_GMAC_CMN_GMAC0_RGMII_CTL 0x110 ++#define BCMA_GMAC_CMN_CFP_ACCESS 0x200 ++#define BCMA_GMAC_CMN_CFP_TCAM_DATA0 0x210 ++#define BCMA_GMAC_CMN_CFP_TCAM_DATA1 0x214 ++#define BCMA_GMAC_CMN_CFP_TCAM_DATA2 0x218 ++#define BCMA_GMAC_CMN_CFP_TCAM_DATA3 0x21C ++#define BCMA_GMAC_CMN_CFP_TCAM_DATA4 0x220 ++#define BCMA_GMAC_CMN_CFP_TCAM_DATA5 0x224 ++#define BCMA_GMAC_CMN_CFP_TCAM_DATA6 0x228 ++#define BCMA_GMAC_CMN_CFP_TCAM_DATA7 0x22C ++#define BCMA_GMAC_CMN_CFP_TCAM_MASK0 0x230 ++#define BCMA_GMAC_CMN_CFP_TCAM_MASK1 0x234 ++#define BCMA_GMAC_CMN_CFP_TCAM_MASK2 0x238 ++#define BCMA_GMAC_CMN_CFP_TCAM_MASK3 0x23C ++#define BCMA_GMAC_CMN_CFP_TCAM_MASK4 0x240 ++#define BCMA_GMAC_CMN_CFP_TCAM_MASK5 0x244 ++#define BCMA_GMAC_CMN_CFP_TCAM_MASK6 0x248 ++#define BCMA_GMAC_CMN_CFP_TCAM_MASK7 0x24C ++#define BCMA_GMAC_CMN_CFP_ACTION_DATA 0x250 ++#define BCMA_GMAC_CMN_TCAM_BIST_CTL 0x2A0 ++#define BCMA_GMAC_CMN_TCAM_BIST_STATUS 0x2A4 ++#define BCMA_GMAC_CMN_TCAM_CMP_STATUS 0x2A8 ++#define BCMA_GMAC_CMN_TCAM_DISABLE 0x2AC ++#define BCMA_GMAC_CMN_TCAM_TEST_CTL 0x2F0 ++#define BCMA_GMAC_CMN_UDF_0_A3_A0 0x300 ++#define BCMA_GMAC_CMN_UDF_0_A7_A4 0x304 ++#define BCMA_GMAC_CMN_UDF_0_A8 0x308 ++#define BCMA_GMAC_CMN_UDF_1_A3_A0 0x310 ++#define BCMA_GMAC_CMN_UDF_1_A7_A4 0x314 ++#define BCMA_GMAC_CMN_UDF_1_A8 0x318 ++#define BCMA_GMAC_CMN_UDF_2_A3_A0 0x320 ++#define BCMA_GMAC_CMN_UDF_2_A7_A4 0x324 ++#define BCMA_GMAC_CMN_UDF_2_A8 0x328 ++#define BCMA_GMAC_CMN_UDF_0_B3_B0 0x330 ++#define BCMA_GMAC_CMN_UDF_0_B7_B4 0x334 ++#define BCMA_GMAC_CMN_UDF_0_B8 0x338 ++#define BCMA_GMAC_CMN_UDF_1_B3_B0 0x340 ++#define BCMA_GMAC_CMN_UDF_1_B7_B4 0x344 ++#define BCMA_GMAC_CMN_UDF_1_B8 0x348 ++#define BCMA_GMAC_CMN_UDF_2_B3_B0 0x350 ++#define BCMA_GMAC_CMN_UDF_2_B7_B4 0x354 ++#define BCMA_GMAC_CMN_UDF_2_B8 0x358 ++#define BCMA_GMAC_CMN_UDF_0_C3_C0 0x360 ++#define BCMA_GMAC_CMN_UDF_0_C7_C4 0x364 ++#define BCMA_GMAC_CMN_UDF_0_C8 0x368 ++#define BCMA_GMAC_CMN_UDF_1_C3_C0 0x370 ++#define BCMA_GMAC_CMN_UDF_1_C7_C4 0x374 ++#define BCMA_GMAC_CMN_UDF_1_C8 0x378 ++#define BCMA_GMAC_CMN_UDF_2_C3_C0 0x380 ++#define BCMA_GMAC_CMN_UDF_2_C7_C4 0x384 ++#define BCMA_GMAC_CMN_UDF_2_C8 0x388 ++#define BCMA_GMAC_CMN_UDF_0_D3_D0 0x390 ++#define BCMA_GMAC_CMN_UDF_0_D7_D4 0x394 ++#define BCMA_GMAC_CMN_UDF_0_D11_D8 0x394 ++ ++struct bcma_drv_gmac_cmn { ++ struct bcma_device *core; ++ ++ /* Drivers accessing BCMA_GMAC_CMN_PHY_ACCESS and ++ * BCMA_GMAC_CMN_PHY_CTL need to take that mutex first. */ ++ struct mutex phy_mutex; ++}; ++ ++/* Register access */ ++#define gmac_cmn_read16(gc, offset) bcma_read16((gc)->core, offset) ++#define gmac_cmn_read32(gc, offset) bcma_read32((gc)->core, offset) ++#define gmac_cmn_write16(gc, offset, val) bcma_write16((gc)->core, offset, val) ++#define gmac_cmn_write32(gc, offset, val) bcma_write32((gc)->core, offset, val) ++ ++#ifdef CONFIG_BCMA_DRIVER_GMAC_CMN ++extern void __devinit bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc); ++#else ++static inline void bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc) { } ++#endif ++ ++#endif /* LINUX_BCMA_DRIVER_GMAC_CMN_H_ */ +--- a/include/linux/bcma/bcma_driver_mips.h ++++ b/include/linux/bcma/bcma_driver_mips.h +@@ -35,13 +35,15 @@ struct bcma_device; + struct bcma_drv_mips { + struct bcma_device *core; + u8 setup_done:1; +- unsigned int assigned_irqs; ++ u8 early_setup_done:1; + }; + + #ifdef CONFIG_BCMA_DRIVER_MIPS + extern void bcma_core_mips_init(struct bcma_drv_mips *mcore); ++extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore); + #else + static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { } ++static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { } + #endif + + extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore); +--- a/include/linux/bcma/bcma_driver_pci.h ++++ b/include/linux/bcma/bcma_driver_pci.h +@@ -53,11 +53,47 @@ struct pci_dev; + #define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000 + #define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */ + #define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000 ++#define BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */ ++#define BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */ ++#define BCMA_CORE_PCI_MDIO_CONTROL 0x0128 /* controls the mdio access */ ++#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */ ++#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL 0x2 ++#define BCMA_CORE_PCI_MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */ ++#define BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */ ++#define BCMA_CORE_PCI_MDIO_DATA 0x012c /* Data to the mdio access */ ++#define BCMA_CORE_PCI_MDIODATA_MASK 0x0000ffff /* data 2 bytes */ ++#define BCMA_CORE_PCI_MDIODATA_TA 0x00020000 /* Turnaround */ ++#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */ ++#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */ ++#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */ ++#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */ ++#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF 18 /* Regaddr shift */ ++#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */ ++#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */ ++#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */ ++#define BCMA_CORE_PCI_MDIODATA_WRITE 0x10000000 /* write Transaction */ ++#define BCMA_CORE_PCI_MDIODATA_READ 0x20000000 /* Read Transaction */ ++#define BCMA_CORE_PCI_MDIODATA_START 0x40000000 /* start of Transaction */ ++#define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */ ++#define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */ ++#define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */ ++#define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */ ++#define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */ ++#define BCMA_CORE_PCI_PCIEIND_ADDR 0x0130 /* indirect access to the internal register */ ++#define BCMA_CORE_PCI_PCIEIND_DATA 0x0134 /* Data to/from the internal regsiter */ ++#define BCMA_CORE_PCI_CLKREQENCTRL 0x0138 /* >= rev 6, Clkreq rdma control */ + #define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */ + #define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */ + #define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */ + #define BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */ + #define BCMA_CORE_PCI_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */ ++#define BCMA_CORE_PCI_SPROM_PI_OFFSET 0 /* first word */ ++#define BCMA_CORE_PCI_SPROM_PI_MASK 0xf000 /* bit 15:12 */ ++#define BCMA_CORE_PCI_SPROM_PI_SHIFT 12 /* bit 15:12 */ ++#define BCMA_CORE_PCI_SPROM_MISC_CONFIG 5 /* word 5 */ ++#define BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST 0x8000 /* bit 15 */ ++#define BCMA_CORE_PCI_SPROM_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */ ++#define BCMA_CORE_PCI_SPROM_CLKREQ_ENB 0x0800 /* bit 11 */ + + /* SBtoPCIx */ + #define BCMA_CORE_PCI_SBTOPCI_MEM 0x00000000 +@@ -72,20 +108,118 @@ struct pci_dev; + #define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */ + #define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */ + ++/* PCIE protocol PHY diagnostic registers */ ++#define BCMA_CORE_PCI_PLP_MODEREG 0x200 /* Mode */ ++#define BCMA_CORE_PCI_PLP_STATUSREG 0x204 /* Status */ ++#define BCMA_CORE_PCI_PLP_POLARITYINV_STAT 0x10 /* Status reg PCIE_PLP_STATUSREG */ ++#define BCMA_CORE_PCI_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */ ++#define BCMA_CORE_PCI_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */ ++#define BCMA_CORE_PCI_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */ ++#define BCMA_CORE_PCI_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */ ++#define BCMA_CORE_PCI_PLP_ATTNREG 0x218 /* Attention */ ++#define BCMA_CORE_PCI_PLP_ATTNMASKREG 0x21C /* Attention Mask */ ++#define BCMA_CORE_PCI_PLP_RXERRCTR 0x220 /* Rx Error */ ++#define BCMA_CORE_PCI_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */ ++#define BCMA_CORE_PCI_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */ ++#define BCMA_CORE_PCI_PLP_TESTCTRLREG 0x22C /* Test Control reg */ ++#define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */ ++#define BCMA_CORE_PCI_PLP_TIMINGOVRDREG 0x234 /* Timing param override */ ++#define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */ ++#define BCMA_CORE_PCI_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */ ++ ++/* PCIE protocol DLLP diagnostic registers */ ++#define BCMA_CORE_PCI_DLLP_LCREG 0x100 /* Link Control */ ++#define BCMA_CORE_PCI_DLLP_LSREG 0x104 /* Link Status */ ++#define BCMA_CORE_PCI_DLLP_LAREG 0x108 /* Link Attention */ ++#define BCMA_CORE_PCI_DLLP_LSREG_LINKUP (1 << 16) ++#define BCMA_CORE_PCI_DLLP_LAMASKREG 0x10C /* Link Attention Mask */ ++#define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */ ++#define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */ ++#define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */ ++#define BCMA_CORE_PCI_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */ ++#define BCMA_CORE_PCI_DLLP_LRREG 0x120 /* Link Replay */ ++#define BCMA_CORE_PCI_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */ ++#define BCMA_CORE_PCI_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */ ++#define BCMA_CORE_PCI_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */ ++#define BCMA_CORE_PCI_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */ ++#define BCMA_CORE_PCI_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */ ++#define BCMA_CORE_PCI_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */ ++#define BCMA_CORE_PCI_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */ ++#define BCMA_CORE_PCI_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */ ++#define BCMA_CORE_PCI_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */ ++#define BCMA_CORE_PCI_DLLP_ERRCTRREG 0x144 /* Error Counter */ ++#define BCMA_CORE_PCI_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */ ++#define BCMA_CORE_PCI_DLLP_TESTREG 0x14C /* Test */ ++#define BCMA_CORE_PCI_DLLP_PKTBIST 0x150 /* Packet BIST */ ++#define BCMA_CORE_PCI_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */ ++ ++/* SERDES RX registers */ ++#define BCMA_CORE_PCI_SERDES_RX_CTRL 1 /* Rx cntrl */ ++#define BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */ ++#define BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */ ++#define BCMA_CORE_PCI_SERDES_RX_TIMER1 2 /* Rx Timer1 */ ++#define BCMA_CORE_PCI_SERDES_RX_CDR 6 /* CDR */ ++#define BCMA_CORE_PCI_SERDES_RX_CDRBW 7 /* CDR BW */ ++ ++/* SERDES PLL registers */ ++#define BCMA_CORE_PCI_SERDES_PLL_CTRL 1 /* PLL control reg */ ++#define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */ ++ + /* PCIcore specific boardflags */ + #define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */ + ++/* PCIE Config space accessing MACROS */ ++#define BCMA_CORE_PCI_CFG_BUS_SHIFT 24 /* Bus shift */ ++#define BCMA_CORE_PCI_CFG_SLOT_SHIFT 19 /* Slot/Device shift */ ++#define BCMA_CORE_PCI_CFG_FUN_SHIFT 16 /* Function shift */ ++#define BCMA_CORE_PCI_CFG_OFF_SHIFT 0 /* Register shift */ ++ ++#define BCMA_CORE_PCI_CFG_BUS_MASK 0xff /* Bus mask */ ++#define BCMA_CORE_PCI_CFG_SLOT_MASK 0x1f /* Slot/Device mask */ ++#define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */ ++#define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */ ++ ++/* PCIE Root Capability Register bits (Host mode only) */ ++#define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001 ++ ++struct bcma_drv_pci; ++ ++#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE ++struct bcma_drv_pci_host { ++ struct bcma_drv_pci *pdev; ++ ++ u32 host_cfg_addr; ++ spinlock_t cfgspace_lock; ++ ++ struct pci_controller pci_controller; ++ struct pci_ops pci_ops; ++ struct resource mem_resource; ++ struct resource io_resource; ++}; ++#endif ++ + struct bcma_drv_pci { + struct bcma_device *core; + u8 setup_done:1; ++ u8 hostmode:1; ++ ++#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE ++ struct bcma_drv_pci_host *host_controller; ++#endif + }; + + /* Register access */ ++#define pcicore_read16(pc, offset) bcma_read16((pc)->core, offset) + #define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset) ++#define pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val) + #define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val) + +-extern void bcma_core_pci_init(struct bcma_drv_pci *pc); ++extern void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc); + extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, + struct bcma_device *core, bool enable); ++extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend); ++ ++extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev); ++extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev); + + #endif /* LINUX_BCMA_DRIVER_PCI_H_ */ +--- a/include/linux/bcma/bcma_regs.h ++++ b/include/linux/bcma/bcma_regs.h +@@ -11,11 +11,13 @@ + #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */ + #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */ + #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */ ++#define BCMA_CLKCTLST_EXTRESREQ_SHIFT 8 + #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */ + #define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */ + #define BCMA_CLKCTLST_BP_ON_ALP 0x00040000 /* RO: running on ALP clock */ + #define BCMA_CLKCTLST_BP_ON_HT 0x00080000 /* RO: running on HT clock */ + #define BCMA_CLKCTLST_EXTRESST 0x07000000 /* Mask of external resource status */ ++#define BCMA_CLKCTLST_EXTRESST_SHIFT 24 + /* Is there any BCM4328 on BCMA bus? */ + #define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */ + #define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */ +@@ -56,4 +58,36 @@ + #define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */ + #define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */ + ++/* SiliconBackplane Address Map. ++ * All regions may not exist on all chips. ++ */ ++#define BCMA_SOC_SDRAM_BASE 0x00000000U /* Physical SDRAM */ ++#define BCMA_SOC_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */ ++#define BCMA_SOC_PCI_MEM_SZ (64 * 1024 * 1024) ++#define BCMA_SOC_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */ ++#define BCMA_SOC_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */ ++#define BCMA_SOC_SDRAM_R2 0x80000000U /* Region 2 for sdram (512 MB) */ ++ ++ ++#define BCMA_SOC_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */ ++#define BCMA_SOC_PCI_DMA2 0x80000000U /* Client Mode sb2pcitranslation2 (1 GB) */ ++#define BCMA_SOC_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */ ++#define BCMA_SOC_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2 ++ * (2 ZettaBytes), low 32 bits ++ */ ++#define BCMA_SOC_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2 ++ * (2 ZettaBytes), high 32 bits ++ */ ++ ++#define BCMA_SOC_PCI1_MEM 0x40000000U /* Host Mode sb2pcitranslation0 (64 MB) */ ++#define BCMA_SOC_PCI1_CFG 0x44000000U /* Host Mode sb2pcitranslation1 (64 MB) */ ++#define BCMA_SOC_PCIE1_DMA_H32 0xc0000000U /* PCIE Client Mode sb2pcitranslation2 ++ * (2 ZettaBytes), high 32 bits ++ */ ++ ++#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */ ++#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */ ++#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */ ++#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */ ++ + #endif /* LINUX_BCMA_REGS_H_ */ +--- a/drivers/net/wireless/b43/main.c ++++ b/drivers/net/wireless/b43/main.c +@@ -4618,7 +4618,7 @@ static int b43_wireless_core_init(struct + switch (dev->dev->bus_type) { + #ifdef CONFIG_B43_BCMA + case B43_BUS_BCMA: +- bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci, ++ bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0], + dev->dev->bdev, true); + break; + #endif +--- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c ++++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c +@@ -533,7 +533,7 @@ ai_buscore_setup(struct si_info *sii, st + + /* fixup necessary chip/core configurations */ + if (!sii->pch) { +- sii->pch = pcicore_init(&sii->pub, sii->icbus->drv_pci.core); ++ sii->pch = pcicore_init(&sii->pub, sii->icbus->drv_pci[0].core); + if (sii->pch == NULL) + return false; + } |