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diff --git a/target/linux/ar71xx/patches-3.8/.svn/entries b/target/linux/ar71xx/patches-3.8/.svn/entries
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@@ -0,0 +1,3734 @@
+10
+
+dir
+36060
+svn://svn.openwrt.org/openwrt/trunk/target/linux/ar71xx/patches-3.8
+svn://svn.openwrt.org/openwrt
+
+
+
+2013-03-15T14:39:51.655286Z
+36039
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+3c298f89-4303-0410-b956-a3cf2f4a3e73
+
+010-MIPS-pci-ar724x-convert-into-a-platform-driver.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+46b1582f07deb3c857a6f0f2bba20b94
+2013-03-04T11:48:08.614211Z
+35877
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+2671
+
+460-spi-bitbang-export-spi_bitbang_bufs.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+a5855d0c1ee5cb9597a6ac1dde62109b
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1073
+
+029-MIPS-ath79-add-SoC-detection-code-for-the-QCA955X-So.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+338c6b966023251aafe9db62e9a9a824
+2013-03-04T11:48:15.694775Z
+35878
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+3077
+
+310-lib-add-rle-decompression.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+7cf1d3edcb76a8e62964a07e045cee1b
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+2311
+
+011-MIPS-pci-ar71xx-convert-into-a-platform-driver.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+86b85b19b1dd9f40e0e79c41812f9e92
+2013-03-04T11:48:08.614211Z
+35877
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+3012
+
+404-mtd-wrt160nl-trx-parser.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+64d1cead7ece92f948cb3d504b8c0ee9
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+912
+
+522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+27e9580670896ba1946b795a06b38906
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+562
+
+601-MIPS-ath79-add-more-register-defines.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+1821b82feb713abe5605f80b0ff262f7
+2013-03-11T19:52:51.657695Z
+35965
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+12317
+
+039-watchdog-ath79_wdt-convert-to-use-devm_clk_get.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+a2238b4c2c9c9d7f8c1d7fdf12b7ae78
+2013-03-04T12:08:28.129931Z
+35879
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1315
+
+030-MIPS-ath79-add-clock-setup-code-for-the-QCA955X-SoCs.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+a4e65a505d4f0a9914376a075027815f
+2013-03-04T11:48:15.694775Z
+35878
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+6504
+
+615-MIPS-ath79-RB951G-support.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+bf71bd217d768c538ee12722113d539e
+2013-03-11T15:55:13.563652Z
+35957
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1804
+
+031-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+626caa3df212c8c196ef35e749b770f8
+2013-03-04T11:48:15.694775Z
+35878
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+7227
+
+038-MIPS-ath79-add-support-for-the-Qualcomm-Atheros-AP13.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+9365b1007b5092f9666ca810b1633c5e
+2013-03-04T11:48:15.694775Z
+35878
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+6923
+
+033-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+24cb55390ba26480f9e848bfe2099851
+2013-03-04T11:48:15.694775Z
+35878
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1814
+
+606-MIPS-ath79-pb44-fixes.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+9dcbacae570516e9bdfdf9b27701b62c
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+4039
+
+612-MIPS-ath79-add-DIR-825-C1-support.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+58a3c97b082a5906da5f22f42e207a1a
+2013-03-11T15:55:13.563652Z
+35957
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1645
+
+524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+2f48e7254c6f308dc3bd9f08259ff79c
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+751
+
+401-mtd-physmap-add-lock-unlock.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+3b48455d6ca012c83bfe62c92dfebe1a
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+2601
+
+508-MIPS-ath79-prom-image-command-line-hack.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+e3c98df384c0968f42ceb45a7a50c261
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1083
+
+420-net-ar71xx_mac_driver.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+347b8101962159049e4dc171e8d1327e
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+836
+
+403-mtd_fix_cfi_cmdset_0002_status_check.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+6e08394dfd33c98812cb708a763e7e71
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1624
+
+607-MIPS-ath79-ubnt-xm-fixes.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+176dfc8f0618e972d5bb0960a1d1fcc9
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+2740
+
+003-spi-ath79-remove-superfluous-chip-select-code.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+e0bfdc17550f3cbd5fb345d2c32ac06b
+2013-03-04T09:40:44.640743Z
+35873
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1012
+
+411-mtd-cfi_cmdset_0002-force-word-write.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+4d038206687dd947daf858639199da98
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1938
+
+008-MIPS-ath79-simplify-ath79_gpio_function_-routines.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+4ea22b182560f0caed82ab53cf88a9e7
+2013-03-04T11:48:04.269897Z
+35875
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+2068
+
+406-mtd-m25p80-allow-to-specify-max-read-size.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+77a7468f2f9ab21c0de8d59ef4ba588c
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+2798
+
+041-watchdog-ath79_wdt-get-register-base-from-platform-d.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+9d635ca807e2fa46833d06efc7e30f96
+2013-03-04T12:08:28.129931Z
+35879
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+4297
+
+004-spi-ath79-use-gpio_request_one.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+bcb39f0df9417e08461992073d1e9db5
+2013-03-04T09:40:44.640743Z
+35873
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1609
+
+441-leds-rb750-led-driver.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+288a7477ab1da155fe59ec16337c35c9
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+796
+
+520-MIPS-ath79-enable-UART-function.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+3003778e2a5910d61b464852c784515b
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+621
+
+408-mtd-redboot_partition_scan.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+3d9c3d00b34c78922328346b55ad3a64
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1233
+
+007-MIPS-ath79-fix-GPIO-function-selection-for-AR934x-So.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+18f80347a0507fc09dfe155673736d59
+2013-03-04T11:48:04.269897Z
+35875
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+3240
+
+502-MIPS-ath79-export-ath79_gpio_base.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+92c0fe8918d12ba0b0424b6fd66b2a0a
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+643
+
+432-spi-rb4xx-spi-driver.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+a08c30d03e425e129b5d4da256066971
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+831
+
+037-MIPS-ath79-add-USB-controller-registration-code-for-.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+5baea080cc6d02a455537eda62a4e430
+2013-03-04T11:48:15.694775Z
+35878
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+2047
+
+410-mtd-rb750-nand-driver.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+09d48ebc6012f79e4e47e234a27999ba
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+792
+
+509-MIPS-ath79-process-board-kernel-option.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+a05e4c93bf3faf17b1ba2f3091ad9818
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+268
+
+002-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+2a8040cfc8483e96edfe5ae75d5de5d1
+2013-03-04T09:40:44.640743Z
+35873
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1025
+
+027-MIPS-ath79-fix-WMAC-IRQ-resource-assignment.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+c8d05b12abdb60485c9f98b3d0e44905
+2013-03-04T11:48:15.694775Z
+35878
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1141
+
+431-spi-add-various-flags.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+2b17f16578166a37a5aa266c24087262
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+511
+
+461-spi-add-type-field-to-spi_transfer.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+70a2ad2c43a7d0e64e538d83ec0d6f62
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+571
+
+021-MIPS-pci-ar71xx-use-dynamically-allocated-PCI-contro.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+4292dcf658474849256315a5128968d9
+2013-03-04T11:48:08.614211Z
+35877
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+6951
+
+504-MIPS-ath79-add-ath79_device_reset_get.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+31d822ad5771e75d853cc8b5ac780287
+2013-03-04T11:48:15.694775Z
+35878
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1236
+
+902-unaligned_access_hacks.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+f5776d08d244c43f697dce71aaa2bcc2
+2013-03-03T13:58:52.105153Z
+35862
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+23376
+
+450-gpio-nxp-74hc153-gpio-chip-driver.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+b2a960cda376d44e39a1c228010ad199
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+874
+
+505-MIPS-ath79-add-ath79_gpio_function_select.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+941be9f4469aa7de7fc450b09d1b56f8
+2013-03-04T11:48:04.269897Z
+35875
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1167
+
+616-MIPS-ath79-TL-MR3420-v2-support.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+d5890406efb3ca063bc00be2425347c0
+2013-03-11T15:55:20.809371Z
+35961
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+954
+
+423-dsa-add-88e6063-driver.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+5829b5cf3fcd36af6b8e7213d26e996e
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+729
+
+013-MIPS-ath79-register-platform-devices-for-the-PCI-con.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+e5feada88a9a94bab0e042ba270d626a
+2013-03-04T11:48:08.614211Z
+35877
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+3568
+
+016-MIPS-ath79-allow-to-specify-bus-number-in-PCI-IRQ-ma.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+6ddda491c780fcb115c39ba677e7d498
+2013-03-04T11:48:08.614211Z
+35877
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1141
+
+433-spi-rb4xx-cpld-driver.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+9ff0f88da2de96f3f17f6c7944337434
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+901
+
+001-spi-ath79-add-delay-between-SCK-changes.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+40beff6ce90becd7d9217392f2ab02ab
+2013-03-04T09:40:44.640743Z
+35873
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+3382
+
+523-MIPS-ath79-OTP-support.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+eadf8cab07aa4be897aa34ed5a5fb549
+2013-03-04T11:48:15.694775Z
+35878
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+3716
+
+506-MIPS-ath79-prom-parse-redboot-args.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+de4266639caab9262a4adf4cb1bb4c64
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+2026
+
+025-ath79-remove-ATH79_MISC_IRQ_-defines.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+5436dfeeaf9ad2ba29819684d2354977
+2013-03-04T11:48:15.694775Z
+35878
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+2948
+
+470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+5d64d7a17b425347b1e11e7dae6a24e9
+2013-03-04T11:48:08.614211Z
+35877
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+3255
+
+613-MIPS-ath79-add-TL-WDR3500-support.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+98d848c7ad5d2c0aeff03085c6b89f6a
+2013-03-11T15:55:13.563652Z
+35957
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1580
+
+020-MIPS-pci-ar724x-setup-command-register-of-the-PCI-co.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+c1e1b5b56ef4dfce3ab67b1d5a2c4811
+2013-03-04T11:48:08.614211Z
+35877
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+4939
+
+023-MIPS-pci-ar71xx-move-irq-base-to-the-controller-stru.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+47e6c0b8a4ad06c1e351779a92097811
+2013-03-04T11:48:08.614211Z
+35877
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+3303
+
+434-spi-ap83_spi_controller.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+51ee6c241890d14388a5469e85152fae
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+900
+
+022-MIPS-pci-ar71xx-remove-static-PCI-IO-MEM-resources.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+780e85bee4023962aed392801b2d1677
+2013-03-04T11:48:08.614211Z
+35877
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+3302
+
+402-mtd-SST39VF6401B-support.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+c0c9af2af0f32bb0cf7f098ba2f34568
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+820
+
+012-MIPS-ath79-move-global-PCI-defines-into-a-common-hea.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+a1239bd850dc55f19687375ab009a6d9
+2013-03-04T11:48:08.614211Z
+35877
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+3367
+
+501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+aa80230098d41b10baf17a02c00da803
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+2500
+
+435-spi-vsc7385_driver.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+446203fde5b7b6d28f7d6f2d7a42a315
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+774
+
+507-MIPS-ath79-prom-add-myloader-support.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+37b68645d0dc8c71803b78bbb4a074c7
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1248
+
+440-leds-wndr3700-usb-led-driver.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+4ea234f6f5b15d47b95cb45d1108eefd
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+941
+
+032-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+5cb68bbe3a5625c49b276d2e1c5bbd7d
+2013-03-04T11:48:15.694775Z
+35878
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1772
+
+422-dsa-trailer-tag-validation-fix.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+856cd408513d6ea518c4a6718d03d9b4
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+390
+
+521-MIPS-ath79-enable-UART-for-early_serial.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+2be7d0711b7eada9b9a85a9c8c1091b2
+2013-03-04T11:48:15.694775Z
+35878
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1247
+
+407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+169b2b9a84124eb8ca47710ed8005ac2
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+763
+
+006-spi-ath79-add-shutdown-handler.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+d787e9e1cbd8ea10489de39ee3bd5964
+2013-03-04T09:40:44.640743Z
+35873
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1624
+
+608-MIPS-ath79-ubnt-xm-add-more-boards.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+2a760c5ffcbcd1feda7245f24787fa83
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+9430
+
+028-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+a8eecbd75bd768b8f4fb71841f980232
+2013-03-04T11:48:15.694775Z
+35878
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1532
+
+009-MIPS-ath79-simplify-MISC-IRQ-handling.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+0789baa929d64a65b6c7706ea91b44da
+2013-03-04T11:48:06.486048Z
+35876
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+2768
+
+901-mdio_bitbang_ignore_ta_value.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+d4052e34560198c749e3042bfe950de2
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+531
+
+014-MIPS-ath79-remove-unused-ar7-1x-24-x_pcibios_init-fu.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+325b2c25b0b9c37e6f88770cd87c7ae5
+2013-03-04T11:48:08.614211Z
+35877
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+4300
+
+206-spi-ath79-make-chipselect-logic-more-flexible.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+87f6c7bc77640e2f86801c3324105ff4
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+7964
+
+035-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+a6be38fe3ed1e63b1021f67400720321
+2013-03-04T11:48:15.694775Z
+35878
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+2532
+
+017-MIPS-pci-ar724x-use-dynamically-allocated-PCI-contro.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+c4db4c93534c4fc6f437f59dbf3de385
+2013-03-04T11:48:08.614211Z
+35877
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+8902
+
+510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+685e825cc39a20277d7d493eec396729
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+334
+
+019-MIPS-pci-ar724x-use-per-controller-IRQ-base.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+6d3d58ad2b4bd3337007d2dc21570ea7
+2013-03-04T11:48:08.614211Z
+35877
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+3443
+
+409-mtd-rb4xx_nand_driver.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+a949172423751e3ad7b34042e7c6f458
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+811
+
+609-MIPS-ath79-ap136-fixes.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+c6b3ea78dbacbb706cb0b7972fb1fcd4
+2013-03-04T11:48:15.694775Z
+35878
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+9174
+
+040-MIPS-ath79-use-dynamically-allocated-watchdog-device.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+d9539f010d6a3048dcb4fb9486a3e7b2
+2013-03-04T12:08:28.129931Z
+35879
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1062
+
+463-spi-ath79-add-fast-flash-read.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+bc1784d26ffd75d3682bfc2c4bbf1dd1
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+4682
+
+015-MIPS-avoid-possible-resource-conflict-in-register_pc.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+2b9c11a23853ac02e28f1bd6f474f231
+2013-03-04T11:48:08.614211Z
+35877
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1631
+
+213-MIPS-ath79-fix-ar933x-wmac-reset.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+903fc665ad3a935124408c85743bc5b9
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+645
+
+610-MIPS-ath79-openwrt-machines.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+7238f149bc7637970c97f332ab5b3f6a
+2013-03-03T21:59:34.159649Z
+35865
+luka
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+26262
+
+413-mtd-ar934x-nand-driver.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+3dce752297574bded67da09812f66c96
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+831
+
+430-drivers-link-spi-before-mtd.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+45d3248c438dafd5fd93fdc6b9363bfe
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+335
+
+026-MIPS-ath79-use-dynamically-allocated-USB-platform-de.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+89d0098db98e4b4603ad3bee04468657
+2013-03-04T11:48:15.694775Z
+35878
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+6698
+
+604-MIPS-ath79-ap81-fixes.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+41c09041f48fd766693bacb37bffd561
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+3150
+
+605-MIPS-ath79-db120-fixes.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+4735e2e745265f923e294c4035d245a2
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+5825
+
+220-add_cpu_feature_overrides.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+b45819602942dcf1ac8939ddf441c728
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+770
+
+503-MIPS-ath79-add-flash-acquire-release.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+284e6a1973f4920a2641dc0961493448
+2013-03-04T11:48:15.694775Z
+35878
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+996
+
+018-MIPS-pci-ar724x-remove-static-PCI-IO-MEM-resources.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+13cbc3a3fe68d2aa46512c4802658ba8
+2013-03-04T11:48:08.614211Z
+35877
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+4175
+
+614-MIPS-ath79-MR600v2-support.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+31b0e0b4382c27c14203fef45e03c3f4
+2013-03-11T15:55:13.563652Z
+35957
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+438
+
+500-MIPS-fw-myloader.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+ad3d13f7468a59e4fc235e7e7cc0d56b
+2013-03-15T14:39:51.655286Z
+36039
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+484
+
+005-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+b9ec6385fc5a240388aa0ca91a862c80
+2013-03-04T09:40:44.640743Z
+35873
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+3167
+
+024-ath79-add-ATH79_CPU_IRQ-macro.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+2385dbf677f992e4f6cadcef4463d4be
+2013-03-04T11:48:15.694775Z
+35878
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+8394
+
+034-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+e9397ed0957b63c30af60dc683154554
+2013-03-04T11:48:15.694775Z
+35878
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1226
+
+603-MIPS-ath79-ap121-fixes.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+b47001417a03a9a4d735786eb3ed0d13
+2013-03-04T11:48:15.694775Z
+35878
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+4665
+
+412-mtd-m25p80-zero-partition-parser-data.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+b912ef770d758613b934fba5b13f7e09
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+357
+
+405-mtd-tp-link-partition-parser.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+e340cfd282f47a06c245609c9ff5b1d2
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1119
+
+611-MIPS-ath79-add-QCA9556-SoC-on-AP132.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+a335b880bad4d823fb9839ee0d52fe8c
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1611
+
+036-MIPS-ath79-add-PCI-controller-registration-code-for-.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+240de63aed0d62313063058d7e3304d5
+2013-03-04T11:48:15.694775Z
+35878
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+3588
+
+462-mtd-m25p80-set-spi-transfer-type.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+5a0a9886a15a4dd69fac5979195c0d84
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+504
+
+602-MIPS-ath79-add-openwrt-stuff.patch
+file
+
+
+
+
+2013-03-17T12:12:45.000000Z
+f2ec80aff3980939015cae13b7645b64
+2013-02-21T17:47:15.387673Z
+35728
+juhosg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1724
+
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/001-spi-ath79-add-delay-between-SCK-changes.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/001-spi-ath79-add-delay-between-SCK-changes.patch.svn-base
new file mode 100644
index 0000000..9a10622
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/001-spi-ath79-add-delay-between-SCK-changes.patch.svn-base
@@ -0,0 +1,126 @@
+From 486c150478777ef53cfef6f0d46840b9406b0612 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 27 Dec 2012 10:42:24 +0100
+Subject: [PATCH] spi/ath79: add delay between SCK changes
+
+commit 440114fdb13cbc53ea734bcc05b86bcf5b1e430c upstream.
+
+The driver uses the "as fast as it can" approach
+to drive the SCK signal. However this does not
+work with certain low speed SPI chips (e.g. the
+PCF2123 RTC chip).
+
+The patch adds per-bit slowdowns in order to be
+able to use the driver with such chips as well.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+---
+ drivers/spi/spi-ath79.c |   44 +++++++++++++++++++++++++++++++++++++++++++-
+ 1 file changed, 43 insertions(+), 1 deletion(-)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -24,17 +24,24 @@
+ #include <linux/spi/spi_bitbang.h>
+ #include <linux/bitops.h>
+ #include <linux/gpio.h>
++#include <linux/clk.h>
++#include <linux/err.h>
+ 
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79_spi_platform.h>
+ 
+ #define DRV_NAME	"ath79-spi"
+ 
++#define ATH79_SPI_RRW_DELAY_FACTOR	12000
++#define MHZ				(1000 * 1000)
++
+ struct ath79_spi {
+ 	struct spi_bitbang	bitbang;
+ 	u32			ioc_base;
+ 	u32			reg_ctrl;
+ 	void __iomem		*base;
++	struct clk		*clk;
++	unsigned		rrw_delay;
+ };
+ 
+ static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
+@@ -52,6 +59,12 @@ static inline struct ath79_spi *ath79_sp
+ 	return spi_master_get_devdata(spi->master);
+ }
+ 
++static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs)
++{
++	if (nsecs > sp->rrw_delay)
++		ndelay(nsecs - sp->rrw_delay);
++}
++
+ static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
+ {
+ 	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+@@ -184,7 +197,9 @@ static u32 ath79_spi_txrx_mode0(struct s
+ 
+ 		/* setup MSB (to slave) on trailing edge */
+ 		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
++		ath79_spi_delay(sp, nsecs);
+ 		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
++		ath79_spi_delay(sp, nsecs);
+ 
+ 		word <<= 1;
+ 	}
+@@ -198,6 +213,7 @@ static int ath79_spi_probe(struct platfo
+ 	struct ath79_spi *sp;
+ 	struct ath79_spi_platform_data *pdata;
+ 	struct resource	*r;
++	unsigned long rate;
+ 	int ret;
+ 
+ 	master = spi_alloc_master(&pdev->dev, sizeof(*sp));
+@@ -236,12 +252,36 @@ static int ath79_spi_probe(struct platfo
+ 		goto err_put_master;
+ 	}
+ 
++	sp->clk = clk_get(&pdev->dev, "ahb");
++	if (IS_ERR(sp->clk)) {
++		ret = PTR_ERR(sp->clk);
++		goto err_unmap;
++	}
++
++	ret = clk_enable(sp->clk);
++	if (ret)
++		goto err_clk_put;
++
++	rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
++	if (!rate) {
++		ret = -EINVAL;
++		goto err_clk_disable;
++	}
++
++	sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
++	dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
++		sp->rrw_delay);
++
+ 	ret = spi_bitbang_start(&sp->bitbang);
+ 	if (ret)
+-		goto err_unmap;
++		goto err_clk_disable;
+ 
+ 	return 0;
+ 
++err_clk_disable:
++	clk_disable(sp->clk);
++err_clk_put:
++	clk_put(sp->clk);
+ err_unmap:
+ 	iounmap(sp->base);
+ err_put_master:
+@@ -256,6 +296,8 @@ static int ath79_spi_remove(struct platf
+ 	struct ath79_spi *sp = platform_get_drvdata(pdev);
+ 
+ 	spi_bitbang_stop(&sp->bitbang);
++	clk_disable(sp->clk);
++	clk_put(sp->clk);
+ 	iounmap(sp->base);
+ 	platform_set_drvdata(pdev, NULL);
+ 	spi_master_put(sp->bitbang.master);
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/002-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/002-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch.svn-base
new file mode 100644
index 0000000..393ffa5
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/002-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch.svn-base
@@ -0,0 +1,31 @@
+From c7c943b1e3813ff5764ee6417a14530cb7cd6f57 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 27 Dec 2012 10:42:25 +0100
+Subject: [PATCH] spi/ath79: add missing HIGH->LOW SCK transition
+
+commit 72611db0eef21f4456d79ba302af4b34ea384f30 upstream.
+
+The 'ath79_spi_txrx_mode0' function does not
+set the SCK signal to LOW at the end of a word
+transfer. This causes communications errors with
+certain devices (e.g. the PCF2123 RTC chip).
+
+The patch ensures that the SCK signal will be LOW.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+---
+ drivers/spi/spi-ath79.c |    2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -200,6 +200,8 @@ static u32 ath79_spi_txrx_mode0(struct s
+ 		ath79_spi_delay(sp, nsecs);
+ 		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
+ 		ath79_spi_delay(sp, nsecs);
++		if (bits == 1)
++			ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
+ 
+ 		word <<= 1;
+ 	}
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/003-spi-ath79-remove-superfluous-chip-select-code.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/003-spi-ath79-remove-superfluous-chip-select-code.patch.svn-base
new file mode 100644
index 0000000..58272bd
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/003-spi-ath79-remove-superfluous-chip-select-code.patch.svn-base
@@ -0,0 +1,33 @@
+From 622d87da7f99b29dde053881bf42c46de7572ce5 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 27 Dec 2012 10:42:26 +0100
+Subject: [PATCH] spi/ath79: remove superfluous chip select code
+
+commit f1e8fc9898fd8ca78b7438d3c2e60028d3ae2a34 upstream.
+
+The spi_bitbang driver calls the chipselect function
+of the driver from spi_bitbang_setup in order to
+deselect the given SPI chip, so we don't have to
+initialize the CS line here.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+---
+ drivers/spi/spi-ath79.c |    6 ------
+ 1 file changed, 6 deletions(-)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -128,12 +128,6 @@ static int ath79_spi_setup_cs(struct spi
+ 			gpio_free(cdata->gpio);
+ 			return status;
+ 		}
+-	} else {
+-		if (spi->mode & SPI_CS_HIGH)
+-			sp->ioc_base |= AR71XX_SPI_IOC_CS0;
+-		else
+-			sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
+-		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
+ 	}
+ 
+ 	return 0;
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/004-spi-ath79-use-gpio_request_one.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/004-spi-ath79-use-gpio_request_one.patch.svn-base
new file mode 100644
index 0000000..ee81ecd
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/004-spi-ath79-use-gpio_request_one.patch.svn-base
@@ -0,0 +1,59 @@
+From f0b166c931c9971f2ae9614881565d23f58b3178 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 27 Dec 2012 10:42:27 +0100
+Subject: [PATCH] spi/ath79: use gpio_request_one
+
+commit 95d79419feffb326a3d5cb50e2248129dec06bb0 upstream.
+
+Use gpio_request_one() instead of multiple gpiolib calls.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+---
+ drivers/spi/spi-ath79.c |   22 +++++++++++-----------
+ 1 file changed, 11 insertions(+), 11 deletions(-)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -100,6 +100,7 @@ static int ath79_spi_setup_cs(struct spi
+ {
+ 	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+ 	struct ath79_spi_controller_data *cdata;
++	int status;
+ 
+ 	cdata = spi->controller_data;
+ 	if (spi->chip_select && !cdata)
+@@ -115,22 +116,21 @@ static int ath79_spi_setup_cs(struct spi
+ 	/* TODO: setup speed? */
+ 	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
+ 
++	status = 0;
+ 	if (spi->chip_select) {
+-		int status = 0;
++		unsigned long flags;
+ 
+-		status = gpio_request(cdata->gpio, dev_name(&spi->dev));
+-		if (status)
+-			return status;
+-
+-		status = gpio_direction_output(cdata->gpio,
+-					       spi->mode & SPI_CS_HIGH);
+-		if (status) {
+-			gpio_free(cdata->gpio);
+-			return status;
+-		}
++		flags = GPIOF_DIR_OUT;
++		if (spi->mode & SPI_CS_HIGH)
++			flags |= GPIOF_INIT_HIGH;
++		else
++			flags |= GPIOF_INIT_LOW;
++
++		status = gpio_request_one(cdata->gpio, flags,
++					  dev_name(&spi->dev));
+ 	}
+ 
+-	return 0;
++	return status;
+ }
+ 
+ static void ath79_spi_cleanup_cs(struct spi_device *spi)
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/005-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/005-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch.svn-base
new file mode 100644
index 0000000..8ad1dc3
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/005-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch.svn-base
@@ -0,0 +1,112 @@
+From d731c08cf1d264fd6113b9a97790c5a3a86ea520 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 27 Dec 2012 10:42:28 +0100
+Subject: [PATCH] spi/ath79: avoid multiple initialization of the SPI
+ controller
+
+commit c4a31f43005512b366e8bfc346e7f14c1a7a1ba7 upstream.
+
+Currently we are initializing the SPI controller in
+the chip select line function, and that function is
+called once for each SPI device on the bus. If a
+board has multiple SPI devices, the controller will
+be initialized multiple times.
+
+Introduce ath79_spi_{en,dis}able helper functions,
+and call those from probe/response in order to avoid
+the mutliple initialization of the controller.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+---
+ drivers/spi/spi-ath79.c |   41 ++++++++++++++++++++++++-----------------
+ 1 file changed, 24 insertions(+), 17 deletions(-)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -96,16 +96,8 @@ static void ath79_spi_chipselect(struct
+ 
+ }
+ 
+-static int ath79_spi_setup_cs(struct spi_device *spi)
++static void ath79_spi_enable(struct ath79_spi *sp)
+ {
+-	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+-	struct ath79_spi_controller_data *cdata;
+-	int status;
+-
+-	cdata = spi->controller_data;
+-	if (spi->chip_select && !cdata)
+-		return -EINVAL;
+-
+ 	/* enable GPIO mode */
+ 	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
+ 
+@@ -115,6 +107,24 @@ static int ath79_spi_setup_cs(struct spi
+ 
+ 	/* TODO: setup speed? */
+ 	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
++}
++
++static void ath79_spi_disable(struct ath79_spi *sp)
++{
++	/* restore CTRL register */
++	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
++	/* disable GPIO mode */
++	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
++}
++
++static int ath79_spi_setup_cs(struct spi_device *spi)
++{
++	struct ath79_spi_controller_data *cdata;
++	int status;
++
++	cdata = spi->controller_data;
++	if (spi->chip_select && !cdata)
++		return -EINVAL;
+ 
+ 	status = 0;
+ 	if (spi->chip_select) {
+@@ -135,17 +145,10 @@ static int ath79_spi_setup_cs(struct spi
+ 
+ static void ath79_spi_cleanup_cs(struct spi_device *spi)
+ {
+-	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+-
+ 	if (spi->chip_select) {
+ 		struct ath79_spi_controller_data *cdata = spi->controller_data;
+ 		gpio_free(cdata->gpio);
+ 	}
+-
+-	/* restore CTRL register */
+-	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
+-	/* disable GPIO mode */
+-	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
+ }
+ 
+ static int ath79_spi_setup(struct spi_device *spi)
+@@ -268,12 +271,15 @@ static int ath79_spi_probe(struct platfo
+ 	dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
+ 		sp->rrw_delay);
+ 
++	ath79_spi_enable(sp);
+ 	ret = spi_bitbang_start(&sp->bitbang);
+ 	if (ret)
+-		goto err_clk_disable;
++		goto err_disable;
+ 
+ 	return 0;
+ 
++err_disable:
++	ath79_spi_disable(sp);
+ err_clk_disable:
+ 	clk_disable(sp->clk);
+ err_clk_put:
+@@ -292,6 +298,7 @@ static int ath79_spi_remove(struct platf
+ 	struct ath79_spi *sp = platform_get_drvdata(pdev);
+ 
+ 	spi_bitbang_stop(&sp->bitbang);
++	ath79_spi_disable(sp);
+ 	clk_disable(sp->clk);
+ 	clk_put(sp->clk);
+ 	iounmap(sp->base);
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/006-spi-ath79-add-shutdown-handler.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/006-spi-ath79-add-shutdown-handler.patch.svn-base
new file mode 100644
index 0000000..6f59884
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/006-spi-ath79-add-shutdown-handler.patch.svn-base
@@ -0,0 +1,54 @@
+From a32b0e7851320cba0144d20e87e5326ee81e1063 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Tue, 5 Feb 2013 20:57:55 +0100
+Subject: [PATCH] spi/ath79: add shutdown handler
+
+commit 7410e848583f9120dd5f9414629f01bb76b5ee5f upstream.
+
+The SPI controller of the AR7xxx/AR9xxx SoCs
+have a special mode which allows the SoC to
+directly read data from SPI flash chips. In
+this mode, the content of the SPI flash chip
+can be accessed via a memory mapped region.
+
+During early init time, the kernel expects
+that the flash chip is accessible through
+that memory region because it reads board
+specific values (e.g. MAC address, WiFi
+calibration data) from the flash on various
+boards.
+
+This is working if the kernel is loaded
+directly by the bootloader because that
+leaves the SPI controller in the special
+mode. However it is not working in a kexec'd
+kernel because the SPI driver does not restore
+the special mode during shutdown.
+
+The patch adds a shutdown handler to fix this
+issue.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+---
+ drivers/spi/spi-ath79.c |    6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -308,9 +308,15 @@ static int ath79_spi_remove(struct platf
+ 	return 0;
+ }
+ 
++static void ath79_spi_shutdown(struct platform_device *pdev)
++{
++	ath79_spi_remove(pdev);
++}
++
+ static struct platform_driver ath79_spi_driver = {
+ 	.probe		= ath79_spi_probe,
+ 	.remove		= ath79_spi_remove,
++	.shutdown	= ath79_spi_shutdown,
+ 	.driver		= {
+ 		.name	= DRV_NAME,
+ 		.owner	= THIS_MODULE,
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/007-MIPS-ath79-fix-GPIO-function-selection-for-AR934x-So.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/007-MIPS-ath79-fix-GPIO-function-selection-for-AR934x-So.patch.svn-base
new file mode 100644
index 0000000..c1f1247
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/007-MIPS-ath79-fix-GPIO-function-selection-for-AR934x-So.patch.svn-base
@@ -0,0 +1,110 @@
+From 2e6a41e0be6a09ed839e3afbe1fb413a015d8870 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Tue, 29 Jan 2013 08:19:12 +0000
+Subject: [PATCH] MIPS: ath79: fix GPIO function selection for AR934x SoCs
+
+commit 8838becdf5f7261d7f5dfbbe957fe9b9ed188aec upstream.
+
+GPIO function selection is not working on the AR934x
+SoCs because the offset of the function selection
+register is different on those.
+
+Add a helper routine which returns the correct
+register address based on the SoC type, and use
+that in the 'ath79_gpio_function_*' routines.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4870/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/gpio.c                         |   38 ++++++++++++++++--------
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    2 ++
+ 2 files changed, 28 insertions(+), 12 deletions(-)
+
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -137,47 +137,61 @@ static struct gpio_chip ath79_gpio_chip
+ 	.base			= 0,
+ };
+ 
++static void __iomem *ath79_gpio_get_function_reg(void)
++{
++	u32 reg = 0;
++
++	if (soc_is_ar71xx() ||
++	    soc_is_ar724x() ||
++	    soc_is_ar913x() ||
++	    soc_is_ar933x())
++		reg = AR71XX_GPIO_REG_FUNC;
++	else if (soc_is_ar934x())
++		reg = AR934X_GPIO_REG_FUNC;
++	else
++		BUG();
++
++	return ath79_gpio_base + reg;
++}
++
+ void ath79_gpio_function_enable(u32 mask)
+ {
+-	void __iomem *base = ath79_gpio_base;
++	void __iomem *reg = ath79_gpio_get_function_reg();
+ 	unsigned long flags;
+ 
+ 	spin_lock_irqsave(&ath79_gpio_lock, flags);
+ 
+-	__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) | mask,
+-		     base + AR71XX_GPIO_REG_FUNC);
++	__raw_writel(__raw_readl(reg) | mask, reg);
+ 	/* flush write */
+-	__raw_readl(base + AR71XX_GPIO_REG_FUNC);
++	__raw_readl(reg);
+ 
+ 	spin_unlock_irqrestore(&ath79_gpio_lock, flags);
+ }
+ 
+ void ath79_gpio_function_disable(u32 mask)
+ {
+-	void __iomem *base = ath79_gpio_base;
++	void __iomem *reg = ath79_gpio_get_function_reg();
+ 	unsigned long flags;
+ 
+ 	spin_lock_irqsave(&ath79_gpio_lock, flags);
+ 
+-	__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~mask,
+-		     base + AR71XX_GPIO_REG_FUNC);
++	__raw_writel(__raw_readl(reg) & ~mask, reg);
+ 	/* flush write */
+-	__raw_readl(base + AR71XX_GPIO_REG_FUNC);
++	__raw_readl(reg);
+ 
+ 	spin_unlock_irqrestore(&ath79_gpio_lock, flags);
+ }
+ 
+ void ath79_gpio_function_setup(u32 set, u32 clear)
+ {
+-	void __iomem *base = ath79_gpio_base;
++	void __iomem *reg = ath79_gpio_get_function_reg();
+ 	unsigned long flags;
+ 
+ 	spin_lock_irqsave(&ath79_gpio_lock, flags);
+ 
+-	__raw_writel((__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~clear) | set,
+-		     base + AR71XX_GPIO_REG_FUNC);
++	__raw_writel((__raw_readl(reg) & ~clear) | set, reg);
+ 	/* flush write */
+-	__raw_readl(base + AR71XX_GPIO_REG_FUNC);
++	__raw_readl(reg);
+ 
+ 	spin_unlock_irqrestore(&ath79_gpio_lock, flags);
+ }
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -401,6 +401,8 @@
+ #define AR71XX_GPIO_REG_INT_ENABLE	0x24
+ #define AR71XX_GPIO_REG_FUNC		0x28
+ 
++#define AR934X_GPIO_REG_FUNC		0x6c
++
+ #define AR71XX_GPIO_COUNT		16
+ #define AR7240_GPIO_COUNT		18
+ #define AR7241_GPIO_COUNT		20
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/008-MIPS-ath79-simplify-ath79_gpio_function_-routines.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/008-MIPS-ath79-simplify-ath79_gpio_function_-routines.patch.svn-base
new file mode 100644
index 0000000..8606f3b
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/008-MIPS-ath79-simplify-ath79_gpio_function_-routines.patch.svn-base
@@ -0,0 +1,72 @@
+From 6c888a88f2a9939182bf41151f079a6b59f1593c Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Tue, 29 Jan 2013 08:19:13 +0000
+Subject: [PATCH] MIPS: ath79: simplify ath79_gpio_function_* routines
+
+commit f160a289e0e8848391f5ec48ff1a014b9c04b162 upstream.
+
+Make ath79_gpio_function_{en,dis}able to be wrappers
+around ath79_gpio_function_setup.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4871/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/gpio.c |   30 ++++++------------------------
+ 1 file changed, 6 insertions(+), 24 deletions(-)
+
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -154,46 +154,28 @@ static void __iomem *ath79_gpio_get_func
+ 	return ath79_gpio_base + reg;
+ }
+ 
+-void ath79_gpio_function_enable(u32 mask)
++void ath79_gpio_function_setup(u32 set, u32 clear)
+ {
+ 	void __iomem *reg = ath79_gpio_get_function_reg();
+ 	unsigned long flags;
+ 
+ 	spin_lock_irqsave(&ath79_gpio_lock, flags);
+ 
+-	__raw_writel(__raw_readl(reg) | mask, reg);
++	__raw_writel((__raw_readl(reg) & ~clear) | set, reg);
+ 	/* flush write */
+ 	__raw_readl(reg);
+ 
+ 	spin_unlock_irqrestore(&ath79_gpio_lock, flags);
+ }
+ 
+-void ath79_gpio_function_disable(u32 mask)
++void ath79_gpio_function_enable(u32 mask)
+ {
+-	void __iomem *reg = ath79_gpio_get_function_reg();
+-	unsigned long flags;
+-
+-	spin_lock_irqsave(&ath79_gpio_lock, flags);
+-
+-	__raw_writel(__raw_readl(reg) & ~mask, reg);
+-	/* flush write */
+-	__raw_readl(reg);
+-
+-	spin_unlock_irqrestore(&ath79_gpio_lock, flags);
++	ath79_gpio_function_setup(mask, 0);
+ }
+ 
+-void ath79_gpio_function_setup(u32 set, u32 clear)
++void ath79_gpio_function_disable(u32 mask)
+ {
+-	void __iomem *reg = ath79_gpio_get_function_reg();
+-	unsigned long flags;
+-
+-	spin_lock_irqsave(&ath79_gpio_lock, flags);
+-
+-	__raw_writel((__raw_readl(reg) & ~clear) | set, reg);
+-	/* flush write */
+-	__raw_readl(reg);
+-
+-	spin_unlock_irqrestore(&ath79_gpio_lock, flags);
++	ath79_gpio_function_setup(0, mask);
+ }
+ 
+ void __init ath79_gpio_init(void)
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/009-MIPS-ath79-simplify-MISC-IRQ-handling.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/009-MIPS-ath79-simplify-MISC-IRQ-handling.patch.svn-base
new file mode 100644
index 0000000..146bf25
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/009-MIPS-ath79-simplify-MISC-IRQ-handling.patch.svn-base
@@ -0,0 +1,90 @@
+From 1690e8f8efdeedbd23bb34a3bc5803c34f2d3f66 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Tue, 29 Jan 2013 16:13:17 +0000
+Subject: [PATCH] MIPS: ath79: simplify MISC IRQ handling
+
+commit 9c099c4e79b67d5578ce8142e6214950be4fcf43 upstream.
+
+The current code uses multiple if statements for
+demultiplexing the different interrupt sources.
+Additionally, the MISC interrupt controller has
+32 interrupt sources and the current code does not
+handles all of them.
+
+Get rid of the if statements and process all interrupt
+sources in a loop to fix these issues.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4874/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/irq.c                  |   45 +++++++-------------------------
+ arch/mips/include/asm/mach-ath79/irq.h |    1 +
+ 2 files changed, 10 insertions(+), 36 deletions(-)
+
+--- a/arch/mips/ath79/irq.c
++++ b/arch/mips/ath79/irq.c
+@@ -35,44 +35,17 @@ static void ath79_misc_irq_handler(unsig
+ 	pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
+ 		  __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
+ 
+-	if (pending & MISC_INT_UART)
+-		generic_handle_irq(ATH79_MISC_IRQ_UART);
+-
+-	else if (pending & MISC_INT_DMA)
+-		generic_handle_irq(ATH79_MISC_IRQ_DMA);
+-
+-	else if (pending & MISC_INT_PERFC)
+-		generic_handle_irq(ATH79_MISC_IRQ_PERFC);
+-
+-	else if (pending & MISC_INT_TIMER)
+-		generic_handle_irq(ATH79_MISC_IRQ_TIMER);
+-
+-	else if (pending & MISC_INT_TIMER2)
+-		generic_handle_irq(ATH79_MISC_IRQ_TIMER2);
+-
+-	else if (pending & MISC_INT_TIMER3)
+-		generic_handle_irq(ATH79_MISC_IRQ_TIMER3);
+-
+-	else if (pending & MISC_INT_TIMER4)
+-		generic_handle_irq(ATH79_MISC_IRQ_TIMER4);
+-
+-	else if (pending & MISC_INT_OHCI)
+-		generic_handle_irq(ATH79_MISC_IRQ_OHCI);
+-
+-	else if (pending & MISC_INT_ERROR)
+-		generic_handle_irq(ATH79_MISC_IRQ_ERROR);
+-
+-	else if (pending & MISC_INT_GPIO)
+-		generic_handle_irq(ATH79_MISC_IRQ_GPIO);
+-
+-	else if (pending & MISC_INT_WDOG)
+-		generic_handle_irq(ATH79_MISC_IRQ_WDOG);
++	if (!pending) {
++		spurious_interrupt();
++		return;
++	}
+ 
+-	else if (pending & MISC_INT_ETHSW)
+-		generic_handle_irq(ATH79_MISC_IRQ_ETHSW);
++	while (pending) {
++		int bit = __ffs(pending);
+ 
+-	else
+-		spurious_interrupt();
++		generic_handle_irq(ATH79_MISC_IRQ(bit));
++		pending &= ~BIT(bit);
++	}
+ }
+ 
+ static void ar71xx_misc_irq_unmask(struct irq_data *d)
+--- a/arch/mips/include/asm/mach-ath79/irq.h
++++ b/arch/mips/include/asm/mach-ath79/irq.h
+@@ -14,6 +14,7 @@
+ 
+ #define ATH79_MISC_IRQ_BASE	8
+ #define ATH79_MISC_IRQ_COUNT	32
++#define ATH79_MISC_IRQ(_x)	(ATH79_MISC_IRQ_BASE + (_x))
+ 
+ #define ATH79_PCI_IRQ_BASE	(ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT)
+ #define ATH79_PCI_IRQ_COUNT	6
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/010-MIPS-pci-ar724x-convert-into-a-platform-driver.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/010-MIPS-pci-ar724x-convert-into-a-platform-driver.patch.svn-base
new file mode 100644
index 0000000..e7b7b15
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/010-MIPS-pci-ar724x-convert-into-a-platform-driver.patch.svn-base
@@ -0,0 +1,102 @@
+From 42541838d9fdbad8573141d69cf8e38831a6cbb6 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sat, 2 Feb 2013 11:40:42 +0000
+Subject: [PATCH] MIPS: pci-ar724x: convert into a platform driver
+
+commit 58d2e9bcd682d76bcb9575dc56c85f1d82a81bfa upstream.
+
+The patch converts the pci-ar724x driver into a
+platform driver. This makes it possible to register
+the PCI controller as a plain platform device.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4905/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/pci-ar724x.c |   57 ++++++++++++++++++++++++++++++++++++++++++--
+ 1 file changed, 55 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -11,6 +11,8 @@
+ 
+ #include <linux/irq.h>
+ #include <linux/pci.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/pci.h>
+@@ -262,7 +264,7 @@ static struct irq_chip ar724x_pci_irq_ch
+ 	.irq_mask_ack	= ar724x_pci_irq_mask,
+ };
+ 
+-static void __init ar724x_pci_irq_init(int irq)
++static void ar724x_pci_irq_init(int irq)
+ {
+ 	void __iomem *base;
+ 	int i;
+@@ -282,7 +284,7 @@ static void __init ar724x_pci_irq_init(i
+ 	irq_set_chained_handler(irq, ar724x_pci_irq_handler);
+ }
+ 
+-int __init ar724x_pcibios_init(int irq)
++int ar724x_pcibios_init(int irq)
+ {
+ 	int ret;
+ 
+@@ -312,3 +314,54 @@ err_unmap_devcfg:
+ err:
+ 	return ret;
+ }
++
++static int ar724x_pci_probe(struct platform_device *pdev)
++{
++	struct resource *res;
++	int irq;
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base");
++	if (!res)
++		return -EINVAL;
++
++	ar724x_pci_ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
++	if (ar724x_pci_ctrl_base == NULL)
++		return -EBUSY;
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
++	if (!res)
++		return -EINVAL;
++
++	ar724x_pci_devcfg_base = devm_request_and_ioremap(&pdev->dev, res);
++	if (!ar724x_pci_devcfg_base)
++		return -EBUSY;
++
++	irq = platform_get_irq(pdev, 0);
++	if (irq < 0)
++		return -EINVAL;
++
++	ar724x_pci_link_up = ar724x_pci_check_link();
++	if (!ar724x_pci_link_up)
++		dev_warn(&pdev->dev, "PCIe link is down\n");
++
++	ar724x_pci_irq_init(irq);
++
++	register_pci_controller(&ar724x_pci_controller);
++
++	return 0;
++}
++
++static struct platform_driver ar724x_pci_driver = {
++	.probe = ar724x_pci_probe,
++	.driver = {
++		.name = "ar724x-pci",
++		.owner = THIS_MODULE,
++	},
++};
++
++static int __init ar724x_pci_init(void)
++{
++	return platform_driver_register(&ar724x_pci_driver);
++}
++
++postcore_initcall(ar724x_pci_init);
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/011-MIPS-pci-ar71xx-convert-into-a-platform-driver.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/011-MIPS-pci-ar71xx-convert-into-a-platform-driver.patch.svn-base
new file mode 100644
index 0000000..e6bd8d0
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/011-MIPS-pci-ar71xx-convert-into-a-platform-driver.patch.svn-base
@@ -0,0 +1,112 @@
+From 060c9a226a25e044167e877d9830ec53f836da9e Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sat, 2 Feb 2013 11:40:43 +0000
+Subject: [PATCH] MIPS: pci-ar71xx: convert into a platform driver
+
+commit fb167e891d5cc6386840dd092af2d461b38eb802 upstream.
+
+The patch converts the pci-ar71xx driver into a
+platform driver. This makes it possible to register
+the PCI controller as a plain platform device.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4906/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/pci-ar71xx.c |   60 +++++++++++++++++++++++++++++++++++++++++---
+ 1 file changed, 56 insertions(+), 4 deletions(-)
+
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -18,6 +18,8 @@
+ #include <linux/pci.h>
+ #include <linux/pci_regs.h>
+ #include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
+ 
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
+@@ -309,7 +311,7 @@ static struct irq_chip ar71xx_pci_irq_ch
+ 	.irq_mask_ack	= ar71xx_pci_irq_mask,
+ };
+ 
+-static __init void ar71xx_pci_irq_init(void)
++static void ar71xx_pci_irq_init(int irq)
+ {
+ 	void __iomem *base = ath79_reset_base;
+ 	int i;
+@@ -324,10 +326,10 @@ static __init void ar71xx_pci_irq_init(v
+ 		irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
+ 					 handle_level_irq);
+ 
+-	irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar71xx_pci_irq_handler);
++	irq_set_chained_handler(irq, ar71xx_pci_irq_handler);
+ }
+ 
+-static __init void ar71xx_pci_reset(void)
++static void ar71xx_pci_reset(void)
+ {
+ 	void __iomem *ddr_base = ath79_ddr_base;
+ 
+@@ -367,9 +369,59 @@ __init int ar71xx_pcibios_init(void)
+ 	/* clear bus errors */
+ 	ar71xx_pci_check_error(1);
+ 
+-	ar71xx_pci_irq_init();
++	ar71xx_pci_irq_init(ATH79_CPU_IRQ_IP2);
+ 
+ 	register_pci_controller(&ar71xx_pci_controller);
+ 
+ 	return 0;
+ }
++
++static int ar71xx_pci_probe(struct platform_device *pdev)
++{
++	struct resource *res;
++	int irq;
++	u32 t;
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
++	if (!res)
++		return -EINVAL;
++
++	ar71xx_pcicfg_base = devm_request_and_ioremap(&pdev->dev, res);
++	if (!ar71xx_pcicfg_base)
++		return -ENOMEM;
++
++	irq = platform_get_irq(pdev, 0);
++	if (irq < 0)
++		return -EINVAL;
++
++	ar71xx_pci_reset();
++
++	/* setup COMMAND register */
++	t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
++	  | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
++	ar71xx_pci_local_write(PCI_COMMAND, 4, t);
++
++	/* clear bus errors */
++	ar71xx_pci_check_error(1);
++
++	ar71xx_pci_irq_init(irq);
++
++	register_pci_controller(&ar71xx_pci_controller);
++
++	return 0;
++}
++
++static struct platform_driver ar71xx_pci_driver = {
++	.probe = ar71xx_pci_probe,
++	.driver = {
++		.name = "ar71xx-pci",
++		.owner = THIS_MODULE,
++	},
++};
++
++static int __init ar71xx_pci_init(void)
++{
++	return platform_driver_register(&ar71xx_pci_driver);
++}
++
++postcore_initcall(ar71xx_pci_init);
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/012-MIPS-ath79-move-global-PCI-defines-into-a-common-hea.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/012-MIPS-ath79-move-global-PCI-defines-into-a-common-hea.patch.svn-base
new file mode 100644
index 0000000..eaff04b
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/012-MIPS-ath79-move-global-PCI-defines-into-a-common-hea.patch.svn-base
@@ -0,0 +1,98 @@
+From 1dece618b107f5db28c8f63d4d32424dd18324d1 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 4 Feb 2013 11:56:53 +0100
+Subject: [PATCH] MIPS: ath79: move global PCI defines into a common header
+
+commit ad4ce92e919f7ad5561a2060deb58899de58b40c upstream.
+
+The constants will be used by a subsequent patch.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4907/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |   24 ++++++++++++++++++++++++
+ arch/mips/pci/pci-ar71xx.c                     |   16 ----------------
+ arch/mips/pci/pci-ar724x.c                     |    8 --------
+ 3 files changed, 24 insertions(+), 24 deletions(-)
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -41,11 +41,35 @@
+ #define AR71XX_RESET_BASE	(AR71XX_APB_BASE + 0x00060000)
+ #define AR71XX_RESET_SIZE	0x100
+ 
++#define AR71XX_PCI_MEM_BASE	0x10000000
++#define AR71XX_PCI_MEM_SIZE	0x07000000
++
++#define AR71XX_PCI_WIN0_OFFS	0x10000000
++#define AR71XX_PCI_WIN1_OFFS	0x11000000
++#define AR71XX_PCI_WIN2_OFFS	0x12000000
++#define AR71XX_PCI_WIN3_OFFS	0x13000000
++#define AR71XX_PCI_WIN4_OFFS	0x14000000
++#define AR71XX_PCI_WIN5_OFFS	0x15000000
++#define AR71XX_PCI_WIN6_OFFS	0x16000000
++#define AR71XX_PCI_WIN7_OFFS	0x07000000
++
++#define AR71XX_PCI_CFG_BASE	\
++	(AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
++#define AR71XX_PCI_CFG_SIZE	0x100
++
+ #define AR7240_USB_CTRL_BASE	(AR71XX_APB_BASE + 0x00030000)
+ #define AR7240_USB_CTRL_SIZE	0x100
+ #define AR7240_OHCI_BASE	0x1b000000
+ #define AR7240_OHCI_SIZE	0x1000
+ 
++#define AR724X_PCI_MEM_BASE	0x10000000
++#define AR724X_PCI_MEM_SIZE	0x04000000
++
++#define AR724X_PCI_CFG_BASE	0x14000000
++#define AR724X_PCI_CFG_SIZE	0x1000
++#define AR724X_PCI_CTRL_BASE	(AR71XX_APB_BASE + 0x000f0000)
++#define AR724X_PCI_CTRL_SIZE	0x100
++
+ #define AR724X_EHCI_BASE	0x1b000000
+ #define AR724X_EHCI_SIZE	0x1000
+ 
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -25,22 +25,6 @@
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/pci.h>
+ 
+-#define AR71XX_PCI_MEM_BASE	0x10000000
+-#define AR71XX_PCI_MEM_SIZE	0x07000000
+-
+-#define AR71XX_PCI_WIN0_OFFS		0x10000000
+-#define AR71XX_PCI_WIN1_OFFS		0x11000000
+-#define AR71XX_PCI_WIN2_OFFS		0x12000000
+-#define AR71XX_PCI_WIN3_OFFS		0x13000000
+-#define AR71XX_PCI_WIN4_OFFS		0x14000000
+-#define AR71XX_PCI_WIN5_OFFS		0x15000000
+-#define AR71XX_PCI_WIN6_OFFS		0x16000000
+-#define AR71XX_PCI_WIN7_OFFS		0x07000000
+-
+-#define AR71XX_PCI_CFG_BASE		\
+-	(AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
+-#define AR71XX_PCI_CFG_SIZE		0x100
+-
+ #define AR71XX_PCI_REG_CRP_AD_CBE	0x00
+ #define AR71XX_PCI_REG_CRP_WRDATA	0x04
+ #define AR71XX_PCI_REG_CRP_RDDATA	0x08
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -17,14 +17,6 @@
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/pci.h>
+ 
+-#define AR724X_PCI_CFG_BASE	0x14000000
+-#define AR724X_PCI_CFG_SIZE	0x1000
+-#define AR724X_PCI_CTRL_BASE	(AR71XX_APB_BASE + 0x000f0000)
+-#define AR724X_PCI_CTRL_SIZE	0x100
+-
+-#define AR724X_PCI_MEM_BASE	0x10000000
+-#define AR724X_PCI_MEM_SIZE	0x04000000
+-
+ #define AR724X_PCI_REG_RESET		0x18
+ #define AR724X_PCI_REG_INT_STATUS	0x4c
+ #define AR724X_PCI_REG_INT_MASK		0x50
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/013-MIPS-ath79-register-platform-devices-for-the-PCI-con.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/013-MIPS-ath79-register-platform-devices-for-the-PCI-con.patch.svn-base
new file mode 100644
index 0000000..eee791e
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/013-MIPS-ath79-register-platform-devices-for-the-PCI-con.patch.svn-base
@@ -0,0 +1,129 @@
+From 87cdbe4315e4c72c2bc8568d1258e1207e1c772b Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sat, 2 Feb 2013 11:44:24 +0000
+Subject: [PATCH] MIPS: ath79: register platform devices for the PCI
+ controllers
+
+commit 9fc1ca5b73a82daedffa2d1d5daa48dd2093c39a upstream.
+
+The pci-ar71xx and pci-ar724x drivers were converted
+into platform drivers. Register the corresponding
+platform devices for the PCI controllers instead
+of using the ar7{1x,24}x_pcibios_init functions.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4908/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/pci.c |   87 ++++++++++++++++++++++++++++++++++++++++++++-----
+ 1 file changed, 78 insertions(+), 9 deletions(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -14,6 +14,8 @@
+ 
+ #include <linux/init.h>
+ #include <linux/pci.h>
++#include <linux/resource.h>
++#include <linux/platform_device.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/irq.h>
+@@ -110,21 +112,88 @@ void __init ath79_pci_set_plat_dev_init(
+ 	ath79_pci_plat_dev_init = func;
+ }
+ 
+-int __init ath79_register_pci(void)
++static struct platform_device *
++ath79_register_pci_ar71xx(void)
+ {
+-	if (soc_is_ar71xx())
+-		return ar71xx_pcibios_init();
++	struct platform_device *pdev;
++	struct resource res[2];
++
++	memset(res, 0, sizeof(res));
+ 
+-	if (soc_is_ar724x())
+-		return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
++	res[0].name = "cfg_base";
++	res[0].flags = IORESOURCE_MEM;
++	res[0].start = AR71XX_PCI_CFG_BASE;
++	res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1;
++
++	res[1].flags = IORESOURCE_IRQ;
++	res[1].start = ATH79_CPU_IRQ_IP2;
++	res[1].end = ATH79_CPU_IRQ_IP2;
++
++	pdev = platform_device_register_simple("ar71xx-pci", -1,
++					       res, ARRAY_SIZE(res));
++	return pdev;
++}
+ 
+-	if (soc_is_ar9342() || soc_is_ar9344()) {
++static struct platform_device *
++ath79_register_pci_ar724x(int id,
++			  unsigned long cfg_base,
++			  unsigned long ctrl_base,
++			  int irq)
++{
++	struct platform_device *pdev;
++	struct resource res[3];
++
++	memset(res, 0, sizeof(res));
++
++	res[0].name = "cfg_base";
++	res[0].flags = IORESOURCE_MEM;
++	res[0].start = cfg_base;
++	res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1;
++
++	res[1].name = "ctrl_base";
++	res[1].flags = IORESOURCE_MEM;
++	res[1].start = ctrl_base;
++	res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1;
++
++	res[2].flags = IORESOURCE_IRQ;
++	res[2].start = irq;
++	res[2].end = irq;
++
++	pdev = platform_device_register_simple("ar724x-pci", id,
++					       res, ARRAY_SIZE(res));
++	return pdev;
++}
++
++int __init ath79_register_pci(void)
++{
++	struct platform_device *pdev = NULL;
++
++	if (soc_is_ar71xx()) {
++		pdev = ath79_register_pci_ar71xx();
++	} else if (soc_is_ar724x()) {
++		pdev = ath79_register_pci_ar724x(-1,
++						 AR724X_PCI_CFG_BASE,
++						 AR724X_PCI_CTRL_BASE,
++						 ATH79_CPU_IRQ_IP2);
++	} else if (soc_is_ar9342() ||
++		   soc_is_ar9344()) {
+ 		u32 bootstrap;
+ 
+ 		bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
+-		if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC)
+-			return ar724x_pcibios_init(ATH79_IP2_IRQ(0));
++		if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0)
++			return -ENODEV;
++
++		pdev = ath79_register_pci_ar724x(-1,
++						 AR724X_PCI_CFG_BASE,
++						 AR724X_PCI_CTRL_BASE,
++						 ATH79_IP2_IRQ(0));
++	} else {
++		/* No PCI support */
++		return -ENODEV;
+ 	}
+ 
+-	return -ENODEV;
++	if (!pdev)
++		pr_err("unable to register PCI controller device\n");
++
++	return pdev ? 0 : -ENODEV;
+ }
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/014-MIPS-ath79-remove-unused-ar7-1x-24-x_pcibios_init-fu.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/014-MIPS-ath79-remove-unused-ar7-1x-24-x_pcibios_init-fu.patch.svn-base
new file mode 100644
index 0000000..978a33d
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/014-MIPS-ath79-remove-unused-ar7-1x-24-x_pcibios_init-fu.patch.svn-base
@@ -0,0 +1,152 @@
+From db36c9d6a6be232bdee245407fc8ccde53ea69c6 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 4 Feb 2013 11:58:49 +0100
+Subject: [PATCH] MIPS: ath79: remove unused ar7{1x,24}x_pcibios_init
+ functions
+
+commit 6e783865b4e60f2ecf7708f8ea24db5c5ea07ced upstream.
+
+The functions are unused now, so remove them.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4909/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/pci.c                  |    1 -
+ arch/mips/include/asm/mach-ath79/pci.h |   28 ----------------------------
+ arch/mips/pci/pci-ar71xx.c             |   26 --------------------------
+ arch/mips/pci/pci-ar724x.c             |   32 --------------------------------
+ 4 files changed, 87 deletions(-)
+ delete mode 100644 arch/mips/include/asm/mach-ath79/pci.h
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -19,7 +19,6 @@
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/irq.h>
+-#include <asm/mach-ath79/pci.h>
+ #include "pci.h"
+ 
+ static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
+--- a/arch/mips/include/asm/mach-ath79/pci.h
++++ /dev/null
+@@ -1,28 +0,0 @@
+-/*
+- *  Atheros AR71XX/AR724X PCI support
+- *
+- *  Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
+- *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+- *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+- *
+- *  This program is free software; you can redistribute it and/or modify it
+- *  under the terms of the GNU General Public License version 2 as published
+- *  by the Free Software Foundation.
+- */
+-
+-#ifndef __ASM_MACH_ATH79_PCI_H
+-#define __ASM_MACH_ATH79_PCI_H
+-
+-#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX)
+-int ar71xx_pcibios_init(void);
+-#else
+-static inline int ar71xx_pcibios_init(void) { return 0; }
+-#endif
+-
+-#if defined(CONFIG_PCI_AR724X)
+-int ar724x_pcibios_init(int irq);
+-#else
+-static inline int ar724x_pcibios_init(int irq) { return 0; }
+-#endif
+-
+-#endif /* __ASM_MACH_ATH79_PCI_H */
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -23,7 +23,6 @@
+ 
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
+-#include <asm/mach-ath79/pci.h>
+ 
+ #define AR71XX_PCI_REG_CRP_AD_CBE	0x00
+ #define AR71XX_PCI_REG_CRP_WRDATA	0x04
+@@ -335,31 +334,6 @@ static void ar71xx_pci_reset(void)
+ 	mdelay(100);
+ }
+ 
+-__init int ar71xx_pcibios_init(void)
+-{
+-	u32 t;
+-
+-	ar71xx_pcicfg_base = ioremap(AR71XX_PCI_CFG_BASE, AR71XX_PCI_CFG_SIZE);
+-	if (ar71xx_pcicfg_base == NULL)
+-		return -ENOMEM;
+-
+-	ar71xx_pci_reset();
+-
+-	/* setup COMMAND register */
+-	t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
+-	  | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
+-	ar71xx_pci_local_write(PCI_COMMAND, 4, t);
+-
+-	/* clear bus errors */
+-	ar71xx_pci_check_error(1);
+-
+-	ar71xx_pci_irq_init(ATH79_CPU_IRQ_IP2);
+-
+-	register_pci_controller(&ar71xx_pci_controller);
+-
+-	return 0;
+-}
+-
+ static int ar71xx_pci_probe(struct platform_device *pdev)
+ {
+ 	struct resource *res;
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -15,7 +15,6 @@
+ #include <linux/platform_device.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
+-#include <asm/mach-ath79/pci.h>
+ 
+ #define AR724X_PCI_REG_RESET		0x18
+ #define AR724X_PCI_REG_INT_STATUS	0x4c
+@@ -276,37 +275,6 @@ static void ar724x_pci_irq_init(int irq)
+ 	irq_set_chained_handler(irq, ar724x_pci_irq_handler);
+ }
+ 
+-int ar724x_pcibios_init(int irq)
+-{
+-	int ret;
+-
+-	ret = -ENOMEM;
+-
+-	ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE,
+-					 AR724X_PCI_CFG_SIZE);
+-	if (ar724x_pci_devcfg_base == NULL)
+-		goto err;
+-
+-	ar724x_pci_ctrl_base = ioremap(AR724X_PCI_CTRL_BASE,
+-				       AR724X_PCI_CTRL_SIZE);
+-	if (ar724x_pci_ctrl_base == NULL)
+-		goto err_unmap_devcfg;
+-
+-	ar724x_pci_link_up = ar724x_pci_check_link();
+-	if (!ar724x_pci_link_up)
+-		pr_warn("ar724x: PCIe link is down\n");
+-
+-	ar724x_pci_irq_init(irq);
+-	register_pci_controller(&ar724x_pci_controller);
+-
+-	return PCIBIOS_SUCCESSFUL;
+-
+-err_unmap_devcfg:
+-	iounmap(ar724x_pci_devcfg_base);
+-err:
+-	return ret;
+-}
+-
+ static int ar724x_pci_probe(struct platform_device *pdev)
+ {
+ 	struct resource *res;
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/015-MIPS-avoid-possible-resource-conflict-in-register_pc.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/015-MIPS-avoid-possible-resource-conflict-in-register_pc.patch.svn-base
new file mode 100644
index 0000000..613c7ad
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/015-MIPS-avoid-possible-resource-conflict-in-register_pc.patch.svn-base
@@ -0,0 +1,52 @@
+From 4da85831c8eaf2de2cadae6723e8231068c313b7 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sat, 2 Feb 2013 13:18:54 +0000
+Subject: [PATCH] MIPS: avoid possible resource conflict in
+ register_pci_controller
+
+commit 222831787704c9ad9215f6b56f975b233968607c upstream.
+
+The IO and memory resources of a PCI controller
+might already have a parent resource set when
+they are passed to 'register_pci_controller'.
+
+If the parent resource is set, the request_resource
+call will fail due to resource conflict and the
+current code will not be able to register the
+PCI controller.
+
+Use the parent resource if it is available in the
+request_resource call to avoid the isssue.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4910/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/pci.c |   15 +++++++++++++--
+ 1 file changed, 13 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/pci/pci.c
++++ b/arch/mips/pci/pci.c
+@@ -175,9 +175,20 @@ static DEFINE_MUTEX(pci_scan_mutex);
+ 
+ void register_pci_controller(struct pci_controller *hose)
+ {
+-	if (request_resource(&iomem_resource, hose->mem_resource) < 0)
++	struct resource *parent;
++
++	parent = hose->mem_resource->parent;
++	if (!parent)
++		parent = &iomem_resource;
++
++	if (request_resource(parent, hose->mem_resource) < 0)
+ 		goto out;
+-	if (request_resource(&ioport_resource, hose->io_resource) < 0) {
++
++	parent = hose->io_resource->parent;
++	if (!parent)
++		parent = &ioport_resource;
++
++	if (request_resource(parent, hose->io_resource) < 0) {
+ 		release_resource(hose->mem_resource);
+ 		goto out;
+ 	}
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/016-MIPS-ath79-allow-to-specify-bus-number-in-PCI-IRQ-ma.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/016-MIPS-ath79-allow-to-specify-bus-number-in-PCI-IRQ-ma.patch.svn-base
new file mode 100644
index 0000000..477bddb
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/016-MIPS-ath79-allow-to-specify-bus-number-in-PCI-IRQ-ma.patch.svn-base
@@ -0,0 +1,40 @@
+From 53ba4919664636487155c810fb49781169780e0c Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 3 Feb 2013 09:58:37 +0000
+Subject: [PATCH] MIPS: ath79: allow to specify bus number in PCI IRQ maps
+
+commit 617fed41e98417f3ea3e9974be251e125c8796f2 upstream.
+
+This is needed for multiple PCI bus support.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4913/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/pci.c |    4 +++-
+ arch/mips/ath79/pci.h |    1 +
+ 2 files changed, 4 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -75,7 +75,9 @@ int __init pcibios_map_irq(const struct
+ 		const struct ath79_pci_irq *entry;
+ 
+ 		entry = &ath79_pci_irq_map[i];
+-		if (entry->slot == slot && entry->pin == pin) {
++		if (entry->bus == dev->bus->number &&
++		    entry->slot == slot &&
++		    entry->pin == pin) {
+ 			irq = entry->irq;
+ 			break;
+ 		}
+--- a/arch/mips/ath79/pci.h
++++ b/arch/mips/ath79/pci.h
+@@ -14,6 +14,7 @@
+ #define _ATH79_PCI_H
+ 
+ struct ath79_pci_irq {
++	int	bus;
+ 	u8	slot;
+ 	u8	pin;
+ 	int	irq;
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/017-MIPS-pci-ar724x-use-dynamically-allocated-PCI-contro.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/017-MIPS-pci-ar724x-use-dynamically-allocated-PCI-contro.patch.svn-base
new file mode 100644
index 0000000..a960cb3
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/017-MIPS-pci-ar724x-use-dynamically-allocated-PCI-contro.patch.svn-base
@@ -0,0 +1,321 @@
+From 21b3cafae425cf2e317a22292a9a5773ff0e2e5e Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 3 Feb 2013 09:58:38 +0000
+Subject: [PATCH] MIPS: pci-ar724x: use dynamically allocated PCI controller
+ structure
+
+commit 908339ef25b1d5e80f1c6fab22b9958174708b4a upstream.
+
+The current code uses static variables to store the
+PCI controller specific data. This works if the system
+contains one PCI controller only, however it becomes
+impractical when multiple PCI controllers are present.
+
+Move the variables into a dynamically allocated controller
+specific structure, and use that instead of the static
+variables.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4912/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/pci-ar724x.c |  129 ++++++++++++++++++++++++++++----------------
+ 1 file changed, 82 insertions(+), 47 deletions(-)
+
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -9,6 +9,7 @@
+  *  by the Free Software Foundation.
+  */
+ 
++#include <linux/spinlock.h>
+ #include <linux/irq.h>
+ #include <linux/pci.h>
+ #include <linux/module.h>
+@@ -28,38 +29,56 @@
+ 
+ #define AR7240_BAR0_WAR_VALUE	0xffff
+ 
+-static DEFINE_SPINLOCK(ar724x_pci_lock);
+-static void __iomem *ar724x_pci_devcfg_base;
+-static void __iomem *ar724x_pci_ctrl_base;
+-
+-static u32 ar724x_pci_bar0_value;
+-static bool ar724x_pci_bar0_is_cached;
+-static bool ar724x_pci_link_up;
++struct ar724x_pci_controller {
++	void __iomem *devcfg_base;
++	void __iomem *ctrl_base;
+ 
+-static inline bool ar724x_pci_check_link(void)
++	int irq;
++
++	bool link_up;
++	bool bar0_is_cached;
++	u32  bar0_value;
++
++	spinlock_t lock;
++
++	struct pci_controller pci_controller;
++};
++
++static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
+ {
+ 	u32 reset;
+ 
+-	reset = __raw_readl(ar724x_pci_ctrl_base + AR724X_PCI_REG_RESET);
++	reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET);
+ 	return reset & AR724X_PCI_RESET_LINK_UP;
+ }
+ 
++static inline struct ar724x_pci_controller *
++pci_bus_to_ar724x_controller(struct pci_bus *bus)
++{
++	struct pci_controller *hose;
++
++	hose = (struct pci_controller *) bus->sysdata;
++	return container_of(hose, struct ar724x_pci_controller, pci_controller);
++}
++
+ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+ 			    int size, uint32_t *value)
+ {
++	struct ar724x_pci_controller *apc;
+ 	unsigned long flags;
+ 	void __iomem *base;
+ 	u32 data;
+ 
+-	if (!ar724x_pci_link_up)
++	apc = pci_bus_to_ar724x_controller(bus);
++	if (!apc->link_up)
+ 		return PCIBIOS_DEVICE_NOT_FOUND;
+ 
+ 	if (devfn)
+ 		return PCIBIOS_DEVICE_NOT_FOUND;
+ 
+-	base = ar724x_pci_devcfg_base;
++	base = apc->devcfg_base;
+ 
+-	spin_lock_irqsave(&ar724x_pci_lock, flags);
++	spin_lock_irqsave(&apc->lock, flags);
+ 	data = __raw_readl(base + (where & ~3));
+ 
+ 	switch (size) {
+@@ -78,17 +97,17 @@ static int ar724x_pci_read(struct pci_bu
+ 	case 4:
+ 		break;
+ 	default:
+-		spin_unlock_irqrestore(&ar724x_pci_lock, flags);
++		spin_unlock_irqrestore(&apc->lock, flags);
+ 
+ 		return PCIBIOS_BAD_REGISTER_NUMBER;
+ 	}
+ 
+-	spin_unlock_irqrestore(&ar724x_pci_lock, flags);
++	spin_unlock_irqrestore(&apc->lock, flags);
+ 
+ 	if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
+-	    ar724x_pci_bar0_is_cached) {
++	    apc->bar0_is_cached) {
+ 		/* use the cached value */
+-		*value = ar724x_pci_bar0_value;
++		*value = apc->bar0_value;
+ 	} else {
+ 		*value = data;
+ 	}
+@@ -99,12 +118,14 @@ static int ar724x_pci_read(struct pci_bu
+ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
+ 			     int size, uint32_t value)
+ {
++	struct ar724x_pci_controller *apc;
+ 	unsigned long flags;
+ 	void __iomem *base;
+ 	u32 data;
+ 	int s;
+ 
+-	if (!ar724x_pci_link_up)
++	apc = pci_bus_to_ar724x_controller(bus);
++	if (!apc->link_up)
+ 		return PCIBIOS_DEVICE_NOT_FOUND;
+ 
+ 	if (devfn)
+@@ -122,18 +143,18 @@ static int ar724x_pci_write(struct pci_b
+ 			 * BAR0 register in order to make the device memory
+ 			 * accessible.
+ 			 */
+-			ar724x_pci_bar0_is_cached = true;
+-			ar724x_pci_bar0_value = value;
++			apc->bar0_is_cached = true;
++			apc->bar0_value = value;
+ 
+ 			value = AR7240_BAR0_WAR_VALUE;
+ 		} else {
+-			ar724x_pci_bar0_is_cached = false;
++			apc->bar0_is_cached = false;
+ 		}
+ 	}
+ 
+-	base = ar724x_pci_devcfg_base;
++	base = apc->devcfg_base;
+ 
+-	spin_lock_irqsave(&ar724x_pci_lock, flags);
++	spin_lock_irqsave(&apc->lock, flags);
+ 	data = __raw_readl(base + (where & ~3));
+ 
+ 	switch (size) {
+@@ -151,7 +172,7 @@ static int ar724x_pci_write(struct pci_b
+ 		data = value;
+ 		break;
+ 	default:
+-		spin_unlock_irqrestore(&ar724x_pci_lock, flags);
++		spin_unlock_irqrestore(&apc->lock, flags);
+ 
+ 		return PCIBIOS_BAD_REGISTER_NUMBER;
+ 	}
+@@ -159,7 +180,7 @@ static int ar724x_pci_write(struct pci_b
+ 	__raw_writel(data, base + (where & ~3));
+ 	/* flush write */
+ 	__raw_readl(base + (where & ~3));
+-	spin_unlock_irqrestore(&ar724x_pci_lock, flags);
++	spin_unlock_irqrestore(&apc->lock, flags);
+ 
+ 	return PCIBIOS_SUCCESSFUL;
+ }
+@@ -183,18 +204,14 @@ static struct resource ar724x_mem_resour
+ 	.flags  = IORESOURCE_MEM,
+ };
+ 
+-static struct pci_controller ar724x_pci_controller = {
+-	.pci_ops        = &ar724x_pci_ops,
+-	.io_resource    = &ar724x_io_resource,
+-	.mem_resource	= &ar724x_mem_resource,
+-};
+-
+ static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
+ {
++	struct ar724x_pci_controller *apc;
+ 	void __iomem *base;
+ 	u32 pending;
+ 
+-	base = ar724x_pci_ctrl_base;
++	apc = irq_get_handler_data(irq);
++	base = apc->ctrl_base;
+ 
+ 	pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
+ 		  __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+@@ -208,10 +225,12 @@ static void ar724x_pci_irq_handler(unsig
+ 
+ static void ar724x_pci_irq_unmask(struct irq_data *d)
+ {
++	struct ar724x_pci_controller *apc;
+ 	void __iomem *base;
+ 	u32 t;
+ 
+-	base = ar724x_pci_ctrl_base;
++	apc = irq_data_get_irq_chip_data(d);
++	base = apc->ctrl_base;
+ 
+ 	switch (d->irq) {
+ 	case ATH79_PCI_IRQ(0):
+@@ -225,10 +244,12 @@ static void ar724x_pci_irq_unmask(struct
+ 
+ static void ar724x_pci_irq_mask(struct irq_data *d)
+ {
++	struct ar724x_pci_controller *apc;
+ 	void __iomem *base;
+ 	u32 t;
+ 
+-	base = ar724x_pci_ctrl_base;
++	apc = irq_data_get_irq_chip_data(d);
++	base = apc->ctrl_base;
+ 
+ 	switch (d->irq) {
+ 	case ATH79_PCI_IRQ(0):
+@@ -255,12 +276,12 @@ static struct irq_chip ar724x_pci_irq_ch
+ 	.irq_mask_ack	= ar724x_pci_irq_mask,
+ };
+ 
+-static void ar724x_pci_irq_init(int irq)
++static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc)
+ {
+ 	void __iomem *base;
+ 	int i;
+ 
+-	base = ar724x_pci_ctrl_base;
++	base = apc->ctrl_base;
+ 
+ 	__raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
+ 	__raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
+@@ -268,45 +289,59 @@ static void ar724x_pci_irq_init(int irq)
+ 	BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT);
+ 
+ 	for (i = ATH79_PCI_IRQ_BASE;
+-	     i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++)
++	     i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) {
+ 		irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
+ 					 handle_level_irq);
++		irq_set_chip_data(i, apc);
++	}
+ 
+-	irq_set_chained_handler(irq, ar724x_pci_irq_handler);
++	irq_set_handler_data(apc->irq, apc);
++	irq_set_chained_handler(apc->irq, ar724x_pci_irq_handler);
+ }
+ 
+ static int ar724x_pci_probe(struct platform_device *pdev)
+ {
++	struct ar724x_pci_controller *apc;
+ 	struct resource *res;
+-	int irq;
++
++	apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller),
++			    GFP_KERNEL);
++	if (!apc)
++		return -ENOMEM;
+ 
+ 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base");
+ 	if (!res)
+ 		return -EINVAL;
+ 
+-	ar724x_pci_ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
+-	if (ar724x_pci_ctrl_base == NULL)
++	apc->ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
++	if (apc->ctrl_base == NULL)
+ 		return -EBUSY;
+ 
+ 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
+ 	if (!res)
+ 		return -EINVAL;
+ 
+-	ar724x_pci_devcfg_base = devm_request_and_ioremap(&pdev->dev, res);
+-	if (!ar724x_pci_devcfg_base)
++	apc->devcfg_base = devm_request_and_ioremap(&pdev->dev, res);
++	if (!apc->devcfg_base)
+ 		return -EBUSY;
+ 
+-	irq = platform_get_irq(pdev, 0);
+-	if (irq < 0)
++	apc->irq = platform_get_irq(pdev, 0);
++	if (apc->irq < 0)
+ 		return -EINVAL;
+ 
+-	ar724x_pci_link_up = ar724x_pci_check_link();
+-	if (!ar724x_pci_link_up)
++	spin_lock_init(&apc->lock);
++
++	apc->pci_controller.pci_ops = &ar724x_pci_ops;
++	apc->pci_controller.io_resource = &ar724x_io_resource;
++	apc->pci_controller.mem_resource = &ar724x_mem_resource;
++
++	apc->link_up = ar724x_pci_check_link(apc);
++	if (!apc->link_up)
+ 		dev_warn(&pdev->dev, "PCIe link is down\n");
+ 
+-	ar724x_pci_irq_init(irq);
++	ar724x_pci_irq_init(apc);
+ 
+-	register_pci_controller(&ar724x_pci_controller);
++	register_pci_controller(&apc->pci_controller);
+ 
+ 	return 0;
+ }
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/018-MIPS-pci-ar724x-remove-static-PCI-IO-MEM-resources.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/018-MIPS-pci-ar724x-remove-static-PCI-IO-MEM-resources.patch.svn-base
new file mode 100644
index 0000000..823488a
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/018-MIPS-pci-ar724x-remove-static-PCI-IO-MEM-resources.patch.svn-base
@@ -0,0 +1,139 @@
+From d80b05d19c2772ded40403d578d8e90d38c85257 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 3 Feb 2013 09:59:45 +0000
+Subject: [PATCH] MIPS: pci-ar724x: remove static PCI IO/MEM resources
+
+commit 34b134aebda89888b6985b7a3139e9cbdf209236 upstream.
+
+Static resources become impractical when multiple
+PCI controllers are present. Move the resources
+into the platform device registration code and
+change the probe routine to get those from there
+platform device's resources.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4914/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/pci.c      |   21 ++++++++++++++++++++-
+ arch/mips/pci/pci-ar724x.c |   40 ++++++++++++++++++++++++----------------
+ 2 files changed, 44 insertions(+), 17 deletions(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -139,10 +139,13 @@ static struct platform_device *
+ ath79_register_pci_ar724x(int id,
+ 			  unsigned long cfg_base,
+ 			  unsigned long ctrl_base,
++			  unsigned long mem_base,
++			  unsigned long mem_size,
++			  unsigned long io_base,
+ 			  int irq)
+ {
+ 	struct platform_device *pdev;
+-	struct resource res[3];
++	struct resource res[5];
+ 
+ 	memset(res, 0, sizeof(res));
+ 
+@@ -160,6 +163,16 @@ ath79_register_pci_ar724x(int id,
+ 	res[2].start = irq;
+ 	res[2].end = irq;
+ 
++	res[3].name = "mem_base";
++	res[3].flags = IORESOURCE_MEM;
++	res[3].start = mem_base;
++	res[3].end = mem_base + mem_size - 1;
++
++	res[4].name = "io_base";
++	res[4].flags = IORESOURCE_IO;
++	res[4].start = io_base;
++	res[4].end = io_base;
++
+ 	pdev = platform_device_register_simple("ar724x-pci", id,
+ 					       res, ARRAY_SIZE(res));
+ 	return pdev;
+@@ -175,6 +188,9 @@ int __init ath79_register_pci(void)
+ 		pdev = ath79_register_pci_ar724x(-1,
+ 						 AR724X_PCI_CFG_BASE,
+ 						 AR724X_PCI_CTRL_BASE,
++						 AR724X_PCI_MEM_BASE,
++						 AR724X_PCI_MEM_SIZE,
++						 0,
+ 						 ATH79_CPU_IRQ_IP2);
+ 	} else if (soc_is_ar9342() ||
+ 		   soc_is_ar9344()) {
+@@ -187,6 +203,9 @@ int __init ath79_register_pci(void)
+ 		pdev = ath79_register_pci_ar724x(-1,
+ 						 AR724X_PCI_CFG_BASE,
+ 						 AR724X_PCI_CTRL_BASE,
++						 AR724X_PCI_MEM_BASE,
++						 AR724X_PCI_MEM_SIZE,
++						 0,
+ 						 ATH79_IP2_IRQ(0));
+ 	} else {
+ 		/* No PCI support */
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -42,6 +42,8 @@ struct ar724x_pci_controller {
+ 	spinlock_t lock;
+ 
+ 	struct pci_controller pci_controller;
++	struct resource io_res;
++	struct resource mem_res;
+ };
+ 
+ static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
+@@ -190,20 +192,6 @@ static struct pci_ops ar724x_pci_ops = {
+ 	.write	= ar724x_pci_write,
+ };
+ 
+-static struct resource ar724x_io_resource = {
+-	.name   = "PCI IO space",
+-	.start  = 0,
+-	.end    = 0,
+-	.flags  = IORESOURCE_IO,
+-};
+-
+-static struct resource ar724x_mem_resource = {
+-	.name   = "PCI memory space",
+-	.start  = AR724X_PCI_MEM_BASE,
+-	.end    = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1,
+-	.flags  = IORESOURCE_MEM,
+-};
+-
+ static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
+ {
+ 	struct ar724x_pci_controller *apc;
+@@ -331,9 +319,29 @@ static int ar724x_pci_probe(struct platf
+ 
+ 	spin_lock_init(&apc->lock);
+ 
++	res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
++	if (!res)
++		return -EINVAL;
++
++	apc->io_res.parent = res;
++	apc->io_res.name = "PCI IO space";
++	apc->io_res.start = res->start;
++	apc->io_res.end = res->end;
++	apc->io_res.flags = IORESOURCE_IO;
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
++	if (!res)
++		return -EINVAL;
++
++	apc->mem_res.parent = res;
++	apc->mem_res.name = "PCI memory space";
++	apc->mem_res.start = res->start;
++	apc->mem_res.end = res->end;
++	apc->mem_res.flags = IORESOURCE_MEM;
++
+ 	apc->pci_controller.pci_ops = &ar724x_pci_ops;
+-	apc->pci_controller.io_resource = &ar724x_io_resource;
+-	apc->pci_controller.mem_resource = &ar724x_mem_resource;
++	apc->pci_controller.io_resource = &apc->io_res;
++	apc->pci_controller.mem_resource = &apc->mem_res;
+ 
+ 	apc->link_up = ar724x_pci_check_link(apc);
+ 	if (!apc->link_up)
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/019-MIPS-pci-ar724x-use-per-controller-IRQ-base.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/019-MIPS-pci-ar724x-use-per-controller-IRQ-base.patch.svn-base
new file mode 100644
index 0000000..0eabfb1
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/019-MIPS-pci-ar724x-use-per-controller-IRQ-base.patch.svn-base
@@ -0,0 +1,117 @@
+From d85015ff3ab6df0e776c2aefc51f2da023c1edcf Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 3 Feb 2013 10:00:16 +0000
+Subject: [PATCH] MIPS: pci-ar724x: use per-controller IRQ base
+
+commit 8b66d461187ff61c5755001af7296e6edde48423 upstream.
+
+Change to the code to use per-controller IRQ base.
+This is needed for multiple PCI controller support.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4915/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/pci-ar724x.c |   31 +++++++++++++++++++++----------
+ 1 file changed, 21 insertions(+), 10 deletions(-)
+
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -34,6 +34,7 @@ struct ar724x_pci_controller {
+ 	void __iomem *ctrl_base;
+ 
+ 	int irq;
++	int irq_base;
+ 
+ 	bool link_up;
+ 	bool bar0_is_cached;
+@@ -205,7 +206,7 @@ static void ar724x_pci_irq_handler(unsig
+ 		  __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+ 
+ 	if (pending & AR724X_PCI_INT_DEV0)
+-		generic_handle_irq(ATH79_PCI_IRQ(0));
++		generic_handle_irq(apc->irq_base + 0);
+ 
+ 	else
+ 		spurious_interrupt();
+@@ -215,13 +216,15 @@ static void ar724x_pci_irq_unmask(struct
+ {
+ 	struct ar724x_pci_controller *apc;
+ 	void __iomem *base;
++	int offset;
+ 	u32 t;
+ 
+ 	apc = irq_data_get_irq_chip_data(d);
+ 	base = apc->ctrl_base;
++	offset = apc->irq_base - d->irq;
+ 
+-	switch (d->irq) {
+-	case ATH79_PCI_IRQ(0):
++	switch (offset) {
++	case 0:
+ 		t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+ 		__raw_writel(t | AR724X_PCI_INT_DEV0,
+ 			     base + AR724X_PCI_REG_INT_MASK);
+@@ -234,13 +237,15 @@ static void ar724x_pci_irq_mask(struct i
+ {
+ 	struct ar724x_pci_controller *apc;
+ 	void __iomem *base;
++	int offset;
+ 	u32 t;
+ 
+ 	apc = irq_data_get_irq_chip_data(d);
+ 	base = apc->ctrl_base;
++	offset = apc->irq_base - d->irq;
+ 
+-	switch (d->irq) {
+-	case ATH79_PCI_IRQ(0):
++	switch (offset) {
++	case 0:
+ 		t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+ 		__raw_writel(t & ~AR724X_PCI_INT_DEV0,
+ 			     base + AR724X_PCI_REG_INT_MASK);
+@@ -264,7 +269,8 @@ static struct irq_chip ar724x_pci_irq_ch
+ 	.irq_mask_ack	= ar724x_pci_irq_mask,
+ };
+ 
+-static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc)
++static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
++				int id)
+ {
+ 	void __iomem *base;
+ 	int i;
+@@ -274,10 +280,10 @@ static void ar724x_pci_irq_init(struct a
+ 	__raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
+ 	__raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
+ 
+-	BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT);
++	apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
+ 
+-	for (i = ATH79_PCI_IRQ_BASE;
+-	     i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) {
++	for (i = apc->irq_base;
++	     i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
+ 		irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
+ 					 handle_level_irq);
+ 		irq_set_chip_data(i, apc);
+@@ -291,6 +297,11 @@ static int ar724x_pci_probe(struct platf
+ {
+ 	struct ar724x_pci_controller *apc;
+ 	struct resource *res;
++	int id;
++
++	id = pdev->id;
++	if (id == -1)
++		id = 0;
+ 
+ 	apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller),
+ 			    GFP_KERNEL);
+@@ -347,7 +358,7 @@ static int ar724x_pci_probe(struct platf
+ 	if (!apc->link_up)
+ 		dev_warn(&pdev->dev, "PCIe link is down\n");
+ 
+-	ar724x_pci_irq_init(apc);
++	ar724x_pci_irq_init(apc, id);
+ 
+ 	register_pci_controller(&apc->pci_controller);
+ 
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/020-MIPS-pci-ar724x-setup-command-register-of-the-PCI-co.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/020-MIPS-pci-ar724x-setup-command-register-of-the-PCI-co.patch.svn-base
new file mode 100644
index 0000000..301803c
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/020-MIPS-pci-ar724x-setup-command-register-of-the-PCI-co.patch.svn-base
@@ -0,0 +1,178 @@
+From 5e079d9b7ac5dda3be9f215f8440333597f57b26 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 3 Feb 2013 14:52:47 +0000
+Subject: [PATCH] MIPS: pci-ar724x: setup command register of the PCI
+ controller
+
+commit 12401fc28d40aa5bf8bda6991a96b6d7a3dae3ac upstream.
+
+The command register of the PCI controller is
+not initialized correctly by the bootloader on
+some boards and this leads to non working PCI
+bus.
+
+Add code to initialize the command register
+from the Linux code to avoid this.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4916/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/pci.c                          |   10 +++-
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    2 +
+ arch/mips/pci/pci-ar724x.c                     |   63 ++++++++++++++++++++++++
+ 3 files changed, 74 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -139,13 +139,14 @@ static struct platform_device *
+ ath79_register_pci_ar724x(int id,
+ 			  unsigned long cfg_base,
+ 			  unsigned long ctrl_base,
++			  unsigned long crp_base,
+ 			  unsigned long mem_base,
+ 			  unsigned long mem_size,
+ 			  unsigned long io_base,
+ 			  int irq)
+ {
+ 	struct platform_device *pdev;
+-	struct resource res[5];
++	struct resource res[6];
+ 
+ 	memset(res, 0, sizeof(res));
+ 
+@@ -173,6 +174,11 @@ ath79_register_pci_ar724x(int id,
+ 	res[4].start = io_base;
+ 	res[4].end = io_base;
+ 
++	res[5].name = "crp_base";
++	res[5].flags = IORESOURCE_MEM;
++	res[5].start = crp_base;
++	res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1;
++
+ 	pdev = platform_device_register_simple("ar724x-pci", id,
+ 					       res, ARRAY_SIZE(res));
+ 	return pdev;
+@@ -188,6 +194,7 @@ int __init ath79_register_pci(void)
+ 		pdev = ath79_register_pci_ar724x(-1,
+ 						 AR724X_PCI_CFG_BASE,
+ 						 AR724X_PCI_CTRL_BASE,
++						 AR724X_PCI_CRP_BASE,
+ 						 AR724X_PCI_MEM_BASE,
+ 						 AR724X_PCI_MEM_SIZE,
+ 						 0,
+@@ -203,6 +210,7 @@ int __init ath79_register_pci(void)
+ 		pdev = ath79_register_pci_ar724x(-1,
+ 						 AR724X_PCI_CFG_BASE,
+ 						 AR724X_PCI_CTRL_BASE,
++						 AR724X_PCI_CRP_BASE,
+ 						 AR724X_PCI_MEM_BASE,
+ 						 AR724X_PCI_MEM_SIZE,
+ 						 0,
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -67,6 +67,8 @@
+ 
+ #define AR724X_PCI_CFG_BASE	0x14000000
+ #define AR724X_PCI_CFG_SIZE	0x1000
++#define AR724X_PCI_CRP_BASE	(AR71XX_APB_BASE + 0x000c0000)
++#define AR724X_PCI_CRP_SIZE	0x1000
+ #define AR724X_PCI_CTRL_BASE	(AR71XX_APB_BASE + 0x000f0000)
+ #define AR724X_PCI_CTRL_SIZE	0x100
+ 
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -29,9 +29,17 @@
+ 
+ #define AR7240_BAR0_WAR_VALUE	0xffff
+ 
++#define AR724X_PCI_CMD_INIT	(PCI_COMMAND_MEMORY |		\
++				 PCI_COMMAND_MASTER |		\
++				 PCI_COMMAND_INVALIDATE |	\
++				 PCI_COMMAND_PARITY |		\
++				 PCI_COMMAND_SERR |		\
++				 PCI_COMMAND_FAST_BACK)
++
+ struct ar724x_pci_controller {
+ 	void __iomem *devcfg_base;
+ 	void __iomem *ctrl_base;
++	void __iomem *crp_base;
+ 
+ 	int irq;
+ 	int irq_base;
+@@ -64,6 +72,51 @@ pci_bus_to_ar724x_controller(struct pci_
+ 	return container_of(hose, struct ar724x_pci_controller, pci_controller);
+ }
+ 
++static int ar724x_pci_local_write(struct ar724x_pci_controller *apc,
++				  int where, int size, u32 value)
++{
++	unsigned long flags;
++	void __iomem *base;
++	u32 data;
++	int s;
++
++	WARN_ON(where & (size - 1));
++
++	if (!apc->link_up)
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	base = apc->crp_base;
++
++	spin_lock_irqsave(&apc->lock, flags);
++	data = __raw_readl(base + (where & ~3));
++
++	switch (size) {
++	case 1:
++		s = ((where & 3) * 8);
++		data &= ~(0xff << s);
++		data |= ((value & 0xff) << s);
++		break;
++	case 2:
++		s = ((where & 2) * 8);
++		data &= ~(0xffff << s);
++		data |= ((value & 0xffff) << s);
++		break;
++	case 4:
++		data = value;
++		break;
++	default:
++		spin_unlock_irqrestore(&apc->lock, flags);
++		return PCIBIOS_BAD_REGISTER_NUMBER;
++	}
++
++	__raw_writel(data, base + (where & ~3));
++	/* flush write */
++	__raw_readl(base + (where & ~3));
++	spin_unlock_irqrestore(&apc->lock, flags);
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
+ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+ 			    int size, uint32_t *value)
+ {
+@@ -324,6 +377,14 @@ static int ar724x_pci_probe(struct platf
+ 	if (!apc->devcfg_base)
+ 		return -EBUSY;
+ 
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crp_base");
++	if (!res)
++		return -EINVAL;
++
++	apc->crp_base = devm_request_and_ioremap(&pdev->dev, res);
++	if (apc->crp_base == NULL)
++		return -EBUSY;
++
+ 	apc->irq = platform_get_irq(pdev, 0);
+ 	if (apc->irq < 0)
+ 		return -EINVAL;
+@@ -360,6 +421,8 @@ static int ar724x_pci_probe(struct platf
+ 
+ 	ar724x_pci_irq_init(apc, id);
+ 
++	ar724x_pci_local_write(apc, PCI_COMMAND, 4, AR724X_PCI_CMD_INIT);
++
+ 	register_pci_controller(&apc->pci_controller);
+ 
+ 	return 0;
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/021-MIPS-pci-ar71xx-use-dynamically-allocated-PCI-contro.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/021-MIPS-pci-ar71xx-use-dynamically-allocated-PCI-contro.patch.svn-base
new file mode 100644
index 0000000..a8b53c8
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/021-MIPS-pci-ar71xx-use-dynamically-allocated-PCI-contro.patch.svn-base
@@ -0,0 +1,226 @@
+From 0f0f7d810226c734141a20de85289dbb0dda8f96 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 7 Feb 2013 19:28:14 +0000
+Subject: [PATCH] MIPS: pci-ar71xx: use dynamically allocated PCI controller
+ structure
+
+commit f18118a868f1f7e7bdfea176a204fcc44fae2985 upstream.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4926/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/pci-ar71xx.c |   84 ++++++++++++++++++++++++++++----------------
+ 1 file changed, 53 insertions(+), 31 deletions(-)
+
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -48,8 +48,12 @@
+ 
+ #define AR71XX_PCI_IRQ_COUNT		5
+ 
+-static DEFINE_SPINLOCK(ar71xx_pci_lock);
+-static void __iomem *ar71xx_pcicfg_base;
++struct ar71xx_pci_controller {
++	void __iomem *cfg_base;
++	spinlock_t lock;
++	int irq;
++	struct pci_controller pci_ctrl;
++};
+ 
+ /* Byte lane enable bits */
+ static const u8 ar71xx_pci_ble_table[4][4] = {
+@@ -92,9 +96,18 @@ static inline u32 ar71xx_pci_bus_addr(st
+ 	return ret;
+ }
+ 
+-static int ar71xx_pci_check_error(int quiet)
++static inline struct ar71xx_pci_controller *
++pci_bus_to_ar71xx_controller(struct pci_bus *bus)
+ {
+-	void __iomem *base = ar71xx_pcicfg_base;
++	struct pci_controller *hose;
++
++	hose = (struct pci_controller *) bus->sysdata;
++	return container_of(hose, struct ar71xx_pci_controller, pci_ctrl);
++}
++
++static int ar71xx_pci_check_error(struct ar71xx_pci_controller *apc, int quiet)
++{
++	void __iomem *base = apc->cfg_base;
+ 	u32 pci_err;
+ 	u32 ahb_err;
+ 
+@@ -129,9 +142,10 @@ static int ar71xx_pci_check_error(int qu
+ 	return !!(ahb_err | pci_err);
+ }
+ 
+-static inline void ar71xx_pci_local_write(int where, int size, u32 value)
++static inline void ar71xx_pci_local_write(struct ar71xx_pci_controller *apc,
++					  int where, int size, u32 value)
+ {
+-	void __iomem *base = ar71xx_pcicfg_base;
++	void __iomem *base = apc->cfg_base;
+ 	u32 ad_cbe;
+ 
+ 	value = value << (8 * (where & 3));
+@@ -147,7 +161,8 @@ static inline int ar71xx_pci_set_cfgaddr
+ 					 unsigned int devfn,
+ 					 int where, int size, u32 cmd)
+ {
+-	void __iomem *base = ar71xx_pcicfg_base;
++	struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
++	void __iomem *base = apc->cfg_base;
+ 	u32 addr;
+ 
+ 	addr = ar71xx_pci_bus_addr(bus, devfn, where);
+@@ -156,13 +171,14 @@ static inline int ar71xx_pci_set_cfgaddr
+ 	__raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
+ 		     base + AR71XX_PCI_REG_CFG_CBE);
+ 
+-	return ar71xx_pci_check_error(1);
++	return ar71xx_pci_check_error(apc, 1);
+ }
+ 
+ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+ 				  int where, int size, u32 *value)
+ {
+-	void __iomem *base = ar71xx_pcicfg_base;
++	struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
++	void __iomem *base = apc->cfg_base;
+ 	unsigned long flags;
+ 	u32 data;
+ 	int err;
+@@ -171,7 +187,7 @@ static int ar71xx_pci_read_config(struct
+ 	ret = PCIBIOS_SUCCESSFUL;
+ 	data = ~0;
+ 
+-	spin_lock_irqsave(&ar71xx_pci_lock, flags);
++	spin_lock_irqsave(&apc->lock, flags);
+ 
+ 	err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
+ 				     AR71XX_PCI_CFG_CMD_READ);
+@@ -180,7 +196,7 @@ static int ar71xx_pci_read_config(struct
+ 	else
+ 		data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
+ 
+-	spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
++	spin_unlock_irqrestore(&apc->lock, flags);
+ 
+ 	*value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7];
+ 
+@@ -190,7 +206,8 @@ static int ar71xx_pci_read_config(struct
+ static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+ 				   int where, int size, u32 value)
+ {
+-	void __iomem *base = ar71xx_pcicfg_base;
++	struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
++	void __iomem *base = apc->cfg_base;
+ 	unsigned long flags;
+ 	int err;
+ 	int ret;
+@@ -198,7 +215,7 @@ static int ar71xx_pci_write_config(struc
+ 	value = value << (8 * (where & 3));
+ 	ret = PCIBIOS_SUCCESSFUL;
+ 
+-	spin_lock_irqsave(&ar71xx_pci_lock, flags);
++	spin_lock_irqsave(&apc->lock, flags);
+ 
+ 	err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
+ 				     AR71XX_PCI_CFG_CMD_WRITE);
+@@ -207,7 +224,7 @@ static int ar71xx_pci_write_config(struc
+ 	else
+ 		__raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
+ 
+-	spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
++	spin_unlock_irqrestore(&apc->lock, flags);
+ 
+ 	return ret;
+ }
+@@ -231,12 +248,6 @@ static struct resource ar71xx_pci_mem_re
+ 	.flags		= IORESOURCE_MEM
+ };
+ 
+-static struct pci_controller ar71xx_pci_controller = {
+-	.pci_ops	= &ar71xx_pci_ops,
+-	.mem_resource	= &ar71xx_pci_mem_resource,
+-	.io_resource	= &ar71xx_pci_io_resource,
+-};
+-
+ static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
+ {
+ 	void __iomem *base = ath79_reset_base;
+@@ -294,7 +305,7 @@ static struct irq_chip ar71xx_pci_irq_ch
+ 	.irq_mask_ack	= ar71xx_pci_irq_mask,
+ };
+ 
+-static void ar71xx_pci_irq_init(int irq)
++static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
+ {
+ 	void __iomem *base = ath79_reset_base;
+ 	int i;
+@@ -309,7 +320,7 @@ static void ar71xx_pci_irq_init(int irq)
+ 		irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
+ 					 handle_level_irq);
+ 
+-	irq_set_chained_handler(irq, ar71xx_pci_irq_handler);
++	irq_set_chained_handler(apc->irq, ar71xx_pci_irq_handler);
+ }
+ 
+ static void ar71xx_pci_reset(void)
+@@ -336,20 +347,27 @@ static void ar71xx_pci_reset(void)
+ 
+ static int ar71xx_pci_probe(struct platform_device *pdev)
+ {
++	struct ar71xx_pci_controller *apc;
+ 	struct resource *res;
+-	int irq;
+ 	u32 t;
+ 
++	apc = devm_kzalloc(&pdev->dev, sizeof(struct ar71xx_pci_controller),
++			   GFP_KERNEL);
++	if (!apc)
++		return -ENOMEM;
++
++	spin_lock_init(&apc->lock);
++
+ 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
+ 	if (!res)
+ 		return -EINVAL;
+ 
+-	ar71xx_pcicfg_base = devm_request_and_ioremap(&pdev->dev, res);
+-	if (!ar71xx_pcicfg_base)
++	apc->cfg_base = devm_request_and_ioremap(&pdev->dev, res);
++	if (!apc->cfg_base)
+ 		return -ENOMEM;
+ 
+-	irq = platform_get_irq(pdev, 0);
+-	if (irq < 0)
++	apc->irq = platform_get_irq(pdev, 0);
++	if (apc->irq < 0)
+ 		return -EINVAL;
+ 
+ 	ar71xx_pci_reset();
+@@ -357,14 +375,18 @@ static int ar71xx_pci_probe(struct platf
+ 	/* setup COMMAND register */
+ 	t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
+ 	  | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
+-	ar71xx_pci_local_write(PCI_COMMAND, 4, t);
++	ar71xx_pci_local_write(apc, PCI_COMMAND, 4, t);
+ 
+ 	/* clear bus errors */
+-	ar71xx_pci_check_error(1);
++	ar71xx_pci_check_error(apc, 1);
++
++	ar71xx_pci_irq_init(apc);
+ 
+-	ar71xx_pci_irq_init(irq);
++	apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
++	apc->pci_ctrl.mem_resource = &ar71xx_pci_mem_resource;
++	apc->pci_ctrl.io_resource = &ar71xx_pci_io_resource;
+ 
+-	register_pci_controller(&ar71xx_pci_controller);
++	register_pci_controller(&apc->pci_ctrl);
+ 
+ 	return 0;
+ }
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/022-MIPS-pci-ar71xx-remove-static-PCI-IO-MEM-resources.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/022-MIPS-pci-ar71xx-remove-static-PCI-IO-MEM-resources.patch.svn-base
new file mode 100644
index 0000000..c7c4064
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/022-MIPS-pci-ar71xx-remove-static-PCI-IO-MEM-resources.patch.svn-base
@@ -0,0 +1,113 @@
+From f073cb029873ed487e14784d3682b6aa25afe997 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 7 Feb 2013 19:28:15 +0000
+Subject: [PATCH] MIPS: pci-ar71xx: remove static PCI IO/MEM resources
+
+commit 42cb60d1fab4c81ef24876d985e08fc5bb899e41 upstream.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4927/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/pci.c      |   12 +++++++++++-
+ arch/mips/pci/pci-ar71xx.c |   40 ++++++++++++++++++++++++----------------
+ 2 files changed, 35 insertions(+), 17 deletions(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -117,7 +117,7 @@ static struct platform_device *
+ ath79_register_pci_ar71xx(void)
+ {
+ 	struct platform_device *pdev;
+-	struct resource res[2];
++	struct resource res[4];
+ 
+ 	memset(res, 0, sizeof(res));
+ 
+@@ -130,6 +130,16 @@ ath79_register_pci_ar71xx(void)
+ 	res[1].start = ATH79_CPU_IRQ_IP2;
+ 	res[1].end = ATH79_CPU_IRQ_IP2;
+ 
++	res[2].name = "io_base";
++	res[2].flags = IORESOURCE_IO;
++	res[2].start = 0;
++	res[2].end = 0;
++
++	res[3].name = "mem_base";
++	res[3].flags = IORESOURCE_MEM;
++	res[3].start = AR71XX_PCI_MEM_BASE;
++	res[3].end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1;
++
+ 	pdev = platform_device_register_simple("ar71xx-pci", -1,
+ 					       res, ARRAY_SIZE(res));
+ 	return pdev;
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -53,6 +53,8 @@ struct ar71xx_pci_controller {
+ 	spinlock_t lock;
+ 	int irq;
+ 	struct pci_controller pci_ctrl;
++	struct resource io_res;
++	struct resource mem_res;
+ };
+ 
+ /* Byte lane enable bits */
+@@ -234,20 +236,6 @@ static struct pci_ops ar71xx_pci_ops = {
+ 	.write	= ar71xx_pci_write_config,
+ };
+ 
+-static struct resource ar71xx_pci_io_resource = {
+-	.name		= "PCI IO space",
+-	.start		= 0,
+-	.end		= 0,
+-	.flags		= IORESOURCE_IO,
+-};
+-
+-static struct resource ar71xx_pci_mem_resource = {
+-	.name		= "PCI memory space",
+-	.start		= AR71XX_PCI_MEM_BASE,
+-	.end		= AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
+-	.flags		= IORESOURCE_MEM
+-};
+-
+ static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
+ {
+ 	void __iomem *base = ath79_reset_base;
+@@ -370,6 +358,26 @@ static int ar71xx_pci_probe(struct platf
+ 	if (apc->irq < 0)
+ 		return -EINVAL;
+ 
++	res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
++	if (!res)
++		return -EINVAL;
++
++	apc->io_res.parent = res;
++	apc->io_res.name = "PCI IO space";
++	apc->io_res.start = res->start;
++	apc->io_res.end = res->end;
++	apc->io_res.flags = IORESOURCE_IO;
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
++	if (!res)
++		return -EINVAL;
++
++	apc->mem_res.parent = res;
++	apc->mem_res.name = "PCI memory space";
++	apc->mem_res.start = res->start;
++	apc->mem_res.end = res->end;
++	apc->mem_res.flags = IORESOURCE_MEM;
++
+ 	ar71xx_pci_reset();
+ 
+ 	/* setup COMMAND register */
+@@ -383,8 +391,8 @@ static int ar71xx_pci_probe(struct platf
+ 	ar71xx_pci_irq_init(apc);
+ 
+ 	apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
+-	apc->pci_ctrl.mem_resource = &ar71xx_pci_mem_resource;
+-	apc->pci_ctrl.io_resource = &ar71xx_pci_io_resource;
++	apc->pci_ctrl.mem_resource = &apc->mem_res;
++	apc->pci_ctrl.io_resource = &apc->io_res;
+ 
+ 	register_pci_controller(&apc->pci_ctrl);
+ 
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/023-MIPS-pci-ar71xx-move-irq-base-to-the-controller-stru.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/023-MIPS-pci-ar71xx-move-irq-base-to-the-controller-stru.patch.svn-base
new file mode 100644
index 0000000..78c2f07
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/023-MIPS-pci-ar71xx-move-irq-base-to-the-controller-stru.patch.svn-base
@@ -0,0 +1,105 @@
+From bec8339e917651e51592dd57ed005f8ccd9b0e8d Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 7 Feb 2013 19:29:38 +0000
+Subject: [PATCH] MIPS: pci-ar71xx: move irq base to the controller structure
+
+commit 326e8d17d73fdf213f6334917ef46b2ba7b1354a upstream.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4928/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/pci-ar71xx.c |   32 ++++++++++++++++++++++++--------
+ 1 file changed, 24 insertions(+), 8 deletions(-)
+
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -52,6 +52,7 @@ struct ar71xx_pci_controller {
+ 	void __iomem *cfg_base;
+ 	spinlock_t lock;
+ 	int irq;
++	int irq_base;
+ 	struct pci_controller pci_ctrl;
+ 	struct resource io_res;
+ 	struct resource mem_res;
+@@ -238,23 +239,26 @@ static struct pci_ops ar71xx_pci_ops = {
+ 
+ static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
+ {
++	struct ar71xx_pci_controller *apc;
+ 	void __iomem *base = ath79_reset_base;
+ 	u32 pending;
+ 
++	apc = irq_get_handler_data(irq);
++
+ 	pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
+ 		  __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+ 
+ 	if (pending & AR71XX_PCI_INT_DEV0)
+-		generic_handle_irq(ATH79_PCI_IRQ(0));
++		generic_handle_irq(apc->irq_base + 0);
+ 
+ 	else if (pending & AR71XX_PCI_INT_DEV1)
+-		generic_handle_irq(ATH79_PCI_IRQ(1));
++		generic_handle_irq(apc->irq_base + 1);
+ 
+ 	else if (pending & AR71XX_PCI_INT_DEV2)
+-		generic_handle_irq(ATH79_PCI_IRQ(2));
++		generic_handle_irq(apc->irq_base + 2);
+ 
+ 	else if (pending & AR71XX_PCI_INT_CORE)
+-		generic_handle_irq(ATH79_PCI_IRQ(4));
++		generic_handle_irq(apc->irq_base + 4);
+ 
+ 	else
+ 		spurious_interrupt();
+@@ -262,10 +266,14 @@ static void ar71xx_pci_irq_handler(unsig
+ 
+ static void ar71xx_pci_irq_unmask(struct irq_data *d)
+ {
+-	unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE;
++	struct ar71xx_pci_controller *apc;
++	unsigned int irq;
+ 	void __iomem *base = ath79_reset_base;
+ 	u32 t;
+ 
++	apc = irq_data_get_irq_chip_data(d);
++	irq = d->irq - apc->irq_base;
++
+ 	t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+ 	__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+ 
+@@ -275,10 +283,14 @@ static void ar71xx_pci_irq_unmask(struct
+ 
+ static void ar71xx_pci_irq_mask(struct irq_data *d)
+ {
+-	unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE;
++	struct ar71xx_pci_controller *apc;
++	unsigned int irq;
+ 	void __iomem *base = ath79_reset_base;
+ 	u32 t;
+ 
++	apc = irq_data_get_irq_chip_data(d);
++	irq = d->irq - apc->irq_base;
++
+ 	t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+ 	__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+ 
+@@ -303,11 +315,15 @@ static void ar71xx_pci_irq_init(struct a
+ 
+ 	BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
+ 
+-	for (i = ATH79_PCI_IRQ_BASE;
+-	     i < ATH79_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++)
++	apc->irq_base = ATH79_PCI_IRQ_BASE;
++	for (i = apc->irq_base;
++	     i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) {
+ 		irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
+ 					 handle_level_irq);
++		irq_set_chip_data(i, apc);
++	}
+ 
++	irq_set_handler_data(apc->irq, apc);
+ 	irq_set_chained_handler(apc->irq, ar71xx_pci_irq_handler);
+ }
+ 
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/024-ath79-add-ATH79_CPU_IRQ-macro.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/024-ath79-add-ATH79_CPU_IRQ-macro.patch.svn-base
new file mode 100644
index 0000000..3624433
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/024-ath79-add-ATH79_CPU_IRQ-macro.patch.svn-base
@@ -0,0 +1,266 @@
+From 7377d32d37490f0804662c76a72b68d45d93966e Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 7 Feb 2013 19:32:23 +0000
+Subject: [PATCH] ath79: add ATH79_CPU_IRQ() macro
+
+commit 7e69c10a8ee1f201c040997c6742c27e915730ad upstream.
+
+Remove the individual ATH79_CPU_IRQ_* constants and
+use the new macro instead of those.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4929/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/dev-usb.c              |   12 ++++++------
+ arch/mips/ath79/dev-wmac.c             |    8 ++++----
+ arch/mips/ath79/irq.c                  |   32 ++++++++++++++++----------------
+ arch/mips/ath79/pci.c                  |    6 +++---
+ arch/mips/include/asm/mach-ath79/irq.h |    9 ++-------
+ 5 files changed, 31 insertions(+), 36 deletions(-)
+
+--- a/arch/mips/ath79/dev-usb.c
++++ b/arch/mips/ath79/dev-usb.c
+@@ -111,7 +111,7 @@ static void __init ath79_usb_setup(void)
+ 	platform_device_register(&ath79_ohci_device);
+ 
+ 	ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE,
+-				AR71XX_EHCI_SIZE, ATH79_CPU_IRQ_USB);
++				AR71XX_EHCI_SIZE, ATH79_CPU_IRQ(3));
+ 	ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1;
+ 	platform_device_register(&ath79_ehci_device);
+ }
+@@ -136,7 +136,7 @@ static void __init ar7240_usb_setup(void
+ 	iounmap(usb_ctrl_base);
+ 
+ 	ath79_usb_init_resource(ath79_ohci_resources, AR7240_OHCI_BASE,
+-				AR7240_OHCI_SIZE, ATH79_CPU_IRQ_USB);
++				AR7240_OHCI_SIZE, ATH79_CPU_IRQ(3));
+ 	platform_device_register(&ath79_ohci_device);
+ }
+ 
+@@ -152,7 +152,7 @@ static void __init ar724x_usb_setup(void
+ 	mdelay(10);
+ 
+ 	ath79_usb_init_resource(ath79_ehci_resources, AR724X_EHCI_BASE,
+-				AR724X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
++				AR724X_EHCI_SIZE, ATH79_CPU_IRQ(3));
+ 	ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
+ 	platform_device_register(&ath79_ehci_device);
+ }
+@@ -169,7 +169,7 @@ static void __init ar913x_usb_setup(void
+ 	mdelay(10);
+ 
+ 	ath79_usb_init_resource(ath79_ehci_resources, AR913X_EHCI_BASE,
+-				AR913X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
++				AR913X_EHCI_SIZE, ATH79_CPU_IRQ(3));
+ 	ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
+ 	platform_device_register(&ath79_ehci_device);
+ }
+@@ -186,7 +186,7 @@ static void __init ar933x_usb_setup(void
+ 	mdelay(10);
+ 
+ 	ath79_usb_init_resource(ath79_ehci_resources, AR933X_EHCI_BASE,
+-				AR933X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
++				AR933X_EHCI_SIZE, ATH79_CPU_IRQ(3));
+ 	ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
+ 	platform_device_register(&ath79_ehci_device);
+ }
+@@ -212,7 +212,7 @@ static void __init ar934x_usb_setup(void
+ 	udelay(1000);
+ 
+ 	ath79_usb_init_resource(ath79_ehci_resources, AR934X_EHCI_BASE,
+-				AR934X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
++				AR934X_EHCI_SIZE, ATH79_CPU_IRQ(3));
+ 	ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
+ 	platform_device_register(&ath79_ehci_device);
+ }
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -55,8 +55,8 @@ static void __init ar913x_wmac_setup(voi
+ 
+ 	ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
+ 	ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
+-	ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
+-	ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
++	ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
++	ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
+ }
+ 
+ 
+@@ -83,8 +83,8 @@ static void __init ar933x_wmac_setup(voi
+ 
+ 	ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
+ 	ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
+-	ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
+-	ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
++	ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
++	ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
+ 
+ 	t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
+ 	if (t & AR933X_BOOTSTRAP_REF_CLK_40)
+--- a/arch/mips/ath79/irq.c
++++ b/arch/mips/ath79/irq.c
+@@ -114,7 +114,7 @@ static void __init ath79_misc_irq_init(v
+ 					 handle_level_irq);
+ 	}
+ 
+-	irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
++	irq_set_chained_handler(ATH79_CPU_IRQ(6), ath79_misc_irq_handler);
+ }
+ 
+ static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
+@@ -147,7 +147,7 @@ static void ar934x_ip2_irq_init(void)
+ 		irq_set_chip_and_handler(i, &dummy_irq_chip,
+ 					 handle_level_irq);
+ 
+-	irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch);
++	irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
+ }
+ 
+ asmlinkage void plat_irq_dispatch(void)
+@@ -157,22 +157,22 @@ asmlinkage void plat_irq_dispatch(void)
+ 	pending = read_c0_status() & read_c0_cause() & ST0_IM;
+ 
+ 	if (pending & STATUSF_IP7)
+-		do_IRQ(ATH79_CPU_IRQ_TIMER);
++		do_IRQ(ATH79_CPU_IRQ(7));
+ 
+ 	else if (pending & STATUSF_IP2)
+ 		ath79_ip2_handler();
+ 
+ 	else if (pending & STATUSF_IP4)
+-		do_IRQ(ATH79_CPU_IRQ_GE0);
++		do_IRQ(ATH79_CPU_IRQ(4));
+ 
+ 	else if (pending & STATUSF_IP5)
+-		do_IRQ(ATH79_CPU_IRQ_GE1);
++		do_IRQ(ATH79_CPU_IRQ(5));
+ 
+ 	else if (pending & STATUSF_IP3)
+ 		ath79_ip3_handler();
+ 
+ 	else if (pending & STATUSF_IP6)
+-		do_IRQ(ATH79_CPU_IRQ_MISC);
++		do_IRQ(ATH79_CPU_IRQ(6));
+ 
+ 	else
+ 		spurious_interrupt();
+@@ -188,60 +188,60 @@ asmlinkage void plat_irq_dispatch(void)
+ static void ar71xx_ip2_handler(void)
+ {
+ 	ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI);
+-	do_IRQ(ATH79_CPU_IRQ_IP2);
++	do_IRQ(ATH79_CPU_IRQ(2));
+ }
+ 
+ static void ar724x_ip2_handler(void)
+ {
+ 	ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE);
+-	do_IRQ(ATH79_CPU_IRQ_IP2);
++	do_IRQ(ATH79_CPU_IRQ(2));
+ }
+ 
+ static void ar913x_ip2_handler(void)
+ {
+ 	ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC);
+-	do_IRQ(ATH79_CPU_IRQ_IP2);
++	do_IRQ(ATH79_CPU_IRQ(2));
+ }
+ 
+ static void ar933x_ip2_handler(void)
+ {
+ 	ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC);
+-	do_IRQ(ATH79_CPU_IRQ_IP2);
++	do_IRQ(ATH79_CPU_IRQ(2));
+ }
+ 
+ static void ar934x_ip2_handler(void)
+ {
+-	do_IRQ(ATH79_CPU_IRQ_IP2);
++	do_IRQ(ATH79_CPU_IRQ(2));
+ }
+ 
+ static void ar71xx_ip3_handler(void)
+ {
+ 	ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
+-	do_IRQ(ATH79_CPU_IRQ_USB);
++	do_IRQ(ATH79_CPU_IRQ(3));
+ }
+ 
+ static void ar724x_ip3_handler(void)
+ {
+ 	ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB);
+-	do_IRQ(ATH79_CPU_IRQ_USB);
++	do_IRQ(ATH79_CPU_IRQ(3));
+ }
+ 
+ static void ar913x_ip3_handler(void)
+ {
+ 	ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB);
+-	do_IRQ(ATH79_CPU_IRQ_USB);
++	do_IRQ(ATH79_CPU_IRQ(3));
+ }
+ 
+ static void ar933x_ip3_handler(void)
+ {
+ 	ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB);
+-	do_IRQ(ATH79_CPU_IRQ_USB);
++	do_IRQ(ATH79_CPU_IRQ(3));
+ }
+ 
+ static void ar934x_ip3_handler(void)
+ {
+ 	ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB);
+-	do_IRQ(ATH79_CPU_IRQ_USB);
++	do_IRQ(ATH79_CPU_IRQ(3));
+ }
+ 
+ void __init arch_init_irq(void)
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -127,8 +127,8 @@ ath79_register_pci_ar71xx(void)
+ 	res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1;
+ 
+ 	res[1].flags = IORESOURCE_IRQ;
+-	res[1].start = ATH79_CPU_IRQ_IP2;
+-	res[1].end = ATH79_CPU_IRQ_IP2;
++	res[1].start = ATH79_CPU_IRQ(2);
++	res[1].end = ATH79_CPU_IRQ(2);
+ 
+ 	res[2].name = "io_base";
+ 	res[2].flags = IORESOURCE_IO;
+@@ -208,7 +208,7 @@ int __init ath79_register_pci(void)
+ 						 AR724X_PCI_MEM_BASE,
+ 						 AR724X_PCI_MEM_SIZE,
+ 						 0,
+-						 ATH79_CPU_IRQ_IP2);
++						 ATH79_CPU_IRQ(2));
+ 	} else if (soc_is_ar9342() ||
+ 		   soc_is_ar9344()) {
+ 		u32 bootstrap;
+--- a/arch/mips/include/asm/mach-ath79/irq.h
++++ b/arch/mips/include/asm/mach-ath79/irq.h
+@@ -12,6 +12,8 @@
+ #define MIPS_CPU_IRQ_BASE	0
+ #define NR_IRQS			48
+ 
++#define ATH79_CPU_IRQ(_x)	(MIPS_CPU_IRQ_BASE + (_x))
++
+ #define ATH79_MISC_IRQ_BASE	8
+ #define ATH79_MISC_IRQ_COUNT	32
+ #define ATH79_MISC_IRQ(_x)	(ATH79_MISC_IRQ_BASE + (_x))
+@@ -24,13 +26,6 @@
+ #define ATH79_IP2_IRQ_COUNT	2
+ #define ATH79_IP2_IRQ(_x)	(ATH79_IP2_IRQ_BASE + (_x))
+ 
+-#define ATH79_CPU_IRQ_IP2	(MIPS_CPU_IRQ_BASE + 2)
+-#define ATH79_CPU_IRQ_USB	(MIPS_CPU_IRQ_BASE + 3)
+-#define ATH79_CPU_IRQ_GE0	(MIPS_CPU_IRQ_BASE + 4)
+-#define ATH79_CPU_IRQ_GE1	(MIPS_CPU_IRQ_BASE + 5)
+-#define ATH79_CPU_IRQ_MISC	(MIPS_CPU_IRQ_BASE + 6)
+-#define ATH79_CPU_IRQ_TIMER	(MIPS_CPU_IRQ_BASE + 7)
+-
+ #define ATH79_MISC_IRQ_TIMER	(ATH79_MISC_IRQ_BASE + 0)
+ #define ATH79_MISC_IRQ_ERROR	(ATH79_MISC_IRQ_BASE + 1)
+ #define ATH79_MISC_IRQ_GPIO	(ATH79_MISC_IRQ_BASE + 2)
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/025-ath79-remove-ATH79_MISC_IRQ_-defines.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/025-ath79-remove-ATH79_MISC_IRQ_-defines.patch.svn-base
new file mode 100644
index 0000000..8278ad3
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/025-ath79-remove-ATH79_MISC_IRQ_-defines.patch.svn-base
@@ -0,0 +1,85 @@
+From f4414336ae509d20c043264bc9f8f6bafb0e8a6f Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 7 Feb 2013 19:32:24 +0000
+Subject: [PATCH] ath79: remove ATH79_MISC_IRQ_* defines
+
+commit fd633cf1cfe978003888dc78ff94f926fbe7dd8a upstream.
+
+Use the ATH79_MISC_IRQ() macro instead.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4930/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/dev-common.c           |    6 +++---
+ arch/mips/ath79/dev-usb.c              |    2 +-
+ arch/mips/ath79/irq.c                  |    2 +-
+ arch/mips/include/asm/mach-ath79/irq.h |   13 -------------
+ 4 files changed, 5 insertions(+), 18 deletions(-)
+
+--- a/arch/mips/ath79/dev-common.c
++++ b/arch/mips/ath79/dev-common.c
+@@ -36,7 +36,7 @@ static struct resource ath79_uart_resour
+ static struct plat_serial8250_port ath79_uart_data[] = {
+ 	{
+ 		.mapbase	= AR71XX_UART_BASE,
+-		.irq		= ATH79_MISC_IRQ_UART,
++		.irq		= ATH79_MISC_IRQ(3),
+ 		.flags		= AR71XX_UART_FLAGS,
+ 		.iotype		= UPIO_MEM32,
+ 		.regshift	= 2,
+@@ -62,8 +62,8 @@ static struct resource ar933x_uart_resou
+ 		.flags	= IORESOURCE_MEM,
+ 	},
+ 	{
+-		.start	= ATH79_MISC_IRQ_UART,
+-		.end	= ATH79_MISC_IRQ_UART,
++		.start	= ATH79_MISC_IRQ(3),
++		.end	= ATH79_MISC_IRQ(3),
+ 		.flags	= IORESOURCE_IRQ,
+ 	},
+ };
+--- a/arch/mips/ath79/dev-usb.c
++++ b/arch/mips/ath79/dev-usb.c
+@@ -107,7 +107,7 @@ static void __init ath79_usb_setup(void)
+ 	mdelay(900);
+ 
+ 	ath79_usb_init_resource(ath79_ohci_resources, AR71XX_OHCI_BASE,
+-				AR71XX_OHCI_SIZE, ATH79_MISC_IRQ_OHCI);
++				AR71XX_OHCI_SIZE, ATH79_MISC_IRQ(6));
+ 	platform_device_register(&ath79_ohci_device);
+ 
+ 	ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE,
+--- a/arch/mips/ath79/irq.c
++++ b/arch/mips/ath79/irq.c
+@@ -265,7 +265,7 @@ void __init arch_init_irq(void)
+ 		BUG();
+ 	}
+ 
+-	cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC;
++	cp0_perfcount_irq = ATH79_MISC_IRQ(5);
+ 	mips_cpu_irq_init();
+ 	ath79_misc_irq_init();
+ 
+--- a/arch/mips/include/asm/mach-ath79/irq.h
++++ b/arch/mips/include/asm/mach-ath79/irq.h
+@@ -26,19 +26,6 @@
+ #define ATH79_IP2_IRQ_COUNT	2
+ #define ATH79_IP2_IRQ(_x)	(ATH79_IP2_IRQ_BASE + (_x))
+ 
+-#define ATH79_MISC_IRQ_TIMER	(ATH79_MISC_IRQ_BASE + 0)
+-#define ATH79_MISC_IRQ_ERROR	(ATH79_MISC_IRQ_BASE + 1)
+-#define ATH79_MISC_IRQ_GPIO	(ATH79_MISC_IRQ_BASE + 2)
+-#define ATH79_MISC_IRQ_UART	(ATH79_MISC_IRQ_BASE + 3)
+-#define ATH79_MISC_IRQ_WDOG	(ATH79_MISC_IRQ_BASE + 4)
+-#define ATH79_MISC_IRQ_PERFC	(ATH79_MISC_IRQ_BASE + 5)
+-#define ATH79_MISC_IRQ_OHCI	(ATH79_MISC_IRQ_BASE + 6)
+-#define ATH79_MISC_IRQ_DMA	(ATH79_MISC_IRQ_BASE + 7)
+-#define ATH79_MISC_IRQ_TIMER2	(ATH79_MISC_IRQ_BASE + 8)
+-#define ATH79_MISC_IRQ_TIMER3	(ATH79_MISC_IRQ_BASE + 9)
+-#define ATH79_MISC_IRQ_TIMER4	(ATH79_MISC_IRQ_BASE + 10)
+-#define ATH79_MISC_IRQ_ETHSW	(ATH79_MISC_IRQ_BASE + 12)
+-
+ #include_next <irq.h>
+ 
+ #endif /* __ASM_MACH_ATH79_IRQ_H */
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/026-MIPS-ath79-use-dynamically-allocated-USB-platform-de.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/026-MIPS-ath79-use-dynamically-allocated-USB-platform-de.patch.svn-base
new file mode 100644
index 0000000..e7770cc
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/026-MIPS-ath79-use-dynamically-allocated-USB-platform-de.patch.svn-base
@@ -0,0 +1,205 @@
+From 9c3c3f7be27c88b59359e743be0437eb6f9af41f Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sat, 9 Feb 2013 17:57:52 +0000
+Subject: [PATCH] MIPS: ath79: use dynamically allocated USB platform devices
+
+commit 90a938d1add4859ad3e43c3dd5ee54bd0627e42d upstream.
+
+The current code uses static resources and static platform
+device instances for the possible USB controllers in the
+system. These static variables contains initial values which
+leads to data segment pollution.
+
+Remove the static variables and use dynamically allocated
+structures instead.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4933/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/dev-usb.c |  111 +++++++++++++++++++++------------------------
+ 1 file changed, 51 insertions(+), 60 deletions(-)
+
+--- a/arch/mips/ath79/dev-usb.c
++++ b/arch/mips/ath79/dev-usb.c
+@@ -25,29 +25,11 @@
+ #include "common.h"
+ #include "dev-usb.h"
+ 
+-static struct resource ath79_ohci_resources[2];
+-
+-static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32);
++static u64 ath79_usb_dmamask = DMA_BIT_MASK(32);
+ 
+ static struct usb_ohci_pdata ath79_ohci_pdata = {
+ };
+ 
+-static struct platform_device ath79_ohci_device = {
+-	.name		= "ohci-platform",
+-	.id		= -1,
+-	.resource	= ath79_ohci_resources,
+-	.num_resources	= ARRAY_SIZE(ath79_ohci_resources),
+-	.dev = {
+-		.dma_mask		= &ath79_ohci_dmamask,
+-		.coherent_dma_mask	= DMA_BIT_MASK(32),
+-		.platform_data		= &ath79_ohci_pdata,
+-	},
+-};
+-
+-static struct resource ath79_ehci_resources[2];
+-
+-static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32);
+-
+ static struct usb_ehci_pdata ath79_ehci_pdata_v1 = {
+ 	.has_synopsys_hc_bug	= 1,
+ };
+@@ -57,22 +39,16 @@ static struct usb_ehci_pdata ath79_ehci_
+ 	.has_tt			= 1,
+ };
+ 
+-static struct platform_device ath79_ehci_device = {
+-	.name		= "ehci-platform",
+-	.id		= -1,
+-	.resource	= ath79_ehci_resources,
+-	.num_resources	= ARRAY_SIZE(ath79_ehci_resources),
+-	.dev = {
+-		.dma_mask		= &ath79_ehci_dmamask,
+-		.coherent_dma_mask	= DMA_BIT_MASK(32),
+-	},
+-};
+-
+-static void __init ath79_usb_init_resource(struct resource res[2],
+-					   unsigned long base,
+-					   unsigned long size,
+-					   int irq)
++static void __init ath79_usb_register(const char *name, int id,
++				      unsigned long base, unsigned long size,
++				      int irq, const void *data,
++				      size_t data_size)
+ {
++	struct resource res[2];
++	struct platform_device *pdev;
++
++	memset(res, 0, sizeof(res));
++
+ 	res[0].flags = IORESOURCE_MEM;
+ 	res[0].start = base;
+ 	res[0].end = base + size - 1;
+@@ -80,6 +56,19 @@ static void __init ath79_usb_init_resour
+ 	res[1].flags = IORESOURCE_IRQ;
+ 	res[1].start = irq;
+ 	res[1].end = irq;
++
++	pdev = platform_device_register_resndata(NULL, name, id,
++						 res, ARRAY_SIZE(res),
++						 data, data_size);
++
++	if (IS_ERR(pdev)) {
++		pr_err("ath79: unable to register USB at %08lx, err=%d\n",
++		       base, (int) PTR_ERR(pdev));
++		return;
++	}
++
++	pdev->dev.dma_mask = &ath79_usb_dmamask;
++	pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+ }
+ 
+ #define AR71XX_USB_RESET_MASK	(AR71XX_RESET_USB_HOST | \
+@@ -106,14 +95,15 @@ static void __init ath79_usb_setup(void)
+ 
+ 	mdelay(900);
+ 
+-	ath79_usb_init_resource(ath79_ohci_resources, AR71XX_OHCI_BASE,
+-				AR71XX_OHCI_SIZE, ATH79_MISC_IRQ(6));
+-	platform_device_register(&ath79_ohci_device);
+-
+-	ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE,
+-				AR71XX_EHCI_SIZE, ATH79_CPU_IRQ(3));
+-	ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1;
+-	platform_device_register(&ath79_ehci_device);
++	ath79_usb_register("ohci-platform", -1,
++			   AR71XX_OHCI_BASE, AR71XX_OHCI_SIZE,
++			   ATH79_MISC_IRQ(6),
++			   &ath79_ohci_pdata, sizeof(ath79_ohci_pdata));
++
++	ath79_usb_register("ehci-platform", -1,
++			   AR71XX_EHCI_BASE, AR71XX_EHCI_SIZE,
++			   ATH79_CPU_IRQ(3),
++			   &ath79_ehci_pdata_v1, sizeof(ath79_ehci_pdata_v1));
+ }
+ 
+ static void __init ar7240_usb_setup(void)
+@@ -135,9 +125,10 @@ static void __init ar7240_usb_setup(void
+ 
+ 	iounmap(usb_ctrl_base);
+ 
+-	ath79_usb_init_resource(ath79_ohci_resources, AR7240_OHCI_BASE,
+-				AR7240_OHCI_SIZE, ATH79_CPU_IRQ(3));
+-	platform_device_register(&ath79_ohci_device);
++	ath79_usb_register("ohci-platform", -1,
++			   AR7240_OHCI_BASE, AR7240_OHCI_SIZE,
++			   ATH79_CPU_IRQ(3),
++			   &ath79_ohci_pdata, sizeof(ath79_ohci_pdata));
+ }
+ 
+ static void __init ar724x_usb_setup(void)
+@@ -151,10 +142,10 @@ static void __init ar724x_usb_setup(void
+ 	ath79_device_reset_clear(AR724X_RESET_USB_PHY);
+ 	mdelay(10);
+ 
+-	ath79_usb_init_resource(ath79_ehci_resources, AR724X_EHCI_BASE,
+-				AR724X_EHCI_SIZE, ATH79_CPU_IRQ(3));
+-	ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
+-	platform_device_register(&ath79_ehci_device);
++	ath79_usb_register("ehci-platform", -1,
++			   AR724X_EHCI_BASE, AR724X_EHCI_SIZE,
++			   ATH79_CPU_IRQ(3),
++			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+ }
+ 
+ static void __init ar913x_usb_setup(void)
+@@ -168,10 +159,10 @@ static void __init ar913x_usb_setup(void
+ 	ath79_device_reset_clear(AR913X_RESET_USB_PHY);
+ 	mdelay(10);
+ 
+-	ath79_usb_init_resource(ath79_ehci_resources, AR913X_EHCI_BASE,
+-				AR913X_EHCI_SIZE, ATH79_CPU_IRQ(3));
+-	ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
+-	platform_device_register(&ath79_ehci_device);
++	ath79_usb_register("ehci-platform", -1,
++			   AR913X_EHCI_BASE, AR913X_EHCI_SIZE,
++			   ATH79_CPU_IRQ(3),
++			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+ }
+ 
+ static void __init ar933x_usb_setup(void)
+@@ -185,10 +176,10 @@ static void __init ar933x_usb_setup(void
+ 	ath79_device_reset_clear(AR933X_RESET_USB_PHY);
+ 	mdelay(10);
+ 
+-	ath79_usb_init_resource(ath79_ehci_resources, AR933X_EHCI_BASE,
+-				AR933X_EHCI_SIZE, ATH79_CPU_IRQ(3));
+-	ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
+-	platform_device_register(&ath79_ehci_device);
++	ath79_usb_register("ehci-platform", -1,
++			   AR933X_EHCI_BASE, AR933X_EHCI_SIZE,
++			   ATH79_CPU_IRQ(3),
++			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+ }
+ 
+ static void __init ar934x_usb_setup(void)
+@@ -211,10 +202,10 @@ static void __init ar934x_usb_setup(void
+ 	ath79_device_reset_clear(AR934X_RESET_USB_HOST);
+ 	udelay(1000);
+ 
+-	ath79_usb_init_resource(ath79_ehci_resources, AR934X_EHCI_BASE,
+-				AR934X_EHCI_SIZE, ATH79_CPU_IRQ(3));
+-	ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
+-	platform_device_register(&ath79_ehci_device);
++	ath79_usb_register("ehci-platform", -1,
++			   AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
++			   ATH79_CPU_IRQ(3),
++			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+ }
+ 
+ void __init ath79_register_usb(void)
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/027-MIPS-ath79-fix-WMAC-IRQ-resource-assignment.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/027-MIPS-ath79-fix-WMAC-IRQ-resource-assignment.patch.svn-base
new file mode 100644
index 0000000..97065d5
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/027-MIPS-ath79-fix-WMAC-IRQ-resource-assignment.patch.svn-base
@@ -0,0 +1,29 @@
+From acb28a2a03a93e351e26230511a9f38d0da62fdd Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 18:51:57 +0000
+Subject: [PATCH] MIPS: ath79: fix WMAC IRQ resource assignment
+
+commit e3b25cead4b58fbf60270ba73a1669bf9e5635f5 upstream.
+
+The '.start' field of the IRQ resource assigned twice
+in ar934x_wmac_setup(). The second assignment must
+set the '.end' field. Fix it.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4954/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/dev-wmac.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -107,7 +107,7 @@ static void ar934x_wmac_setup(void)
+ 	ath79_wmac_resources[0].start = AR934X_WMAC_BASE;
+ 	ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1;
+ 	ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
+-	ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
++	ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
+ 
+ 	t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
+ 	if (t & AR934X_BOOTSTRAP_REF_CLK_40)
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/028-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/028-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch.svn-base
new file mode 100644
index 0000000..38d735b
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/028-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch.svn-base
@@ -0,0 +1,43 @@
+From 8a4de56e3b7a6fbb777c78f87142bafc22c32ac2 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 13:38:15 +0000
+Subject: [PATCH] MIPS: ath79: add early printk support for the QCA955X SoCs
+
+commit 908987797076b848f01b32c21d61d0e152efc236 upstream.
+
+The patch allows to see kernel messages on the
+QCA955X SoCs in early boot stage.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4944/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/early_printk.c                 |    2 ++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    2 ++
+ 2 files changed, 4 insertions(+)
+
+--- a/arch/mips/ath79/early_printk.c
++++ b/arch/mips/ath79/early_printk.c
+@@ -74,6 +74,8 @@ static void prom_putchar_init(void)
+ 	case REV_ID_MAJOR_AR9341:
+ 	case REV_ID_MAJOR_AR9342:
+ 	case REV_ID_MAJOR_AR9344:
++	case REV_ID_MAJOR_QCA9556:
++	case REV_ID_MAJOR_QCA9558:
+ 		_prom_putchar = prom_putchar_ar71xx;
+ 		break;
+ 
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -370,6 +370,8 @@
+ #define REV_ID_MAJOR_AR9341		0x0120
+ #define REV_ID_MAJOR_AR9342		0x1120
+ #define REV_ID_MAJOR_AR9344		0x2120
++#define REV_ID_MAJOR_QCA9556		0x0130
++#define REV_ID_MAJOR_QCA9558		0x1130
+ 
+ #define AR71XX_REV_ID_MINOR_MASK	0x3
+ #define AR71XX_REV_ID_MINOR_AR7130	0x0
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/029-MIPS-ath79-add-SoC-detection-code-for-the-QCA955X-So.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/029-MIPS-ath79-add-SoC-detection-code-for-the-QCA955X-So.patch.svn-base
new file mode 100644
index 0000000..5a60ffe
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/029-MIPS-ath79-add-SoC-detection-code-for-the-QCA955X-So.patch.svn-base
@@ -0,0 +1,113 @@
+From f48780829e9de625cb7fa0850fc31d050da6adeb Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 13:38:16 +0000
+Subject: [PATCH] MIPS: ath79: add SoC detection code for the QCA955X SoCs
+
+commit 2e6c91e392fd7be2ef0ba1e9a20e0ebe8ab79cf3 upstream.
+
+Also add 'soc_is_qca955[68x]' helper functions
+and a Kconfig symbol for the SoC family.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4943/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/Kconfig                        |    4 ++++
+ arch/mips/ath79/setup.c                        |   18 +++++++++++++++++-
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    2 ++
+ arch/mips/include/asm/mach-ath79/ath79.h       |   17 +++++++++++++++++
+ 4 files changed, 40 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -88,6 +88,10 @@ config SOC_AR934X
+ 	select PCI_AR724X if PCI
+ 	def_bool n
+ 
++config SOC_QCA955X
++	select USB_ARCH_HAS_EHCI
++	def_bool n
++
+ config PCI_AR724X
+ 	def_bool n
+ 
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -164,13 +164,29 @@ static void __init ath79_detect_sys_type
+ 		rev = id & AR934X_REV_ID_REVISION_MASK;
+ 		break;
+ 
++	case REV_ID_MAJOR_QCA9556:
++		ath79_soc = ATH79_SOC_QCA9556;
++		chip = "9556";
++		rev = id & QCA955X_REV_ID_REVISION_MASK;
++		break;
++
++	case REV_ID_MAJOR_QCA9558:
++		ath79_soc = ATH79_SOC_QCA9558;
++		chip = "9558";
++		rev = id & QCA955X_REV_ID_REVISION_MASK;
++		break;
++
+ 	default:
+ 		panic("ath79: unknown SoC, id:0x%08x", id);
+ 	}
+ 
+ 	ath79_soc_rev = rev;
+ 
+-	sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
++	if (soc_is_qca955x())
++		sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
++			chip, rev);
++	else
++		sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
+ 	pr_info("SoC: %s\n", ath79_sys_type);
+ }
+ 
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -392,6 +392,8 @@
+ 
+ #define AR934X_REV_ID_REVISION_MASK     0xf
+ 
++#define QCA955X_REV_ID_REVISION_MASK	0xf
++
+ /*
+  * SPI block
+  */
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -32,6 +32,8 @@ enum ath79_soc_type {
+ 	ATH79_SOC_AR9341,
+ 	ATH79_SOC_AR9342,
+ 	ATH79_SOC_AR9344,
++	ATH79_SOC_QCA9556,
++	ATH79_SOC_QCA9558,
+ };
+ 
+ extern enum ath79_soc_type ath79_soc;
+@@ -98,6 +100,21 @@ static inline int soc_is_ar934x(void)
+ 	return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
+ }
+ 
++static inline int soc_is_qca9556(void)
++{
++	return ath79_soc == ATH79_SOC_QCA9556;
++}
++
++static inline int soc_is_qca9558(void)
++{
++	return ath79_soc == ATH79_SOC_QCA9558;
++}
++
++static inline int soc_is_qca955x(void)
++{
++	return soc_is_qca9556() || soc_is_qca9558();
++}
++
+ extern void __iomem *ath79_ddr_base;
+ extern void __iomem *ath79_pll_base;
+ extern void __iomem *ath79_reset_base;
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/030-MIPS-ath79-add-clock-setup-code-for-the-QCA955X-SoCs.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/030-MIPS-ath79-add-clock-setup-code-for-the-QCA955X-SoCs.patch.svn-base
new file mode 100644
index 0000000..e1d4bfc
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/030-MIPS-ath79-add-clock-setup-code-for-the-QCA955X-SoCs.patch.svn-base
@@ -0,0 +1,177 @@
+From 64d8592fd1f7265de8b31dbf294928eaf9983db5 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 13:38:17 +0000
+Subject: [PATCH] MIPS: ath79: add clock setup code for the QCA955X SoCs
+
+commit 41583c05c15cd3adb848f9ee8316bf8084c961cb upstream.
+
+The patch adds code to get various clock frequencies
+from the PLLs used in the QCA955x SoCs.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4945/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/clock.c                        |   78 ++++++++++++++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |   39 ++++++++++++
+ 2 files changed, 117 insertions(+)
+
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -295,6 +295,82 @@ static void __init ar934x_clocks_init(vo
+ 	iounmap(dpll_base);
+ }
+ 
++static void __init qca955x_clocks_init(void)
++{
++	u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
++	u32 cpu_pll, ddr_pll;
++	u32 bootstrap;
++
++	bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
++	if (bootstrap &	QCA955X_BOOTSTRAP_REF_CLK_40)
++		ath79_ref_clk.rate = 40 * 1000 * 1000;
++	else
++		ath79_ref_clk.rate = 25 * 1000 * 1000;
++
++	pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
++	out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
++		  QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
++	ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
++		  QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
++	nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
++	       QCA955X_PLL_CPU_CONFIG_NINT_MASK;
++	frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
++	       QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
++
++	cpu_pll = nint * ath79_ref_clk.rate / ref_div;
++	cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6));
++	cpu_pll /= (1 << out_div);
++
++	pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
++	out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
++		  QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
++	ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
++		  QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
++	nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
++	       QCA955X_PLL_DDR_CONFIG_NINT_MASK;
++	frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
++	       QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
++
++	ddr_pll = nint * ath79_ref_clk.rate / ref_div;
++	ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10));
++	ddr_pll /= (1 << out_div);
++
++	clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
++
++	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
++		  QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
++
++	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
++		ath79_cpu_clk.rate = ath79_ref_clk.rate;
++	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
++		ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
++	else
++		ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
++
++	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
++		  QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
++
++	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
++		ath79_ddr_clk.rate = ath79_ref_clk.rate;
++	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
++		ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
++	else
++		ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
++
++	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
++		  QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
++
++	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
++		ath79_ahb_clk.rate = ath79_ref_clk.rate;
++	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
++		ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
++	else
++		ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
++
++	ath79_wdt_clk.rate = ath79_ref_clk.rate;
++	ath79_uart_clk.rate = ath79_ref_clk.rate;
++}
++
+ void __init ath79_clocks_init(void)
+ {
+ 	if (soc_is_ar71xx())
+@@ -307,6 +383,8 @@ void __init ath79_clocks_init(void)
+ 		ar933x_clocks_init();
+ 	else if (soc_is_ar934x())
+ 		ar934x_clocks_init();
++	else if (soc_is_qca955x())
++		qca955x_clocks_init();
+ 	else
+ 		BUG();
+ 
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -225,6 +225,41 @@
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL	BIT(21)
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL	BIT(24)
+ 
++#define QCA955X_PLL_CPU_CONFIG_REG		0x00
++#define QCA955X_PLL_DDR_CONFIG_REG		0x04
++#define QCA955X_PLL_CLK_CTRL_REG		0x08
++
++#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
++#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
++#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT	6
++#define QCA955X_PLL_CPU_CONFIG_NINT_MASK	0x3f
++#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT	12
++#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
++#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT	19
++#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK	0x3
++
++#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT	0
++#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK	0x3ff
++#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT	10
++#define QCA955X_PLL_DDR_CONFIG_NINT_MASK	0x3f
++#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT	16
++#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK	0x1f
++#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT	23
++#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK	0x7
++
++#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
++#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
++#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS		BIT(4)
++#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
++#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x1f
++#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
++#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x1f
++#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
++#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x1f
++#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL		BIT(20)
++#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL		BIT(21)
++#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)
++
+ /*
+  * USB_CONFIG block
+  */
+@@ -264,6 +299,8 @@
+ #define AR934X_RESET_REG_BOOTSTRAP		0xb0
+ #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS	0xac
+ 
++#define QCA955X_RESET_REG_BOOTSTRAP		0xb0
++
+ #define MISC_INT_ETHSW			BIT(12)
+ #define MISC_INT_TIMER4			BIT(10)
+ #define MISC_INT_TIMER3			BIT(9)
+@@ -341,6 +378,8 @@
+ #define AR934X_BOOTSTRAP_SDRAM_DISABLED	BIT(1)
+ #define AR934X_BOOTSTRAP_DDR1		BIT(0)
+ 
++#define QCA955X_BOOTSTRAP_REF_CLK_40	BIT(4)
++
+ #define AR934X_PCIE_WMAC_INT_WMAC_MISC		BIT(0)
+ #define AR934X_PCIE_WMAC_INT_WMAC_TX		BIT(1)
+ #define AR934X_PCIE_WMAC_INT_WMAC_RXLP		BIT(2)
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/031-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/031-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch.svn-base
new file mode 100644
index 0000000..dd79fa9
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/031-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch.svn-base
@@ -0,0 +1,246 @@
+From f1c0239d61d6d43469133d144e458f485b6cbda6 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 18:53:47 +0000
+Subject: [PATCH] MIPS: ath79: add IRQ handling code for the QCA955X SoCs
+
+commit 53330332f176eaa9567481c69bbad8b2176b4eb5 upstream.
+
+The IRQ routing in the QCA955x SoCs is slightly
+different from the routing implemented in the
+already supported SoCs.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4955/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/irq.c                          |  110 ++++++++++++++++++++++--
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |   32 +++++++
+ arch/mips/include/asm/mach-ath79/irq.h         |    6 +-
+ 3 files changed, 140 insertions(+), 8 deletions(-)
+
+--- a/arch/mips/ath79/irq.c
++++ b/arch/mips/ath79/irq.c
+@@ -103,7 +103,10 @@ static void __init ath79_misc_irq_init(v
+ 
+ 	if (soc_is_ar71xx() || soc_is_ar913x())
+ 		ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
+-	else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x())
++	else if (soc_is_ar724x() ||
++		 soc_is_ar933x() ||
++		 soc_is_ar934x() ||
++		 soc_is_qca955x())
+ 		ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
+ 	else
+ 		BUG();
+@@ -150,6 +153,88 @@ static void ar934x_ip2_irq_init(void)
+ 	irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
+ }
+ 
++static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
++{
++	u32 status;
++
++	disable_irq_nosync(irq);
++
++	status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
++	status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
++
++	if (status == 0) {
++		spurious_interrupt();
++		goto enable;
++	}
++
++	if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
++		/* TODO: flush DDR? */
++		generic_handle_irq(ATH79_IP2_IRQ(0));
++	}
++
++	if (status & QCA955X_EXT_INT_WMAC_ALL) {
++		/* TODO: flush DDR? */
++		generic_handle_irq(ATH79_IP2_IRQ(1));
++	}
++
++enable:
++	enable_irq(irq);
++}
++
++static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
++{
++	u32 status;
++
++	disable_irq_nosync(irq);
++
++	status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
++	status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
++		  QCA955X_EXT_INT_USB1 |
++		  QCA955X_EXT_INT_USB2;
++
++	if (status == 0) {
++		spurious_interrupt();
++		goto enable;
++	}
++
++	if (status & QCA955X_EXT_INT_USB1) {
++		/* TODO: flush DDR? */
++		generic_handle_irq(ATH79_IP3_IRQ(0));
++	}
++
++	if (status & QCA955X_EXT_INT_USB2) {
++		/* TODO: flush DDR? */
++		generic_handle_irq(ATH79_IP3_IRQ(1));
++	}
++
++	if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
++		/* TODO: flush DDR? */
++		generic_handle_irq(ATH79_IP3_IRQ(2));
++	}
++
++enable:
++	enable_irq(irq);
++}
++
++static void qca955x_irq_init(void)
++{
++	int i;
++
++	for (i = ATH79_IP2_IRQ_BASE;
++	     i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
++		irq_set_chip_and_handler(i, &dummy_irq_chip,
++					 handle_level_irq);
++
++	irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
++
++	for (i = ATH79_IP3_IRQ_BASE;
++	     i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
++		irq_set_chip_and_handler(i, &dummy_irq_chip,
++					 handle_level_irq);
++
++	irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
++}
++
+ asmlinkage void plat_irq_dispatch(void)
+ {
+ 	unsigned long pending;
+@@ -185,6 +270,17 @@ asmlinkage void plat_irq_dispatch(void)
+  * Issue a flush in the handlers to ensure that the driver sees
+  * the update.
+  */
++
++static void ath79_default_ip2_handler(void)
++{
++	do_IRQ(ATH79_CPU_IRQ(2));
++}
++
++static void ath79_default_ip3_handler(void)
++{
++	do_IRQ(ATH79_CPU_IRQ(3));
++}
++
+ static void ar71xx_ip2_handler(void)
+ {
+ 	ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI);
+@@ -209,11 +305,6 @@ static void ar933x_ip2_handler(void)
+ 	do_IRQ(ATH79_CPU_IRQ(2));
+ }
+ 
+-static void ar934x_ip2_handler(void)
+-{
+-	do_IRQ(ATH79_CPU_IRQ(2));
+-}
+-
+ static void ar71xx_ip3_handler(void)
+ {
+ 	ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
+@@ -259,8 +350,11 @@ void __init arch_init_irq(void)
+ 		ath79_ip2_handler = ar933x_ip2_handler;
+ 		ath79_ip3_handler = ar933x_ip3_handler;
+ 	} else if (soc_is_ar934x()) {
+-		ath79_ip2_handler = ar934x_ip2_handler;
++		ath79_ip2_handler = ath79_default_ip2_handler;
+ 		ath79_ip3_handler = ar934x_ip3_handler;
++	} else if (soc_is_qca955x()) {
++		ath79_ip2_handler = ath79_default_ip2_handler;
++		ath79_ip3_handler = ath79_default_ip3_handler;
+ 	} else {
+ 		BUG();
+ 	}
+@@ -271,4 +365,6 @@ void __init arch_init_irq(void)
+ 
+ 	if (soc_is_ar934x())
+ 		ar934x_ip2_irq_init();
++	else if (soc_is_qca955x())
++		qca955x_irq_init();
+ }
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -300,6 +300,7 @@
+ #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS	0xac
+ 
+ #define QCA955X_RESET_REG_BOOTSTRAP		0xb0
++#define QCA955X_RESET_REG_EXT_INT_STATUS	0xac
+ 
+ #define MISC_INT_ETHSW			BIT(12)
+ #define MISC_INT_TIMER4			BIT(10)
+@@ -398,6 +399,37 @@
+ 	 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
+ 	 AR934X_PCIE_WMAC_INT_PCIE_RC3)
+ 
++#define QCA955X_EXT_INT_WMAC_MISC		BIT(0)
++#define QCA955X_EXT_INT_WMAC_TX			BIT(1)
++#define QCA955X_EXT_INT_WMAC_RXLP		BIT(2)
++#define QCA955X_EXT_INT_WMAC_RXHP		BIT(3)
++#define QCA955X_EXT_INT_PCIE_RC1		BIT(4)
++#define QCA955X_EXT_INT_PCIE_RC1_INT0		BIT(5)
++#define QCA955X_EXT_INT_PCIE_RC1_INT1		BIT(6)
++#define QCA955X_EXT_INT_PCIE_RC1_INT2		BIT(7)
++#define QCA955X_EXT_INT_PCIE_RC1_INT3		BIT(8)
++#define QCA955X_EXT_INT_PCIE_RC2		BIT(12)
++#define QCA955X_EXT_INT_PCIE_RC2_INT0		BIT(13)
++#define QCA955X_EXT_INT_PCIE_RC2_INT1		BIT(14)
++#define QCA955X_EXT_INT_PCIE_RC2_INT2		BIT(15)
++#define QCA955X_EXT_INT_PCIE_RC2_INT3		BIT(16)
++#define QCA955X_EXT_INT_USB1			BIT(24)
++#define QCA955X_EXT_INT_USB2			BIT(28)
++
++#define QCA955X_EXT_INT_WMAC_ALL \
++	(QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
++	 QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
++
++#define QCA955X_EXT_INT_PCIE_RC1_ALL \
++	(QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
++	 QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
++	 QCA955X_EXT_INT_PCIE_RC1_INT3)
++
++#define QCA955X_EXT_INT_PCIE_RC2_ALL \
++	(QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
++	 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
++	 QCA955X_EXT_INT_PCIE_RC2_INT3)
++
+ #define REV_ID_MAJOR_MASK		0xfff0
+ #define REV_ID_MAJOR_AR71XX		0x00a0
+ #define REV_ID_MAJOR_AR913X		0x00b0
+--- a/arch/mips/include/asm/mach-ath79/irq.h
++++ b/arch/mips/include/asm/mach-ath79/irq.h
+@@ -10,7 +10,7 @@
+ #define __ASM_MACH_ATH79_IRQ_H
+ 
+ #define MIPS_CPU_IRQ_BASE	0
+-#define NR_IRQS			48
++#define NR_IRQS			51
+ 
+ #define ATH79_CPU_IRQ(_x)	(MIPS_CPU_IRQ_BASE + (_x))
+ 
+@@ -26,6 +26,10 @@
+ #define ATH79_IP2_IRQ_COUNT	2
+ #define ATH79_IP2_IRQ(_x)	(ATH79_IP2_IRQ_BASE + (_x))
+ 
++#define ATH79_IP3_IRQ_BASE	(ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT)
++#define ATH79_IP3_IRQ_COUNT     3
++#define ATH79_IP3_IRQ(_x)       (ATH79_IP3_IRQ_BASE + (_x))
++
+ #include_next <irq.h>
+ 
+ #endif /* __ASM_MACH_ATH79_IRQ_H */
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/032-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/032-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch.svn-base
new file mode 100644
index 0000000..538da3c
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/032-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch.svn-base
@@ -0,0 +1,50 @@
+From 8817bcbbaf64d54bd4d06659cc77d1bfc9e53dad Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 13:38:19 +0000
+Subject: [PATCH] MIPS: ath79: add GPIO setup code for the QCA955X SoCs
+
+commit f818ca3e6894d4a630a1ecc673c91df8fb6f6898 upstream.
+
+The existing code can handle the GPIO controller of
+the QCA955x SoCs. Add a minimal glue code to make it
+working.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4947/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/gpio.c                         |    4 +++-
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    1 +
+ 2 files changed, 4 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -194,12 +194,14 @@ void __init ath79_gpio_init(void)
+ 		ath79_gpio_count = AR933X_GPIO_COUNT;
+ 	else if (soc_is_ar934x())
+ 		ath79_gpio_count = AR934X_GPIO_COUNT;
++	else if (soc_is_qca955x())
++		ath79_gpio_count = QCA955X_GPIO_COUNT;
+ 	else
+ 		BUG();
+ 
+ 	ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
+ 	ath79_gpio_chip.ngpio = ath79_gpio_count;
+-	if (soc_is_ar934x()) {
++	if (soc_is_ar934x() || soc_is_qca955x()) {
+ 		ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
+ 		ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
+ 	}
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -510,6 +510,7 @@
+ #define AR913X_GPIO_COUNT		22
+ #define AR933X_GPIO_COUNT		30
+ #define AR934X_GPIO_COUNT		23
++#define QCA955X_GPIO_COUNT		24
+ 
+ /*
+  * SRIF block
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/033-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/033-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch.svn-base
new file mode 100644
index 0000000..42877ff
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/033-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch.svn-base
@@ -0,0 +1,53 @@
+From d3cc7a15c1e1a04e8d561c0b05d176434142bf9a Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 13:38:20 +0000
+Subject: [PATCH] MIPS: ath79: add QCA955X specific glue to
+ ath79_device_reset_{set, clear}
+
+commit 7d4c2af9bdbbe789fe4a93f32c5890d72cbf60a1 upstream.
+
+The ath79_device_reset_* are causing BUG when
+those are used on the QCA955x SoCs. The patch
+adds the required code to avoid that.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4948/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/common.c                       |    4 ++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    1 +
+ 2 files changed, 5 insertions(+)
+
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -72,6 +72,8 @@ void ath79_device_reset_set(u32 mask)
+ 		reg = AR933X_RESET_REG_RESET_MODULE;
+ 	else if (soc_is_ar934x())
+ 		reg = AR934X_RESET_REG_RESET_MODULE;
++	else if (soc_is_qca955x())
++		reg = QCA955X_RESET_REG_RESET_MODULE;
+ 	else
+ 		BUG();
+ 
+@@ -98,6 +100,8 @@ void ath79_device_reset_clear(u32 mask)
+ 		reg = AR933X_RESET_REG_RESET_MODULE;
+ 	else if (soc_is_ar934x())
+ 		reg = AR934X_RESET_REG_RESET_MODULE;
++	else if (soc_is_qca955x())
++		reg = QCA955X_RESET_REG_RESET_MODULE;
+ 	else
+ 		BUG();
+ 
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -299,6 +299,7 @@
+ #define AR934X_RESET_REG_BOOTSTRAP		0xb0
+ #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS	0xac
+ 
++#define QCA955X_RESET_REG_RESET_MODULE		0x1c
+ #define QCA955X_RESET_REG_BOOTSTRAP		0xb0
+ #define QCA955X_RESET_REG_EXT_INT_STATUS	0xac
+ 
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/034-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/034-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch.svn-base
new file mode 100644
index 0000000..38acf45
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/034-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch.svn-base
@@ -0,0 +1,34 @@
+From 25320dbceda508afc5b2de1986072caa9e04ad1b Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 13:38:21 +0000
+Subject: [PATCH] MIPS: ath79: register UART for the QCA955X SoCs
+
+commit 13992303fa705ae1e4acf4660c69687672996029 upstream.
+
+Similarly to the preceding SoCs, the QCA955X SoCs
+also have a built-in NS16650 compatible UART.
+Register the platform device for that to make
+it usable.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4949/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/dev-common.c |    3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ath79/dev-common.c
++++ b/arch/mips/ath79/dev-common.c
+@@ -90,7 +90,8 @@ void __init ath79_register_uart(void)
+ 	if (soc_is_ar71xx() ||
+ 	    soc_is_ar724x() ||
+ 	    soc_is_ar913x() ||
+-	    soc_is_ar934x()) {
++	    soc_is_ar934x() ||
++	    soc_is_qca955x()) {
+ 		ath79_uart_data[0].uartclk = clk_get_rate(clk);
+ 		platform_device_register(&ath79_uart_device);
+ 	} else if (soc_is_ar933x()) {
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/035-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/035-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch.svn-base
new file mode 100644
index 0000000..d208fff
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/035-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch.svn-base
@@ -0,0 +1,81 @@
+From cf40fbb509eaa53ff787dce41911b2545bd001ea Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 18:54:33 +0000
+Subject: [PATCH] MIPS: ath79: add WMAC registration code for the QCA955X SoCs
+
+commit e9c0d0aaa3a7a6e66135e8b44f3323143a635098 upstream.
+
+The SoC has a built-in wireless MAC. Register a platform
+device for that to make it usable with the ath9k driver.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4956/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/Kconfig                        |    2 +-
+ arch/mips/ath79/dev-wmac.c                     |   20 ++++++++++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    3 +++
+ 3 files changed, 24 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -108,7 +108,7 @@ config ATH79_DEV_USB
+ 	def_bool n
+ 
+ config ATH79_DEV_WMAC
+-	depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X)
++	depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
+ 	def_bool n
+ 
+ endif
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -116,6 +116,24 @@ static void ar934x_wmac_setup(void)
+ 		ath79_wmac_data.is_clk_25mhz = true;
+ }
+ 
++static void qca955x_wmac_setup(void)
++{
++	u32 t;
++
++	ath79_wmac_device.name = "qca955x_wmac";
++
++	ath79_wmac_resources[0].start = QCA955X_WMAC_BASE;
++	ath79_wmac_resources[0].end = QCA955X_WMAC_BASE + QCA955X_WMAC_SIZE - 1;
++	ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
++	ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
++
++	t = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
++	if (t & QCA955X_BOOTSTRAP_REF_CLK_40)
++		ath79_wmac_data.is_clk_25mhz = false;
++	else
++		ath79_wmac_data.is_clk_25mhz = true;
++}
++
+ void __init ath79_register_wmac(u8 *cal_data)
+ {
+ 	if (soc_is_ar913x())
+@@ -124,6 +142,8 @@ void __init ath79_register_wmac(u8 *cal_
+ 		ar933x_wmac_setup();
+ 	else if (soc_is_ar934x())
+ 		ar934x_wmac_setup();
++	else if (soc_is_qca955x())
++		qca955x_wmac_setup();
+ 	else
+ 		BUG();
+ 
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -94,6 +94,9 @@
+ #define AR934X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
+ #define AR934X_SRIF_SIZE	0x1000
+ 
++#define QCA955X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
++#define QCA955X_WMAC_SIZE	0x20000
++
+ /*
+  * DDR_CTRL block
+  */
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/036-MIPS-ath79-add-PCI-controller-registration-code-for-.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/036-MIPS-ath79-add-PCI-controller-registration-code-for-.patch.svn-base
new file mode 100644
index 0000000..c431f94
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/036-MIPS-ath79-add-PCI-controller-registration-code-for-.patch.svn-base
@@ -0,0 +1,115 @@
+From bc14333054c5ecee4bc7e8760d0ffbb730f32c54 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 13:38:23 +0000
+Subject: [PATCH] MIPS: ath79: add PCI controller registration code for the
+ QCA955X SoCs
+
+commit 0a5f3b1c9f20eb44142e3b37662de15c944f759d upstream.
+
+Add SoC specific PCI IRQ map, and register platform
+devices for the two built-in PCIe RCs.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4951/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/Kconfig                        |    2 ++
+ arch/mips/ath79/pci.c                          |   36 ++++++++++++++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |   13 +++++++++
+ 3 files changed, 51 insertions(+)
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -90,6 +90,8 @@ config SOC_AR934X
+ 
+ config SOC_QCA955X
+ 	select USB_ARCH_HAS_EHCI
++	select HW_HAS_PCI
++	select PCI_AR724X if PCI
+ 	def_bool n
+ 
+ config PCI_AR724X
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -49,6 +49,21 @@ static const struct ath79_pci_irq ar724x
+ 	}
+ };
+ 
++static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = {
++	{
++		.bus	= 0,
++		.slot	= 0,
++		.pin	= 1,
++		.irq	= ATH79_PCI_IRQ(0),
++	},
++	{
++		.bus	= 1,
++		.slot	= 0,
++		.pin	= 1,
++		.irq	= ATH79_PCI_IRQ(1),
++	},
++};
++
+ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
+ {
+ 	int irq = -1;
+@@ -64,6 +79,9 @@ int __init pcibios_map_irq(const struct
+ 			   soc_is_ar9344()) {
+ 			ath79_pci_irq_map = ar724x_pci_irq_map;
+ 			ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
++		} else if (soc_is_qca955x()) {
++			ath79_pci_irq_map = qca955x_pci_irq_map;
++			ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
+ 		} else {
+ 			pr_crit("pci %s: invalid irq map\n",
+ 				pci_name((struct pci_dev *) dev));
+@@ -225,6 +243,24 @@ int __init ath79_register_pci(void)
+ 						 AR724X_PCI_MEM_SIZE,
+ 						 0,
+ 						 ATH79_IP2_IRQ(0));
++	} else if (soc_is_qca9558()) {
++		pdev = ath79_register_pci_ar724x(0,
++						 QCA955X_PCI_CFG_BASE0,
++						 QCA955X_PCI_CTRL_BASE0,
++						 QCA955X_PCI_CRP_BASE0,
++						 QCA955X_PCI_MEM_BASE0,
++						 QCA955X_PCI_MEM_SIZE,
++						 0,
++						 ATH79_IP2_IRQ(0));
++
++		pdev = ath79_register_pci_ar724x(1,
++						 QCA955X_PCI_CFG_BASE1,
++						 QCA955X_PCI_CTRL_BASE1,
++						 QCA955X_PCI_CRP_BASE1,
++						 QCA955X_PCI_MEM_BASE1,
++						 QCA955X_PCI_MEM_SIZE,
++						 1,
++						 ATH79_IP3_IRQ(2));
+ 	} else {
+ 		/* No PCI support */
+ 		return -ENODEV;
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -94,6 +94,19 @@
+ #define AR934X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
+ #define AR934X_SRIF_SIZE	0x1000
+ 
++#define QCA955X_PCI_MEM_BASE0	0x10000000
++#define QCA955X_PCI_MEM_BASE1	0x12000000
++#define QCA955X_PCI_MEM_SIZE	0x02000000
++#define QCA955X_PCI_CFG_BASE0	0x14000000
++#define QCA955X_PCI_CFG_BASE1	0x16000000
++#define QCA955X_PCI_CFG_SIZE	0x1000
++#define QCA955X_PCI_CRP_BASE0	(AR71XX_APB_BASE + 0x000c0000)
++#define QCA955X_PCI_CRP_BASE1	(AR71XX_APB_BASE + 0x00250000)
++#define QCA955X_PCI_CRP_SIZE	0x1000
++#define QCA955X_PCI_CTRL_BASE0	(AR71XX_APB_BASE + 0x000f0000)
++#define QCA955X_PCI_CTRL_BASE1	(AR71XX_APB_BASE + 0x00280000)
++#define QCA955X_PCI_CTRL_SIZE	0x100
++
+ #define QCA955X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+ #define QCA955X_WMAC_SIZE	0x20000
+ 
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/037-MIPS-ath79-add-USB-controller-registration-code-for-.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/037-MIPS-ath79-add-USB-controller-registration-code-for-.patch.svn-base
new file mode 100644
index 0000000..15b7c75
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/037-MIPS-ath79-add-USB-controller-registration-code-for-.patch.svn-base
@@ -0,0 +1,65 @@
+From 281db30007b5836ce8acf5a45160fde6b176eda4 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 13:38:24 +0000
+Subject: [PATCH] MIPS: ath79: add USB controller registration code for the
+ QCA955X SoCs
+
+commit 82c46840ae6bd8a147c59cd51f636d913989324a upstream.
+
+Register platfom devices for the built-in USB
+controllers of the SoCs.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4952/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/dev-usb.c                      |   15 +++++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    3 +++
+ 2 files changed, 18 insertions(+)
+
+--- a/arch/mips/ath79/dev-usb.c
++++ b/arch/mips/ath79/dev-usb.c
+@@ -208,6 +208,19 @@ static void __init ar934x_usb_setup(void
+ 			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+ }
+ 
++static void __init qca955x_usb_setup(void)
++{
++	ath79_usb_register("ehci-platform", 0,
++			   QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
++			   ATH79_IP3_IRQ(0),
++			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
++
++	ath79_usb_register("ehci-platform", 1,
++			   QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE,
++			   ATH79_IP3_IRQ(1),
++			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
++}
++
+ void __init ath79_register_usb(void)
+ {
+ 	if (soc_is_ar71xx())
+@@ -222,6 +235,8 @@ void __init ath79_register_usb(void)
+ 		ar933x_usb_setup();
+ 	else if (soc_is_ar934x())
+ 		ar934x_usb_setup();
++	else if (soc_is_qca955x())
++		qca955x_usb_setup();
+ 	else
+ 		BUG();
+ }
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -109,6 +109,9 @@
+ 
+ #define QCA955X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+ #define QCA955X_WMAC_SIZE	0x20000
++#define QCA955X_EHCI0_BASE	0x1b000000
++#define QCA955X_EHCI1_BASE	0x1b400000
++#define QCA955X_EHCI_SIZE	0x1000
+ 
+ /*
+  * DDR_CTRL block
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/038-MIPS-ath79-add-support-for-the-Qualcomm-Atheros-AP13.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/038-MIPS-ath79-add-support-for-the-Qualcomm-Atheros-AP13.patch.svn-base
new file mode 100644
index 0000000..e235570
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/038-MIPS-ath79-add-support-for-the-Qualcomm-Atheros-AP13.patch.svn-base
@@ -0,0 +1,234 @@
+From 7f8c0c731409b9c3e62fa8a6eb4830ace8568769 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 13:38:25 +0000
+Subject: [PATCH] MIPS: ath79: add support for the Qualcomm Atheros AP136-010
+ board
+
+commit 27ea052acb9eaca98cc90bf1b8738b6d0ea5bc2f upstream.
+
+Also enable the board in the default configuration.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4953/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/Kconfig           |   12 +++
+ arch/mips/ath79/Makefile          |    1 +
+ arch/mips/ath79/mach-ap136.c      |  156 +++++++++++++++++++++++++++++++++++++
+ arch/mips/ath79/machtypes.h       |    1 +
+ arch/mips/configs/ath79_defconfig |    1 +
+ 5 files changed, 171 insertions(+)
+ create mode 100644 arch/mips/ath79/mach-ap136.c
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -14,6 +14,18 @@ config ATH79_MACH_AP121
+ 	  Say 'Y' here if you want your kernel to support the
+ 	  Atheros AP121 reference board.
+ 
++config ATH79_MACH_AP136
++	bool "Atheros AP136 reference board"
++	select SOC_QCA955X
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_SPI
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++	help
++	  Say 'Y' here if you want your kernel to support the
++	  Atheros AP136 reference board.
++
+ config ATH79_MACH_AP81
+ 	bool "Atheros AP81 reference board"
+ 	select SOC_AR913X
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -27,6 +27,7 @@ obj-$(CONFIG_ATH79_DEV_WMAC)		+= dev-wma
+ # Machines
+ #
+ obj-$(CONFIG_ATH79_MACH_AP121)		+= mach-ap121.o
++obj-$(CONFIG_ATH79_MACH_AP136)		+= mach-ap136.o
+ obj-$(CONFIG_ATH79_MACH_AP81)		+= mach-ap81.o
+ obj-$(CONFIG_ATH79_MACH_DB120)		+= mach-db120.o
+ obj-$(CONFIG_ATH79_MACH_PB44)		+= mach-pb44.o
+--- /dev/null
++++ b/arch/mips/ath79/mach-ap136.c
+@@ -0,0 +1,156 @@
++/*
++ * Qualcomm Atheros AP136 reference board support
++ *
++ * Copyright (c) 2012 Qualcomm Atheros
++ * Copyright (c) 2012-2013 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ *
++ */
++
++#include <linux/pci.h>
++#include <linux/ath9k_platform.h>
++
++#include "machtypes.h"
++#include "dev-gpio-buttons.h"
++#include "dev-leds-gpio.h"
++#include "dev-spi.h"
++#include "dev-usb.h"
++#include "dev-wmac.h"
++#include "pci.h"
++
++#define AP136_GPIO_LED_STATUS_RED	14
++#define AP136_GPIO_LED_STATUS_GREEN	19
++#define AP136_GPIO_LED_USB		4
++#define AP136_GPIO_LED_WLAN_2G		13
++#define AP136_GPIO_LED_WLAN_5G		12
++#define AP136_GPIO_LED_WPS_RED		15
++#define AP136_GPIO_LED_WPS_GREEN	20
++
++#define AP136_GPIO_BTN_WPS		16
++#define AP136_GPIO_BTN_RFKILL		21
++
++#define AP136_KEYS_POLL_INTERVAL	20	/* msecs */
++#define AP136_KEYS_DEBOUNCE_INTERVAL	(3 * AP136_KEYS_POLL_INTERVAL)
++
++#define AP136_WMAC_CALDATA_OFFSET 0x1000
++#define AP136_PCIE_CALDATA_OFFSET 0x5000
++
++static struct gpio_led ap136_leds_gpio[] __initdata = {
++	{
++		.name		= "qca:green:status",
++		.gpio		= AP136_GPIO_LED_STATUS_GREEN,
++		.active_low	= 1,
++	},
++	{
++		.name		= "qca:red:status",
++		.gpio		= AP136_GPIO_LED_STATUS_RED,
++		.active_low	= 1,
++	},
++	{
++		.name		= "qca:green:wps",
++		.gpio		= AP136_GPIO_LED_WPS_GREEN,
++		.active_low	= 1,
++	},
++	{
++		.name		= "qca:red:wps",
++		.gpio		= AP136_GPIO_LED_WPS_RED,
++		.active_low	= 1,
++	},
++	{
++		.name		= "qca:red:wlan-2g",
++		.gpio		= AP136_GPIO_LED_WLAN_2G,
++		.active_low	= 1,
++	},
++	{
++		.name		= "qca:red:usb",
++		.gpio		= AP136_GPIO_LED_USB,
++		.active_low	= 1,
++	}
++};
++
++static struct gpio_keys_button ap136_gpio_keys[] __initdata = {
++	{
++		.desc		= "WPS button",
++		.type		= EV_KEY,
++		.code		= KEY_WPS_BUTTON,
++		.debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL,
++		.gpio		= AP136_GPIO_BTN_WPS,
++		.active_low	= 1,
++	},
++	{
++		.desc		= "RFKILL button",
++		.type		= EV_KEY,
++		.code		= KEY_RFKILL,
++		.debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL,
++		.gpio		= AP136_GPIO_BTN_RFKILL,
++		.active_low	= 1,
++	},
++};
++
++static struct spi_board_info ap136_spi_info[] = {
++	{
++		.bus_num	= 0,
++		.chip_select	= 0,
++		.max_speed_hz	= 25000000,
++		.modalias	= "mx25l6405d",
++	}
++};
++
++static struct ath79_spi_platform_data ap136_spi_data = {
++	.bus_num	= 0,
++	.num_chipselect	= 1,
++};
++
++#ifdef CONFIG_PCI
++static struct ath9k_platform_data ap136_ath9k_data;
++
++static int ap136_pci_plat_dev_init(struct pci_dev *dev)
++{
++	if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
++		dev->dev.platform_data = &ap136_ath9k_data;
++
++	return 0;
++}
++
++static void __init ap136_pci_init(u8 *eeprom)
++{
++	memcpy(ap136_ath9k_data.eeprom_data, eeprom,
++	       sizeof(ap136_ath9k_data.eeprom_data));
++
++	ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
++	ath79_register_pci();
++}
++#else
++static inline void ap136_pci_init(void) {}
++#endif /* CONFIG_PCI */
++
++static void __init ap136_setup(void)
++{
++	u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
++
++	ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
++				 ap136_leds_gpio);
++	ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
++					ARRAY_SIZE(ap136_gpio_keys),
++					ap136_gpio_keys);
++	ath79_register_spi(&ap136_spi_data, ap136_spi_info,
++			   ARRAY_SIZE(ap136_spi_info));
++	ath79_register_usb();
++	ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
++	ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
++}
++
++MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
++	     "Atheros AP136-010 reference board",
++	     ap136_setup);
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -17,6 +17,7 @@
+ enum ath79_mach_type {
+ 	ATH79_MACH_GENERIC = 0,
+ 	ATH79_MACH_AP121,		/* Atheros AP121 reference board */
++	ATH79_MACH_AP136_010,		/* Atheros AP136-010 reference board */
+ 	ATH79_MACH_AP81,		/* Atheros AP81 reference board */
+ 	ATH79_MACH_DB120,		/* Atheros DB120 reference board */
+ 	ATH79_MACH_PB44,		/* Atheros PB44 reference board */
+--- a/arch/mips/configs/ath79_defconfig
++++ b/arch/mips/configs/ath79_defconfig
+@@ -1,5 +1,6 @@
+ CONFIG_ATH79=y
+ CONFIG_ATH79_MACH_AP121=y
++CONFIG_ATH79_MACH_AP136=y
+ CONFIG_ATH79_MACH_AP81=y
+ CONFIG_ATH79_MACH_DB120=y
+ CONFIG_ATH79_MACH_PB44=y
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/039-watchdog-ath79_wdt-convert-to-use-devm_clk_get.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/039-watchdog-ath79_wdt-convert-to-use-devm_clk_get.patch.svn-base
new file mode 100644
index 0000000..e0b8d50
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/039-watchdog-ath79_wdt-convert-to-use-devm_clk_get.patch.svn-base
@@ -0,0 +1,51 @@
+From 7ddf72f2337b5f7790994df966c26cd1180e1585 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 27 Dec 2012 15:38:24 +0100
+Subject: [PATCH] watchdog: ath79_wdt: convert to use devm_clk_get
+
+commit 5071a88475b758bf60191e53606463fe7290c71e upstream.
+
+Use the managed version of clk_get. This allows to
+simplify the probe/remove functions a bit.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
+---
+ drivers/watchdog/ath79_wdt.c |    7 ++-----
+ 1 file changed, 2 insertions(+), 5 deletions(-)
+
+--- a/drivers/watchdog/ath79_wdt.c
++++ b/drivers/watchdog/ath79_wdt.c
+@@ -229,13 +229,13 @@ static int ath79_wdt_probe(struct platfo
+ 	u32 ctrl;
+ 	int err;
+ 
+-	wdt_clk = clk_get(&pdev->dev, "wdt");
++	wdt_clk = devm_clk_get(&pdev->dev, "wdt");
+ 	if (IS_ERR(wdt_clk))
+ 		return PTR_ERR(wdt_clk);
+ 
+ 	err = clk_enable(wdt_clk);
+ 	if (err)
+-		goto err_clk_put;
++		return err;
+ 
+ 	wdt_freq = clk_get_rate(wdt_clk);
+ 	if (!wdt_freq) {
+@@ -265,8 +265,6 @@ static int ath79_wdt_probe(struct platfo
+ 
+ err_clk_disable:
+ 	clk_disable(wdt_clk);
+-err_clk_put:
+-	clk_put(wdt_clk);
+ 	return err;
+ }
+ 
+@@ -274,7 +272,6 @@ static int ath79_wdt_remove(struct platf
+ {
+ 	misc_deregister(&ath79_wdt_miscdev);
+ 	clk_disable(wdt_clk);
+-	clk_put(wdt_clk);
+ 	return 0;
+ }
+ 
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/040-MIPS-ath79-use-dynamically-allocated-watchdog-device.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/040-MIPS-ath79-use-dynamically-allocated-watchdog-device.patch.svn-base
new file mode 100644
index 0000000..082195f
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/040-MIPS-ath79-use-dynamically-allocated-watchdog-device.patch.svn-base
@@ -0,0 +1,35 @@
+From 5e25d5207d21e65b5a2e58b64aba6804653e95b8 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 27 Dec 2012 15:38:25 +0100
+Subject: [PATCH] MIPS: ath79: use dynamically allocated watchdog device
+
+commit 0f2ad9ed7c6fecb008372e8a709595a2a21059aa upstream.
+
+Remove the static watchdog device variable and use
+the 'platform_device_register_simple' helper to
+allocate and register the device in one step.
+
+This allows us to save a few bytes in the kernel image.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
+---
+ arch/mips/ath79/dev-common.c |    7 +------
+ 1 file changed, 1 insertion(+), 6 deletions(-)
+
+--- a/arch/mips/ath79/dev-common.c
++++ b/arch/mips/ath79/dev-common.c
+@@ -102,12 +102,7 @@ void __init ath79_register_uart(void)
+ 	}
+ }
+ 
+-static struct platform_device ath79_wdt_device = {
+-	.name		= "ath79-wdt",
+-	.id		= -1,
+-};
+-
+ void __init ath79_register_wdt(void)
+ {
+-	platform_device_register(&ath79_wdt_device);
++	platform_device_register_simple("ath79-wdt", -1, NULL, 0);
+ }
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/041-watchdog-ath79_wdt-get-register-base-from-platform-d.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/041-watchdog-ath79_wdt-get-register-base-from-platform-d.patch.svn-base
new file mode 100644
index 0000000..b863829
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/041-watchdog-ath79_wdt-get-register-base-from-platform-d.patch.svn-base
@@ -0,0 +1,151 @@
+From 9c0785757dacd1aaf9e6e58b4f559e345093f1d4 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 27 Dec 2012 15:38:26 +0100
+Subject: [PATCH] watchdog: ath79_wdt: get register base from platform
+ device's resources
+
+commit 09f5100a592d11dad06b218f41d560ff1f87f666 upstream.
+
+The ath79_wdt driver uses a fixed memory address
+currently. Although this is working with each
+currently supported SoCs, but this may change
+in the future. Additionally, the driver includes
+platform specific header files in order to be
+able to get the memory base of the watchdog
+device.
+
+The patch adds a memory resource to the platform
+device, and converts the driver to get the base
+address of the watchdog device from that.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
+---
+ arch/mips/ath79/dev-common.c |   10 ++++++++-
+ drivers/watchdog/ath79_wdt.c |   48 +++++++++++++++++++++++++++++++++---------
+ 2 files changed, 47 insertions(+), 11 deletions(-)
+
+--- a/arch/mips/ath79/dev-common.c
++++ b/arch/mips/ath79/dev-common.c
+@@ -104,5 +104,13 @@ void __init ath79_register_uart(void)
+ 
+ void __init ath79_register_wdt(void)
+ {
+-	platform_device_register_simple("ath79-wdt", -1, NULL, 0);
++	struct resource res;
++
++	memset(&res, 0, sizeof(res));
++
++	res.flags = IORESOURCE_MEM;
++	res.start = AR71XX_RESET_BASE + AR71XX_RESET_REG_WDOG_CTRL;
++	res.end = res.start + 0x8 - 1;
++
++	platform_device_register_simple("ath79-wdt", -1, &res, 1);
+ }
+--- a/drivers/watchdog/ath79_wdt.c
++++ b/drivers/watchdog/ath79_wdt.c
+@@ -23,6 +23,7 @@
+ #include <linux/errno.h>
+ #include <linux/fs.h>
+ #include <linux/init.h>
++#include <linux/io.h>
+ #include <linux/kernel.h>
+ #include <linux/miscdevice.h>
+ #include <linux/module.h>
+@@ -33,13 +34,13 @@
+ #include <linux/clk.h>
+ #include <linux/err.h>
+ 
+-#include <asm/mach-ath79/ath79.h>
+-#include <asm/mach-ath79/ar71xx_regs.h>
+-
+ #define DRIVER_NAME	"ath79-wdt"
+ 
+ #define WDT_TIMEOUT	15	/* seconds */
+ 
++#define WDOG_REG_CTRL		0x00
++#define WDOG_REG_TIMER		0x04
++
+ #define WDOG_CTRL_LAST_RESET	BIT(31)
+ #define WDOG_CTRL_ACTION_MASK	3
+ #define WDOG_CTRL_ACTION_NONE	0	/* no action */
+@@ -66,27 +67,38 @@ static struct clk *wdt_clk;
+ static unsigned long wdt_freq;
+ static int boot_status;
+ static int max_timeout;
++static void __iomem *wdt_base;
++
++static inline void ath79_wdt_wr(unsigned reg, u32 val)
++{
++	iowrite32(val, wdt_base + reg);
++}
++
++static inline u32 ath79_wdt_rr(unsigned reg)
++{
++	return ioread32(wdt_base + reg);
++}
+ 
+ static inline void ath79_wdt_keepalive(void)
+ {
+-	ath79_reset_wr(AR71XX_RESET_REG_WDOG, wdt_freq * timeout);
++	ath79_wdt_wr(WDOG_REG_TIMER, wdt_freq * timeout);
+ 	/* flush write */
+-	ath79_reset_rr(AR71XX_RESET_REG_WDOG);
++	ath79_wdt_rr(WDOG_REG_TIMER);
+ }
+ 
+ static inline void ath79_wdt_enable(void)
+ {
+ 	ath79_wdt_keepalive();
+-	ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR);
++	ath79_wdt_wr(WDOG_REG_CTRL, WDOG_CTRL_ACTION_FCR);
+ 	/* flush write */
+-	ath79_reset_rr(AR71XX_RESET_REG_WDOG_CTRL);
++	ath79_wdt_rr(WDOG_REG_CTRL);
+ }
+ 
+ static inline void ath79_wdt_disable(void)
+ {
+-	ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_NONE);
++	ath79_wdt_wr(WDOG_REG_CTRL, WDOG_CTRL_ACTION_NONE);
+ 	/* flush write */
+-	ath79_reset_rr(AR71XX_RESET_REG_WDOG_CTRL);
++	ath79_wdt_rr(WDOG_REG_CTRL);
+ }
+ 
+ static int ath79_wdt_set_timeout(int val)
+@@ -226,9 +238,25 @@ static struct miscdevice ath79_wdt_miscd
+ 
+ static int ath79_wdt_probe(struct platform_device *pdev)
+ {
++	struct resource *res;
+ 	u32 ctrl;
+ 	int err;
+ 
++	if (wdt_base)
++		return -EBUSY;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res) {
++		dev_err(&pdev->dev, "no memory resource found\n");
++		return -EINVAL;
++	}
++
++	wdt_base = devm_request_and_ioremap(&pdev->dev, res);
++	if (!wdt_base) {
++		dev_err(&pdev->dev, "unable to remap memory region\n");
++		return -ENOMEM;
++	}
++
+ 	wdt_clk = devm_clk_get(&pdev->dev, "wdt");
+ 	if (IS_ERR(wdt_clk))
+ 		return PTR_ERR(wdt_clk);
+@@ -251,7 +279,7 @@ static int ath79_wdt_probe(struct platfo
+ 			max_timeout, timeout);
+ 	}
+ 
+-	ctrl = ath79_reset_rr(AR71XX_RESET_REG_WDOG_CTRL);
++	ctrl = ath79_wdt_rr(WDOG_REG_CTRL);
+ 	boot_status = (ctrl & WDOG_CTRL_LAST_RESET) ? WDIOF_CARDRESET : 0;
+ 
+ 	err = misc_register(&ath79_wdt_miscdev);
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/206-spi-ath79-make-chipselect-logic-more-flexible.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/206-spi-ath79-make-chipselect-logic-more-flexible.patch.svn-base
new file mode 100644
index 0000000..93df466
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/206-spi-ath79-make-chipselect-logic-more-flexible.patch.svn-base
@@ -0,0 +1,310 @@
+From 7008284716403237f6bc7d7590b3ed073555bd56 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 11 Jan 2012 22:25:11 +0100
+Subject: [PATCH 34/34] spi/ath79: make chipselect logic more flexible
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/mach-ap121.c                       |    6 ++
+ arch/mips/ath79/mach-ap136.c                       |    6 ++
+ arch/mips/ath79/mach-ap81.c                        |    6 ++
+ arch/mips/ath79/mach-db120.c                       |    6 ++
+ arch/mips/ath79/mach-pb44.c                        |    6 ++
+ arch/mips/ath79/mach-ubnt-xm.c                     |    6 ++
+ .../include/asm/mach-ath79/ath79_spi_platform.h    |    8 ++-
+ drivers/spi/spi-ath79.c                            |   67 +++++++++++++-------
+ 8 files changed, 88 insertions(+), 23 deletions(-)
+
+--- a/arch/mips/ath79/mach-ap121.c
++++ b/arch/mips/ath79/mach-ap121.c
+@@ -58,12 +58,18 @@ static struct gpio_keys_button ap121_gpi
+ 	}
+ };
+ 
++static struct ath79_spi_controller_data ap121_spi0_data = {
++	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++	.cs_line = 0,
++};
++
+ static struct spi_board_info ap121_spi_info[] = {
+ 	{
+ 		.bus_num	= 0,
+ 		.chip_select	= 0,
+ 		.max_speed_hz	= 25000000,
+ 		.modalias	= "mx25l1606e",
++		.controller_data = &ap121_spi0_data,
+ 	}
+ };
+ 
+--- a/arch/mips/ath79/mach-ap136.c
++++ b/arch/mips/ath79/mach-ap136.c
+@@ -98,12 +98,18 @@ static struct gpio_keys_button ap136_gpi
+ 	},
+ };
+ 
++static struct ath79_spi_controller_data ap136_spi0_data = {
++	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++	.cs_line = 0,
++};
++
+ static struct spi_board_info ap136_spi_info[] = {
+ 	{
+ 		.bus_num	= 0,
+ 		.chip_select	= 0,
+ 		.max_speed_hz	= 25000000,
+ 		.modalias	= "mx25l6405d",
++		.controller_data = &ap136_spi0_data,
+ 	}
+ };
+ 
+--- a/arch/mips/ath79/mach-ap81.c
++++ b/arch/mips/ath79/mach-ap81.c
+@@ -67,12 +67,18 @@ static struct gpio_keys_button ap81_gpio
+ 	}
+ };
+ 
++static struct ath79_spi_controller_data ap81_spi0_data = {
++	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++	.cs_line = 0,
++};
++
+ static struct spi_board_info ap81_spi_info[] = {
+ 	{
+ 		.bus_num	= 0,
+ 		.chip_select	= 0,
+ 		.max_speed_hz	= 25000000,
+ 		.modalias	= "m25p64",
++		.controller_data = &ap81_spi0_data,
+ 	}
+ };
+ 
+--- a/arch/mips/ath79/mach-db120.c
++++ b/arch/mips/ath79/mach-db120.c
+@@ -76,12 +76,18 @@ static struct gpio_keys_button db120_gpi
+ 	},
+ };
+ 
++static struct ath79_spi_controller_data db120_spi0_data = {
++	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++	.cs_line = 0,
++};
++
+ static struct spi_board_info db120_spi_info[] = {
+ 	{
+ 		.bus_num	= 0,
+ 		.chip_select	= 0,
+ 		.max_speed_hz	= 25000000,
+ 		.modalias	= "s25sl064a",
++		.controller_data = &db120_spi0_data,
+ 	}
+ };
+ 
+--- a/arch/mips/ath79/mach-pb44.c
++++ b/arch/mips/ath79/mach-pb44.c
+@@ -87,12 +87,18 @@ static struct gpio_keys_button pb44_gpio
+ 	}
+ };
+ 
++static struct ath79_spi_controller_data pb44_spi0_data = {
++	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++	.cs_line = 0,
++};
++
+ static struct spi_board_info pb44_spi_info[] = {
+ 	{
+ 		.bus_num	= 0,
+ 		.chip_select	= 0,
+ 		.max_speed_hz	= 25000000,
+ 		.modalias	= "m25p64",
++		.controller_data = &pb44_spi0_data,
+ 	},
+ };
+ 
+--- a/arch/mips/ath79/mach-ubnt-xm.c
++++ b/arch/mips/ath79/mach-ubnt-xm.c
+@@ -65,12 +65,18 @@ static struct gpio_keys_button ubnt_xm_g
+ 	}
+ };
+ 
++static struct ath79_spi_controller_data ubnt_xm_spi0_data = {
++	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++	.cs_line = 0,
++};
++
+ static struct spi_board_info ubnt_xm_spi_info[] = {
+ 	{
+ 		.bus_num	= 0,
+ 		.chip_select	= 0,
+ 		.max_speed_hz	= 25000000,
+ 		.modalias	= "mx25l6405d",
++		.controller_data = &ubnt_xm_spi0_data,
+ 	}
+ };
+ 
+--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
++++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
+@@ -16,8 +16,14 @@ struct ath79_spi_platform_data {
+ 	unsigned	num_chipselect;
+ };
+ 
++enum ath79_spi_cs_type {
++	ATH79_SPI_CS_TYPE_INTERNAL,
++	ATH79_SPI_CS_TYPE_GPIO,
++};
++
+ struct ath79_spi_controller_data {
+-	unsigned	gpio;
++	enum ath79_spi_cs_type cs_type;
++	unsigned cs_line;
+ };
+ 
+ #endif /* _ATH79_SPI_PLATFORM_H */
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -35,6 +35,8 @@
+ #define ATH79_SPI_RRW_DELAY_FACTOR	12000
+ #define MHZ				(1000 * 1000)
+ 
++#define ATH79_SPI_CS_LINE_MAX		2
++
+ struct ath79_spi {
+ 	struct spi_bitbang	bitbang;
+ 	u32			ioc_base;
+@@ -69,6 +71,7 @@ static void ath79_spi_chipselect(struct
+ {
+ 	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+ 	int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
++	struct ath79_spi_controller_data *cdata = spi->controller_data;
+ 
+ 	if (is_active) {
+ 		/* set initial clock polarity */
+@@ -80,20 +83,24 @@ static void ath79_spi_chipselect(struct
+ 		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
+ 	}
+ 
+-	if (spi->chip_select) {
+-		struct ath79_spi_controller_data *cdata = spi->controller_data;
+-
+-		/* SPI is normally active-low */
+-		gpio_set_value(cdata->gpio, cs_high);
+-	} else {
++	switch (cdata->cs_type) {
++	case ATH79_SPI_CS_TYPE_INTERNAL:
+ 		if (cs_high)
+-			sp->ioc_base |= AR71XX_SPI_IOC_CS0;
++			sp->ioc_base |= AR71XX_SPI_IOC_CS(cdata->cs_line);
+ 		else
+-			sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
++			sp->ioc_base &= ~AR71XX_SPI_IOC_CS(cdata->cs_line);
+ 
+ 		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
+-	}
++		break;
+ 
++	case ATH79_SPI_CS_TYPE_GPIO:
++		/* SPI is normally active-low */
++		if (gpio_cansleep(cdata->cs_line))
++			gpio_set_value_cansleep(cdata->cs_line, cs_high);
++		else
++			gpio_set_value(cdata->cs_line, cs_high);
++		break;
++	}
+ }
+ 
+ static void ath79_spi_enable(struct ath79_spi *sp)
+@@ -120,24 +127,30 @@ static void ath79_spi_disable(struct ath
+ static int ath79_spi_setup_cs(struct spi_device *spi)
+ {
+ 	struct ath79_spi_controller_data *cdata;
++	unsigned long flags;
+ 	int status;
+ 
+ 	cdata = spi->controller_data;
+-	if (spi->chip_select && !cdata)
++	if (!cdata)
+ 		return -EINVAL;
+ 
+ 	status = 0;
+-	if (spi->chip_select) {
+-		unsigned long flags;
++	switch (cdata->cs_type) {
++	case ATH79_SPI_CS_TYPE_INTERNAL:
++		if (cdata->cs_line > ATH79_SPI_CS_LINE_MAX)
++			status = -EINVAL;
++		break;
+ 
++	case ATH79_SPI_CS_TYPE_GPIO:
+ 		flags = GPIOF_DIR_OUT;
+ 		if (spi->mode & SPI_CS_HIGH)
+ 			flags |= GPIOF_INIT_HIGH;
+ 		else
+ 			flags |= GPIOF_INIT_LOW;
+ 
+-		status = gpio_request_one(cdata->gpio, flags,
++		status = gpio_request_one(cdata->cs_line, flags,
+ 					  dev_name(&spi->dev));
++		break;
+ 	}
+ 
+ 	return status;
+@@ -145,9 +158,19 @@ static int ath79_spi_setup_cs(struct spi
+ 
+ static void ath79_spi_cleanup_cs(struct spi_device *spi)
+ {
+-	if (spi->chip_select) {
+-		struct ath79_spi_controller_data *cdata = spi->controller_data;
+-		gpio_free(cdata->gpio);
++	struct ath79_spi_controller_data *cdata;
++
++	cdata = spi->controller_data;
++	if (!cdata)
++		return;
++
++	switch (cdata->cs_type) {
++	case ATH79_SPI_CS_TYPE_INTERNAL:
++		/* nothing to do */
++		break;
++	case ATH79_SPI_CS_TYPE_GPIO:
++		gpio_free(cdata->cs_line);
++		break;
+ 	}
+ }
+ 
+@@ -155,6 +178,9 @@ static int ath79_spi_setup(struct spi_de
+ {
+ 	int status = 0;
+ 
++	if (spi->controller_data == NULL)
++		return -EINVAL;
++
+ 	if (spi->bits_per_word > 32)
+ 		return -EINVAL;
+ 
+@@ -215,6 +241,10 @@ static int ath79_spi_probe(struct platfo
+ 	unsigned long rate;
+ 	int ret;
+ 
++	pdata = pdev->dev.platform_data;
++	if (!pdata)
++		return -EINVAL;
++
+ 	master = spi_alloc_master(&pdev->dev, sizeof(*sp));
+ 	if (master == NULL) {
+ 		dev_err(&pdev->dev, "failed to allocate spi master\n");
+@@ -224,14 +254,10 @@ static int ath79_spi_probe(struct platfo
+ 	sp = spi_master_get_devdata(master);
+ 	platform_set_drvdata(pdev, sp);
+ 
+-	pdata = pdev->dev.platform_data;
+-
+ 	master->setup = ath79_spi_setup;
+ 	master->cleanup = ath79_spi_cleanup;
+-	if (pdata) {
+-		master->bus_num = pdata->bus_num;
+-		master->num_chipselect = pdata->num_chipselect;
+-	}
++	master->bus_num = pdata->bus_num;
++	master->num_chipselect = pdata->num_chipselect;
+ 
+ 	sp->bitbang.master = spi_master_get(master);
+ 	sp->bitbang.chipselect = ath79_spi_chipselect;
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/213-MIPS-ath79-fix-ar933x-wmac-reset.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/213-MIPS-ath79-fix-ar933x-wmac-reset.patch.svn-base
new file mode 100644
index 0000000..e0821a7
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/213-MIPS-ath79-fix-ar933x-wmac-reset.patch.svn-base
@@ -0,0 +1,31 @@
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -62,10 +62,27 @@ static void __init ar913x_wmac_setup(voi
+ 
+ static int ar933x_wmac_reset(void)
+ {
++	int retries = 20;
++
+ 	ath79_device_reset_set(AR933X_RESET_WMAC);
+ 	ath79_device_reset_clear(AR933X_RESET_WMAC);
+ 
+-	return 0;
++	while (1) {
++		u32 bootstrap;
++
++		bootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
++		if ((bootstrap & AR933X_BOOTSTRAP_EEPBUSY) == 0)
++			return 0;
++
++		if (retries-- == 0)
++			break;
++
++		udelay(10000);
++		retries++;
++	}
++
++	pr_err("ar933x: WMAC reset timed out");
++	return -ETIMEDOUT;
+ }
+ 
+ static int ar933x_r1_get_wmac_revision(void)
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/220-add_cpu_feature_overrides.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/220-add_cpu_feature_overrides.patch.svn-base
new file mode 100644
index 0000000..05406f2
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/220-add_cpu_feature_overrides.patch.svn-base
@@ -0,0 +1,28 @@
+--- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
++++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
+@@ -36,6 +36,7 @@
+ #define cpu_has_mdmx		0
+ #define cpu_has_mips3d		0
+ #define cpu_has_smartmips	0
++#define cpu_has_rixi		0
+ 
+ #define cpu_has_mips32r1	1
+ #define cpu_has_mips32r2	1
+@@ -45,6 +46,7 @@
+ #define cpu_has_dsp		0
+ #define cpu_has_dsp2		0
+ #define cpu_has_mipsmt		0
++#define cpu_has_userlocal	0
+ 
+ #define cpu_has_64bits		0
+ #define cpu_has_64bit_zero_reg	0
+@@ -53,5 +55,9 @@
+ 
+ #define cpu_dcache_line_size()	32
+ #define cpu_icache_line_size()	32
++#define cpu_has_vtag_icache	0
++#define cpu_has_dc_aliases	1
++#define cpu_has_ic_fills_f_dc	0
++#define cpu_has_pindexed_dcache	0
+ 
+ #endif /* __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H */
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/310-lib-add-rle-decompression.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/310-lib-add-rle-decompression.patch.svn-base
new file mode 100644
index 0000000..d81fdd8
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/310-lib-add-rle-decompression.patch.svn-base
@@ -0,0 +1,114 @@
+--- a/lib/Kconfig
++++ b/lib/Kconfig
+@@ -197,6 +197,9 @@ config LZMA_COMPRESS
+ config LZMA_DECOMPRESS
+     tristate
+ 
++config RLE_DECOMPRESS
++	tristate
++
+ #
+ # These all provide a common interface (hence the apparent duplication with
+ # ZLIB_INFLATE; DECOMPRESS_GZIP is just a wrapper.)
+--- a/lib/Makefile
++++ b/lib/Makefile
+@@ -86,6 +86,7 @@ obj-$(CONFIG_XZ_DEC) += xz/
+ obj-$(CONFIG_RAID6_PQ) += raid6/
+ obj-$(CONFIG_LZMA_COMPRESS) += lzma/
+ obj-$(CONFIG_LZMA_DECOMPRESS) += lzma/
++obj-$(CONFIG_RLE_DECOMPRESS) += rle.o
+ 
+ lib-$(CONFIG_DECOMPRESS_GZIP) += decompress_inflate.o
+ lib-$(CONFIG_DECOMPRESS_BZIP2) += decompress_bunzip2.o
+--- /dev/null
++++ b/include/linux/rle.h
+@@ -0,0 +1,8 @@
++#ifndef _RLE_H_
++#define _RLE_H_
++
++int rle_decode(const unsigned char *src, size_t srclen,
++	       unsigned char *dst, size_t dstlen,
++	       size_t *src_done, size_t *dst_done);
++
++#endif /* _RLE_H_ */
+--- /dev/null
++++ b/lib/rle.c
+@@ -0,0 +1,78 @@
++/*
++ *  RLE decoding routine
++ *
++ *  Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/rle.h>
++
++int rle_decode(const unsigned char *src, size_t srclen,
++	       unsigned char *dst, size_t dstlen,
++	       size_t *src_done, size_t *dst_done)
++{
++	size_t srcpos, dstpos;
++	int ret;
++
++	srcpos = 0;
++	dstpos = 0;
++	ret = -EINVAL;
++
++	/* sanity checks */
++	if (!src || !srclen || !dst || !dstlen)
++		goto out;
++
++	while (1) {
++		char count;
++
++		if (srcpos >= srclen)
++			break;
++
++		count = (char) src[srcpos++];
++		if (count == 0) {
++			ret = 0;
++			break;
++		}
++
++		if (count > 0) {
++			unsigned char c;
++
++			if (srcpos >= srclen)
++				break;
++
++			c = src[srcpos++];
++
++			while (count--) {
++				if (dstpos >= dstlen)
++					break;
++
++				dst[dstpos++] = c;
++			}
++		} else {
++			count *= -1;
++
++			while (count--) {
++				if (srcpos >= srclen)
++					break;
++				if (dstpos >= dstlen)
++					break;
++				dst[dstpos++] = src[srcpos++];
++			}
++		}
++	}
++
++out:
++	if (src_done)
++		*src_done = srcpos;
++	if (dst_done)
++		*dst_done = dstpos;
++
++	return ret;
++}
++
++EXPORT_SYMBOL_GPL(rle_decode);
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/401-mtd-physmap-add-lock-unlock.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/401-mtd-physmap-add-lock-unlock.patch.svn-base
new file mode 100644
index 0000000..ead7685
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/401-mtd-physmap-add-lock-unlock.patch.svn-base
@@ -0,0 +1,94 @@
+--- a/drivers/mtd/maps/physmap.c
++++ b/drivers/mtd/maps/physmap.c
+@@ -31,6 +31,66 @@ struct physmap_flash_info {
+ 	int			vpp_refcnt;
+ };
+ 
++static struct platform_device *physmap_map2pdev(struct map_info *map)
++{
++	return (struct platform_device *) map->map_priv_1;
++}
++
++static void physmap_lock(struct map_info *map)
++{
++	struct platform_device *pdev;
++	struct physmap_flash_data *physmap_data;
++
++	pdev = physmap_map2pdev(map);
++	physmap_data = pdev->dev.platform_data;
++	physmap_data->lock(pdev);
++}
++
++static void physmap_unlock(struct map_info *map)
++{
++	struct platform_device *pdev;
++	struct physmap_flash_data *physmap_data;
++
++	pdev = physmap_map2pdev(map);
++	physmap_data = pdev->dev.platform_data;
++	physmap_data->unlock(pdev);
++}
++
++static map_word physmap_flash_read_lock(struct map_info *map, unsigned long ofs)
++{
++	map_word ret;
++
++	physmap_lock(map);
++	ret = inline_map_read(map, ofs);
++	physmap_unlock(map);
++
++	return ret;
++}
++
++static void physmap_flash_write_lock(struct map_info *map, map_word d,
++				     unsigned long ofs)
++{
++	physmap_lock(map);
++	inline_map_write(map, d, ofs);
++	physmap_unlock(map);
++}
++
++static void physmap_flash_copy_from_lock(struct map_info *map, void *to,
++					 unsigned long from, ssize_t len)
++{
++	physmap_lock(map);
++	inline_map_copy_from(map, to, from, len);
++	physmap_unlock(map);
++}
++
++static void physmap_flash_copy_to_lock(struct map_info *map, unsigned long to,
++				       const void *from, ssize_t len)
++{
++	physmap_lock(map);
++	inline_map_copy_to(map, to, from, len);
++	physmap_unlock(map);
++}
++
+ static int physmap_flash_remove(struct platform_device *dev)
+ {
+ 	struct physmap_flash_info *info;
+@@ -157,6 +217,13 @@ static int physmap_flash_probe(struct pl
+ 
+ 		simple_map_init(&info->map[i]);
+ 
++		if (physmap_data->lock && physmap_data->unlock) {
++			info->map[i].read = physmap_flash_read_lock;
++			info->map[i].write = physmap_flash_write_lock;
++			info->map[i].copy_from = physmap_flash_copy_from_lock;
++			info->map[i].copy_to = physmap_flash_copy_to_lock;
++		}
++
+ 		probe_type = rom_probe_types;
+ 		if (physmap_data->probe_type == NULL) {
+ 			for (; info->mtd[i] == NULL && *probe_type != NULL; probe_type++)
+--- a/include/linux/mtd/physmap.h
++++ b/include/linux/mtd/physmap.h
+@@ -26,6 +26,8 @@ struct physmap_flash_data {
+ 	unsigned int		width;
+ 	int			(*init)(struct platform_device *);
+ 	void			(*exit)(struct platform_device *);
++	void			(*lock)(struct platform_device *);
++	void			(*unlock)(struct platform_device *);
+ 	void			(*set_vpp)(struct platform_device *, int);
+ 	unsigned int		nr_parts;
+ 	unsigned int		pfow_base;
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/402-mtd-SST39VF6401B-support.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/402-mtd-SST39VF6401B-support.patch.svn-base
new file mode 100644
index 0000000..246abd5
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/402-mtd-SST39VF6401B-support.patch.svn-base
@@ -0,0 +1,29 @@
+--- a/drivers/mtd/chips/jedec_probe.c
++++ b/drivers/mtd/chips/jedec_probe.c
+@@ -148,6 +148,7 @@
+ #define SST39LF160	0x2782
+ #define SST39VF1601	0x234b
+ #define SST39VF3201	0x235b
++#define SST39VF6401B	0x236d
+ #define SST39WF1601	0x274b
+ #define SST39WF1602	0x274a
+ #define SST39LF512	0x00D4
+@@ -1568,6 +1569,18 @@ static const struct amd_flash_info jedec
+ 			ERASEINFO(0x10000,64),
+ 		}
+ 	}, {
++		.mfr_id         = CFI_MFR_SST,
++		.dev_id         = SST39VF6401B,
++		.name           = "SST 39VF6401B",
++		.devtypes       = CFI_DEVICETYPE_X16,
++		.uaddr          = MTD_UADDR_0xAAAA_0x5555,
++		.dev_size       = SIZE_8MiB,
++		.cmd_set        = P_ID_AMD_STD,
++		.nr_regions     = 1,
++		.regions        = {
++			ERASEINFO(0x10000,128)
++		}
++	}, {
+ 		.mfr_id		= CFI_MFR_ST,
+ 		.dev_id		= M29F800AB,
+ 		.name		= "ST M29F800AB",
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/403-mtd_fix_cfi_cmdset_0002_status_check.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/403-mtd_fix_cfi_cmdset_0002_status_check.patch.svn-base
new file mode 100644
index 0000000..e569fe1
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/403-mtd_fix_cfi_cmdset_0002_status_check.patch.svn-base
@@ -0,0 +1,69 @@
+--- a/drivers/mtd/chips/cfi_cmdset_0002.c
++++ b/drivers/mtd/chips/cfi_cmdset_0002.c
+@@ -1288,8 +1288,8 @@ static int __xipram do_write_oneword(str
+ 			break;
+ 		}
+ 
+-		if (chip_ready(map, adr))
+-			break;
++		if (chip_good(map, adr, datum))
++			goto enable_xip;
+ 
+ 		/* Latency issues. Drop the lock, wait a while and retry */
+ 		UDELAY(map, chip, adr, 1);
+@@ -1305,6 +1305,8 @@ static int __xipram do_write_oneword(str
+ 
+ 		ret = -EIO;
+ 	}
++
++ enable_xip:
+ 	xip_enable(map, chip, adr);
+  op_done:
+ 	chip->state = FL_READY;
+@@ -1875,7 +1877,6 @@ static int cfi_amdstd_panic_write(struct
+ 	return 0;
+ }
+ 
+-
+ /*
+  * Handle devices with one erase region, that only implement
+  * the chip erase command.
+@@ -1939,8 +1940,8 @@ static int __xipram do_erase_chip(struct
+ 			chip->erase_suspended = 0;
+ 		}
+ 
+-		if (chip_ready(map, adr))
+-			break;
++		if (chip_good(map, adr, map_word_ff(map)))
++			goto op_done;
+ 
+ 		if (time_after(jiffies, timeo)) {
+ 			printk(KERN_WARNING "MTD %s(): software timeout\n",
+@@ -1960,6 +1961,7 @@ static int __xipram do_erase_chip(struct
+ 		ret = -EIO;
+ 	}
+ 
++ op_done:
+ 	chip->state = FL_READY;
+ 	xip_enable(map, chip, adr);
+ 	DISABLE_VPP(map);
+@@ -2028,9 +2030,9 @@ static int __xipram do_erase_oneblock(st
+ 			chip->erase_suspended = 0;
+ 		}
+ 
+-		if (chip_ready(map, adr)) {
++		if (chip_good(map, adr, map_word_ff(map))) {
+ 			xip_enable(map, chip, adr);
+-			break;
++			goto op_done;
+ 		}
+ 
+ 		if (time_after(jiffies, timeo)) {
+@@ -2052,6 +2054,7 @@ static int __xipram do_erase_oneblock(st
+ 		ret = -EIO;
+ 	}
+ 
++ op_done:
+ 	chip->state = FL_READY;
+ 	DISABLE_VPP(map);
+ 	put_chip(map, chip, adr);
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/404-mtd-wrt160nl-trx-parser.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/404-mtd-wrt160nl-trx-parser.patch.svn-base
new file mode 100644
index 0000000..71798c4
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/404-mtd-wrt160nl-trx-parser.patch.svn-base
@@ -0,0 +1,25 @@
+--- a/drivers/mtd/Kconfig
++++ b/drivers/mtd/Kconfig
+@@ -163,6 +163,12 @@ config MTD_BCM47XX_PARTS
+ 	  This provides partitions parser for devices based on BCM47xx
+ 	  boards.
+ 
++config MTD_WRT160NL_PARTS
++	tristate "Linksys WRT160NL partitioning support"
++	depends on MTD_PARTITIONS && ATH79_MACH_WRT160NL
++	---help---
++	   Linksys WRT160NL partitioning support
++
+ config MTD_MYLOADER_PARTS
+ 	tristate "MyLoader partition parsing"
+ 	depends on ADM5120 || ATHEROS_AR231X || ATHEROS_AR71XX || ATH79
+--- a/drivers/mtd/Makefile
++++ b/drivers/mtd/Makefile
+@@ -14,6 +14,7 @@ obj-$(CONFIG_MTD_AR7_PARTS)	+= ar7part.o
+ obj-$(CONFIG_MTD_BCM63XX_PARTS)	+= bcm63xxpart.o
+ obj-$(CONFIG_MTD_BCM47XX_PARTS)	+= bcm47xxpart.o
+ obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o
++obj-$(CONFIG_MTD_WRT160NL_PARTS) += wrt160nl_part.o
+ 
+ # 'Users' - code which presents functionality to userspace.
+ obj-$(CONFIG_MTD_CHAR)		+= mtdchar.o
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/405-mtd-tp-link-partition-parser.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/405-mtd-tp-link-partition-parser.patch.svn-base
new file mode 100644
index 0000000..45676ec
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/405-mtd-tp-link-partition-parser.patch.svn-base
@@ -0,0 +1,34 @@
+--- a/drivers/mtd/Kconfig
++++ b/drivers/mtd/Kconfig
+@@ -165,7 +165,7 @@ config MTD_BCM47XX_PARTS
+ 
+ config MTD_WRT160NL_PARTS
+ 	tristate "Linksys WRT160NL partitioning support"
+-	depends on MTD_PARTITIONS && ATH79_MACH_WRT160NL
++	depends on ATH79_MACH_WRT160NL
+ 	---help---
+ 	   Linksys WRT160NL partitioning support
+ 
+@@ -185,6 +185,12 @@ config MTD_MYLOADER_PARTS
+ 	  You will still need the parsing functions to be called by the driver
+ 	  for your particular device. It won't happen automatically.
+ 
++config MTD_TPLINK_PARTS
++	tristate "TP-Link AR7XXX/AR9XXX partitioning support"
++	depends on ATH79
++	---help---
++	  TBD.
++
+ comment "User Modules And Translation Layers"
+ 
+ config MTD_CHAR
+--- a/drivers/mtd/Makefile
++++ b/drivers/mtd/Makefile
+@@ -14,6 +14,7 @@ obj-$(CONFIG_MTD_AR7_PARTS)	+= ar7part.o
+ obj-$(CONFIG_MTD_BCM63XX_PARTS)	+= bcm63xxpart.o
+ obj-$(CONFIG_MTD_BCM47XX_PARTS)	+= bcm47xxpart.o
+ obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o
++obj-$(CONFIG_MTD_TPLINK_PARTS)	+= tplinkpart.o
+ obj-$(CONFIG_MTD_WRT160NL_PARTS) += wrt160nl_part.o
+ 
+ # 'Users' - code which presents functionality to userspace.
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/406-mtd-m25p80-allow-to-specify-max-read-size.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/406-mtd-m25p80-allow-to-specify-max-read-size.patch.svn-base
new file mode 100644
index 0000000..be308c6
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/406-mtd-m25p80-allow-to-specify-max-read-size.patch.svn-base
@@ -0,0 +1,109 @@
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -93,6 +93,7 @@ struct m25p {
+ 	u8			erase_opcode;
+ 	u8			*command;
+ 	bool			fast_read;
++	size_t			max_read_len;
+ };
+ 
+ static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
+@@ -344,6 +345,7 @@ static int m25p80_read(struct mtd_info *
+ 	struct spi_transfer t[2];
+ 	struct spi_message m;
+ 	uint8_t opcode;
++	loff_t ofs;
+ 
+ 	pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
+ 			__func__, (u32)from, len);
+@@ -359,19 +361,10 @@ static int m25p80_read(struct mtd_info *
+ 	t[0].len = m25p_cmdsz(flash) + (flash->fast_read ? 1 : 0);
+ 	spi_message_add_tail(&t[0], &m);
+ 
+-	t[1].rx_buf = buf;
+-	t[1].len = len;
+ 	spi_message_add_tail(&t[1], &m);
+ 
+ 	mutex_lock(&flash->lock);
+ 
+-	/* Wait till previous write/erase is done. */
+-	if (wait_till_ready(flash)) {
+-		/* REVISIT status return?? */
+-		mutex_unlock(&flash->lock);
+-		return 1;
+-	}
+-
+ 	/* FIXME switch to OPCODE_FAST_READ.  It's required for higher
+ 	 * clocks; and at this writing, every chip this driver handles
+ 	 * supports that opcode.
+@@ -380,13 +373,43 @@ static int m25p80_read(struct mtd_info *
+ 	/* Set up the write data buffer. */
+ 	opcode = flash->fast_read ? OPCODE_FAST_READ : OPCODE_NORM_READ;
+ 	flash->command[0] = opcode;
+-	m25p_addr2cmd(flash, from, flash->command);
++	ofs = 0;
++	while (len) {
++		size_t readlen;
++		size_t done;
++		int ret;
++
++		ret = wait_till_ready(flash);
++		if (ret) {
++			mutex_unlock(&flash->lock);
++			return 1;
++		}
++
++		if (flash->max_read_len > 0 &&
++		    flash->max_read_len < len)
++			readlen = flash->max_read_len;
++		else
++			readlen = len;
++
++		t[1].rx_buf = buf + ofs;
++		t[1].len = readlen;
++
++		m25p_addr2cmd(flash, from + ofs, flash->command);
++
++		spi_sync(flash->spi, &m);
+ 
+-	spi_sync(flash->spi, &m);
++		done = m.actual_length - m25p_cmdsz(flash) -
++		       (flash->fast_read ? 1 : 0);
++		if (done != readlen) {
++			mutex_unlock(&flash->lock);
++			return 1;
++		}
+ 
+-	*retlen = m.actual_length - m25p_cmdsz(flash) -
+-			(flash->fast_read ? 1 : 0);
++		ofs += done;
++		len -= done;
++	}
+ 
++	*retlen = ofs;
+ 	mutex_unlock(&flash->lock);
+ 
+ 	return 0;
+@@ -916,6 +939,12 @@ static int m25p_probe(struct spi_device
+ 	flash->mtd._erase = m25p80_erase;
+ 	flash->mtd._read = m25p80_read;
+ 
++	if (data && data->max_read_len) {
++		flash->max_read_len = data->max_read_len;
++		dev_warn(&spi->dev, "max_read_len set to %d bytes\n",
++			flash->max_read_len);
++	}
++
+ 	/* sst flash chips use AAI word program */
+ 	if (JEDEC_MFR(info->jedec_id) == CFI_MFR_SST)
+ 		flash->mtd._write = sst_write;
+--- a/include/linux/spi/flash.h
++++ b/include/linux/spi/flash.h
+@@ -25,6 +25,7 @@ struct flash_platform_data {
+ 
+ 	char		*type;
+ 
++	size_t		max_read_len;
+ 	/* we'll likely add more ... use JEDEC IDs, etc */
+ };
+ 
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch.svn-base
new file mode 100644
index 0000000..db0a542
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch.svn-base
@@ -0,0 +1,23 @@
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -1016,7 +1016,9 @@ static int m25p_probe(struct spi_device
+ 	/* partitions should match sector boundaries; and it may be good to
+ 	 * use readonly partitions for writeprotected sectors (BP2..BP0).
+ 	 */
+-	return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
++	return mtd_device_parse_register(&flash->mtd,
++			data ? data->part_probes : NULL,
++			&ppdata,
+ 			data ? data->parts : NULL,
+ 			data ? data->nr_parts : 0);
+ }
+--- a/include/linux/spi/flash.h
++++ b/include/linux/spi/flash.h
+@@ -24,6 +24,7 @@ struct flash_platform_data {
+ 	unsigned int	nr_parts;
+ 
+ 	char		*type;
++	const char	**part_probes;
+ 
+ 	size_t		max_read_len;
+ 	/* we'll likely add more ... use JEDEC IDs, etc */
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/408-mtd-redboot_partition_scan.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/408-mtd-redboot_partition_scan.patch.svn-base
new file mode 100644
index 0000000..cd41e7c
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/408-mtd-redboot_partition_scan.patch.svn-base
@@ -0,0 +1,44 @@
+--- a/drivers/mtd/redboot.c
++++ b/drivers/mtd/redboot.c
+@@ -76,12 +76,18 @@ static int parse_redboot_partitions(stru
+ 	static char nullstring[] = "unallocated";
+ #endif
+ 
++	buf = vmalloc(master->erasesize);
++	if (!buf)
++		return -ENOMEM;
++
++ restart:
+ 	if ( directory < 0 ) {
+ 		offset = master->size + directory * master->erasesize;
+ 		while (mtd_block_isbad(master, offset)) {
+ 			if (!offset) {
+ 			nogood:
+ 				printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n");
++				vfree(buf);
+ 				return -EIO;
+ 			}
+ 			offset -= master->erasesize;
+@@ -94,10 +100,6 @@ static int parse_redboot_partitions(stru
+ 				goto nogood;
+ 		}
+ 	}
+-	buf = vmalloc(master->erasesize);
+-
+-	if (!buf)
+-		return -ENOMEM;
+ 
+ 	printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n",
+ 	       master->name, offset);
+@@ -170,6 +172,11 @@ static int parse_redboot_partitions(stru
+ 	}
+ 	if (i == numslots) {
+ 		/* Didn't find it */
++		if (offset + master->erasesize < master->size) {
++			/* not at the end of the flash yet, maybe next block :) */
++			directory++;
++			goto restart;
++		}
+ 		printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
+ 		       master->name);
+ 		ret = 0;
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/409-mtd-rb4xx_nand_driver.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/409-mtd-rb4xx_nand_driver.patch.svn-base
new file mode 100644
index 0000000..082df87
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/409-mtd-rb4xx_nand_driver.patch.svn-base
@@ -0,0 +1,21 @@
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -575,4 +575,8 @@ config MTD_NAND_XWAY
+ 	  Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
+ 	  to the External Bus Unit (EBU).
+ 
++config MTD_NAND_RB4XX
++	tristate "NAND flash driver for RouterBoard 4xx series"
++	depends on MTD_NAND && ATH79_MACH_RB4XX
++
+ endif # MTD_NAND
+--- a/drivers/mtd/nand/Makefile
++++ b/drivers/mtd/nand/Makefile
+@@ -34,6 +34,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270)		+= cmx27
+ obj-$(CONFIG_MTD_NAND_PXA3xx)		+= pxa3xx_nand.o
+ obj-$(CONFIG_MTD_NAND_TMIO)		+= tmio_nand.o
+ obj-$(CONFIG_MTD_NAND_PLATFORM)		+= plat_nand.o
++obj-$(CONFIG_MTD_NAND_RB4XX)		+= rb4xx_nand.o
+ obj-$(CONFIG_MTD_ALAUDA)		+= alauda.o
+ obj-$(CONFIG_MTD_NAND_PASEMI)		+= pasemi_nand.o
+ obj-$(CONFIG_MTD_NAND_ORION)		+= orion_nand.o
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/410-mtd-rb750-nand-driver.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/410-mtd-rb750-nand-driver.patch.svn-base
new file mode 100644
index 0000000..1247866
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/410-mtd-rb750-nand-driver.patch.svn-base
@@ -0,0 +1,21 @@
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -579,4 +579,8 @@ config MTD_NAND_RB4XX
+ 	tristate "NAND flash driver for RouterBoard 4xx series"
+ 	depends on MTD_NAND && ATH79_MACH_RB4XX
+ 
++config MTD_NAND_RB750
++	tristate "NAND flash driver for the RouterBoard 750"
++	depends on MTD_NAND && ATH79_MACH_RB750
++
+ endif # MTD_NAND
+--- a/drivers/mtd/nand/Makefile
++++ b/drivers/mtd/nand/Makefile
+@@ -35,6 +35,7 @@ obj-$(CONFIG_MTD_NAND_PXA3xx)		+= pxa3xx
+ obj-$(CONFIG_MTD_NAND_TMIO)		+= tmio_nand.o
+ obj-$(CONFIG_MTD_NAND_PLATFORM)		+= plat_nand.o
+ obj-$(CONFIG_MTD_NAND_RB4XX)		+= rb4xx_nand.o
++obj-$(CONFIG_MTD_NAND_RB750)		+= rb750_nand.o
+ obj-$(CONFIG_MTD_ALAUDA)		+= alauda.o
+ obj-$(CONFIG_MTD_NAND_PASEMI)		+= pasemi_nand.o
+ obj-$(CONFIG_MTD_NAND_ORION)		+= orion_nand.o
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/411-mtd-cfi_cmdset_0002-force-word-write.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/411-mtd-cfi_cmdset_0002-force-word-write.patch.svn-base
new file mode 100644
index 0000000..2d8e6e6
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/411-mtd-cfi_cmdset_0002-force-word-write.patch.svn-base
@@ -0,0 +1,61 @@
+--- a/drivers/mtd/chips/cfi_cmdset_0002.c
++++ b/drivers/mtd/chips/cfi_cmdset_0002.c
+@@ -39,7 +39,7 @@
+ #include <linux/mtd/xip.h>
+ 
+ #define AMD_BOOTLOC_BUG
+-#define FORCE_WORD_WRITE 0
++#define FORCE_WORD_WRITE 1
+ 
+ #define MAX_WORD_RETRIES 3
+ 
+@@ -50,7 +50,9 @@
+ 
+ static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
+ static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
++#if !FORCE_WORD_WRITE
+ static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
++#endif
+ static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
+ static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
+ static void cfi_amdstd_sync (struct mtd_info *);
+@@ -186,6 +188,7 @@ static void fixup_amd_bootblock(struct m
+ }
+ #endif
+ 
++#if !FORCE_WORD_WRITE
+ static void fixup_use_write_buffers(struct mtd_info *mtd)
+ {
+ 	struct map_info *map = mtd->priv;
+@@ -195,6 +198,7 @@ static void fixup_use_write_buffers(stru
+ 		mtd->_write = cfi_amdstd_write_buffers;
+ 	}
+ }
++#endif /* !FORCE_WORD_WRITE */
+ 
+ /* Atmel chips don't use the same PRI format as AMD chips */
+ static void fixup_convert_atmel_pri(struct mtd_info *mtd)
+@@ -1445,6 +1449,7 @@ static int cfi_amdstd_write_words(struct
+ /*
+  * FIXME: interleaved mode not tested, and probably not supported!
+  */
++#if !FORCE_WORD_WRITE
+ static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
+ 				    unsigned long adr, const u_char *buf,
+ 				    int len)
+@@ -1569,7 +1574,6 @@ static int __xipram do_write_buffer(stru
+ 	return ret;
+ }
+ 
+-
+ static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
+ 				    size_t *retlen, const u_char *buf)
+ {
+@@ -1644,6 +1648,7 @@ static int cfi_amdstd_write_buffers(stru
+ 
+ 	return 0;
+ }
++#endif /* !FORCE_WORD_WRITE */
+ 
+ /*
+  * Wait for the flash chip to become ready to write data
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/412-mtd-m25p80-zero-partition-parser-data.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/412-mtd-m25p80-zero-partition-parser-data.patch.svn-base
new file mode 100644
index 0000000..e9beb6b
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/412-mtd-m25p80-zero-partition-parser-data.patch.svn-base
@@ -0,0 +1,10 @@
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -966,6 +966,7 @@ static int m25p_probe(struct spi_device
+ 	if (info->flags & M25P_NO_ERASE)
+ 		flash->mtd.flags |= MTD_NO_ERASE;
+ 
++	memset(&ppdata, '\0', sizeof(ppdata));
+ 	ppdata.of_node = spi->dev.of_node;
+ 	flash->mtd.dev.parent = &spi->dev;
+ 	flash->page_size = info->page_size;
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/413-mtd-ar934x-nand-driver.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/413-mtd-ar934x-nand-driver.patch.svn-base
new file mode 100644
index 0000000..f8362cb
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/413-mtd-ar934x-nand-driver.patch.svn-base
@@ -0,0 +1,21 @@
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -583,4 +583,8 @@ config MTD_NAND_RB750
+ 	tristate "NAND flash driver for the RouterBoard 750"
+ 	depends on MTD_NAND && ATH79_MACH_RB750
+ 
++config MTD_NAND_AR934X
++	tristate "NAND flash driver for the Qualcomm Atheros AR934x/QCA955x SoCs"
++	depends on (SOC_AR934X || SOC_QCA955X)
++
+ endif # MTD_NAND
+--- a/drivers/mtd/nand/Makefile
++++ b/drivers/mtd/nand/Makefile
+@@ -13,6 +13,7 @@ obj-$(CONFIG_MTD_NAND_AMS_DELTA)	+= ams-
+ obj-$(CONFIG_MTD_NAND_DENALI)		+= denali.o
+ obj-$(CONFIG_MTD_NAND_DENALI_PCI)	+= denali_pci.o
+ obj-$(CONFIG_MTD_NAND_DENALI_DT)	+= denali_dt.o
++obj-$(CONFIG_MTD_NAND_AR934X)		+= ar934x_nfc.o
+ obj-$(CONFIG_MTD_NAND_AU1550)		+= au1550nd.o
+ obj-$(CONFIG_MTD_NAND_BF5XX)		+= bf5xx_nand.o
+ obj-$(CONFIG_MTD_NAND_PPCHAMELEONEVB)	+= ppchameleonevb.o
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/420-net-ar71xx_mac_driver.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/420-net-ar71xx_mac_driver.patch.svn-base
new file mode 100644
index 0000000..f117133
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/420-net-ar71xx_mac_driver.patch.svn-base
@@ -0,0 +1,28 @@
+--- a/drivers/net/ethernet/atheros/Kconfig
++++ b/drivers/net/ethernet/atheros/Kconfig
+@@ -5,7 +5,7 @@
+ config NET_VENDOR_ATHEROS
+ 	bool "Atheros devices"
+ 	default y
+-	depends on PCI
++	depends on (PCI || ATH79)
+ 	---help---
+ 	  If you have a network (Ethernet) card belonging to this class, say Y
+ 	  and read the Ethernet-HOWTO, available from
+@@ -67,4 +67,6 @@ config ATL1C
+ 	  To compile this driver as a module, choose M here.  The module
+ 	  will be called atl1c.
+ 
++source drivers/net/ethernet/atheros/ag71xx/Kconfig
++
+ endif # NET_VENDOR_ATHEROS
+--- a/drivers/net/ethernet/atheros/Makefile
++++ b/drivers/net/ethernet/atheros/Makefile
+@@ -2,6 +2,7 @@
+ # Makefile for the Atheros network device drivers.
+ #
+ 
++obj-$(CONFIG_AG71XX) += ag71xx/
+ obj-$(CONFIG_ATL1) += atlx/
+ obj-$(CONFIG_ATL2) += atlx/
+ obj-$(CONFIG_ATL1E) += atl1e/
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/422-dsa-trailer-tag-validation-fix.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/422-dsa-trailer-tag-validation-fix.patch.svn-base
new file mode 100644
index 0000000..3e3902b
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/422-dsa-trailer-tag-validation-fix.patch.svn-base
@@ -0,0 +1,11 @@
+--- a/net/dsa/tag_trailer.c
++++ b/net/dsa/tag_trailer.c
+@@ -87,7 +87,7 @@ static int trailer_rcv(struct sk_buff *s
+ 
+ 	trailer = skb_tail_pointer(skb) - 4;
+ 	if (trailer[0] != 0x80 || (trailer[1] & 0xf8) != 0x00 ||
+-	    (trailer[3] & 0xef) != 0x00 || trailer[3] != 0x00)
++	    (trailer[2] & 0xef) != 0x00 || (trailer[3] & 0xfe) != 0x00)
+ 		goto out_drop;
+ 
+ 	source_port = trailer[1] & 7;
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/423-dsa-add-88e6063-driver.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/423-dsa-add-88e6063-driver.patch.svn-base
new file mode 100644
index 0000000..1348cd9
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/423-dsa-add-88e6063-driver.patch.svn-base
@@ -0,0 +1,24 @@
+--- a/drivers/net/dsa/Kconfig
++++ b/drivers/net/dsa/Kconfig
+@@ -13,6 +13,13 @@ config NET_DSA_MV88E6060
+ 	  This enables support for the Marvell 88E6060 ethernet switch
+ 	  chip.
+ 
++config NET_DSA_MV88E6063
++	bool "Marvell 88E6063 ethernet switch chip support"
++	select NET_DSA_TAG_TRAILER
++	---help---
++	  This enables support for the Marvell 88E6063 ethernet switch
++	  chip
++
+ config NET_DSA_MV88E6XXX_NEED_PPU
+ 	bool
+ 	default n
+--- a/drivers/net/dsa/Makefile
++++ b/drivers/net/dsa/Makefile
+@@ -1,4 +1,5 @@
+ obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
++obj-$(CONFIG_NET_DSA_MV88E6063) += mv88e6063.o
+ obj-$(CONFIG_NET_DSA_MV88E6XXX) += mv88e6xxx_drv.o
+ mv88e6xxx_drv-y += mv88e6xxx.o
+ ifdef CONFIG_NET_DSA_MV88E6123_61_65
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/430-drivers-link-spi-before-mtd.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/430-drivers-link-spi-before-mtd.patch.svn-base
new file mode 100644
index 0000000..88d1457
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/430-drivers-link-spi-before-mtd.patch.svn-base
@@ -0,0 +1,12 @@
+--- a/drivers/Makefile
++++ b/drivers/Makefile
+@@ -60,8 +60,8 @@ obj-$(CONFIG_IDE)		+= ide/
+ obj-$(CONFIG_SCSI)		+= scsi/
+ obj-$(CONFIG_ATA)		+= ata/
+ obj-$(CONFIG_TARGET_CORE)	+= target/
+-obj-$(CONFIG_MTD)		+= mtd/
+ obj-$(CONFIG_SPI)		+= spi/
++obj-$(CONFIG_MTD)		+= mtd/
+ obj-y				+= hsi/
+ obj-y				+= net/
+ obj-$(CONFIG_ATM)		+= atm/
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/431-spi-add-various-flags.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/431-spi-add-various-flags.patch.svn-base
new file mode 100644
index 0000000..9f13db2
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/431-spi-add-various-flags.patch.svn-base
@@ -0,0 +1,19 @@
+--- a/include/linux/spi/spi.h
++++ b/include/linux/spi/spi.h
+@@ -506,6 +506,8 @@ struct spi_transfer {
+ 	dma_addr_t	rx_dma;
+ 
+ 	unsigned	cs_change:1;
++	unsigned	verify:1;
++	unsigned	fast_write:1;
+ 	u8		bits_per_word;
+ 	u16		delay_usecs;
+ 	u32		speed_hz;
+@@ -547,6 +549,7 @@ struct spi_message {
+ 	struct spi_device	*spi;
+ 
+ 	unsigned		is_dma_mapped:1;
++	unsigned		fast_read:1;
+ 
+ 	/* REVISIT:  we might want a flag affecting the behavior of the
+ 	 * last transfer ... allowing things like "read 16 bit length L"
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/432-spi-rb4xx-spi-driver.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/432-spi-rb4xx-spi-driver.patch.svn-base
new file mode 100644
index 0000000..1ff133c
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/432-spi-rb4xx-spi-driver.patch.svn-base
@@ -0,0 +1,25 @@
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -324,6 +324,12 @@ config SPI_RSPI
+ 	help
+ 	  SPI driver for Renesas RSPI blocks.
+ 
++config SPI_RB4XX
++	tristate "Mikrotik RB4XX SPI master"
++	depends on SPI_MASTER && ATH79_MACH_RB4XX
++	help
++	  SPI controller driver for the Mikrotik RB4xx series boards.
++
+ config SPI_S3C24XX
+ 	tristate "Samsung S3C24XX series SPI"
+ 	depends on ARCH_S3C24XX && EXPERIMENTAL
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -50,6 +50,7 @@ obj-$(CONFIG_SPI_PL022)			+= spi-pl022.o
+ obj-$(CONFIG_SPI_PPC4xx)		+= spi-ppc4xx.o
+ obj-$(CONFIG_SPI_PXA2XX)		+= spi-pxa2xx.o
+ obj-$(CONFIG_SPI_PXA2XX_PCI)		+= spi-pxa2xx-pci.o
++obj-$(CONFIG_SPI_RB4XX)			+= spi-rb4xx.o
+ obj-$(CONFIG_SPI_RSPI)			+= spi-rspi.o
+ obj-$(CONFIG_SPI_S3C24XX)		+= spi-s3c24xx-hw.o
+ spi-s3c24xx-hw-y			:= spi-s3c24xx.o
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/433-spi-rb4xx-cpld-driver.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/433-spi-rb4xx-cpld-driver.patch.svn-base
new file mode 100644
index 0000000..8fb9fa5
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/433-spi-rb4xx-cpld-driver.patch.svn-base
@@ -0,0 +1,26 @@
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -509,6 +509,13 @@ config SPI_TLE62X0
+ 	  sysfs interface, with each line presented as a kind of GPIO
+ 	  exposing both switch control and diagnostic feedback.
+ 
++config SPI_RB4XX_CPLD
++	tristate "MikroTik RB4XX CPLD driver"
++	depends on ATH79_MACH_RB4XX
++	help
++	  SPI driver for the Xilinx CPLD chip present on the
++	  MikroTik RB4xx boards.
++
+ #
+ # Add new SPI protocol masters in alphabetical order above this line
+ #
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -51,6 +51,7 @@ obj-$(CONFIG_SPI_PPC4xx)		+= spi-ppc4xx.
+ obj-$(CONFIG_SPI_PXA2XX)		+= spi-pxa2xx.o
+ obj-$(CONFIG_SPI_PXA2XX_PCI)		+= spi-pxa2xx-pci.o
+ obj-$(CONFIG_SPI_RB4XX)			+= spi-rb4xx.o
++obj-$(CONFIG_SPI_RB4XX_CPLD)		+= spi-rb4xx-cpld.o
+ obj-$(CONFIG_SPI_RSPI)			+= spi-rspi.o
+ obj-$(CONFIG_SPI_S3C24XX)		+= spi-s3c24xx-hw.o
+ spi-s3c24xx-hw-y			:= spi-s3c24xx.o
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/434-spi-ap83_spi_controller.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/434-spi-ap83_spi_controller.patch.svn-base
new file mode 100644
index 0000000..964ffe3
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/434-spi-ap83_spi_controller.patch.svn-base
@@ -0,0 +1,27 @@
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -12,6 +12,7 @@ obj-$(CONFIG_SPI_SPIDEV)		+= spidev.o
+ # SPI master controller drivers (bus)
+ obj-$(CONFIG_SPI_ALTERA)		+= spi-altera.o
+ obj-$(CONFIG_SPI_ATMEL)			+= spi-atmel.o
++obj-$(CONFIG_SPI_AP83)			+= spi-ap83.o
+ obj-$(CONFIG_SPI_ATH79)			+= spi-ath79.o
+ obj-$(CONFIG_SPI_AU1550)		+= spi-au1550.o
+ obj-$(CONFIG_SPI_BCM63XX)		+= spi-bcm63xx.o
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -59,6 +59,14 @@ config SPI_ALTERA
+ 	help
+ 	  This is the driver for the Altera SPI Controller.
+ 
++config SPI_AP83
++	tristate "Atheros AP83 specific SPI Controller"
++	depends on SPI_MASTER && ATH79_MACH_AP83
++	select SPI_BITBANG
++	help
++	  This is a specific SPI controller driver for the Atheros AP83
++	  reference board.
++
+ config SPI_ATH79
+ 	tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver"
+ 	depends on ATH79 && GENERIC_GPIO
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/435-spi-vsc7385_driver.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/435-spi-vsc7385_driver.patch.svn-base
new file mode 100644
index 0000000..c06ae53
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/435-spi-vsc7385_driver.patch.svn-base
@@ -0,0 +1,23 @@
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -524,6 +524,11 @@ config SPI_RB4XX_CPLD
+ 	  SPI driver for the Xilinx CPLD chip present on the
+ 	  MikroTik RB4xx boards.
+ 
++config SPI_VSC7385
++	tristate "Vitesse VSC7385 ethernet switch driver"
++	help
++	  SPI driver for the Vitesse VSC7385 ethernet switch.
++
+ #
+ # Add new SPI protocol masters in alphabetical order above this line
+ #
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -70,5 +70,6 @@ obj-$(CONFIG_SPI_TI_SSP)		+= spi-ti-ssp.
+ obj-$(CONFIG_SPI_TLE62X0)		+= spi-tle62x0.o
+ obj-$(CONFIG_SPI_TOPCLIFF_PCH)		+= spi-topcliff-pch.o
+ obj-$(CONFIG_SPI_TXX9)			+= spi-txx9.o
++obj-$(CONFIG_SPI_VSC7385)		+= spi-vsc7385.o
+ obj-$(CONFIG_SPI_XCOMM)		+= spi-xcomm.o
+ obj-$(CONFIG_SPI_XILINX)		+= spi-xilinx.o
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/440-leds-wndr3700-usb-led-driver.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/440-leds-wndr3700-usb-led-driver.patch.svn-base
new file mode 100644
index 0000000..e82277a
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/440-leds-wndr3700-usb-led-driver.patch.svn-base
@@ -0,0 +1,26 @@
+--- a/drivers/leds/Kconfig
++++ b/drivers/leds/Kconfig
+@@ -467,6 +467,13 @@ config LEDS_TRIGGERS
+ 	  These triggers allow kernel events to drive the LEDs and can
+ 	  be configured via sysfs. If unsure, say Y.
+ 
++config LEDS_WNDR3700_USB
++	tristate "NETGEAR WNDR3700 USB LED driver"
++	depends on LEDS_CLASS && ATH79_MACH_WNDR3700
++	help
++	  This option enables support for the USB LED found on the
++	  NETGEAR WNDR3700 board.
++
+ comment "LED Triggers"
+ 
+ config LEDS_TRIGGER_TIMER
+--- a/drivers/leds/Makefile
++++ b/drivers/leds/Makefile
+@@ -38,6 +38,7 @@ obj-$(CONFIG_LEDS_DA9052)		+= leds-da905
+ obj-$(CONFIG_LEDS_WM831X_STATUS)	+= leds-wm831x-status.o
+ obj-$(CONFIG_LEDS_WM8350)		+= leds-wm8350.o
+ obj-$(CONFIG_LEDS_PWM)			+= leds-pwm.o
++obj-${CONFIG_LEDS_WNDR3700_USB}		+= leds-wndr3700-usb.o
+ obj-$(CONFIG_LEDS_REGULATOR)		+= leds-regulator.o
+ obj-$(CONFIG_LEDS_INTEL_SS4200)		+= leds-ss4200.o
+ obj-$(CONFIG_LEDS_LT3593)		+= leds-lt3593.o
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/441-leds-rb750-led-driver.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/441-leds-rb750-led-driver.patch.svn-base
new file mode 100644
index 0000000..4eaa604
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/441-leds-rb750-led-driver.patch.svn-base
@@ -0,0 +1,23 @@
+--- a/drivers/leds/Kconfig
++++ b/drivers/leds/Kconfig
+@@ -474,6 +474,10 @@ config LEDS_WNDR3700_USB
+ 	  This option enables support for the USB LED found on the
+ 	  NETGEAR WNDR3700 board.
+ 
++config LEDS_RB750
++	tristate "LED driver for the Mikrotik RouterBOARD 750"
++	depends on LEDS_CLASS && ATH79_MACH_RB750
++
+ comment "LED Triggers"
+ 
+ config LEDS_TRIGGER_TIMER
+--- a/drivers/leds/Makefile
++++ b/drivers/leds/Makefile
+@@ -45,6 +45,7 @@ obj-$(CONFIG_LEDS_LT3593)		+= leds-lt359
+ obj-$(CONFIG_LEDS_ADP5520)		+= leds-adp5520.o
+ obj-$(CONFIG_LEDS_DELL_NETBOOKS)	+= dell-led.o
+ obj-$(CONFIG_LEDS_MC13783)		+= leds-mc13783.o
++obj-$(CONFIG_LEDS_RB750)		+= leds-rb750.o
+ obj-$(CONFIG_LEDS_NS2)			+= leds-ns2.o
+ obj-$(CONFIG_LEDS_NETXBIG)		+= leds-netxbig.o
+ obj-$(CONFIG_LEDS_ASIC3)		+= leds-asic3.o
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/450-gpio-nxp-74hc153-gpio-chip-driver.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/450-gpio-nxp-74hc153-gpio-chip-driver.patch.svn-base
new file mode 100644
index 0000000..97e15cd
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/450-gpio-nxp-74hc153-gpio-chip-driver.patch.svn-base
@@ -0,0 +1,25 @@
+--- a/drivers/gpio/Kconfig
++++ b/drivers/gpio/Kconfig
+@@ -697,4 +697,12 @@ config GPIO_VIPERBOARD
+           River Tech's viperboard.h for detailed meaning
+           of the module parameters.
+ 
++comment "Other GPIO expanders"
++
++config GPIO_NXP_74HC153
++	tristate "NXP 74HC153 Dual 4-input multiplexer"
++	help
++	  Platform driver for NXP 74HC153 Dual 4-input Multiplexer. This
++	  provides a GPIO interface supporting input mode only.
++
+ endif
+--- a/drivers/gpio/Makefile
++++ b/drivers/gpio/Makefile
+@@ -48,6 +48,7 @@ obj-$(CONFIG_GPIO_MSM_V2)	+= gpio-msm-v2
+ obj-$(CONFIG_GPIO_MVEBU)        += gpio-mvebu.o
+ obj-$(CONFIG_GPIO_MXC)		+= gpio-mxc.o
+ obj-$(CONFIG_GPIO_MXS)		+= gpio-mxs.o
++obj-$(CONFIG_GPIO_NXP_74HC153)	+= gpio-nxp-74hc153.o
+ obj-$(CONFIG_ARCH_OMAP)		+= gpio-omap.o
+ obj-$(CONFIG_GPIO_PCA953X)	+= gpio-pca953x.o
+ obj-$(CONFIG_GPIO_PCF857X)	+= gpio-pcf857x.o
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/460-spi-bitbang-export-spi_bitbang_bufs.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/460-spi-bitbang-export-spi_bitbang_bufs.patch.svn-base
new file mode 100644
index 0000000..919b85c
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/460-spi-bitbang-export-spi_bitbang_bufs.patch.svn-base
@@ -0,0 +1,28 @@
+--- a/drivers/spi/spi-bitbang.c
++++ b/drivers/spi/spi-bitbang.c
+@@ -234,13 +234,14 @@ void spi_bitbang_cleanup(struct spi_devi
+ }
+ EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);
+ 
+-static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
++int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
+ {
+ 	struct spi_bitbang_cs	*cs = spi->controller_state;
+ 	unsigned		nsecs = cs->nsecs;
+ 
+ 	return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t);
+ }
++EXPORT_SYMBOL_GPL(spi_bitbang_bufs);
+ 
+ /*----------------------------------------------------------------------*/
+ 
+--- a/include/linux/spi/spi_bitbang.h
++++ b/include/linux/spi/spi_bitbang.h
+@@ -44,6 +44,7 @@ extern void spi_bitbang_cleanup(struct s
+ extern int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m);
+ extern int spi_bitbang_setup_transfer(struct spi_device *spi,
+ 				      struct spi_transfer *t);
++extern int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t);
+ 
+ /* start or stop queue processing */
+ extern int spi_bitbang_start(struct spi_bitbang *spi);
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/461-spi-add-type-field-to-spi_transfer.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/461-spi-add-type-field-to-spi_transfer.patch.svn-base
new file mode 100644
index 0000000..d956499
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/461-spi-add-type-field-to-spi_transfer.patch.svn-base
@@ -0,0 +1,23 @@
+--- a/include/linux/spi/spi.h
++++ b/include/linux/spi/spi.h
+@@ -409,6 +409,12 @@ extern struct spi_master *spi_busnum_to_
+ 
+ /*---------------------------------------------------------------------------*/
+ 
++enum spi_transfer_type {
++	SPI_TRANSFER_GENERIC = 0,
++	SPI_TRANSFER_FLASH_READ_CMD,
++	SPI_TRANSFER_FLASH_READ_DATA,
++};
++
+ /*
+  * I/O INTERFACE between SPI controller and protocol drivers
+  *
+@@ -511,6 +517,7 @@ struct spi_transfer {
+ 	u8		bits_per_word;
+ 	u16		delay_usecs;
+ 	u32		speed_hz;
++	enum spi_transfer_type type;
+ 
+ 	struct list_head transfer_list;
+ };
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/462-mtd-m25p80-set-spi-transfer-type.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/462-mtd-m25p80-set-spi-transfer-type.patch.svn-base
new file mode 100644
index 0000000..e1ceb66
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/462-mtd-m25p80-set-spi-transfer-type.patch.svn-base
@@ -0,0 +1,15 @@
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -357,10 +357,12 @@ static int m25p80_read(struct mtd_info *
+ 	 * OPCODE_FAST_READ (if available) is faster.
+ 	 * Should add 1 byte DUMMY_BYTE.
+ 	 */
++	t[0].type = SPI_TRANSFER_FLASH_READ_CMD;
+ 	t[0].tx_buf = flash->command;
+ 	t[0].len = m25p_cmdsz(flash) + (flash->fast_read ? 1 : 0);
+ 	spi_message_add_tail(&t[0], &m);
+ 
++	t[1].type = SPI_TRANSFER_FLASH_READ_DATA;
+ 	spi_message_add_tail(&t[1], &m);
+ 
+ 	mutex_lock(&flash->lock);
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/463-spi-ath79-add-fast-flash-read.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/463-spi-ath79-add-fast-flash-read.patch.svn-base
new file mode 100644
index 0000000..e861644
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/463-spi-ath79-add-fast-flash-read.patch.svn-base
@@ -0,0 +1,185 @@
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -37,6 +37,11 @@
+ 
+ #define ATH79_SPI_CS_LINE_MAX		2
+ 
++enum ath79_spi_state {
++	ATH79_SPI_STATE_WAIT_CMD = 0,
++	ATH79_SPI_STATE_WAIT_READ,
++};
++
+ struct ath79_spi {
+ 	struct spi_bitbang	bitbang;
+ 	u32			ioc_base;
+@@ -44,6 +49,11 @@ struct ath79_spi {
+ 	void __iomem		*base;
+ 	struct clk		*clk;
+ 	unsigned		rrw_delay;
++
++	enum ath79_spi_state	state;
++	u32			clk_div;
++	unsigned long 		read_addr;
++	unsigned long		ahb_rate;
+ };
+ 
+ static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
+@@ -111,9 +121,6 @@ static void ath79_spi_enable(struct ath7
+ 	/* save CTRL register */
+ 	sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
+ 	sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
+-
+-	/* TODO: setup speed? */
+-	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
+ }
+ 
+ static void ath79_spi_disable(struct ath79_spi *sp)
+@@ -232,6 +239,110 @@ static u32 ath79_spi_txrx_mode0(struct s
+ 	return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
+ }
+ 
++static int ath79_spi_do_read_flash_data(struct spi_device *spi,
++					struct spi_transfer *t)
++{
++	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
++
++	/* disable GPIO mode */
++	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
++
++	memcpy_fromio(t->rx_buf, sp->base + sp->read_addr, t->len);
++
++	/* enable GPIO mode */
++	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
++
++	/* restore IOC register */
++	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
++
++	return t->len;
++}
++
++static int ath79_spi_do_read_flash_cmd(struct spi_device *spi,
++				       struct spi_transfer *t)
++{
++	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
++	int len;
++	const u8 *p;
++
++	sp->read_addr = 0;
++
++	len = t->len - 1;
++	p = t->tx_buf;
++
++	while (len--) {
++		p++;
++		sp->read_addr <<= 8;
++		sp->read_addr |= *p;
++	}
++
++	return t->len;
++}
++
++static bool ath79_spi_is_read_cmd(struct spi_device *spi,
++				 struct spi_transfer *t)
++{
++	return t->type == SPI_TRANSFER_FLASH_READ_CMD;
++}
++
++static bool ath79_spi_is_data_read(struct spi_device *spi,
++				  struct spi_transfer *t)
++{
++	return t->type == SPI_TRANSFER_FLASH_READ_DATA;
++}
++
++static int ath79_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
++{
++	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
++	int ret;
++
++	switch (sp->state) {
++	case ATH79_SPI_STATE_WAIT_CMD:
++		if (ath79_spi_is_read_cmd(spi, t)) {
++			ret = ath79_spi_do_read_flash_cmd(spi, t);
++			sp->state = ATH79_SPI_STATE_WAIT_READ;
++		} else {
++			ret = spi_bitbang_bufs(spi, t);
++		}
++		break;
++
++	case ATH79_SPI_STATE_WAIT_READ:
++		if (ath79_spi_is_data_read(spi, t)) {
++			ret = ath79_spi_do_read_flash_data(spi, t);
++		} else {
++			dev_warn(&spi->dev, "flash data read expected\n");
++			ret = -EIO;
++		}
++		sp->state = ATH79_SPI_STATE_WAIT_CMD;
++		break;
++
++	default:
++		BUG();
++	}
++
++	return ret;
++}
++
++static int ath79_spi_setup_transfer(struct spi_device *spi,
++				    struct spi_transfer *t)
++{
++	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
++	struct ath79_spi_controller_data *cdata;
++	int ret;
++
++	ret = spi_bitbang_setup_transfer(spi, t);
++	if (ret)
++		return ret;
++
++	cdata = spi->controller_data;
++	if (cdata->is_flash)
++		sp->bitbang.txrx_bufs = ath79_spi_txrx_bufs;
++	else
++		sp->bitbang.txrx_bufs = spi_bitbang_bufs;
++
++	return ret;
++}
++
+ static int ath79_spi_probe(struct platform_device *pdev)
+ {
+ 	struct spi_master *master;
+@@ -254,6 +365,8 @@ static int ath79_spi_probe(struct platfo
+ 	sp = spi_master_get_devdata(master);
+ 	platform_set_drvdata(pdev, sp);
+ 
++	sp->state = ATH79_SPI_STATE_WAIT_CMD;
++
+ 	master->setup = ath79_spi_setup;
+ 	master->cleanup = ath79_spi_cleanup;
+ 	master->bus_num = pdata->bus_num;
+@@ -262,7 +375,7 @@ static int ath79_spi_probe(struct platfo
+ 	sp->bitbang.master = spi_master_get(master);
+ 	sp->bitbang.chipselect = ath79_spi_chipselect;
+ 	sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
+-	sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
++	sp->bitbang.setup_transfer = ath79_spi_setup_transfer;
+ 	sp->bitbang.flags = SPI_CS_HIGH;
+ 
+ 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+@@ -287,7 +400,8 @@ static int ath79_spi_probe(struct platfo
+ 	if (ret)
+ 		goto err_clk_put;
+ 
+-	rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
++	sp->ahb_rate = clk_get_rate(sp->clk);
++	rate = DIV_ROUND_UP(sp->ahb_rate, MHZ);
+ 	if (!rate) {
+ 		ret = -EINVAL;
+ 		goto err_clk_disable;
+--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
++++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
+@@ -24,6 +24,7 @@ enum ath79_spi_cs_type {
+ struct ath79_spi_controller_data {
+ 	enum ath79_spi_cs_type cs_type;
+ 	unsigned cs_line;
++	bool is_flash;
+ };
+ 
+ #endif /* _ATH79_SPI_PLATFORM_H */
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch.svn-base
new file mode 100644
index 0000000..520c652
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch.svn-base
@@ -0,0 +1,111 @@
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ath79/mangle-port.h
+@@ -0,0 +1,37 @@
++/*
++ *  Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
++ *
++ *  This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h
++ *      Copyright (C) 2003, 2004 Ralf Baechle
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ */
++
++#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H
++#define __ASM_MACH_ATH79_MANGLE_PORT_H
++
++#ifdef CONFIG_PCI
++extern unsigned long (ath79_pci_swizzle_b)(unsigned long port);
++extern unsigned long (ath79_pci_swizzle_w)(unsigned long port);
++#else
++#define ath79_pci_swizzle_b(port) (port)
++#define ath79_pci_swizzle_w(port) (port)
++#endif
++
++#define __swizzle_addr_b(port)	ath79_pci_swizzle_b(port)
++#define __swizzle_addr_w(port)	ath79_pci_swizzle_w(port)
++#define __swizzle_addr_l(port)	(port)
++#define __swizzle_addr_q(port)	(port)
++
++# define ioswabb(a, x)           (x)
++# define __mem_ioswabb(a, x)     (x)
++# define ioswabw(a, x)           (x)
++# define __mem_ioswabw(a, x)     cpu_to_le16(x)
++# define ioswabl(a, x)           (x)
++# define __mem_ioswabl(a, x)     cpu_to_le32(x)
++# define ioswabq(a, x)           (x)
++# define __mem_ioswabq(a, x)     cpu_to_le64(x)
++
++#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -13,6 +13,7 @@
+  */
+ 
+ #include <linux/init.h>
++#include <linux/export.h>
+ #include <linux/pci.h>
+ #include <linux/resource.h>
+ #include <linux/platform_device.h>
+@@ -25,6 +26,9 @@ static int (*ath79_pci_plat_dev_init)(st
+ static const struct ath79_pci_irq *ath79_pci_irq_map __initdata;
+ static unsigned ath79_pci_nr_irqs __initdata;
+ 
++static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port);
++static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port);
++
+ static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = {
+ 	{
+ 		.slot	= 17,
+@@ -212,12 +216,50 @@ ath79_register_pci_ar724x(int id,
+ 	return pdev;
+ }
+ 
++static inline bool ar71xx_is_pci_addr(unsigned long port)
++{
++	unsigned long phys = CPHYSADDR(port);
++
++	return (phys >= AR71XX_PCI_MEM_BASE &&
++		phys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE);
++}
++
++static unsigned long ar71xx_pci_swizzle_b(unsigned long port)
++{
++	return ar71xx_is_pci_addr(port) ? port ^ 3 : port;
++}
++
++static unsigned long ar71xx_pci_swizzle_w(unsigned long port)
++{
++	return ar71xx_is_pci_addr(port) ? port ^ 2 : port;
++}
++
++unsigned long ath79_pci_swizzle_b(unsigned long port)
++{
++	if (__ath79_pci_swizzle_b)
++		return __ath79_pci_swizzle_b(port);
++
++	return port;
++}
++EXPORT_SYMBOL(ath79_pci_swizzle_b);
++
++unsigned long ath79_pci_swizzle_w(unsigned long port)
++{
++	if (__ath79_pci_swizzle_w)
++		return __ath79_pci_swizzle_w(port);
++
++	return port;
++}
++EXPORT_SYMBOL(ath79_pci_swizzle_w);
++
+ int __init ath79_register_pci(void)
+ {
+ 	struct platform_device *pdev = NULL;
+ 
+ 	if (soc_is_ar71xx()) {
+ 		pdev = ath79_register_pci_ar71xx();
++		__ath79_pci_swizzle_b = ar71xx_pci_swizzle_b;
++		__ath79_pci_swizzle_w = ar71xx_pci_swizzle_w;
+ 	} else if (soc_is_ar724x()) {
+ 		pdev = ath79_register_pci_ar724x(-1,
+ 						 AR724X_PCI_CFG_BASE,
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/500-MIPS-fw-myloader.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/500-MIPS-fw-myloader.patch.svn-base
new file mode 100644
index 0000000..421f6a9
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/500-MIPS-fw-myloader.patch.svn-base
@@ -0,0 +1,22 @@
+--- a/arch/mips/Makefile
++++ b/arch/mips/Makefile
+@@ -182,6 +182,7 @@ endif
+ #
+ libs-$(CONFIG_FW_ARC)		+= arch/mips/fw/arc/
+ libs-$(CONFIG_FW_CFE)		+= arch/mips/fw/cfe/
++libs-$(CONFIG_MYLOADER)		+= arch/mips/fw/myloader/
+ libs-$(CONFIG_FW_SNIPROM)	+= arch/mips/fw/sni/
+ libs-y				+= arch/mips/fw/lib/
+ 
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -989,6 +989,9 @@ config MIPS_NILE4
+ config MIPS_DISABLE_OBSOLETE_IDE
+ 	bool
+ 
++config MYLOADER
++	bool
++
+ config SYNC_R4K
+ 	bool
+ 
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch.svn-base
new file mode 100644
index 0000000..de0db9a
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch.svn-base
@@ -0,0 +1,81 @@
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -15,6 +15,7 @@
+ #include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/irq.h>
++#include <linux/etherdevice.h>
+ #include <linux/platform_device.h>
+ #include <linux/ath9k_platform.h>
+ 
+@@ -22,6 +23,7 @@
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include "dev-wmac.h"
+ 
++static u8 ath79_wmac_mac[ETH_ALEN];
+ static struct ath9k_platform_data ath79_wmac_data;
+ 
+ static struct resource ath79_wmac_resources[] = {
+@@ -151,7 +153,7 @@ static void qca955x_wmac_setup(void)
+ 		ath79_wmac_data.is_clk_25mhz = true;
+ }
+ 
+-void __init ath79_register_wmac(u8 *cal_data)
++void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
+ {
+ 	if (soc_is_ar913x())
+ 		ar913x_wmac_setup();
+@@ -168,5 +170,10 @@ void __init ath79_register_wmac(u8 *cal_
+ 		memcpy(ath79_wmac_data.eeprom_data, cal_data,
+ 		       sizeof(ath79_wmac_data.eeprom_data));
+ 
++	if (mac_addr) {
++		memcpy(ath79_wmac_mac, mac_addr, sizeof(ath79_wmac_mac));
++		ath79_wmac_data.macaddr = ath79_wmac_mac;
++	}
++
+ 	platform_device_register(&ath79_wmac_device);
+ }
+--- a/arch/mips/ath79/dev-wmac.h
++++ b/arch/mips/ath79/dev-wmac.h
+@@ -12,6 +12,6 @@
+ #ifndef _ATH79_DEV_WMAC_H
+ #define _ATH79_DEV_WMAC_H
+ 
+-void ath79_register_wmac(u8 *cal_data);
++void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
+ 
+ #endif /* _ATH79_DEV_WMAC_H */
+--- a/arch/mips/ath79/mach-ap81.c
++++ b/arch/mips/ath79/mach-ap81.c
+@@ -98,7 +98,7 @@ static void __init ap81_setup(void)
+ 					ap81_gpio_keys);
+ 	ath79_register_spi(&ap81_spi_data, ap81_spi_info,
+ 			   ARRAY_SIZE(ap81_spi_info));
+-	ath79_register_wmac(cal_data);
++	ath79_register_wmac(cal_data, NULL);
+ 	ath79_register_usb();
+ }
+ 
+--- a/arch/mips/ath79/mach-db120.c
++++ b/arch/mips/ath79/mach-db120.c
+@@ -134,7 +134,7 @@ static void __init db120_setup(void)
+ 	ath79_register_spi(&db120_spi_data, db120_spi_info,
+ 			   ARRAY_SIZE(db120_spi_info));
+ 	ath79_register_usb();
+-	ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET);
++	ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
+ 	db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
+ }
+ 
+--- a/arch/mips/ath79/mach-ap121.c
++++ b/arch/mips/ath79/mach-ap121.c
+@@ -91,7 +91,7 @@ static void __init ap121_setup(void)
+ 	ath79_register_spi(&ap121_spi_data, ap121_spi_info,
+ 			   ARRAY_SIZE(ap121_spi_info));
+ 	ath79_register_usb();
+-	ath79_register_wmac(cal_data);
++	ath79_register_wmac(cal_data, NULL);
+ }
+ 
+ MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/502-MIPS-ath79-export-ath79_gpio_base.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/502-MIPS-ath79-export-ath79_gpio_base.patch.svn-base
new file mode 100644
index 0000000..73eb8e1
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/502-MIPS-ath79-export-ath79_gpio_base.patch.svn-base
@@ -0,0 +1,23 @@
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -25,7 +25,9 @@
+ #include <asm/mach-ath79/ath79.h>
+ #include "common.h"
+ 
+-static void __iomem *ath79_gpio_base;
++void __iomem *ath79_gpio_base;
++EXPORT_SYMBOL_GPL(ath79_gpio_base);
++
+ static unsigned long ath79_gpio_count;
+ static DEFINE_SPINLOCK(ath79_gpio_lock);
+ 
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -116,6 +116,7 @@ static inline int soc_is_qca955x(void)
+ }
+ 
+ extern void __iomem *ath79_ddr_base;
++extern void __iomem *ath79_gpio_base;
+ extern void __iomem *ath79_pll_base;
+ extern void __iomem *ath79_reset_base;
+ 
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/503-MIPS-ath79-add-flash-acquire-release.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/503-MIPS-ath79-add-flash-acquire-release.patch.svn-base
new file mode 100644
index 0000000..06f7902
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/503-MIPS-ath79-add-flash-acquire-release.patch.svn-base
@@ -0,0 +1,37 @@
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -22,6 +22,7 @@
+ #include "common.h"
+ 
+ static DEFINE_SPINLOCK(ath79_device_reset_lock);
++static DEFINE_MUTEX(ath79_flash_mutex);
+ 
+ u32 ath79_cpu_freq;
+ EXPORT_SYMBOL_GPL(ath79_cpu_freq);
+@@ -111,3 +112,16 @@ void ath79_device_reset_clear(u32 mask)
+ 	spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
+ }
+ EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
++
++void ath79_flash_acquire(void)
++{
++	mutex_lock(&ath79_flash_mutex);
++}
++EXPORT_SYMBOL_GPL(ath79_flash_acquire);
++
++void ath79_flash_release(void)
++{
++	mutex_unlock(&ath79_flash_mutex);
++}
++EXPORT_SYMBOL_GPL(ath79_flash_release);
++
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -143,4 +143,7 @@ static inline u32 ath79_reset_rr(unsigne
+ void ath79_device_reset_set(u32 mask);
+ void ath79_device_reset_clear(u32 mask);
+ 
++void ath79_flash_acquire(void);
++void ath79_flash_release(void);
++
+ #endif /* __ASM_MACH_ATH79_H */
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/504-MIPS-ath79-add-ath79_device_reset_get.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/504-MIPS-ath79-add-ath79_device_reset_get.patch.svn-base
new file mode 100644
index 0000000..024a85d
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/504-MIPS-ath79-add-ath79_device_reset_get.patch.svn-base
@@ -0,0 +1,45 @@
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -142,6 +142,7 @@ static inline u32 ath79_reset_rr(unsigne
+ 
+ void ath79_device_reset_set(u32 mask);
+ void ath79_device_reset_clear(u32 mask);
++u32 ath79_device_reset_get(u32 mask);
+ 
+ void ath79_flash_acquire(void);
+ void ath79_flash_release(void);
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -113,6 +113,32 @@ void ath79_device_reset_clear(u32 mask)
+ }
+ EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
+ 
++u32 ath79_device_reset_get(u32 mask)
++{
++	unsigned long flags;
++	u32 reg;
++	u32 ret;
++
++	if (soc_is_ar71xx())
++		reg = AR71XX_RESET_REG_RESET_MODULE;
++	else if (soc_is_ar724x())
++		reg = AR724X_RESET_REG_RESET_MODULE;
++	else if (soc_is_ar913x())
++		reg = AR913X_RESET_REG_RESET_MODULE;
++	else if (soc_is_ar933x())
++		reg = AR933X_RESET_REG_RESET_MODULE;
++	else if (soc_is_ar934x())
++		reg = AR934X_RESET_REG_RESET_MODULE;
++	else
++		BUG();
++
++	spin_lock_irqsave(&ath79_device_reset_lock, flags);
++	ret = ath79_reset_rr(reg);
++	spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
++	return ret;
++}
++EXPORT_SYMBOL_GPL(ath79_device_reset_get);
++
+ void ath79_flash_acquire(void)
+ {
+ 	mutex_lock(&ath79_flash_mutex);
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/505-MIPS-ath79-add-ath79_gpio_function_select.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/505-MIPS-ath79-add-ath79_gpio_function_select.patch.svn-base
new file mode 100644
index 0000000..9e11381
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/505-MIPS-ath79-add-ath79_gpio_function_select.patch.svn-base
@@ -0,0 +1,47 @@
+--- a/arch/mips/ath79/common.h
++++ b/arch/mips/ath79/common.h
+@@ -26,6 +26,7 @@ void ath79_ddr_wb_flush(unsigned int reg
+ void ath79_gpio_function_enable(u32 mask);
+ void ath79_gpio_function_disable(u32 mask);
+ void ath79_gpio_function_setup(u32 set, u32 clear);
++void ath79_gpio_output_select(unsigned gpio, u8 val);
+ void ath79_gpio_init(void);
+ 
+ #endif /* __ATH79_COMMON_H */
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -180,6 +180,34 @@ void ath79_gpio_function_disable(u32 mas
+ 	ath79_gpio_function_setup(0, mask);
+ }
+ 
++void __init ath79_gpio_output_select(unsigned gpio, u8 val)
++{
++	void __iomem *base = ath79_gpio_base;
++	unsigned long flags;
++	unsigned int reg;
++	u32 t, s;
++
++	BUG_ON(!soc_is_ar934x());
++
++	if (gpio >= AR934X_GPIO_COUNT)
++		return;
++
++	reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4);
++	s = 8 * (gpio % 4);
++
++	spin_lock_irqsave(&ath79_gpio_lock, flags);
++
++	t = __raw_readl(base + reg);
++	t &= ~(0xff << s);
++	t |= val << s;
++	__raw_writel(t, base + reg);
++
++	/* flush write */
++	(void) __raw_readl(base + reg);
++
++	spin_unlock_irqrestore(&ath79_gpio_lock, flags);
++}
++
+ void __init ath79_gpio_init(void)
+ {
+ 	int err;
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/506-MIPS-ath79-prom-parse-redboot-args.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/506-MIPS-ath79-prom-parse-redboot-args.patch.svn-base
new file mode 100644
index 0000000..aab959b
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/506-MIPS-ath79-prom-parse-redboot-args.patch.svn-base
@@ -0,0 +1,86 @@
+--- a/arch/mips/ath79/prom.c
++++ b/arch/mips/ath79/prom.c
+@@ -19,6 +19,8 @@
+ 
+ #include "common.h"
+ 
++static char ath79_cmdline_buf[COMMAND_LINE_SIZE] __initdata;
++
+ static inline int is_valid_ram_addr(void *addr)
+ {
+ 	if (((u32) addr > KSEG0) &&
+@@ -32,6 +34,41 @@ static inline int is_valid_ram_addr(void
+ 	return 0;
+ }
+ 
++static void __init ath79_prom_append_cmdline(const char *name,
++					      const char *value)
++{
++	snprintf(ath79_cmdline_buf, sizeof(ath79_cmdline_buf),
++		 " %s=%s", name, value);
++	strlcat(arcs_cmdline, ath79_cmdline_buf, sizeof(arcs_cmdline));
++}
++
++static const char * __init ath79_prom_find_env(char **envp, const char *name)
++{
++	const char *ret = NULL;
++	int len;
++	char **p;
++
++	if (!is_valid_ram_addr(envp))
++		return NULL;
++
++	len = strlen(name);
++	for (p = envp; is_valid_ram_addr(*p); p++) {
++		if (strncmp(name, *p, len) == 0 && (*p)[len] == '=') {
++			ret = *p + len + 1;
++			break;
++		}
++
++		/* RedBoot env comes in pointer pairs - key, value */
++		if (strncmp(name, *p, len) == 0 && (*p)[len] == 0)
++			if (is_valid_ram_addr(*(++p))) {
++				ret = *p;
++				break;
++			}
++	}
++
++	return ret;
++}
++
+ static __init void ath79_prom_init_cmdline(int argc, char **argv)
+ {
+ 	int i;
+@@ -48,7 +85,32 @@ static __init void ath79_prom_init_cmdli
+ 
+ void __init prom_init(void)
+ {
++	const char *env;
++	char **envp;
++
+ 	ath79_prom_init_cmdline(fw_arg0, (char **)fw_arg1);
++
++	envp = (char **)fw_arg2;
++	if (!strstr(arcs_cmdline, "ethaddr=")) {
++		env = ath79_prom_find_env(envp, "ethaddr");
++		if (env)
++			ath79_prom_append_cmdline("ethaddr", env);
++	}
++
++	if (!strstr(arcs_cmdline, "board=")) {
++		env = ath79_prom_find_env(envp, "board");
++		if (env) {
++			/* Workaround for buggy bootloaders */
++			if (strcmp(env, "RouterStation") == 0 ||
++			    strcmp(env, "Ubiquiti AR71xx-based board") == 0)
++				env = "UBNT-RS";
++
++			if (strcmp(env, "RouterStation PRO") == 0)
++				env = "UBNT-RSPRO";
++
++			ath79_prom_append_cmdline("board", env);
++		}
++	}
+ }
+ 
+ void __init prom_free_prom_memory(void)
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/507-MIPS-ath79-prom-add-myloader-support.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/507-MIPS-ath79-prom-add-myloader-support.patch.svn-base
new file mode 100644
index 0000000..67c1faf
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/507-MIPS-ath79-prom-add-myloader-support.patch.svn-base
@@ -0,0 +1,58 @@
+--- a/arch/mips/ath79/prom.c
++++ b/arch/mips/ath79/prom.c
+@@ -16,6 +16,7 @@
+ 
+ #include <asm/bootinfo.h>
+ #include <asm/addrspace.h>
++#include <asm/fw/myloader/myloader.h>
+ 
+ #include "common.h"
+ 
+@@ -69,6 +70,37 @@ static const char * __init ath79_prom_fi
+ 	return ret;
+ }
+ 
++static int __init ath79_prom_init_myloader(void)
++{
++	struct myloader_info *mylo;
++	char mac_buf[32];
++	unsigned char *mac;
++
++	mylo = myloader_get_info();
++	if (!mylo)
++		return 0;
++
++	switch (mylo->did) {
++	case DEVID_COMPEX_WP543:
++		ath79_prom_append_cmdline("board", "WP543");
++		break;
++	case DEVID_COMPEX_WPE72:
++		ath79_prom_append_cmdline("board", "WPE72");
++		break;
++	default:
++		pr_warn("prom: unknown device id: %x\n", mylo->did);
++		return 0;
++	}
++
++	mac = mylo->macs[0];
++	snprintf(mac_buf, sizeof(mac_buf), "%02x:%02x:%02x:%02x:%02x:%02x",
++		 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
++
++	ath79_prom_append_cmdline("ethaddr", mac_buf);
++
++	return 1;
++}
++
+ static __init void ath79_prom_init_cmdline(int argc, char **argv)
+ {
+ 	int i;
+@@ -88,6 +120,9 @@ void __init prom_init(void)
+ 	const char *env;
+ 	char **envp;
+ 
++	if (ath79_prom_init_myloader())
++		return;
++
+ 	ath79_prom_init_cmdline(fw_arg0, (char **)fw_arg1);
+ 
+ 	envp = (char **)fw_arg2;
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/508-MIPS-ath79-prom-image-command-line-hack.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/508-MIPS-ath79-prom-image-command-line-hack.patch.svn-base
new file mode 100644
index 0000000..72a3b56
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/508-MIPS-ath79-prom-image-command-line-hack.patch.svn-base
@@ -0,0 +1,57 @@
+--- a/arch/mips/ath79/prom.c
++++ b/arch/mips/ath79/prom.c
+@@ -70,6 +70,35 @@ static const char * __init ath79_prom_fi
+ 	return ret;
+ }
+ 
++#ifdef CONFIG_IMAGE_CMDLINE_HACK
++extern char __image_cmdline[];
++
++static int __init ath79_use_image_cmdline(void)
++{
++	char *p = __image_cmdline;
++	int replace = 0;
++
++	if (*p == '-') {
++		replace = 1;
++		p++;
++	}
++
++	if (*p == '\0')
++		return 0;
++
++	if (replace) {
++		strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline));
++	} else {
++		strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
++		strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
++	}
++
++	return 1;
++}
++#else
++static inline int ath79_use_image_cmdline(void) { return 0; }
++#endif
++
+ static int __init ath79_prom_init_myloader(void)
+ {
+ 	struct myloader_info *mylo;
+@@ -98,6 +127,8 @@ static int __init ath79_prom_init_myload
+ 
+ 	ath79_prom_append_cmdline("ethaddr", mac_buf);
+ 
++	ath79_use_image_cmdline();
++
+ 	return 1;
+ }
+ 
+@@ -105,6 +136,9 @@ static __init void ath79_prom_init_cmdli
+ {
+ 	int i;
+ 
++	if (ath79_use_image_cmdline())
++		return;
++
+ 	if (!is_valid_ram_addr(argv))
+ 		return;
+ 
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/509-MIPS-ath79-process-board-kernel-option.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/509-MIPS-ath79-process-board-kernel-option.patch.svn-base
new file mode 100644
index 0000000..7858a90
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/509-MIPS-ath79-process-board-kernel-option.patch.svn-base
@@ -0,0 +1,11 @@
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -231,6 +231,8 @@ void __init plat_time_init(void)
+ 	mips_hpt_frequency = clk_get_rate(clk) / 2;
+ }
+ 
++__setup("board=", mips_machtype_setup);
++
+ static int __init ath79_setup(void)
+ {
+ 	ath79_gpio_init();
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch.svn-base
new file mode 100644
index 0000000..2d2235e
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch.svn-base
@@ -0,0 +1,14 @@
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -24,7 +24,10 @@
+ #include "dev-wmac.h"
+ 
+ static u8 ath79_wmac_mac[ETH_ALEN];
+-static struct ath9k_platform_data ath79_wmac_data;
++
++static struct ath9k_platform_data ath79_wmac_data = {
++	.led_pin = -1,
++};
+ 
+ static struct resource ath79_wmac_resources[] = {
+ 	{
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/520-MIPS-ath79-enable-UART-function.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/520-MIPS-ath79-enable-UART-function.patch.svn-base
new file mode 100644
index 0000000..1cb407f
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/520-MIPS-ath79-enable-UART-function.patch.svn-base
@@ -0,0 +1,18 @@
+--- a/arch/mips/ath79/dev-common.c
++++ b/arch/mips/ath79/dev-common.c
+@@ -87,6 +87,15 @@ void __init ath79_register_uart(void)
+ 	if (IS_ERR(clk))
+ 		panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
+ 
++	if (soc_is_ar71xx())
++		ath79_gpio_function_enable(AR71XX_GPIO_FUNC_UART_EN);
++	else if (soc_is_ar724x())
++		ath79_gpio_function_enable(AR724X_GPIO_FUNC_UART_EN);
++	else if (soc_is_ar913x())
++		ath79_gpio_function_enable(AR913X_GPIO_FUNC_UART_EN);
++	else if (soc_is_ar933x())
++		ath79_gpio_function_enable(AR933X_GPIO_FUNC_UART_EN);
++
+ 	if (soc_is_ar71xx() ||
+ 	    soc_is_ar724x() ||
+ 	    soc_is_ar913x() ||
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/521-MIPS-ath79-enable-UART-for-early_serial.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/521-MIPS-ath79-enable-UART-for-early_serial.patch.svn-base
new file mode 100644
index 0000000..3d6ddfe
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/521-MIPS-ath79-enable-UART-for-early_serial.patch.svn-base
@@ -0,0 +1,61 @@
+--- a/arch/mips/ath79/early_printk.c
++++ b/arch/mips/ath79/early_printk.c
+@@ -56,6 +56,46 @@ static void prom_putchar_dummy(unsigned
+ 	/* nothing to do */
+ }
+ 
++static void prom_enable_uart(u32 id)
++{
++	void __iomem *gpio_base;
++	u32 uart_en;
++	u32 t;
++
++	switch (id) {
++	case REV_ID_MAJOR_AR71XX:
++		uart_en = AR71XX_GPIO_FUNC_UART_EN;
++		break;
++
++	case REV_ID_MAJOR_AR7240:
++	case REV_ID_MAJOR_AR7241:
++	case REV_ID_MAJOR_AR7242:
++		uart_en = AR724X_GPIO_FUNC_UART_EN;
++		break;
++
++	case REV_ID_MAJOR_AR913X:
++		uart_en = AR913X_GPIO_FUNC_UART_EN;
++		break;
++
++	case REV_ID_MAJOR_AR9330:
++	case REV_ID_MAJOR_AR9331:
++		uart_en = AR933X_GPIO_FUNC_UART_EN;
++		break;
++
++	case REV_ID_MAJOR_AR9341:
++	case REV_ID_MAJOR_AR9342:
++	case REV_ID_MAJOR_AR9344:
++		/* TODO */
++	default:
++		return;
++	}
++
++	gpio_base = (void __iomem *)(KSEG1ADDR(AR71XX_GPIO_BASE));
++	t = __raw_readl(gpio_base + AR71XX_GPIO_REG_FUNC);
++	t |= uart_en;
++	__raw_writel(t, gpio_base + AR71XX_GPIO_REG_FUNC);
++}
++
+ static void prom_putchar_init(void)
+ {
+ 	void __iomem *base;
+@@ -86,8 +126,10 @@ static void prom_putchar_init(void)
+ 
+ 	default:
+ 		_prom_putchar = prom_putchar_dummy;
+-		break;
++		return;
+ 	}
++
++	prom_enable_uart(id);
+ }
+ 
+ void prom_putchar(unsigned char ch)
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch.svn-base
new file mode 100644
index 0000000..74309b6
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch.svn-base
@@ -0,0 +1,21 @@
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -180,3 +180,9 @@ void __init ath79_register_wmac(u8 *cal_
+ 
+ 	platform_device_register(&ath79_wmac_device);
+ }
++
++void __init ath79_register_wmac_simple(void)
++{
++	ath79_register_wmac(NULL, NULL);
++	ath79_wmac_data.eeprom_name = "soc_wmac.eeprom";
++}
+--- a/arch/mips/ath79/dev-wmac.h
++++ b/arch/mips/ath79/dev-wmac.h
+@@ -13,5 +13,6 @@
+ #define _ATH79_DEV_WMAC_H
+ 
+ void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
++void ath79_register_wmac_simple(void);
+ 
+ #endif /* _ATH79_DEV_WMAC_H */
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/523-MIPS-ath79-OTP-support.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/523-MIPS-ath79-OTP-support.patch.svn-base
new file mode 100644
index 0000000..84273d3
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/523-MIPS-ath79-OTP-support.patch.svn-base
@@ -0,0 +1,166 @@
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -156,6 +156,137 @@ static void qca955x_wmac_setup(void)
+ 		ath79_wmac_data.is_clk_25mhz = true;
+ }
+ 
++static bool __init
++ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
++{
++	int timeout = 1000;
++	u32 val;
++
++	__raw_readl(base + AR9300_OTP_BASE + (4 * addr));
++	while (timeout--) {
++		val = __raw_readl(base + AR9300_OTP_STATUS);
++		if ((val & AR9300_OTP_STATUS_TYPE) == AR9300_OTP_STATUS_VALID)
++			break;
++
++		udelay(10);
++	}
++
++	if (!timeout)
++		return false;
++
++	*data = __raw_readl(base + AR9300_OTP_READ_DATA);
++	return true;
++}
++
++static bool __init
++ar93xx_wmac_otp_read(void __iomem *base, int addr, u8 *dest, int len)
++{
++	u32 data;
++	int i;
++
++	for (i = 0; i < len; i++) {
++		int offset = 8 * ((addr - i) % 4);
++
++		if (!ar93xx_wmac_otp_read_word(base, (addr - i) / 4, &data))
++			return false;
++
++		dest[i] = (data >> offset) & 0xff;
++	}
++
++	return true;
++}
++
++static bool __init
++ar93xx_wmac_otp_uncompress(void __iomem *base, int addr, int len, u8 *dest,
++			   int dest_start, int dest_len)
++{
++	int dest_bytes = 0;
++	int offset = 0;
++	int end = addr - len;
++	u8 hdr[2];
++
++	while (addr > end) {
++		if (!ar93xx_wmac_otp_read(base, addr, hdr, 2))
++			return false;
++
++		addr -= 2;
++		offset += hdr[0];
++
++		if (offset <= dest_start + dest_len &&
++		    offset + len >= dest_start) {
++			int data_offset = 0;
++			int dest_offset = 0;
++			int copy_len;
++
++			if (offset < dest_start)
++				data_offset = dest_start - offset;
++			else
++				dest_offset = offset - dest_start;
++
++			copy_len = len - data_offset;
++			if (copy_len > dest_len - dest_offset)
++				copy_len = dest_len - dest_offset;
++
++			ar93xx_wmac_otp_read(base, addr - data_offset,
++					     dest + dest_offset,
++					     copy_len);
++
++			dest_bytes += copy_len;
++		}
++		addr -= hdr[1];
++	}
++	return !!dest_bytes;
++}
++
++bool __init ar93xx_wmac_read_mac_address(u8 *dest)
++{
++	void __iomem *base;
++	bool ret = false;
++	int addr = 0x1ff;
++	unsigned int len;
++	u32 hdr_u32;
++	u8 *hdr = (u8 *) &hdr_u32;
++	u8 mac[6] = { 0x00, 0x02, 0x03, 0x04, 0x05, 0x06 };
++	int mac_start = 2, mac_end = 8;
++
++	BUG_ON(!soc_is_ar933x() && !soc_is_ar934x());
++	base = ioremap_nocache(AR933X_WMAC_BASE, AR933X_WMAC_SIZE);
++	while (addr > sizeof(hdr)) {
++		if (!ar93xx_wmac_otp_read(base, addr, hdr, sizeof(hdr)))
++			break;
++
++		if (hdr_u32 == 0 || hdr_u32 == ~0)
++			break;
++
++		len = (hdr[1] << 4) | (hdr[2] >> 4);
++		addr -= 4;
++
++		switch (hdr[0] >> 5) {
++		case 0:
++			if (len < mac_end)
++				break;
++
++			ar93xx_wmac_otp_read(base, addr - mac_start, mac, 6);
++			ret = true;
++			break;
++		case 3:
++			ret |= ar93xx_wmac_otp_uncompress(base, addr, len, mac,
++							  mac_start, 6);
++			break;
++		default:
++			break;
++		}
++
++		addr -= len + 2;
++	}
++
++	iounmap(base);
++	if (ret)
++		memcpy(dest, mac, 6);
++
++	return ret;
++}
++
+ void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
+ {
+ 	if (soc_is_ar913x())
+--- a/arch/mips/ath79/dev-wmac.h
++++ b/arch/mips/ath79/dev-wmac.h
+@@ -14,5 +14,6 @@
+ 
+ void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
+ void ath79_register_wmac_simple(void);
++bool ar93xx_wmac_read_mac_address(u8 *dest);
+ 
+ #endif /* _ATH79_DEV_WMAC_H */
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -113,6 +113,14 @@
+ #define QCA955X_EHCI1_BASE	0x1b400000
+ #define QCA955X_EHCI_SIZE	0x1000
+ 
++#define AR9300_OTP_BASE		0x14000
++#define AR9300_OTP_STATUS	0x15f18
++#define AR9300_OTP_STATUS_TYPE		0x7
++#define AR9300_OTP_STATUS_VALID		0x4
++#define AR9300_OTP_STATUS_ACCESS_BUSY	0x2
++#define AR9300_OTP_STATUS_SM_BUSY	0x1
++#define AR9300_OTP_READ_DATA	0x15f1c
++
+ /*
+  * DDR_CTRL block
+  */
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch.svn-base
new file mode 100644
index 0000000..8c6fd40
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch.svn-base
@@ -0,0 +1,31 @@
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -287,6 +287,16 @@ bool __init ar93xx_wmac_read_mac_address
+ 	return ret;
+ }
+ 
++void __init ath79_wmac_disable_2ghz(void)
++{
++	ath79_wmac_data.disable_2ghz = true;
++}
++
++void __init ath79_wmac_disable_5ghz(void)
++{
++	ath79_wmac_data.disable_5ghz = true;
++}
++
+ void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
+ {
+ 	if (soc_is_ar913x())
+--- a/arch/mips/ath79/dev-wmac.h
++++ b/arch/mips/ath79/dev-wmac.h
+@@ -14,6 +14,9 @@
+ 
+ void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
+ void ath79_register_wmac_simple(void);
++void ath79_wmac_disable_2ghz(void);
++void ath79_wmac_disable_5ghz(void);
++
+ bool ar93xx_wmac_read_mac_address(u8 *dest);
+ 
+ #endif /* _ATH79_DEV_WMAC_H */
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/601-MIPS-ath79-add-more-register-defines.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/601-MIPS-ath79-add-more-register-defines.patch.svn-base
new file mode 100644
index 0000000..d9cdc9f
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/601-MIPS-ath79-add-more-register-defines.patch.svn-base
@@ -0,0 +1,349 @@
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -21,6 +21,10 @@
+ #include <linux/bitops.h>
+ 
+ #define AR71XX_APB_BASE		0x18000000
++#define AR71XX_GE0_BASE		0x19000000
++#define AR71XX_GE0_SIZE		0x10000
++#define AR71XX_GE1_BASE		0x1a000000
++#define AR71XX_GE1_SIZE		0x10000
+ #define AR71XX_EHCI_BASE	0x1b000000
+ #define AR71XX_EHCI_SIZE	0x1000
+ #define AR71XX_OHCI_BASE	0x1c000000
+@@ -40,6 +44,8 @@
+ #define AR71XX_PLL_SIZE		0x100
+ #define AR71XX_RESET_BASE	(AR71XX_APB_BASE + 0x00060000)
+ #define AR71XX_RESET_SIZE	0x100
++#define AR71XX_MII_BASE		(AR71XX_APB_BASE + 0x00070000)
++#define AR71XX_MII_SIZE		0x100
+ 
+ #define AR71XX_PCI_MEM_BASE	0x10000000
+ #define AR71XX_PCI_MEM_SIZE	0x07000000
+@@ -82,15 +88,21 @@
+ 
+ #define AR933X_UART_BASE	(AR71XX_APB_BASE + 0x00020000)
+ #define AR933X_UART_SIZE	0x14
++#define AR933X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
++#define AR933X_GMAC_SIZE	0x04
+ #define AR933X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+ #define AR933X_WMAC_SIZE	0x20000
+ #define AR933X_EHCI_BASE	0x1b000000
+ #define AR933X_EHCI_SIZE	0x1000
+ 
++#define AR934X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
++#define AR934X_GMAC_SIZE	0x14
+ #define AR934X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+ #define AR934X_WMAC_SIZE	0x20000
+ #define AR934X_EHCI_BASE	0x1b000000
+ #define AR934X_EHCI_SIZE	0x200
++#define AR934X_NFC_BASE		0x1b000200
++#define AR934X_NFC_SIZE		0xb8
+ #define AR934X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
+ #define AR934X_SRIF_SIZE	0x1000
+ 
+@@ -107,11 +119,15 @@
+ #define QCA955X_PCI_CTRL_BASE1	(AR71XX_APB_BASE + 0x00280000)
+ #define QCA955X_PCI_CTRL_SIZE	0x100
+ 
++#define QCA955X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
++#define QCA955X_GMAC_SIZE	0x40
+ #define QCA955X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+ #define QCA955X_WMAC_SIZE	0x20000
+ #define QCA955X_EHCI0_BASE	0x1b000000
+ #define QCA955X_EHCI1_BASE	0x1b400000
+ #define QCA955X_EHCI_SIZE	0x1000
++#define QCA955X_NFC_BASE	0x1b800200
++#define QCA955X_NFC_SIZE	0xb8
+ 
+ #define AR9300_OTP_BASE		0x14000
+ #define AR9300_OTP_STATUS	0x15f18
+@@ -175,6 +191,9 @@
+ #define AR71XX_AHB_DIV_SHIFT		20
+ #define AR71XX_AHB_DIV_MASK		0x7
+ 
++#define AR71XX_ETH0_PLL_SHIFT		17
++#define AR71XX_ETH1_PLL_SHIFT		19
++
+ #define AR724X_PLL_REG_CPU_CONFIG	0x00
+ #define AR724X_PLL_REG_PCIE_CONFIG	0x18
+ 
+@@ -187,6 +206,8 @@
+ #define AR724X_DDR_DIV_SHIFT		22
+ #define AR724X_DDR_DIV_MASK		0x3
+ 
++#define AR7242_PLL_REG_ETH0_INT_CLOCK	0x2c
++
+ #define AR913X_PLL_REG_CPU_CONFIG	0x00
+ #define AR913X_PLL_REG_ETH_CONFIG	0x04
+ #define AR913X_PLL_REG_ETH0_INT_CLOCK	0x14
+@@ -199,6 +220,9 @@
+ #define AR913X_AHB_DIV_SHIFT		19
+ #define AR913X_AHB_DIV_MASK		0x1
+ 
++#define AR913X_ETH0_PLL_SHIFT		20
++#define AR913X_ETH1_PLL_SHIFT		22
++
+ #define AR933X_PLL_CPU_CONFIG_REG	0x00
+ #define AR933X_PLL_CLOCK_CTRL_REG	0x08
+ 
+@@ -220,6 +244,8 @@
+ #define AR934X_PLL_CPU_CONFIG_REG		0x00
+ #define AR934X_PLL_DDR_CONFIG_REG		0x04
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG		0x08
++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG	0x24
++#define AR934X_PLL_ETH_XMII_CONTROL_REG		0x2c
+ 
+ #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
+ #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
+@@ -252,9 +278,13 @@
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL	BIT(21)
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL	BIT(24)
+ 
++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL	BIT(6)
++
+ #define QCA955X_PLL_CPU_CONFIG_REG		0x00
+ #define QCA955X_PLL_DDR_CONFIG_REG		0x04
+ #define QCA955X_PLL_CLK_CTRL_REG		0x08
++#define QCA955X_PLL_ETH_XMII_CONTROL_REG	0x28
++#define QCA955X_PLL_ETH_SGMII_CONTROL_REG	0x48
+ 
+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
+@@ -379,16 +409,83 @@
+ #define AR913X_RESET_USB_HOST		BIT(5)
+ #define AR913X_RESET_USB_PHY		BIT(4)
+ 
++#define AR933X_RESET_GE1_MDIO		BIT(23)
++#define AR933X_RESET_GE0_MDIO		BIT(22)
++#define AR933X_RESET_GE1_MAC		BIT(13)
+ #define AR933X_RESET_WMAC		BIT(11)
++#define AR933X_RESET_GE0_MAC		BIT(9)
+ #define AR933X_RESET_USB_HOST		BIT(5)
+ #define AR933X_RESET_USB_PHY		BIT(4)
+ #define AR933X_RESET_USBSUS_OVERRIDE	BIT(3)
+ 
++#define AR934X_RESET_HOST		BIT(31)
++#define AR934X_RESET_SLIC		BIT(30)
++#define AR934X_RESET_HDMA		BIT(29)
++#define AR934X_RESET_EXTERNAL		BIT(28)
++#define AR934X_RESET_RTC		BIT(27)
++#define AR934X_RESET_PCIE_EP_INT	BIT(26)
++#define AR934X_RESET_CHKSUM_ACC		BIT(25)
++#define AR934X_RESET_FULL_CHIP		BIT(24)
++#define AR934X_RESET_GE1_MDIO		BIT(23)
++#define AR934X_RESET_GE0_MDIO		BIT(22)
++#define AR934X_RESET_CPU_NMI		BIT(21)
++#define AR934X_RESET_CPU_COLD		BIT(20)
++#define AR934X_RESET_HOST_RESET_INT	BIT(19)
++#define AR934X_RESET_PCIE_EP		BIT(18)
++#define AR934X_RESET_UART1		BIT(17)
++#define AR934X_RESET_DDR		BIT(16)
++#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
++#define AR934X_RESET_NANDF		BIT(14)
++#define AR934X_RESET_GE1_MAC		BIT(13)
++#define AR934X_RESET_ETH_SWITCH_ANALOG	BIT(12)
+ #define AR934X_RESET_USB_PHY_ANALOG	BIT(11)
++#define AR934X_RESET_HOST_DMA_INT	BIT(10)
++#define AR934X_RESET_GE0_MAC		BIT(9)
++#define AR934X_RESET_ETH_SWITCH		BIT(8)
++#define AR934X_RESET_PCIE_PHY		BIT(7)
++#define AR934X_RESET_PCIE		BIT(6)
+ #define AR934X_RESET_USB_HOST		BIT(5)
+ #define AR934X_RESET_USB_PHY		BIT(4)
+ #define AR934X_RESET_USBSUS_OVERRIDE	BIT(3)
++#define AR934X_RESET_LUT		BIT(2)
++#define AR934X_RESET_MBOX		BIT(1)
++#define AR934X_RESET_I2S		BIT(0)
++
++#define QCA955X_RESET_HOST		BIT(31)
++#define QCA955X_RESET_SLIC		BIT(30)
++#define QCA955X_RESET_HDMA		BIT(29)
++#define QCA955X_RESET_EXTERNAL		BIT(28)
++#define QCA955X_RESET_RTC		BIT(27)
++#define QCA955X_RESET_PCIE_EP_INT	BIT(26)
++#define QCA955X_RESET_CHKSUM_ACC	BIT(25)
++#define QCA955X_RESET_FULL_CHIP		BIT(24)
++#define QCA955X_RESET_GE1_MDIO		BIT(23)
++#define QCA955X_RESET_GE0_MDIO		BIT(22)
++#define QCA955X_RESET_CPU_NMI		BIT(21)
++#define QCA955X_RESET_CPU_COLD		BIT(20)
++#define QCA955X_RESET_HOST_RESET_INT	BIT(19)
++#define QCA955X_RESET_PCIE_EP		BIT(18)
++#define QCA955X_RESET_UART1		BIT(17)
++#define QCA955X_RESET_DDR		BIT(16)
++#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
++#define QCA955X_RESET_NANDF		BIT(14)
++#define QCA955X_RESET_GE1_MAC		BIT(13)
++#define QCA955X_RESET_SGMII_ANALOG	BIT(12)
++#define QCA955X_RESET_USB_PHY_ANALOG	BIT(11)
++#define QCA955X_RESET_HOST_DMA_INT	BIT(10)
++#define QCA955X_RESET_GE0_MAC		BIT(9)
++#define QCA955X_RESET_SGMII		BIT(8)
++#define QCA955X_RESET_PCIE_PHY		BIT(7)
++#define QCA955X_RESET_PCIE		BIT(6)
++#define QCA955X_RESET_USB_HOST		BIT(5)
++#define QCA955X_RESET_USB_PHY		BIT(4)
++#define QCA955X_RESET_USBSUS_OVERRIDE	BIT(3)
++#define QCA955X_RESET_LUT		BIT(2)
++#define QCA955X_RESET_MBOX		BIT(1)
++#define QCA955X_RESET_I2S		BIT(0)
+ 
++#define AR933X_BOOTSTRAP_MDIO_GPIO_EN	BIT(18)
++#define AR933X_BOOTSTRAP_EEPBUSY	BIT(4)
+ #define AR933X_BOOTSTRAP_REF_CLK_40	BIT(0)
+ 
+ #define AR934X_BOOTSTRAP_SW_OPTION8	BIT(23)
+@@ -530,6 +627,12 @@
+ #define AR71XX_GPIO_REG_INT_ENABLE	0x24
+ #define AR71XX_GPIO_REG_FUNC		0x28
+ 
++#define AR934X_GPIO_REG_OUT_FUNC0	0x2c
++#define AR934X_GPIO_REG_OUT_FUNC1	0x30
++#define AR934X_GPIO_REG_OUT_FUNC2	0x34
++#define AR934X_GPIO_REG_OUT_FUNC3	0x38
++#define AR934X_GPIO_REG_OUT_FUNC4	0x3c
++#define AR934X_GPIO_REG_OUT_FUNC5	0x40
+ #define AR934X_GPIO_REG_FUNC		0x6c
+ 
+ #define AR71XX_GPIO_COUNT		16
+@@ -561,4 +664,139 @@
+ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT	13
+ #define AR934X_SRIF_DPLL2_OUTDIV_MASK	0x7
+ 
++#define AR71XX_GPIO_FUNC_STEREO_EN		BIT(17)
++#define AR71XX_GPIO_FUNC_SLIC_EN		BIT(16)
++#define AR71XX_GPIO_FUNC_SPI_CS2_EN		BIT(13)
++#define AR71XX_GPIO_FUNC_SPI_CS1_EN		BIT(12)
++#define AR71XX_GPIO_FUNC_UART_EN		BIT(8)
++#define AR71XX_GPIO_FUNC_USB_OC_EN		BIT(4)
++#define AR71XX_GPIO_FUNC_USB_CLK_EN		BIT(0)
++
++#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN		BIT(19)
++#define AR724X_GPIO_FUNC_SPI_EN			BIT(18)
++#define AR724X_GPIO_FUNC_SPI_CS_EN2		BIT(14)
++#define AR724X_GPIO_FUNC_SPI_CS_EN1		BIT(13)
++#define AR724X_GPIO_FUNC_CLK_OBS5_EN		BIT(12)
++#define AR724X_GPIO_FUNC_CLK_OBS4_EN		BIT(11)
++#define AR724X_GPIO_FUNC_CLK_OBS3_EN		BIT(10)
++#define AR724X_GPIO_FUNC_CLK_OBS2_EN		BIT(9)
++#define AR724X_GPIO_FUNC_CLK_OBS1_EN		BIT(8)
++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN	BIT(7)
++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN	BIT(6)
++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN	BIT(5)
++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN	BIT(4)
++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN	BIT(3)
++#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN	BIT(2)
++#define AR724X_GPIO_FUNC_UART_EN		BIT(1)
++#define AR724X_GPIO_FUNC_JTAG_DISABLE		BIT(0)
++
++#define AR913X_GPIO_FUNC_WMAC_LED_EN		BIT(22)
++#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN		BIT(21)
++#define AR913X_GPIO_FUNC_I2S_REFCLKEN		BIT(20)
++#define AR913X_GPIO_FUNC_I2S_MCKEN		BIT(19)
++#define AR913X_GPIO_FUNC_I2S1_EN		BIT(18)
++#define AR913X_GPIO_FUNC_I2S0_EN		BIT(17)
++#define AR913X_GPIO_FUNC_SLIC_EN		BIT(16)
++#define AR913X_GPIO_FUNC_UART_RTSCTS_EN		BIT(9)
++#define AR913X_GPIO_FUNC_UART_EN		BIT(8)
++#define AR913X_GPIO_FUNC_USB_CLK_EN		BIT(4)
++
++#define AR933X_GPIO_FUNC_SPDIF2TCK		BIT(31)
++#define AR933X_GPIO_FUNC_SPDIF_EN		BIT(30)
++#define AR933X_GPIO_FUNC_I2SO_22_18_EN		BIT(29)
++#define AR933X_GPIO_FUNC_I2S_MCK_EN		BIT(27)
++#define AR933X_GPIO_FUNC_I2SO_EN		BIT(26)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL	BIT(25)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL	BIT(24)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT	BIT(23)
++#define AR933X_GPIO_FUNC_SPI_EN			BIT(18)
++#define AR933X_GPIO_FUNC_SPI_CS_EN2		BIT(14)
++#define AR933X_GPIO_FUNC_SPI_CS_EN1		BIT(13)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN	BIT(7)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN	BIT(6)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN	BIT(5)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN	BIT(4)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN	BIT(3)
++#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN	BIT(2)
++#define AR933X_GPIO_FUNC_UART_EN		BIT(1)
++#define AR933X_GPIO_FUNC_JTAG_DISABLE		BIT(0)
++
++#define AR934X_GPIO_FUNC_CLK_OBS7_EN		BIT(9)
++#define AR934X_GPIO_FUNC_CLK_OBS6_EN		BIT(8)
++#define AR934X_GPIO_FUNC_CLK_OBS5_EN		BIT(7)
++#define AR934X_GPIO_FUNC_CLK_OBS4_EN		BIT(6)
++#define AR934X_GPIO_FUNC_CLK_OBS3_EN		BIT(5)
++#define AR934X_GPIO_FUNC_CLK_OBS2_EN		BIT(4)
++#define AR934X_GPIO_FUNC_CLK_OBS1_EN		BIT(3)
++#define AR934X_GPIO_FUNC_CLK_OBS0_EN		BIT(2)
++#define AR934X_GPIO_FUNC_JTAG_DISABLE		BIT(1)
++
++#define AR934X_GPIO_OUT_GPIO		0x00
++
++/*
++ * MII_CTRL block
++ */
++#define AR71XX_MII_REG_MII0_CTRL	0x00
++#define AR71XX_MII_REG_MII1_CTRL	0x04
++
++#define AR71XX_MII_CTRL_IF_MASK		3
++#define AR71XX_MII_CTRL_SPEED_SHIFT	4
++#define AR71XX_MII_CTRL_SPEED_MASK	3
++#define AR71XX_MII_CTRL_SPEED_10	0
++#define AR71XX_MII_CTRL_SPEED_100	1
++#define AR71XX_MII_CTRL_SPEED_1000	2
++
++#define AR71XX_MII0_CTRL_IF_GMII	0
++#define AR71XX_MII0_CTRL_IF_MII		1
++#define AR71XX_MII0_CTRL_IF_RGMII	2
++#define AR71XX_MII0_CTRL_IF_RMII	3
++
++#define AR71XX_MII1_CTRL_IF_RGMII	0
++#define AR71XX_MII1_CTRL_IF_RMII	1
++
++/*
++ * AR933X GMAC interface
++ */
++#define AR933X_GMAC_REG_ETH_CFG		0x00
++
++#define AR933X_ETH_CFG_RGMII_GE0	BIT(0)
++#define AR933X_ETH_CFG_MII_GE0		BIT(1)
++#define AR933X_ETH_CFG_GMII_GE0		BIT(2)
++#define AR933X_ETH_CFG_MII_GE0_MASTER	BIT(3)
++#define AR933X_ETH_CFG_MII_GE0_SLAVE	BIT(4)
++#define AR933X_ETH_CFG_MII_GE0_ERR_EN	BIT(5)
++#define AR933X_ETH_CFG_SW_PHY_SWAP	BIT(7)
++#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP	BIT(8)
++#define AR933X_ETH_CFG_RMII_GE0		BIT(9)
++#define AR933X_ETH_CFG_RMII_GE0_SPD_10	0
++#define AR933X_ETH_CFG_RMII_GE0_SPD_100	BIT(10)
++
++/*
++ * AR934X GMAC Interface
++ */
++#define AR934X_GMAC_REG_ETH_CFG		0x00
++
++#define AR934X_ETH_CFG_RGMII_GMAC0	BIT(0)
++#define AR934X_ETH_CFG_MII_GMAC0	BIT(1)
++#define AR934X_ETH_CFG_GMII_GMAC0	BIT(2)
++#define AR934X_ETH_CFG_MII_GMAC0_MASTER	BIT(3)
++#define AR934X_ETH_CFG_MII_GMAC0_SLAVE	BIT(4)
++#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN	BIT(5)
++#define AR934X_ETH_CFG_SW_ONLY_MODE	BIT(6)
++#define AR934X_ETH_CFG_SW_PHY_SWAP	BIT(7)
++#define AR934X_ETH_CFG_SW_APB_ACCESS	BIT(9)
++#define AR934X_ETH_CFG_RMII_GMAC0	BIT(10)
++#define AR933X_ETH_CFG_MII_CNTL_SPEED	BIT(11)
++#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
++#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST	BIT(13)
++
++/*
++ * QCA955X GMAC Interface
++ */
++
++#define QCA955X_GMAC_REG_ETH_CFG	0x00
++
++#define QCA955X_ETH_CFG_RGMII_EN	BIT(0)
++#define QCA955X_ETH_CFG_GE0_SGMII	BIT(6)
++
+ #endif /* __ASM_MACH_AR71XX_REGS_H */
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/602-MIPS-ath79-add-openwrt-stuff.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/602-MIPS-ath79-add-openwrt-stuff.patch.svn-base
new file mode 100644
index 0000000..da284e2
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/602-MIPS-ath79-add-openwrt-stuff.patch.svn-base
@@ -0,0 +1,76 @@
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -106,6 +106,20 @@ config SOC_QCA955X
+ 	select PCI_AR724X if PCI
+ 	def_bool n
+ 
++config ATH79_DEV_M25P80
++	select ATH79_DEV_SPI
++	def_bool n
++
++config ATH79_DEV_AP9X_PCI
++	select ATH79_PCI_ATH9K_FIXUP
++	def_bool n
++
++config ATH79_DEV_DSA
++	def_bool n
++
++config ATH79_DEV_ETH
++	def_bool n
++
+ config PCI_AR724X
+ 	def_bool n
+ 
+@@ -115,6 +129,10 @@ config ATH79_DEV_GPIO_BUTTONS
+ config ATH79_DEV_LEDS_GPIO
+ 	def_bool n
+ 
++config ATH79_DEV_NFC
++	depends on (SOC_AR934X || SOC_QCA955X)
++	def_bool n
++
+ config ATH79_DEV_SPI
+ 	def_bool n
+ 
+@@ -125,4 +143,13 @@ config ATH79_DEV_WMAC
+ 	depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
+ 	def_bool n
+ 
++config ATH79_NVRAM
++	def_bool n
++
++config ATH79_PCI_ATH9K_FIXUP
++	def_bool n
++
++config ATH79_ROUTERBOOT
++	def_bool n
++
+ endif
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -17,13 +17,25 @@ obj-$(CONFIG_PCI)			+= pci.o
+ # Devices
+ #
+ obj-y					+= dev-common.o
++obj-$(CONFIG_ATH79_DEV_AP9X_PCI)	+= dev-ap9x-pci.o
++obj-$(CONFIG_ATH79_DEV_DSA)		+= dev-dsa.o
++obj-$(CONFIG_ATH79_DEV_ETH)		+= dev-eth.o
+ obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS)	+= dev-gpio-buttons.o
+ obj-$(CONFIG_ATH79_DEV_LEDS_GPIO)	+= dev-leds-gpio.o
++obj-$(CONFIG_ATH79_DEV_M25P80)		+= dev-m25p80.o
++obj-$(CONFIG_ATH79_DEV_NFC)		+= dev-nfc.o
+ obj-$(CONFIG_ATH79_DEV_SPI)		+= dev-spi.o
+ obj-$(CONFIG_ATH79_DEV_USB)		+= dev-usb.o
+ obj-$(CONFIG_ATH79_DEV_WMAC)		+= dev-wmac.o
+ 
+ #
++# Miscellaneous objects
++#
++obj-$(CONFIG_ATH79_NVRAM)		+= nvram.o
++obj-$(CONFIG_ATH79_PCI_ATH9K_FIXUP)	+= pci-ath9k-fixup.o
++obj-$(CONFIG_ATH79_ROUTERBOOT)		+= routerboot.o
++
++#
+ # Machines
+ #
+ obj-$(CONFIG_ATH79_MACH_AP121)		+= mach-ap121.o
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/603-MIPS-ath79-ap121-fixes.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/603-MIPS-ath79-ap121-fixes.patch.svn-base
new file mode 100644
index 0000000..a51f587
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/603-MIPS-ath79-ap121-fixes.patch.svn-base
@@ -0,0 +1,163 @@
+--- a/arch/mips/ath79/mach-ap121.c
++++ b/arch/mips/ath79/mach-ap121.c
+@@ -1,19 +1,21 @@
+ /*
+  *  Atheros AP121 board support
+  *
+- *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
++ *  Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+  *
+  *  This program is free software; you can redistribute it and/or modify it
+  *  under the terms of the GNU General Public License version 2 as published
+  *  by the Free Software Foundation.
+  */
+ 
+-#include "machtypes.h"
++#include "dev-eth.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
++#include "dev-m25p80.h"
+ #include "dev-spi.h"
+ #include "dev-usb.h"
+ #include "dev-wmac.h"
++#include "machtypes.h"
+ 
+ #define AP121_GPIO_LED_WLAN		0
+ #define AP121_GPIO_LED_USB		1
+@@ -24,7 +26,14 @@
+ #define AP121_KEYS_POLL_INTERVAL	20	/* msecs */
+ #define AP121_KEYS_DEBOUNCE_INTERVAL	(3 * AP121_KEYS_POLL_INTERVAL)
+ 
+-#define AP121_CAL_DATA_ADDR	0x1fff1000
++#define AP121_MAC0_OFFSET		0x0000
++#define AP121_MAC1_OFFSET		0x0006
++#define AP121_CALDATA_OFFSET		0x1000
++#define AP121_WMAC_MAC_OFFSET		0x1002
++
++#define AP121_MINI_GPIO_LED_WLAN	0
++#define AP121_MINI_GPIO_BTN_JUMPSTART	12
++#define AP121_MINI_GPIO_BTN_RESET	11
+ 
+ static struct gpio_led ap121_leds_gpio[] __initdata = {
+ 	{
+@@ -58,41 +67,78 @@ static struct gpio_keys_button ap121_gpi
+ 	}
+ };
+ 
+-static struct ath79_spi_controller_data ap121_spi0_data = {
+-	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+-	.cs_line = 0,
++static struct gpio_led ap121_mini_leds_gpio[] __initdata = {
++	{
++		.name		= "ap121:green:wlan",
++		.gpio		= AP121_MINI_GPIO_LED_WLAN,
++		.active_low	= 0,
++	},
+ };
+ 
+-static struct spi_board_info ap121_spi_info[] = {
++static struct gpio_keys_button ap121_mini_gpio_keys[] __initdata = {
+ 	{
+-		.bus_num	= 0,
+-		.chip_select	= 0,
+-		.max_speed_hz	= 25000000,
+-		.modalias	= "mx25l1606e",
+-		.controller_data = &ap121_spi0_data,
++		.desc		= "jumpstart button",
++		.type		= EV_KEY,
++		.code		= KEY_WPS_BUTTON,
++		.debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
++		.gpio		= AP121_MINI_GPIO_BTN_JUMPSTART,
++		.active_low	= 1,
++	},
++	{
++		.desc		= "reset button",
++		.type		= EV_KEY,
++		.code		= KEY_RESTART,
++		.debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
++		.gpio		= AP121_MINI_GPIO_BTN_RESET,
++		.active_low	= 1,
+ 	}
+ };
+ 
+-static struct ath79_spi_platform_data ap121_spi_data = {
+-	.bus_num	= 0,
+-	.num_chipselect	= 1,
+-};
++static void __init ap121_common_setup(void)
++{
++	u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
++
++	ath79_register_m25p80(NULL);
++	ath79_register_wmac(art + AP121_CALDATA_OFFSET,
++			    art + AP121_WMAC_MAC_OFFSET);
++
++	ath79_init_mac(ath79_eth0_data.mac_addr, art + AP121_MAC0_OFFSET, 0);
++	ath79_init_mac(ath79_eth1_data.mac_addr, art + AP121_MAC1_OFFSET, 0);
++
++	ath79_register_mdio(0, 0x0);
++
++	/* LAN ports */
++	ath79_register_eth(1);
++
++	/* WAN port */
++	ath79_register_eth(0);
++}
+ 
+ static void __init ap121_setup(void)
+ {
+-	u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR);
++	ap121_common_setup();
+ 
+ 	ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio),
+ 				 ap121_leds_gpio);
+ 	ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
+ 					ARRAY_SIZE(ap121_gpio_keys),
+ 					ap121_gpio_keys);
+-
+-	ath79_register_spi(&ap121_spi_data, ap121_spi_info,
+-			   ARRAY_SIZE(ap121_spi_info));
+ 	ath79_register_usb();
+-	ath79_register_wmac(cal_data, NULL);
+ }
+ 
+ MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
+ 	     ap121_setup);
++
++static void __init ap121_mini_setup(void)
++{
++	ap121_common_setup();
++
++	ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_mini_leds_gpio),
++				 ap121_mini_leds_gpio);
++	ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
++					ARRAY_SIZE(ap121_mini_gpio_keys),
++					ap121_mini_gpio_keys);
++}
++
++MIPS_MACHINE(ATH79_MACH_AP121_MINI, "AP121-MINI", "Atheros AP121-MINI",
++	     ap121_mini_setup);
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -5,9 +5,10 @@ menu "Atheros AR71XX/AR724X/AR913X machi
+ config ATH79_MACH_AP121
+ 	bool "Atheros AP121 reference board"
+ 	select SOC_AR933X
++	select ATH79_DEV_ETH
+ 	select ATH79_DEV_GPIO_BUTTONS
+ 	select ATH79_DEV_LEDS_GPIO
+-	select ATH79_DEV_SPI
++	select ATH79_DEV_M25P80
+ 	select ATH79_DEV_USB
+ 	select ATH79_DEV_WMAC
+ 	help
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -17,6 +17,7 @@
+ enum ath79_mach_type {
+ 	ATH79_MACH_GENERIC = 0,
+ 	ATH79_MACH_AP121,		/* Atheros AP121 reference board */
++	ATH79_MACH_AP121_MINI,		/* Atheros AP121-MINI reference board */
+ 	ATH79_MACH_AP136_010,		/* Atheros AP136-010 reference board */
+ 	ATH79_MACH_AP81,		/* Atheros AP81 reference board */
+ 	ATH79_MACH_DB120,		/* Atheros DB120 reference board */
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/604-MIPS-ath79-ap81-fixes.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/604-MIPS-ath79-ap81-fixes.patch.svn-base
new file mode 100644
index 0000000..3cc012d
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/604-MIPS-ath79-ap81-fixes.patch.svn-base
@@ -0,0 +1,128 @@
+--- a/arch/mips/ath79/mach-ap81.c
++++ b/arch/mips/ath79/mach-ap81.c
+@@ -9,12 +9,16 @@
+  *  by the Free Software Foundation.
+  */
+ 
+-#include "machtypes.h"
+-#include "dev-wmac.h"
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++
++#include "dev-eth.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
+-#include "dev-spi.h"
++#include "dev-m25p80.h"
+ #include "dev-usb.h"
++#include "dev-wmac.h"
++#include "machtypes.h"
+ 
+ #define AP81_GPIO_LED_STATUS	1
+ #define AP81_GPIO_LED_AOSS	3
+@@ -29,6 +33,37 @@
+ 
+ #define AP81_CAL_DATA_ADDR	0x1fff1000
+ 
++static struct mtd_partition ap81_partitions[] = {
++	{
++		.name		= "u-boot",
++		.offset		= 0,
++		.size		= 0x040000,
++		.mask_flags	= MTD_WRITEABLE,
++	}, {
++		.name		= "u-boot-env",
++		.offset		= 0x040000,
++		.size		= 0x010000,
++	}, {
++		.name		= "rootfs",
++		.offset		= 0x050000,
++		.size		= 0x500000,
++	}, {
++		.name		= "uImage",
++		.offset		= 0x550000,
++		.size		= 0x100000,
++	}, {
++		.name		= "ART",
++		.offset		= 0x650000,
++		.size		= 0x1b0000,
++		.mask_flags	= MTD_WRITEABLE,
++	}
++};
++
++static struct flash_platform_data ap81_flash_data = {
++	.parts		= ap81_partitions,
++	.nr_parts	= ARRAY_SIZE(ap81_partitions),
++};
++
+ static struct gpio_led ap81_leds_gpio[] __initdata = {
+ 	{
+ 		.name		= "ap81:green:status",
+@@ -67,26 +102,6 @@ static struct gpio_keys_button ap81_gpio
+ 	}
+ };
+ 
+-static struct ath79_spi_controller_data ap81_spi0_data = {
+-	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+-	.cs_line = 0,
+-};
+-
+-static struct spi_board_info ap81_spi_info[] = {
+-	{
+-		.bus_num	= 0,
+-		.chip_select	= 0,
+-		.max_speed_hz	= 25000000,
+-		.modalias	= "m25p64",
+-		.controller_data = &ap81_spi0_data,
+-	}
+-};
+-
+-static struct ath79_spi_platform_data ap81_spi_data = {
+-	.bus_num	= 0,
+-	.num_chipselect	= 1,
+-};
+-
+ static void __init ap81_setup(void)
+ {
+ 	u8 *cal_data = (u8 *) KSEG1ADDR(AP81_CAL_DATA_ADDR);
+@@ -96,10 +111,24 @@ static void __init ap81_setup(void)
+ 	ath79_register_gpio_keys_polled(-1, AP81_KEYS_POLL_INTERVAL,
+ 					ARRAY_SIZE(ap81_gpio_keys),
+ 					ap81_gpio_keys);
+-	ath79_register_spi(&ap81_spi_data, ap81_spi_info,
+-			   ARRAY_SIZE(ap81_spi_info));
++	ath79_register_m25p80(&ap81_flash_data);
+ 	ath79_register_wmac(cal_data, NULL);
+ 	ath79_register_usb();
++
++	ath79_register_mdio(0, 0x0);
++
++	ath79_init_mac(ath79_eth0_data.mac_addr, cal_data, 0);
++	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
++	ath79_eth0_data.speed = SPEED_100;
++	ath79_eth0_data.duplex = DUPLEX_FULL;
++	ath79_eth0_data.has_ar8216 = 1;
++
++	ath79_init_mac(ath79_eth1_data.mac_addr, cal_data, 1);
++	ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
++	ath79_eth1_data.phy_mask = 0x10;
++
++	ath79_register_eth(0);
++	ath79_register_eth(1);
+ }
+ 
+ MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board",
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -30,9 +30,10 @@ config ATH79_MACH_AP136
+ config ATH79_MACH_AP81
+ 	bool "Atheros AP81 reference board"
+ 	select SOC_AR913X
++	select ATH79_DEV_ETH
+ 	select ATH79_DEV_GPIO_BUTTONS
+ 	select ATH79_DEV_LEDS_GPIO
+-	select ATH79_DEV_SPI
++	select ATH79_DEV_M25P80
+ 	select ATH79_DEV_USB
+ 	select ATH79_DEV_WMAC
+ 	help
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/605-MIPS-ath79-db120-fixes.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/605-MIPS-ath79-db120-fixes.patch.svn-base
new file mode 100644
index 0000000..0ca7861
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/605-MIPS-ath79-db120-fixes.patch.svn-base
@@ -0,0 +1,209 @@
+--- a/arch/mips/ath79/mach-db120.c
++++ b/arch/mips/ath79/mach-db120.c
+@@ -2,7 +2,7 @@
+  * Atheros DB120 reference board support
+  *
+  * Copyright (c) 2011 Qualcomm Atheros
+- * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+  *
+  * Permission to use, copy, modify, and/or distribute this software for any
+  * purpose with or without fee is hereby granted, provided that the above
+@@ -19,16 +19,26 @@
+  */
+ 
+ #include <linux/pci.h>
++#include <linux/phy.h>
++#include <linux/platform_device.h>
+ #include <linux/ath9k_platform.h>
++#include <linux/ar8216_platform.h>
+ 
+-#include "machtypes.h"
++#include <asm/mach-ath79/ar71xx_regs.h>
++
++#include "common.h"
++#include "dev-ap9x-pci.h"
++#include "dev-eth.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
++#include "dev-m25p80.h"
++#include "dev-nfc.h"
+ #include "dev-spi.h"
+ #include "dev-usb.h"
+ #include "dev-wmac.h"
+-#include "pci.h"
++#include "machtypes.h"
+ 
++#define DB120_GPIO_LED_USB		11
+ #define DB120_GPIO_LED_WLAN_5G		12
+ #define DB120_GPIO_LED_WLAN_2G		13
+ #define DB120_GPIO_LED_STATUS		14
+@@ -39,8 +49,10 @@
+ #define DB120_KEYS_POLL_INTERVAL	20	/* msecs */
+ #define DB120_KEYS_DEBOUNCE_INTERVAL	(3 * DB120_KEYS_POLL_INTERVAL)
+ 
+-#define DB120_WMAC_CALDATA_OFFSET 0x1000
+-#define DB120_PCIE_CALDATA_OFFSET 0x5000
++#define DB120_MAC0_OFFSET		0
++#define DB120_MAC1_OFFSET		6
++#define DB120_WMAC_CALDATA_OFFSET	0x1000
++#define DB120_PCIE_CALDATA_OFFSET	0x5000
+ 
+ static struct gpio_led db120_leds_gpio[] __initdata = {
+ 	{
+@@ -63,6 +75,11 @@ static struct gpio_led db120_leds_gpio[]
+ 		.gpio		= DB120_GPIO_LED_WLAN_2G,
+ 		.active_low	= 1,
+ 	},
++	{
++		.name		= "db120:green:usb",
++		.gpio		= DB120_GPIO_LED_USB,
++		.active_low	= 1,
++	}
+ };
+ 
+ static struct gpio_keys_button db120_gpio_keys[] __initdata = {
+@@ -76,66 +93,85 @@ static struct gpio_keys_button db120_gpi
+ 	},
+ };
+ 
+-static struct ath79_spi_controller_data db120_spi0_data = {
+-	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+-	.cs_line = 0,
++static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = {
++	.mode = AR8327_PAD_MAC_RGMII,
++	.txclk_delay_en = true,
++	.rxclk_delay_en = true,
++	.txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
++	.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
+ };
+ 
+-static struct spi_board_info db120_spi_info[] = {
+-	{
+-		.bus_num	= 0,
+-		.chip_select	= 0,
+-		.max_speed_hz	= 25000000,
+-		.modalias	= "s25sl064a",
+-		.controller_data = &db120_spi0_data,
+-	}
++static struct ar8327_led_cfg db120_ar8327_led_cfg = {
++	.led_ctrl0 = 0x00000000,
++	.led_ctrl1 = 0xc737c737,
++	.led_ctrl2 = 0x00000000,
++	.led_ctrl3 = 0x00c30c00,
++	.open_drain = true,
+ };
+ 
+-static struct ath79_spi_platform_data db120_spi_data = {
+-	.bus_num	= 0,
+-	.num_chipselect	= 1,
++static struct ar8327_platform_data db120_ar8327_data = {
++	.pad0_cfg = &db120_ar8327_pad0_cfg,
++	.port0_cfg = {
++		.force_link = 1,
++		.speed = AR8327_PORT_SPEED_1000,
++		.duplex = 1,
++		.txpause = 1,
++		.rxpause = 1,
++	},
++	.led_cfg = &db120_ar8327_led_cfg,
+ };
+ 
+-#ifdef CONFIG_PCI
+-static struct ath9k_platform_data db120_ath9k_data;
+-
+-static int db120_pci_plat_dev_init(struct pci_dev *dev)
+-{
+-	switch (PCI_SLOT(dev->devfn)) {
+-	case 0:
+-		dev->dev.platform_data = &db120_ath9k_data;
+-		break;
+-	}
+-
+-	return 0;
+-}
+-
+-static void __init db120_pci_init(u8 *eeprom)
+-{
+-	memcpy(db120_ath9k_data.eeprom_data, eeprom,
+-	       sizeof(db120_ath9k_data.eeprom_data));
+-
+-	ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
+-	ath79_register_pci();
+-}
+-#else
+-static inline void db120_pci_init(void) {}
+-#endif /* CONFIG_PCI */
++static struct mdio_board_info db120_mdio0_info[] = {
++	{
++		.bus_id = "ag71xx-mdio.0",
++		.phy_addr = 0,
++		.platform_data = &db120_ar8327_data,
++	},
++};
+ 
+ static void __init db120_setup(void)
+ {
+ 	u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+ 
++	ath79_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO);
++	ath79_register_m25p80(NULL);
++
+ 	ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
+ 				 db120_leds_gpio);
+ 	ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
+ 					ARRAY_SIZE(db120_gpio_keys),
+ 					db120_gpio_keys);
+-	ath79_register_spi(&db120_spi_data, db120_spi_info,
+-			   ARRAY_SIZE(db120_spi_info));
+ 	ath79_register_usb();
+ 	ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
+-	db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
++	ap91_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL);
++
++	ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
++				   AR934X_ETH_CFG_SW_ONLY_MODE);
++
++	ath79_register_mdio(1, 0x0);
++	ath79_register_mdio(0, 0x0);
++
++	ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0);
++
++	mdiobus_register_board_info(db120_mdio0_info,
++				    ARRAY_SIZE(db120_mdio0_info));
++
++	/* GMAC0 is connected to an AR8327 switch */
++	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
++	ath79_eth0_data.phy_mask = BIT(0);
++	ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
++	ath79_eth0_pll_data.pll_1000 = 0x06000000;
++	ath79_register_eth(0);
++
++	/* GMAC1 is connected to the internal switch */
++	ath79_init_mac(ath79_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0);
++	ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
++	ath79_eth1_data.speed = SPEED_1000;
++	ath79_eth1_data.duplex = DUPLEX_FULL;
++
++	ath79_register_eth(1);
++
++	ath79_register_nfc();
+ }
+ 
+ MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -43,9 +43,12 @@ config ATH79_MACH_AP81
+ config ATH79_MACH_DB120
+ 	bool "Atheros DB120 reference board"
+ 	select SOC_AR934X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
+ 	select ATH79_DEV_GPIO_BUTTONS
+ 	select ATH79_DEV_LEDS_GPIO
+-	select ATH79_DEV_SPI
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_NFC
+ 	select ATH79_DEV_USB
+ 	select ATH79_DEV_WMAC
+ 	help
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/606-MIPS-ath79-pb44-fixes.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/606-MIPS-ath79-pb44-fixes.patch.svn-base
new file mode 100644
index 0000000..f9ec775
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/606-MIPS-ath79-pb44-fixes.patch.svn-base
@@ -0,0 +1,153 @@
+--- a/arch/mips/ath79/mach-pb44.c
++++ b/arch/mips/ath79/mach-pb44.c
+@@ -8,23 +8,48 @@
+  *  by the Free Software Foundation.
+  */
+ 
++#include <linux/delay.h>
+ #include <linux/init.h>
+ #include <linux/platform_device.h>
+ #include <linux/i2c.h>
+ #include <linux/i2c-gpio.h>
+ #include <linux/i2c/pcf857x.h>
++#include <linux/i2c/pcf857x.h>
++#include <linux/spi/flash.h>
++#include <linux/spi/vsc7385.h>
+ 
+-#include "machtypes.h"
++#include <asm/mach-ath79/ar71xx_regs.h>
++#include <asm/mach-ath79/ath79.h>
++
++#include "dev-eth.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
+ #include "dev-spi.h"
+ #include "dev-usb.h"
++#include "machtypes.h"
+ #include "pci.h"
+ 
+ #define PB44_GPIO_I2C_SCL	0
+ #define PB44_GPIO_I2C_SDA	1
+ 
++#define PB44_PCF8757_VSC7395_CS	0
++#define PB44_PCF8757_STEREO_CS	1
++#define PB44_PCF8757_SLIC_CS0	2
++#define PB44_PCF8757_SLIC_TEST	3
++#define PB44_PCF8757_SLIC_INT0	4
++#define PB44_PCF8757_SLIC_INT1	5
++#define PB44_PCF8757_SW_RESET	6
++#define PB44_PCF8757_SW_JUMP	8
++#define PB44_PCF8757_LED_JUMP1	9
++#define PB44_PCF8757_LED_JUMP2	10
++#define PB44_PCF8757_TP24	11
++#define PB44_PCF8757_TP25	12
++#define PB44_PCF8757_TP26	13
++#define PB44_PCF8757_TP27	14
++#define PB44_PCF8757_TP28	15
++
+ #define PB44_GPIO_EXP_BASE	16
++#define PB44_GPIO_VSC7395_CS	(PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS)
+ #define PB44_GPIO_SW_RESET	(PB44_GPIO_EXP_BASE + 6)
+ #define PB44_GPIO_SW_JUMP	(PB44_GPIO_EXP_BASE + 8)
+ #define PB44_GPIO_LED_JUMP1	(PB44_GPIO_EXP_BASE + 9)
+@@ -92,21 +117,66 @@ static struct ath79_spi_controller_data
+ 	.cs_line = 0,
+ };
+ 
++static struct ath79_spi_controller_data pb44_spi1_data = {
++	.cs_type = ATH79_SPI_CS_TYPE_GPIO,
++	.cs_line = PB44_GPIO_VSC7395_CS,
++};
++
++static void pb44_vsc7395_reset(void)
++{
++	ath79_device_reset_set(AR71XX_RESET_GE1_PHY);
++	udelay(10);
++	ath79_device_reset_clear(AR71XX_RESET_GE1_PHY);
++	mdelay(50);
++}
++
++static struct vsc7385_platform_data pb44_vsc7395_data = {
++	.reset		= pb44_vsc7395_reset,
++	.ucode_name	= "vsc7395_ucode_pb44.bin",
++	.mac_cfg = {
++		.tx_ipg		= 6,
++		.bit2		= 1,
++		.clk_sel	= 0,
++	},
++};
++
++static const char *pb44_part_probes[] = {
++	"RedBoot",
++	NULL,
++};
++
++static struct flash_platform_data pb44_flash_data = {
++	.part_probes	= pb44_part_probes,
++};
++
+ static struct spi_board_info pb44_spi_info[] = {
+ 	{
+ 		.bus_num	= 0,
+ 		.chip_select	= 0,
+ 		.max_speed_hz	= 25000000,
+ 		.modalias	= "m25p64",
++		.platform_data	= &pb44_flash_data,
+ 		.controller_data = &pb44_spi0_data,
+ 	},
++	{
++		.bus_num	= 0,
++		.chip_select	= 1,
++		.max_speed_hz	= 25000000,
++		.modalias	= "spi-vsc7385",
++		.platform_data	= &pb44_vsc7395_data,
++		.controller_data = &pb44_spi1_data,
++	}
+ };
+ 
+ static struct ath79_spi_platform_data pb44_spi_data = {
+ 	.bus_num		= 0,
+-	.num_chipselect		= 1,
++	.num_chipselect		= 2,
+ };
+ 
++#define PB44_WAN_PHYMASK	BIT(0)
++#define PB44_LAN_PHYMASK	0
++#define PB44_MDIO_PHYMASK	(PB44_LAN_PHYMASK | PB44_WAN_PHYMASK)
++
+ static void __init pb44_init(void)
+ {
+ 	i2c_register_board_info(0, pb44_i2c_board_info,
+@@ -122,6 +192,22 @@ static void __init pb44_init(void)
+ 			   ARRAY_SIZE(pb44_spi_info));
+ 	ath79_register_usb();
+ 	ath79_register_pci();
++
++	ath79_register_mdio(0, ~PB44_MDIO_PHYMASK);
++
++	ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
++	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
++	ath79_eth0_data.phy_mask = PB44_WAN_PHYMASK;
++
++	ath79_register_eth(0);
++
++	ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
++	ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
++	ath79_eth1_data.speed = SPEED_1000;
++	ath79_eth1_data.duplex = DUPLEX_FULL;
++	ath79_eth1_pll_data.pll_1000 = 0x110000;
++
++	ath79_register_eth(1);
+ }
+ 
+ MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -58,6 +58,7 @@ config ATH79_MACH_DB120
+ config ATH79_MACH_PB44
+ 	bool "Atheros PB44 reference board"
+ 	select SOC_AR71XX
++	select ATH79_DEV_ETH
+ 	select ATH79_DEV_GPIO_BUTTONS
+ 	select ATH79_DEV_LEDS_GPIO
+ 	select ATH79_DEV_SPI
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/607-MIPS-ath79-ubnt-xm-fixes.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/607-MIPS-ath79-ubnt-xm-fixes.patch.svn-base
new file mode 100644
index 0000000..cbbe20b
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/607-MIPS-ath79-ubnt-xm-fixes.patch.svn-base
@@ -0,0 +1,109 @@
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -70,9 +70,10 @@ config ATH79_MACH_PB44
+ config ATH79_MACH_UBNT_XM
+ 	bool "Ubiquiti Networks XM (rev 1.0) board"
+ 	select SOC_AR724X
++	select ATH79_DEV_AP9X_PCI if PCI
+ 	select ATH79_DEV_GPIO_BUTTONS
+ 	select ATH79_DEV_LEDS_GPIO
+-	select ATH79_DEV_SPI
++	select ATH79_DEV_M25P80
+ 	help
+ 	  Say 'Y' here if you want your kernel to support the
+ 	  Ubiquiti Networks XM (rev 1.0) board.
+--- a/arch/mips/ath79/mach-ubnt-xm.c
++++ b/arch/mips/ath79/mach-ubnt-xm.c
+@@ -16,10 +16,11 @@
+ 
+ #include <asm/mach-ath79/irq.h>
+ 
+-#include "machtypes.h"
++#include "dev-ap9x-pci.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
+-#include "dev-spi.h"
++#include "dev-m25p80.h"
++#include "machtypes.h"
+ #include "pci.h"
+ 
+ #define UBNT_XM_GPIO_LED_L1		0
+@@ -32,7 +33,7 @@
+ #define UBNT_XM_KEYS_POLL_INTERVAL	20
+ #define UBNT_XM_KEYS_DEBOUNCE_INTERVAL	(3 * UBNT_XM_KEYS_POLL_INTERVAL)
+ 
+-#define UBNT_XM_EEPROM_ADDR		(u8 *) KSEG1ADDR(0x1fff1000)
++#define UBNT_XM_EEPROM_ADDR		0x1fff1000
+ 
+ static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
+ 	{
+@@ -65,54 +66,10 @@ static struct gpio_keys_button ubnt_xm_g
+ 	}
+ };
+ 
+-static struct ath79_spi_controller_data ubnt_xm_spi0_data = {
+-	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+-	.cs_line = 0,
+-};
+-
+-static struct spi_board_info ubnt_xm_spi_info[] = {
+-	{
+-		.bus_num	= 0,
+-		.chip_select	= 0,
+-		.max_speed_hz	= 25000000,
+-		.modalias	= "mx25l6405d",
+-		.controller_data = &ubnt_xm_spi0_data,
+-	}
+-};
+-
+-static struct ath79_spi_platform_data ubnt_xm_spi_data = {
+-	.bus_num		= 0,
+-	.num_chipselect		= 1,
+-};
+-
+-#ifdef CONFIG_PCI
+-static struct ath9k_platform_data ubnt_xm_eeprom_data;
+-
+-static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev)
+-{
+-	switch (PCI_SLOT(dev->devfn)) {
+-	case 0:
+-		dev->dev.platform_data = &ubnt_xm_eeprom_data;
+-		break;
+-	}
+-
+-	return 0;
+-}
+-
+-static void __init ubnt_xm_pci_init(void)
+-{
+-	memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
+-	       sizeof(ubnt_xm_eeprom_data.eeprom_data));
+-
+-	ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init);
+-	ath79_register_pci();
+-}
+-#else
+-static inline void ubnt_xm_pci_init(void) {}
+-#endif /* CONFIG_PCI */
+-
+ static void __init ubnt_xm_init(void)
+ {
++	u8 *eeprom = (u8 *) KSEG1ADDR(UBNT_XM_EEPROM_ADDR);
++
+ 	ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
+ 				 ubnt_xm_leds_gpio);
+ 
+@@ -120,10 +77,8 @@ static void __init ubnt_xm_init(void)
+ 					ARRAY_SIZE(ubnt_xm_gpio_keys),
+ 					ubnt_xm_gpio_keys);
+ 
+-	ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info,
+-			   ARRAY_SIZE(ubnt_xm_spi_info));
+-
+-	ubnt_xm_pci_init();
++	ath79_register_m25p80(NULL);
++	ap91_pci_init(eeprom, NULL);
+ }
+ 
+ MIPS_MACHINE(ATH79_MACH_UBNT_XM,
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/608-MIPS-ath79-ubnt-xm-add-more-boards.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/608-MIPS-ath79-ubnt-xm-add-more-boards.patch.svn-base
new file mode 100644
index 0000000..2e8fbdc
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/608-MIPS-ath79-ubnt-xm-add-more-boards.patch.svn-base
@@ -0,0 +1,343 @@
+--- a/arch/mips/ath79/mach-ubnt-xm.c
++++ b/arch/mips/ath79/mach-ubnt-xm.c
+@@ -12,16 +12,22 @@
+ 
+ #include <linux/init.h>
+ #include <linux/pci.h>
++#include <linux/platform_device.h>
+ #include <linux/ath9k_platform.h>
++#include <linux/etherdevice.h>
++#include <linux/ar8216_platform.h>
+ 
+ #include <asm/mach-ath79/irq.h>
++#include <asm/mach-ath79/ar71xx_regs.h>
+ 
+ #include "dev-ap9x-pci.h"
++#include "dev-eth.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
+ #include "dev-m25p80.h"
++#include "dev-usb.h"
++#include "dev-wmac.h"
+ #include "machtypes.h"
+-#include "pci.h"
+ 
+ #define UBNT_XM_GPIO_LED_L1		0
+ #define UBNT_XM_GPIO_LED_L2		1
+@@ -37,19 +43,19 @@
+ 
+ static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
+ 	{
+-		.name		= "ubnt-xm:red:link1",
++		.name		= "ubnt:red:link1",
+ 		.gpio		= UBNT_XM_GPIO_LED_L1,
+ 		.active_low	= 0,
+ 	}, {
+-		.name		= "ubnt-xm:orange:link2",
++		.name		= "ubnt:orange:link2",
+ 		.gpio		= UBNT_XM_GPIO_LED_L2,
+ 		.active_low	= 0,
+ 	}, {
+-		.name		= "ubnt-xm:green:link3",
++		.name		= "ubnt:green:link3",
+ 		.gpio		= UBNT_XM_GPIO_LED_L3,
+ 		.active_low	= 0,
+ 	}, {
+-		.name		= "ubnt-xm:green:link4",
++		.name		= "ubnt:green:link4",
+ 		.gpio		= UBNT_XM_GPIO_LED_L4,
+ 		.active_low	= 0,
+ 	},
+@@ -66,9 +72,13 @@ static struct gpio_keys_button ubnt_xm_g
+ 	}
+ };
+ 
++#define UBNT_M_WAN_PHYMASK	BIT(4)
++
+ static void __init ubnt_xm_init(void)
+ {
+ 	u8 *eeprom = (u8 *) KSEG1ADDR(UBNT_XM_EEPROM_ADDR);
++	u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
++	u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN);
+ 
+ 	ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
+ 				 ubnt_xm_leds_gpio);
+@@ -79,9 +89,242 @@ static void __init ubnt_xm_init(void)
+ 
+ 	ath79_register_m25p80(NULL);
+ 	ap91_pci_init(eeprom, NULL);
++
++	ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK);
++	ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
++	ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
++	ath79_register_eth(0);
+ }
+ 
+ MIPS_MACHINE(ATH79_MACH_UBNT_XM,
+ 	     "UBNT-XM",
+ 	     "Ubiquiti Networks XM (rev 1.0) board",
+ 	     ubnt_xm_init);
++
++MIPS_MACHINE(ATH79_MACH_UBNT_BULLET_M, "UBNT-BM", "Ubiquiti Bullet M",
++	     ubnt_xm_init);
++
++static void __init ubnt_rocket_m_setup(void)
++{
++	ubnt_xm_init();
++	ath79_register_usb();
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_ROCKET_M, "UBNT-RM", "Ubiquiti Rocket M",
++	     ubnt_rocket_m_setup);
++
++static void __init ubnt_nano_m_setup(void)
++{
++	ubnt_xm_init();
++	ath79_register_eth(1);
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_NANO_M, "UBNT-NM", "Ubiquiti Nanostation M",
++	     ubnt_nano_m_setup);
++
++static struct gpio_led ubnt_airrouter_leds_gpio[] __initdata = {
++	{
++		.name		= "ubnt:green:globe",
++		.gpio		= 0,
++		.active_low	= 1,
++	}, {
++	        .name		= "ubnt:green:power",
++		.gpio		= 11,
++		.active_low	= 1,
++		.default_state  = LEDS_GPIO_DEFSTATE_ON,
++	}
++};
++
++static void __init ubnt_airrouter_setup(void)
++{
++	u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
++	u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
++
++	ath79_register_m25p80(NULL);
++	ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK);
++
++	ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
++	ath79_init_local_mac(ath79_eth1_data.mac_addr, mac1);
++
++	ath79_register_eth(1);
++	ath79_register_eth(0);
++	ath79_register_usb();
++
++	ap91_pci_init(ee, NULL);
++	ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_airrouter_leds_gpio),
++				 ubnt_airrouter_leds_gpio);
++
++	ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
++                                        ARRAY_SIZE(ubnt_xm_gpio_keys),
++                                        ubnt_xm_gpio_keys);
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_AIRROUTER, "UBNT-AR", "Ubiquiti AirRouter",
++	     ubnt_airrouter_setup);
++
++static struct gpio_led ubnt_unifi_leds_gpio[] __initdata = {
++	{
++		.name		= "ubnt:orange:dome",
++		.gpio		= 1,
++		.active_low	= 0,
++	}, {
++		.name		= "ubnt:green:dome",
++		.gpio		= 0,
++		.active_low	= 0,
++	}
++};
++
++static struct gpio_led ubnt_unifi_outdoor_leds_gpio[] __initdata = {
++	{
++		.name		= "ubnt:orange:front",
++		.gpio		= 1,
++		.active_low	= 0,
++	}, {
++		.name		= "ubnt:green:front",
++		.gpio		= 0,
++		.active_low	= 0,
++	}
++};
++
++static void __init ubnt_unifi_setup(void)
++{
++	u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000);
++	u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
++
++	ath79_register_m25p80(NULL);
++
++	ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK);
++
++	ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
++	ath79_register_eth(0);
++
++	ap91_pci_init(ee, NULL);
++
++	ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_leds_gpio),
++				 ubnt_unifi_leds_gpio);
++
++	ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
++                                        ARRAY_SIZE(ubnt_xm_gpio_keys),
++                                        ubnt_xm_gpio_keys);
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_UNIFI, "UBNT-UF", "Ubiquiti UniFi",
++	     ubnt_unifi_setup);
++
++
++#define UBNT_UNIFIOD_PRI_PHYMASK	BIT(4)
++#define UBNT_UNIFIOD_2ND_PHYMASK	(BIT(0) | BIT(1) | BIT(2) | BIT(3))
++
++static void __init ubnt_unifi_outdoor_setup(void)
++{
++	u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
++	u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN);
++	u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
++
++	ath79_register_m25p80(NULL);
++
++	ath79_register_mdio(0, ~(UBNT_UNIFIOD_PRI_PHYMASK |
++				 UBNT_UNIFIOD_2ND_PHYMASK));
++
++	ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
++	ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
++	ath79_register_eth(0);
++	ath79_register_eth(1);
++
++	ap91_pci_init(ee, NULL);
++
++	ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_outdoor_leds_gpio),
++				 ubnt_unifi_outdoor_leds_gpio);
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_UNIFI_OUTDOOR, "UBNT-U20",
++	     "Ubiquiti UniFiAP Outdoor",
++	     ubnt_unifi_outdoor_setup);
++
++static struct gpio_led ubnt_uap_pro_gpio_leds[] __initdata = {
++	{
++		.name		= "ubnt:white:dome",
++		.gpio		= 12,
++	}, {
++		.name		= "ubnt:blue:dome",
++		.gpio		= 13,
++	}
++};
++
++static struct gpio_keys_button uap_pro_gpio_keys[] __initdata = {
++	{
++		.desc			= "reset",
++		.type			= EV_KEY,
++		.code			= KEY_RESTART,
++		.debounce_interval	= UBNT_XM_KEYS_DEBOUNCE_INTERVAL,
++		.gpio			= 17,
++		.active_low		= 1,
++	}
++};
++
++static struct ar8327_pad_cfg uap_pro_ar8327_pad0_cfg = {
++	.mode = AR8327_PAD_MAC_RGMII,
++	.txclk_delay_en = true,
++	.rxclk_delay_en = true,
++	.txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
++	.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
++};
++
++static struct ar8327_platform_data uap_pro_ar8327_data = {
++	.pad0_cfg = &uap_pro_ar8327_pad0_cfg,
++	.port0_cfg = {
++		.force_link = 1,
++		.speed = AR8327_PORT_SPEED_1000,
++		.duplex = 1,
++		.txpause = 1,
++		.rxpause = 1,
++	},
++};
++
++static struct mdio_board_info uap_pro_mdio0_info[] = {
++	{
++		.bus_id = "ag71xx-mdio.0",
++		.phy_addr = 0,
++		.platform_data = &uap_pro_ar8327_data,
++	},
++};
++
++#define UAP_PRO_MAC0_OFFSET		0x0000
++#define UAP_PRO_MAC1_OFFSET		0x0006
++#define UAP_PRO_WMAC_CALDATA_OFFSET	0x1000
++#define UAP_PRO_PCI_CALDATA_OFFSET	0x5000
++
++static void __init ubnt_uap_pro_setup(void)
++{
++	u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000);
++
++	ath79_register_m25p80(NULL);
++
++	ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_uap_pro_gpio_leds),
++				 ubnt_uap_pro_gpio_leds);
++	ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
++                                        ARRAY_SIZE(uap_pro_gpio_keys),
++                                        uap_pro_gpio_keys);
++
++	ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL);
++	ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL);
++
++	ath79_register_mdio(0, 0x0);
++	mdiobus_register_board_info(uap_pro_mdio0_info,
++				    ARRAY_SIZE(uap_pro_mdio0_info));
++
++	ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
++	ath79_init_mac(ath79_eth0_data.mac_addr,
++		       eeprom + UAP_PRO_MAC0_OFFSET, 0);
++
++	/* GMAC0 is connected to an AR8327 switch */
++	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
++	ath79_eth0_data.phy_mask = BIT(0);
++	ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
++	ath79_eth0_pll_data.pll_1000 = 0x06000000;
++	ath79_register_eth(0);
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_UAP_PRO, "UAP-PRO", "Ubiquiti UniFi AP Pro",
++	     ubnt_uap_pro_setup);
++
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -68,12 +68,16 @@ config ATH79_MACH_PB44
+ 	  Atheros PB44 reference board.
+ 
+ config ATH79_MACH_UBNT_XM
+-	bool "Ubiquiti Networks XM (rev 1.0) board"
++	bool "Ubiquiti Networks XM/UniFi boards"
+ 	select SOC_AR724X
++	select SOC_AR934X
+ 	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
+ 	select ATH79_DEV_GPIO_BUTTONS
+ 	select ATH79_DEV_LEDS_GPIO
+ 	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
+ 	help
+ 	  Say 'Y' here if you want your kernel to support the
+ 	  Ubiquiti Networks XM (rev 1.0) board.
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -22,6 +22,13 @@ enum ath79_mach_type {
+ 	ATH79_MACH_AP81,		/* Atheros AP81 reference board */
+ 	ATH79_MACH_DB120,		/* Atheros DB120 reference board */
+ 	ATH79_MACH_PB44,		/* Atheros PB44 reference board */
++	ATH79_MACH_UBNT_AIRROUTER,	/* Ubiquiti AirRouter */
++	ATH79_MACH_UBNT_BULLET_M,	/* Ubiquiti Bullet M */
++	ATH79_MACH_UBNT_NANO_M, 	/* Ubiquiti NanoStation M */
++	ATH79_MACH_UBNT_ROCKET_M,	/* Ubiquiti Rocket M */
++	ATH79_MACH_UBNT_UAP_PRO,	/* Ubiquiti UniFi AP Pro */
++	ATH79_MACH_UBNT_UNIFI, 		/* Ubiquiti Unifi */
++	ATH79_MACH_UBNT_UNIFI_OUTDOOR,	/* Ubiquiti UnifiAP Outdoor */
+ 	ATH79_MACH_UBNT_XM,		/* Ubiquiti Networks XM board rev 1.0 */
+ };
+ 
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/609-MIPS-ath79-ap136-fixes.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/609-MIPS-ath79-ap136-fixes.patch.svn-base
new file mode 100644
index 0000000..0a8fe0e
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/609-MIPS-ath79-ap136-fixes.patch.svn-base
@@ -0,0 +1,317 @@
+--- a/arch/mips/ath79/mach-ap136.c
++++ b/arch/mips/ath79/mach-ap136.c
+@@ -18,23 +18,28 @@
+  *
+  */
+ 
+-#include <linux/pci.h>
+-#include <linux/ath9k_platform.h>
++#include <linux/platform_device.h>
++#include <linux/ar8216_platform.h>
+ 
+-#include "machtypes.h"
++#include <asm/mach-ath79/ar71xx_regs.h>
++
++#include "common.h"
++#include "dev-ap9x-pci.h"
+ #include "dev-gpio-buttons.h"
++#include "dev-eth.h"
+ #include "dev-leds-gpio.h"
+-#include "dev-spi.h"
++#include "dev-m25p80.h"
++#include "dev-nfc.h"
+ #include "dev-usb.h"
+ #include "dev-wmac.h"
+-#include "pci.h"
++#include "machtypes.h"
+ 
+-#define AP136_GPIO_LED_STATUS_RED	14
+-#define AP136_GPIO_LED_STATUS_GREEN	19
+ #define AP136_GPIO_LED_USB		4
+-#define AP136_GPIO_LED_WLAN_2G		13
+ #define AP136_GPIO_LED_WLAN_5G		12
++#define AP136_GPIO_LED_WLAN_2G		13
++#define AP136_GPIO_LED_STATUS_RED	14
+ #define AP136_GPIO_LED_WPS_RED		15
++#define AP136_GPIO_LED_STATUS_GREEN	19
+ #define AP136_GPIO_LED_WPS_GREEN	20
+ 
+ #define AP136_GPIO_BTN_WPS		16
+@@ -43,37 +48,39 @@
+ #define AP136_KEYS_POLL_INTERVAL	20	/* msecs */
+ #define AP136_KEYS_DEBOUNCE_INTERVAL	(3 * AP136_KEYS_POLL_INTERVAL)
+ 
+-#define AP136_WMAC_CALDATA_OFFSET 0x1000
+-#define AP136_PCIE_CALDATA_OFFSET 0x5000
++#define AP136_MAC0_OFFSET		0
++#define AP136_MAC1_OFFSET		6
++#define AP136_WMAC_CALDATA_OFFSET	0x1000
++#define AP136_PCIE_CALDATA_OFFSET	0x5000
+ 
+ static struct gpio_led ap136_leds_gpio[] __initdata = {
+ 	{
+-		.name		= "qca:green:status",
++		.name		= "ap136:green:status",
+ 		.gpio		= AP136_GPIO_LED_STATUS_GREEN,
+ 		.active_low	= 1,
+ 	},
+ 	{
+-		.name		= "qca:red:status",
++		.name		= "ap136:red:status",
+ 		.gpio		= AP136_GPIO_LED_STATUS_RED,
+ 		.active_low	= 1,
+ 	},
+ 	{
+-		.name		= "qca:green:wps",
++		.name		= "ap136:green:wps",
+ 		.gpio		= AP136_GPIO_LED_WPS_GREEN,
+ 		.active_low	= 1,
+ 	},
+ 	{
+-		.name		= "qca:red:wps",
++		.name		= "ap136:red:wps",
+ 		.gpio		= AP136_GPIO_LED_WPS_RED,
+ 		.active_low	= 1,
+ 	},
+ 	{
+-		.name		= "qca:red:wlan-2g",
++		.name		= "ap136:red:wlan-2g",
+ 		.gpio		= AP136_GPIO_LED_WLAN_2G,
+ 		.active_low	= 1,
+ 	},
+ 	{
+-		.name		= "qca:red:usb",
++		.name		= "ap136:red:usb",
+ 		.gpio		= AP136_GPIO_LED_USB,
+ 		.active_low	= 1,
+ 	}
+@@ -98,65 +105,158 @@ static struct gpio_keys_button ap136_gpi
+ 	},
+ };
+ 
+-static struct ath79_spi_controller_data ap136_spi0_data = {
+-	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+-	.cs_line = 0,
++static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg;
++static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg;
++
++static struct ar8327_platform_data ap136_ar8327_data = {
++	.pad0_cfg = &ap136_ar8327_pad0_cfg,
++	.pad6_cfg = &ap136_ar8327_pad6_cfg,
++	.port0_cfg = {
++		.force_link = 1,
++		.speed = AR8327_PORT_SPEED_1000,
++		.duplex = 1,
++		.txpause = 1,
++		.rxpause = 1,
++	},
++	.port6_cfg = {
++		.force_link = 1,
++		.speed = AR8327_PORT_SPEED_1000,
++		.duplex = 1,
++		.txpause = 1,
++		.rxpause = 1,
++	},
+ };
+ 
+-static struct spi_board_info ap136_spi_info[] = {
++static struct mdio_board_info ap136_mdio0_info[] = {
+ 	{
+-		.bus_num	= 0,
+-		.chip_select	= 0,
+-		.max_speed_hz	= 25000000,
+-		.modalias	= "mx25l6405d",
+-		.controller_data = &ap136_spi0_data,
+-	}
++		.bus_id = "ag71xx-mdio.0",
++		.phy_addr = 0,
++		.platform_data = &ap136_ar8327_data,
++	},
+ };
+ 
+-static struct ath79_spi_platform_data ap136_spi_data = {
+-	.bus_num	= 0,
+-	.num_chipselect	= 1,
+-};
++static void __init ap136_gmac_setup(void)
++{
++	void __iomem *base;
++	u32 t;
+ 
+-#ifdef CONFIG_PCI
+-static struct ath9k_platform_data ap136_ath9k_data;
++	base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
+ 
+-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
+-{
+-	if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
+-		dev->dev.platform_data = &ap136_ath9k_data;
++	t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
+ 
+-	return 0;
+-}
++	t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
++	t |= QCA955X_ETH_CFG_RGMII_EN;
+ 
+-static void __init ap136_pci_init(u8 *eeprom)
+-{
+-	memcpy(ap136_ath9k_data.eeprom_data, eeprom,
+-	       sizeof(ap136_ath9k_data.eeprom_data));
++	__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
+ 
+-	ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
+-	ath79_register_pci();
++	iounmap(base);
+ }
+-#else
+-static inline void ap136_pci_init(void) {}
+-#endif /* CONFIG_PCI */
+ 
+-static void __init ap136_setup(void)
++static void __init ap136_common_setup(void)
+ {
+ 	u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+ 
++	ath79_register_m25p80(NULL);
++
+ 	ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
+ 				 ap136_leds_gpio);
+ 	ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
+ 					ARRAY_SIZE(ap136_gpio_keys),
+ 					ap136_gpio_keys);
+-	ath79_register_spi(&ap136_spi_data, ap136_spi_info,
+-			   ARRAY_SIZE(ap136_spi_info));
++
+ 	ath79_register_usb();
+-	ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
+-	ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
++	ath79_register_nfc();
++
++	ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
++	ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
++
++	ap136_gmac_setup();
++
++	ath79_register_mdio(0, 0x0);
++
++	ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
++
++	mdiobus_register_board_info(ap136_mdio0_info,
++				    ARRAY_SIZE(ap136_mdio0_info));
++
++	/* GMAC0 is connected to the RMGII interface */
++	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
++	ath79_eth0_data.phy_mask = BIT(0);
++	ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
++
++	ath79_register_eth(0);
++
++	/* GMAC1 is connected tot eh SGMII interface */
++	ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
++	ath79_eth1_data.speed = SPEED_1000;
++	ath79_eth1_data.duplex = DUPLEX_FULL;
++
++	ath79_register_eth(1);
++}
++
++static void __init ap136_010_setup(void)
++{
++	/* GMAC0 of the AR8327 switch is connected to GMAC0 via RGMII */
++	ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII;
++	ap136_ar8327_pad0_cfg.txclk_delay_en = true;
++	ap136_ar8327_pad0_cfg.rxclk_delay_en = true;
++	ap136_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
++	ap136_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
++
++	/* GMAC6 of the AR8327 switch is connected to GMAC1 via SGMII */
++	ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
++	ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
++	ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0;
++
++	ath79_eth0_pll_data.pll_1000 = 0xa6000000;
++	ath79_eth1_pll_data.pll_1000 = 0x03000101;
++
++	ap136_common_setup();
+ }
+ 
+ MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
+ 	     "Atheros AP136-010 reference board",
+-	     ap136_setup);
++	     ap136_010_setup);
++
++static void __init ap136_020_setup(void)
++{
++	/* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */
++	ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII;
++	ap136_ar8327_pad0_cfg.sgmii_delay_en = true;
++
++	/* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */
++	ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII;
++	ap136_ar8327_pad6_cfg.txclk_delay_en = true;
++	ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
++	ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
++	ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
++
++	ath79_eth0_pll_data.pll_1000 = 0x56000000;
++	ath79_eth1_pll_data.pll_1000 = 0x03000101;
++
++	ap136_common_setup();
++}
++
++MIPS_MACHINE(ATH79_MACH_AP136_020, "AP136-020",
++	     "Atheros AP136-020 reference board",
++	     ap136_020_setup);
++
++/*
++ * AP135-020 is similar to AP136-020, any future AP135 specific init
++ * code can be added here.
++ */
++static void __init ap135_020_setup(void)
++{
++	ap136_leds_gpio[0].name = "ap135:green:status";
++	ap136_leds_gpio[1].name = "ap135:red:status";
++	ap136_leds_gpio[2].name = "ap135:green:wps";
++	ap136_leds_gpio[3].name = "ap135:red:wps";
++	ap136_leds_gpio[4].name = "ap135:red:wlan-2g";
++	ap136_leds_gpio[5].name = "ap135:red:usb";
++
++	ap136_020_setup();
++}
++
++MIPS_MACHINE(ATH79_MACH_AP135_020, "AP135-020",
++	     "Atheros AP135-020 reference board",
++	     ap135_020_setup);
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -18,7 +18,9 @@ enum ath79_mach_type {
+ 	ATH79_MACH_GENERIC = 0,
+ 	ATH79_MACH_AP121,		/* Atheros AP121 reference board */
+ 	ATH79_MACH_AP121_MINI,		/* Atheros AP121-MINI reference board */
++	ATH79_MACH_AP135_020,		/* Atheros AP135-020 reference board */
+ 	ATH79_MACH_AP136_010,		/* Atheros AP136-010 reference board */
++	ATH79_MACH_AP136_020,		/* Atheros AP136-020 reference board */
+ 	ATH79_MACH_AP81,		/* Atheros AP81 reference board */
+ 	ATH79_MACH_DB120,		/* Atheros DB120 reference board */
+ 	ATH79_MACH_PB44,		/* Atheros PB44 reference board */
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -16,16 +16,17 @@ config ATH79_MACH_AP121
+ 	  Atheros AP121 reference board.
+ 
+ config ATH79_MACH_AP136
+-	bool "Atheros AP136 reference board"
++	bool "Atheros AP136/AP135 reference board"
+ 	select SOC_QCA955X
+ 	select ATH79_DEV_GPIO_BUTTONS
+ 	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_NFC
+ 	select ATH79_DEV_SPI
+ 	select ATH79_DEV_USB
+ 	select ATH79_DEV_WMAC
+ 	help
+ 	  Say 'Y' here if you want your kernel to support the
+-	  Atheros AP136 reference board.
++	  Atheros AP136 or AP135 reference boards.
+ 
+ config ATH79_MACH_AP81
+ 	bool "Atheros AP81 reference board"
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/610-MIPS-ath79-openwrt-machines.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/610-MIPS-ath79-openwrt-machines.patch.svn-base
new file mode 100644
index 0000000..73253bb
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/610-MIPS-ath79-openwrt-machines.patch.svn-base
@@ -0,0 +1,854 @@
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -16,22 +16,112 @@
+ 
+ enum ath79_mach_type {
+ 	ATH79_MACH_GENERIC = 0,
++	ATH79_MACH_ALFA_AP96,		/* ALFA Network AP96 board */
++	ATH79_MACH_ALFA_NX,		/* ALFA Network N2/N5 board */
++	ATH79_MACH_ALL0258N,		/* Allnet ALL0258N */
++	ATH79_MACH_ALL0305,		/* Allnet ALL0305 */
++	ATH79_MACH_ALL0315N,		/* Allnet ALL0315N */
++	ATH79_MACH_AP113,		/* Atheros AP113 reference board */
+ 	ATH79_MACH_AP121,		/* Atheros AP121 reference board */
+ 	ATH79_MACH_AP121_MINI,		/* Atheros AP121-MINI reference board */
+ 	ATH79_MACH_AP135_020,		/* Atheros AP135-020 reference board */
+ 	ATH79_MACH_AP136_010,		/* Atheros AP136-010 reference board */
+ 	ATH79_MACH_AP136_020,		/* Atheros AP136-020 reference board */
+ 	ATH79_MACH_AP81,		/* Atheros AP81 reference board */
++	ATH79_MACH_AP83,		/* Atheros AP83 */
++	ATH79_MACH_AP96,		/* Atheros AP96 */
++	ATH79_MACH_AW_NR580,		/* AzureWave AW-NR580 */
++	ATH79_MACH_CAP4200AG,		/* Senao CAP4200AG */
+ 	ATH79_MACH_DB120,		/* Atheros DB120 reference board */
+ 	ATH79_MACH_PB44,		/* Atheros PB44 reference board */
++	ATH79_MACH_DIR_600_A1,		/* D-Link DIR-600 rev. A1 */
++	ATH79_MACH_DIR_615_C1,		/* D-Link DIR-615 rev. C1 */
++	ATH79_MACH_DIR_615_E4,		/* D-Link DIR-615 rev. E4 */
++	ATH79_MACH_DIR_825_B1,		/* D-Link DIR-825 rev. B1 */
++	ATH79_MACH_EW_DORIN,		/* embedded wireless Dorin Platform */
++	ATH79_MACH_EW_DORIN_ROUTER,	/* embedded wireless Dorin Router Platform */
++	ATH79_MACH_EAP7660D,		/* Senao EAP7660D */
++	ATH79_MACH_JA76PF,		/* jjPlus JA76PF */
++	ATH79_MACH_JA76PF2,		/* jjPlus JA76PF2 */
++	ATH79_MACH_JWAP003,		/* jjPlus JWAP003 */
++	ATH79_MACH_HORNET_UB,		/* ALFA Networks Hornet-UB */
++	ATH79_MACH_MR600,		/* OpenMesh MR600 */
++	ATH79_MACH_MZK_W04NU,		/* Planex MZK-W04NU */
++	ATH79_MACH_MZK_W300NH,		/* Planex MZK-W300NH */
++	ATH79_MACH_NBG460N,		/* Zyxel NBG460N/550N/550NH */
++	ATH79_MACH_OM2P_HS,		/* OpenMesh OM2P-HS */
++	ATH79_MACH_OM2P_LC,		/* OpenMesh OM2P-LC */
++	ATH79_MACH_OM2P,		/* OpenMesh OM2P */
++	ATH79_MACH_PB42,		/* Atheros PB42 */
++	ATH79_MACH_PB92,		/* Atheros PB92 */
++	ATH79_MACH_RB_411,		/* MikroTik RouterBOARD 411/411A/411AH */
++	ATH79_MACH_RB_411U,		/* MikroTik RouterBOARD 411U */
++	ATH79_MACH_RB_433,		/* MikroTik RouterBOARD 433/433AH */
++	ATH79_MACH_RB_433U,		/* MikroTik RouterBOARD 433UAH */
++	ATH79_MACH_RB_435G,		/* MikroTik RouterBOARD 435G */
++	ATH79_MACH_RB_450G,		/* MikroTik RouterBOARD 450G */
++	ATH79_MACH_RB_450,		/* MikroTik RouterBOARD 450 */
++	ATH79_MACH_RB_493,		/* Mikrotik RouterBOARD 493/493AH */
++	ATH79_MACH_RB_493G,		/* Mikrotik RouterBOARD 493G */
++	ATH79_MACH_RB_750,		/* MikroTik RouterBOARD 750 */
++	ATH79_MACH_RB_750G_R3,		/* MikroTik RouterBOARD 750GL */
++	ATH79_MACH_RB_751,		/* MikroTik RouterBOARD 751 */
++	ATH79_MACH_RB_751G,		/* Mikrotik RouterBOARD 751G */
++	ATH79_MACH_RB_2011G,		/* Mikrotik RouterBOARD 2011UAS-2HnD */
++	ATH79_MACH_RB_2011L,		/* Mikrotik RouterBOARD 2011L */
++	ATH79_MACH_RW2458N,		/* Redwave RW2458N */
++	ATH79_MACH_TEW_632BRP,		/* TRENDnet TEW-632BRP */
++	ATH79_MACH_TEW_673GRU,		/* TRENDnet TEW-673GRU */
++	ATH79_MACH_TEW_712BR,		/* TRENDnet TEW-712BR */
++	ATH79_MACH_TL_MR11U,		/* TP-LINK TL-MR11U */
++	ATH79_MACH_TL_MR3020,		/* TP-LINK TL-MR3020 */
++	ATH79_MACH_TL_MR3040,		/* TP-LINK TL-MR3040 */
++	ATH79_MACH_TL_MR3220,		/* TP-LINK TL-MR3220 */
++	ATH79_MACH_TL_MR3220_V2,	/* TP-LINK TL-MR3220 v2 */
++	ATH79_MACH_TL_MR3420,		/* TP-LINK TL-MR3420 */
++	ATH79_MACH_TL_WA7510N_V1,	/* TP-LINK TL-WA7510N v1*/
++	ATH79_MACH_TL_WA901ND,		/* TP-LINK TL-WA901ND */
++	ATH79_MACH_TL_WA901ND_V2,	/* TP-LINK TL-WA901ND v2 */
++	ATH79_MACH_TL_WDR4300,		/* TP-LINK TL-WDR4300 */
++	ATH79_MACH_TL_WR1041N_V2,	/* TP-LINK TL-WR1041N v2 */
++	ATH79_MACH_TL_WR1043ND,		/* TP-LINK TL-WR1043ND */
++	ATH79_MACH_TL_WR2543N,		/* TP-LINK TL-WR2543N/ND */
++	ATH79_MACH_TL_WR703N,		/* TP-LINK TL-WR703N */
++	ATH79_MACH_TL_WR741ND,		/* TP-LINK TL-WR741ND */
++	ATH79_MACH_TL_WR741ND_V4,	/* TP-LINK TL-WR741ND  v4*/
++	ATH79_MACH_TL_WR841N_V1,	/* TP-LINK TL-WR841N v1 */
++	ATH79_MACH_TL_WR841N_V7,	/* TP-LINK TL-WR841N/ND v7 */
++	ATH79_MACH_TL_WR841N_V8,	/* TP-LINK TL-WR841N/ND v8 */
++	ATH79_MACH_TL_WR941ND,		/* TP-LINK TL-WR941ND */
+ 	ATH79_MACH_UBNT_AIRROUTER,	/* Ubiquiti AirRouter */
+ 	ATH79_MACH_UBNT_BULLET_M,	/* Ubiquiti Bullet M */
++	ATH79_MACH_UBNT_LSSR71,		/* Ubiquiti LS-SR71 */
++	ATH79_MACH_UBNT_LSX,		/* Ubiquiti LSX */
+ 	ATH79_MACH_UBNT_NANO_M, 	/* Ubiquiti NanoStation M */
+ 	ATH79_MACH_UBNT_ROCKET_M,	/* Ubiquiti Rocket M */
++	ATH79_MACH_UBNT_RSPRO,		/* Ubiquiti RouterStation Pro */
++	ATH79_MACH_UBNT_RS,		/* Ubiquiti RouterStation */
+ 	ATH79_MACH_UBNT_UAP_PRO,	/* Ubiquiti UniFi AP Pro */
+ 	ATH79_MACH_UBNT_UNIFI, 		/* Ubiquiti Unifi */
+ 	ATH79_MACH_UBNT_UNIFI_OUTDOOR,	/* Ubiquiti UnifiAP Outdoor */
+ 	ATH79_MACH_UBNT_XM,		/* Ubiquiti Networks XM board rev 1.0 */
++	ATH79_MACH_WHR_G301N,		/* Buffalo WHR-G301N */
++	ATH79_MACH_WHR_HP_G300N,	/* Buffalo WHR-HP-G300N */
++	ATH79_MACH_WHR_HP_GN,		/* Buffalo WHR-HP-GN */
++	ATH79_MACH_WLAE_AG300N,		/* Buffalo WLAE-AG300N */
++	ATH79_MACH_WNDR3700,		/* NETGEAR WNDR3700/WNDR3800/WNDRMAC */
++	ATH79_MACH_WNDR4300,		/* NETGEAR WNDR4300 */
++	ATH79_MACH_WNR2000,		/* NETGEAR WNR2000 */
++	ATH79_MACH_WP543,		/* Compex WP543 */
++	ATH79_MACH_WPE72,		/* Compex WPE72 */
++	ATH79_MACH_WRT160NL,		/* Linksys WRT160NL */
++	ATH79_MACH_WRT400N,		/* Linksys WRT400N */
++	ATH79_MACH_WZR_HP_AG300H,	/* Buffalo WZR-HP-AG300H */
++	ATH79_MACH_WZR_HP_G300NH,	/* Buffalo WZR-HP-G300NH */
++	ATH79_MACH_WZR_HP_G300NH2,	/* Buffalo WZR-HP-G300NH2 */
++	ATH79_MACH_WZR_HP_G450H,	/* Buffalo WZR-HP-G450H */
++	ATH79_MACH_ZCN_1523H_2,		/* Zcomax ZCN-1523H-2-xx */
++	ATH79_MACH_ZCN_1523H_5,		/* Zcomax ZCN-1523H-5-xx */
+ };
+ 
+ #endif /* _ATH79_MACHTYPE_H */
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -2,6 +2,61 @@ if ATH79
+ 
+ menu "Atheros AR71XX/AR724X/AR913X machine selection"
+ 
++config ATH79_MACH_ALFA_AP96
++	bool "ALFA Network AP96 board support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_SPI
++	select ATH79_DEV_USB
++
++config ATH79_MACH_HORNET_UB
++	bool "ALFA Network Hornet-UB board support"
++	select SOC_AR933X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_ALFA_NX
++	bool "ALFA Network N2/N5 board support"
++	select SOC_AR724X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_ALL0258N
++	bool "Allnet ALL0258N support"
++	select SOC_AR724X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_ALL0315N
++	bool "Allnet ALL0315N support"
++	select SOC_AR724X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_AP113
++	bool "Atheros AP113 board support"
++	select SOC_AR724X
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_PB9X_PCI if PCI
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_USB
++	select ATH79_DEV_ETH
++
+ config ATH79_MACH_AP121
+ 	bool "Atheros AP121 reference board"
+ 	select SOC_AR933X
+@@ -41,6 +96,24 @@ config ATH79_MACH_AP81
+ 	  Say 'Y' here if you want your kernel to support the
+ 	  Atheros AP81 reference board.
+ 
++config ATH79_MACH_AP83
++	bool "Atheros AP83 board support"
++	select SOC_AR913X
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_AP96
++	bool "Atheros AP96 board support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
+ config ATH79_MACH_DB120
+ 	bool "Atheros DB120 reference board"
+ 	select SOC_AR934X
+@@ -56,6 +129,13 @@ config ATH79_MACH_DB120
+ 	  Say 'Y' here if you want your kernel to support the
+ 	  Atheros DB120 reference board.
+ 
++config ATH79_MACH_PB42
++	bool "Atheros PB42 board support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_M25P80
++
+ config ATH79_MACH_PB44
+ 	bool "Atheros PB44 reference board"
+ 	select SOC_AR71XX
+@@ -68,6 +148,488 @@ config ATH79_MACH_PB44
+ 	  Say 'Y' here if you want your kernel to support the
+ 	  Atheros PB44 reference board.
+ 
++config ATH79_MACH_PB92
++	bool "Atheros PB92 board support"
++	select SOC_AR724X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_PB9X_PCI if PCI
++	select ATH79_DEV_USB
++
++config ATH79_MACH_AW_NR580
++	bool "AzureWave AW-NR580 board support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_WHR_HP_G300N
++	bool "Buffalo WHR-HP-G300N board support"
++	select SOC_AR724X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_WLAE_AG300N
++	bool "Buffalo WLAE-AG300N board support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_WZR_HP_AG300H
++	bool "Buffalo WZR-HP-AG300H board support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
++config ATH79_MACH_WZR_HP_G300NH
++	bool "Buffalo WZR-HP-G300NH board support"
++	select SOC_AR913X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++	select RTL8366_SMI
++
++config ATH79_MACH_WZR_HP_G300NH2
++	bool "Buffalo WZR-HP-G300NH2 board support"
++	select SOC_AR724X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
++config ATH79_MACH_WZR_HP_G450H
++	bool "Buffalo WZR-HP-G450H board support"
++	select SOC_AR724X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
++config ATH79_MACH_WP543
++	bool "Compex WP543/WPJ543 board support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select MYLOADER
++
++config ATH79_MACH_WPE72
++	bool "Compex WPE72/WPE72NX board support"
++	select SOC_AR724X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select MYLOADER
++
++config ATH79_MACH_DIR_600_A1
++	bool "D-Link DIR-600 A1/DIR-615 E4 support"
++	select SOC_AR724X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_NVRAM
++
++config ATH79_MACH_DIR_615_C1
++	bool "D-Link DIR-615 rev. C1 support"
++	select SOC_AR913X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++	select ATH79_NVRAM
++
++config ATH79_MACH_DIR_825_B1
++	bool "D-Link DIR-825 rev. B1 board support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
++config ATH79_MACH_EW_DORIN
++	bool "embedded wireless Dorin Platform support"
++	select SOC_AR933X
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_WMAC
++	select ATH79_DEV_ETH
++	help
++	  Say 'Y' here if you want your kernel to support the
++	  Dorin Platform from www.80211.de .
++
++config ATH79_MACH_JA76PF
++	bool "jjPlus JA76PF board support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
++config ATH79_MACH_JWAP003
++	bool "jjPlus JWAP003 board support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
++config ATH79_MACH_WRT160NL
++	bool "Linksys WRT160NL board support"
++	select SOC_AR913X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++	select ATH79_NVRAM
++
++config ATH79_MACH_WRT400N
++	bool "Linksys WRT400N board support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_RB4XX
++	bool "MikroTik RouterBOARD 4xx series support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_USB
++
++config ATH79_MACH_RB750
++	bool "MikroTik RouterBOARD 750 support"
++	select SOC_AR724X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_USB
++	select ATH79_ROUTERBOOT
++	select RLE_DECOMPRESS
++
++config ATH79_MACH_RB2011
++	bool "MikroTik RouterBOARD 2011 support"
++	select SOC_AR934x
++	select ATH79_DEV_ETH
++	select ATH79_DEV_NFC
++	select ATH79_DEV_WMAC
++	select ATH79_ROUTERBOOT
++
++config ATH79_MACH_WNDR3700
++	bool "NETGEAR WNDR3700 board support"
++	select SOC_AR71XX
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
++config ATH79_MACH_WNDR4300
++	bool "NETGEAR WNDR4300 board support"
++	select SOC_AR934X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_NFC
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_WNR2000
++	bool "NETGEAR WNR2000 board support"
++	select SOC_AR913X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_OM2P
++	bool "OpenMesh OM2P board support"
++	select SOC_AR724X
++	select SOC_AR933X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_MR600
++	bool "OpenMesh MR600 board support"
++	select SOC_AR934X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_MZK_W04NU
++	bool "Planex MZK-W04NU board support"
++	select SOC_AR913X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_MZK_W300NH
++	bool "Planex MZK-W300NH board support"
++	select SOC_AR913X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_RW2458N
++	bool "Redwave RW2458N board support"
++	select SOC_AR724X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
++config ATH79_MACH_CAP4200AG
++	bool "Senao CAP4200AG support"
++	select SOC_AR934X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_EAP7660D
++	bool "Senao EAP7660D support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_TL_MR11U
++	bool "TP-LINK TL-MR11U/TL-MR3040 support"
++	select SOC_AR933X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_MR3020
++	bool "TP-LINK TL-MR3020 support"
++	select SOC_AR933X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_MR3X20
++	bool "TP-LINK TL-MR3220/3420 support"
++	select SOC_AR724X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
++config ATH79_MACH_TL_WA901ND
++	bool "TP-LINK TL-WA901ND/TL-WA7510N support"
++	select SOC_AR724X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_TL_WA901ND_V2
++	bool "TP-LINK TL-WA901ND v2 support"
++	select SOC_AR913X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WDR4300
++	bool "TP-LINK TL-WDR3600/4300/4310 board support"
++	select SOC_AR934X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR703N
++	bool "TP-LINK TL-WR703N support"
++	select SOC_AR933X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR741ND
++	bool "TP-LINK TL-WR741ND support"
++	select SOC_AR724X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_TL_WR741ND_V4
++	bool "TP-LINK TL-WR741ND v4/TL-MR3220 v2 support"
++	select SOC_AR933X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR841N_V1
++	bool "TP-LINK TL-WR841N v1 support"
++	select SOC_AR71XX
++	select ATH79_DEV_DSA
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_TL_WR841N_V8
++	bool "TP-LINK TL-WR841N/ND v8 support"
++	select SOC_AR934X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR941ND
++	bool "TP-LINK TL-WR941ND support"
++	select SOC_AR913X
++	select ATH79_DEV_DSA
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR1041N_V2
++	bool "TP-LINK TL-WR1041N v2 support"
++	select SOC_AR934X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR1043ND
++	bool "TP-LINK TL-WR1043ND support"
++	select SOC_AR913X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR2543N
++	bool "TP-LINK TL-WR2543N/ND support"
++	select SOC_AR724X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
++config ATH79_MACH_TEW_632BRP
++	bool "TRENDnet TEW-632BRP support"
++	select SOC_AR913X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++	select ATH79_NVRAM
++
++config ATH79_MACH_TEW_673GRU
++	bool "TRENDnet TEW-673GRU support"
++	select SOC_AR71XX
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_NVRAM
++
++config ATH79_MACH_TEW_712BR
++	bool "TRENDnet TEW-712BR support"
++	select SOC_AR933X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++	select ATH79_NVRAM
++
++config ATH79_MACH_UBNT
++	bool "Ubiquiti AR71xx based boards support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
+ config ATH79_MACH_UBNT_XM
+ 	bool "Ubiquiti Networks XM/UniFi boards"
+ 	select SOC_AR724X
+@@ -83,6 +645,24 @@ config ATH79_MACH_UBNT_XM
+ 	  Say 'Y' here if you want your kernel to support the
+ 	  Ubiquiti Networks XM (rev 1.0) board.
+ 
++config ATH79_MACH_ZCN_1523H
++	bool "Zcomax ZCN-1523H support"
++	select SOC_AR724X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_NBG460N
++	bool "Zyxel NBG460N/550N/550NH board support"
++	select SOC_AR913X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++
+ endmenu
+ 
+ config SOC_AR71XX
+@@ -118,10 +698,6 @@ config SOC_QCA955X
+ 	select PCI_AR724X if PCI
+ 	def_bool n
+ 
+-config ATH79_DEV_M25P80
+-	select ATH79_DEV_SPI
+-	def_bool n
+-
+ config ATH79_DEV_AP9X_PCI
+ 	select ATH79_PCI_ATH9K_FIXUP
+ 	def_bool n
+@@ -132,7 +708,14 @@ config ATH79_DEV_DSA
+ config ATH79_DEV_ETH
+ 	def_bool n
+ 
+-config PCI_AR724X
++config ATH79_DEV_M25P80
++	select ATH79_DEV_SPI
++	def_bool n
++
++config ATH79_DEV_DSA
++	def_bool n
++
++config ATH79_DEV_ETH
+ 	def_bool n
+ 
+ config ATH79_DEV_GPIO_BUTTONS
+@@ -164,4 +747,7 @@ config ATH79_PCI_ATH9K_FIXUP
+ config ATH79_ROUTERBOOT
+ 	def_bool n
+ 
++config PCI_AR724X
++	def_bool n
++
+ endif
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -38,9 +38,71 @@ obj-$(CONFIG_ATH79_ROUTERBOOT)		+= route
+ #
+ # Machines
+ #
++obj-$(CONFIG_ATH79_MACH_ALFA_AP96)	+= mach-alfa-ap96.o
++obj-$(CONFIG_ATH79_MACH_ALFA_NX)	+= mach-alfa-nx.o
++obj-$(CONFIG_ATH79_MACH_ALL0258N)	+= mach-all0258n.o
++obj-$(CONFIG_ATH79_MACH_ALL0315N)	+= mach-all0315n.o
++obj-$(CONFIG_ATH79_MACH_AP113)		+= mach-ap113.o
+ obj-$(CONFIG_ATH79_MACH_AP121)		+= mach-ap121.o
+ obj-$(CONFIG_ATH79_MACH_AP136)		+= mach-ap136.o
+ obj-$(CONFIG_ATH79_MACH_AP81)		+= mach-ap81.o
++obj-$(CONFIG_ATH79_MACH_AP83)		+= mach-ap83.o
++obj-$(CONFIG_ATH79_MACH_AP96)		+= mach-ap96.o
++obj-$(CONFIG_ATH79_MACH_AW_NR580)	+= mach-aw-nr580.o
++obj-$(CONFIG_ATH79_MACH_CAP4200AG)	+= mach-cap4200ag.o
+ obj-$(CONFIG_ATH79_MACH_DB120)		+= mach-db120.o
++obj-$(CONFIG_ATH79_MACH_DIR_600_A1)	+= mach-dir-600-a1.o
++obj-$(CONFIG_ATH79_MACH_DIR_615_C1)	+= mach-dir-615-c1.o
++obj-$(CONFIG_ATH79_MACH_DIR_825_B1)	+= mach-dir-825-b1.o
++obj-$(CONFIG_ATH79_MACH_EW_DORIN)	+= mach-ew-dorin.o
++obj-$(CONFIG_ATH79_MACH_EAP7660D)	+= mach-eap7660d.o
++obj-$(CONFIG_ATH79_MACH_JA76PF)		+= mach-ja76pf.o
++obj-$(CONFIG_ATH79_MACH_JWAP003)	+= mach-jwap003.o
++obj-$(CONFIG_ATH79_MACH_HORNET_UB)	+= mach-hornet-ub.o
++obj-$(CONFIG_ATH79_MACH_MR600)		+= mach-mr600.o
++obj-$(CONFIG_ATH79_MACH_MZK_W04NU)	+= mach-mzk-w04nu.o
++obj-$(CONFIG_ATH79_MACH_MZK_W300NH)	+= mach-mzk-w300nh.o
++obj-$(CONFIG_ATH79_MACH_NBG460N)	+= mach-nbg460n.o
++obj-$(CONFIG_ATH79_MACH_OM2P)		+= mach-om2p.o
++obj-$(CONFIG_ATH79_MACH_PB42)		+= mach-pb42.o
+ obj-$(CONFIG_ATH79_MACH_PB44)		+= mach-pb44.o
++obj-$(CONFIG_ATH79_MACH_PB92)		+= mach-pb92.o
++obj-$(CONFIG_ATH79_MACH_RB4XX)		+= mach-rb4xx.o
++obj-$(CONFIG_ATH79_MACH_RB750)		+= mach-rb750.o
++obj-$(CONFIG_ATH79_MACH_RB2011)		+= mach-rb2011.o
++obj-$(CONFIG_ATH79_MACH_RW2458N)	+= mach-rw2458n.o
++obj-$(CONFIG_ATH79_MACH_TEW_632BRP)	+= mach-tew-632brp.o
++obj-$(CONFIG_ATH79_MACH_TEW_673GRU)	+= mach-tew-673gru.o
++obj-$(CONFIG_ATH79_MACH_TEW_712BR)	+= mach-tew-712br.o
++obj-$(CONFIG_ATH79_MACH_TL_MR11U)	+= mach-tl-mr11u.o
++obj-$(CONFIG_ATH79_MACH_TL_MR3020)	+= mach-tl-mr3020.o
++obj-$(CONFIG_ATH79_MACH_TL_MR3X20)	+= mach-tl-mr3x20.o
++obj-$(CONFIG_ATH79_MACH_TL_WA901ND)	+= mach-tl-wa901nd.o
++obj-$(CONFIG_ATH79_MACH_TL_WA901ND_V2)	+= mach-tl-wa901nd-v2.o
++obj-$(CONFIG_ATH79_MACH_TL_WDR4300)     += mach-tl-wdr4300.o
++obj-$(CONFIG_ATH79_MACH_TL_WR741ND)	+= mach-tl-wr741nd.o
++obj-$(CONFIG_ATH79_MACH_TL_WR741ND_V4)	+= mach-tl-wr741nd-v4.o
++obj-$(CONFIG_ATH79_MACH_TL_WR841N_V1)	+= mach-tl-wr841n.o
++obj-$(CONFIG_ATH79_MACH_TL_WR841N_V8)	+= mach-tl-wr841n-v8.o
++obj-$(CONFIG_ATH79_MACH_TL_WR941ND)	+= mach-tl-wr941nd.o
++obj-$(CONFIG_ATH79_MACH_TL_WR1041N_V2)	+= mach-tl-wr1041n-v2.o
++obj-$(CONFIG_ATH79_MACH_TL_WR1043ND)	+= mach-tl-wr1043nd.o
++obj-$(CONFIG_ATH79_MACH_TL_WR2543N)	+= mach-tl-wr2543n.o
++obj-$(CONFIG_ATH79_MACH_TL_WR703N)	+= mach-tl-wr703n.o
++obj-$(CONFIG_ATH79_MACH_UBNT)		+= mach-ubnt.o
+ obj-$(CONFIG_ATH79_MACH_UBNT_XM)	+= mach-ubnt-xm.o
++obj-$(CONFIG_ATH79_MACH_WHR_HP_G300N)	+= mach-whr-hp-g300n.o
++obj-$(CONFIG_ATH79_MACH_WLAE_AG300N)	+= mach-wlae-ag300n.o
++obj-$(CONFIG_ATH79_MACH_WNDR3700)	+= mach-wndr3700.o
++obj-$(CONFIG_ATH79_MACH_WNDR4300)	+= mach-wndr4300.o
++obj-$(CONFIG_ATH79_MACH_WNR2000)	+= mach-wnr2000.o
++obj-$(CONFIG_ATH79_MACH_WP543)		+= mach-wp543.o
++obj-$(CONFIG_ATH79_MACH_WPE72)		+= mach-wpe72.o
++obj-$(CONFIG_ATH79_MACH_WRT160NL)	+= mach-wrt160nl.o
++obj-$(CONFIG_ATH79_MACH_WRT400N)	+= mach-wrt400n.o
++obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH)	+= mach-wzr-hp-g300nh.o
++obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH2)	+= mach-wzr-hp-g300nh2.o
++obj-$(CONFIG_ATH79_MACH_WZR_HP_AG300H)	+= mach-wzr-hp-ag300h.o
++obj-$(CONFIG_ATH79_MACH_WZR_HP_G450H)	+= mach-wzr-hp-g450h.o
++obj-$(CONFIG_ATH79_MACH_ZCN_1523H)	+= mach-zcn-1523h.o
++
+--- a/arch/mips/ath79/prom.c
++++ b/arch/mips/ath79/prom.c
+@@ -180,6 +180,10 @@ void __init prom_init(void)
+ 			ath79_prom_append_cmdline("board", env);
+ 		}
+ 	}
++
++	if (strstr(arcs_cmdline, "board=750Gr3") ||
++	    strstr(arcs_cmdline, "board=2011L"))
++		ath79_prom_append_cmdline("console", "ttyS0,115200");
+ }
+ 
+ void __init prom_free_prom_memory(void)
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/611-MIPS-ath79-add-QCA9556-SoC-on-AP132.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/611-MIPS-ath79-add-QCA9556-SoC-on-AP132.patch.svn-base
new file mode 100644
index 0000000..8479ea3
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/611-MIPS-ath79-add-QCA9556-SoC-on-AP132.patch.svn-base
@@ -0,0 +1,41 @@
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -70,6 +70,18 @@ config ATH79_MACH_AP121
+ 	  Say 'Y' here if you want your kernel to support the
+ 	  Atheros AP121 reference board.
+ 
++config ATH79_MACH_AP132
++	bool "Atheros AP132 reference board"
++	select SOC_QCA955X
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_SPI
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++	help
++	  Say 'Y' here if you want your kernel to support the
++	  Atheros AP132 reference boards.
++
+ config ATH79_MACH_AP136
+ 	bool "Atheros AP136/AP135 reference board"
+ 	select SOC_QCA955X
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -24,6 +24,7 @@ enum ath79_mach_type {
+ 	ATH79_MACH_AP113,		/* Atheros AP113 reference board */
+ 	ATH79_MACH_AP121,		/* Atheros AP121 reference board */
+ 	ATH79_MACH_AP121_MINI,		/* Atheros AP121-MINI reference board */
++	ATH79_MACH_AP132,		/* Atheros AP132 reference board */
+ 	ATH79_MACH_AP135_020,		/* Atheros AP135-020 reference board */
+ 	ATH79_MACH_AP136_010,		/* Atheros AP136-010 reference board */
+ 	ATH79_MACH_AP136_020,		/* Atheros AP136-020 reference board */
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -44,6 +44,7 @@ obj-$(CONFIG_ATH79_MACH_ALL0258N)	+= mac
+ obj-$(CONFIG_ATH79_MACH_ALL0315N)	+= mach-all0315n.o
+ obj-$(CONFIG_ATH79_MACH_AP113)		+= mach-ap113.o
+ obj-$(CONFIG_ATH79_MACH_AP121)		+= mach-ap121.o
++obj-$(CONFIG_ATH79_MACH_AP132)		+= mach-ap132.o
+ obj-$(CONFIG_ATH79_MACH_AP136)		+= mach-ap136.o
+ obj-$(CONFIG_ATH79_MACH_AP81)		+= mach-ap81.o
+ obj-$(CONFIG_ATH79_MACH_AP83)		+= mach-ap83.o
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/612-MIPS-ath79-add-DIR-825-C1-support.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/612-MIPS-ath79-add-DIR-825-C1-support.patch.svn-base
new file mode 100644
index 0000000..cacc2d3
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/612-MIPS-ath79-add-DIR-825-C1-support.patch.svn-base
@@ -0,0 +1,41 @@
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -39,6 +39,8 @@ enum ath79_mach_type {
+ 	ATH79_MACH_DIR_615_C1,		/* D-Link DIR-615 rev. C1 */
+ 	ATH79_MACH_DIR_615_E4,		/* D-Link DIR-615 rev. E4 */
+ 	ATH79_MACH_DIR_825_B1,		/* D-Link DIR-825 rev. B1 */
++	ATH79_MACH_DIR_825_C1,		/* D-Link DIR-825 rev. C1 */
++	ATH79_MACH_DIR_835_A1,		/* D-Link DIR-835 rev. A1 */
+ 	ATH79_MACH_EW_DORIN,		/* embedded wireless Dorin Platform */
+ 	ATH79_MACH_EW_DORIN_ROUTER,	/* embedded wireless Dorin Router Platform */
+ 	ATH79_MACH_EAP7660D,		/* Senao EAP7660D */
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -283,6 +283,17 @@ config ATH79_MACH_DIR_825_B1
+ 	select ATH79_DEV_M25P80
+ 	select ATH79_DEV_USB
+ 
++config ATH79_MACH_DIR_825_C1
++	bool "D-Link DIR-825 rev. C1/DIR-835 rev. A1 board support"
++	select SOC_AR934X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
+ config ATH79_MACH_EW_DORIN
+ 	bool "embedded wireless Dorin Platform support"
+ 	select SOC_AR933X
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -55,6 +55,7 @@ obj-$(CONFIG_ATH79_MACH_DB120)		+= mach-
+ obj-$(CONFIG_ATH79_MACH_DIR_600_A1)	+= mach-dir-600-a1.o
+ obj-$(CONFIG_ATH79_MACH_DIR_615_C1)	+= mach-dir-615-c1.o
+ obj-$(CONFIG_ATH79_MACH_DIR_825_B1)	+= mach-dir-825-b1.o
++obj-$(CONFIG_ATH79_MACH_DIR_825_C1)	+= mach-dir-825-c1.o
+ obj-$(CONFIG_ATH79_MACH_EW_DORIN)	+= mach-ew-dorin.o
+ obj-$(CONFIG_ATH79_MACH_EAP7660D)	+= mach-eap7660d.o
+ obj-$(CONFIG_ATH79_MACH_JA76PF)		+= mach-ja76pf.o
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/613-MIPS-ath79-add-TL-WDR3500-support.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/613-MIPS-ath79-add-TL-WDR3500-support.patch.svn-base
new file mode 100644
index 0000000..214e453
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/613-MIPS-ath79-add-TL-WDR3500-support.patch.svn-base
@@ -0,0 +1,40 @@
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -85,6 +85,7 @@ enum ath79_mach_type {
+ 	ATH79_MACH_TL_WA7510N_V1,	/* TP-LINK TL-WA7510N v1*/
+ 	ATH79_MACH_TL_WA901ND,		/* TP-LINK TL-WA901ND */
+ 	ATH79_MACH_TL_WA901ND_V2,	/* TP-LINK TL-WA901ND v2 */
++	ATH79_MACH_TL_WDR3500,		/* TP-LINK TL-WDR3500 */
+ 	ATH79_MACH_TL_WDR4300,		/* TP-LINK TL-WDR4300 */
+ 	ATH79_MACH_TL_WR1041N_V2,	/* TP-LINK TL-WR1041N v2 */
+ 	ATH79_MACH_TL_WR1043ND,		/* TP-LINK TL-WR1043ND */
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -514,6 +514,17 @@ config ATH79_MACH_TL_WA901ND_V2
+ 	select ATH79_DEV_M25P80
+ 	select ATH79_DEV_WMAC
+ 
++config ATH79_MACH_TL_WDR3500
++	bool "TP-LINK TL-WDR3500 board support"
++	select SOC_AR934X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
+ config ATH79_MACH_TL_WDR4300
+ 	bool "TP-LINK TL-WDR3600/4300/4310 board support"
+ 	select SOC_AR934X
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -81,6 +81,7 @@ obj-$(CONFIG_ATH79_MACH_TL_MR3020)	+= ma
+ obj-$(CONFIG_ATH79_MACH_TL_MR3X20)	+= mach-tl-mr3x20.o
+ obj-$(CONFIG_ATH79_MACH_TL_WA901ND)	+= mach-tl-wa901nd.o
+ obj-$(CONFIG_ATH79_MACH_TL_WA901ND_V2)	+= mach-tl-wa901nd-v2.o
++obj-$(CONFIG_ATH79_MACH_TL_WDR3500)     += mach-tl-wdr3500.o
+ obj-$(CONFIG_ATH79_MACH_TL_WDR4300)     += mach-tl-wdr4300.o
+ obj-$(CONFIG_ATH79_MACH_TL_WR741ND)	+= mach-tl-wr741nd.o
+ obj-$(CONFIG_ATH79_MACH_TL_WR741ND_V4)	+= mach-tl-wr741nd-v4.o
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/614-MIPS-ath79-MR600v2-support.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/614-MIPS-ath79-MR600v2-support.patch.svn-base
new file mode 100644
index 0000000..cc89d81
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/614-MIPS-ath79-MR600v2-support.patch.svn-base
@@ -0,0 +1,10 @@
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -48,6 +48,7 @@ enum ath79_mach_type {
+ 	ATH79_MACH_JA76PF2,		/* jjPlus JA76PF2 */
+ 	ATH79_MACH_JWAP003,		/* jjPlus JWAP003 */
+ 	ATH79_MACH_HORNET_UB,		/* ALFA Networks Hornet-UB */
++	ATH79_MACH_MR600V2,		/* OpenMesh MR600v2 */
+ 	ATH79_MACH_MR600,		/* OpenMesh MR600 */
+ 	ATH79_MACH_MZK_W04NU,		/* Planex MZK-W04NU */
+ 	ATH79_MACH_MZK_W300NH,		/* Planex MZK-W300NH */
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/615-MIPS-ath79-RB951G-support.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/615-MIPS-ath79-RB951G-support.patch.svn-base
new file mode 100644
index 0000000..a2e558f
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/615-MIPS-ath79-RB951G-support.patch.svn-base
@@ -0,0 +1,49 @@
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -71,6 +71,7 @@ enum ath79_mach_type {
+ 	ATH79_MACH_RB_750G_R3,		/* MikroTik RouterBOARD 750GL */
+ 	ATH79_MACH_RB_751,		/* MikroTik RouterBOARD 751 */
+ 	ATH79_MACH_RB_751G,		/* Mikrotik RouterBOARD 751G */
++	ATH79_MACH_RB_951G,		/* Mikrotik RouterBOARD 951G */
+ 	ATH79_MACH_RB_2011G,		/* Mikrotik RouterBOARD 2011UAS-2HnD */
+ 	ATH79_MACH_RB_2011L,		/* Mikrotik RouterBOARD 2011L */
+ 	ATH79_MACH_RW2458N,		/* Redwave RW2458N */
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -360,6 +360,16 @@ config ATH79_MACH_RB750
+ 	select ATH79_ROUTERBOOT
+ 	select RLE_DECOMPRESS
+ 
++config ATH79_MACH_RB95X
++       bool "MikroTik RouterBOARD 95X support"
++       select SOC_AR934x
++       select ATH79_DEV_ETH
++       select ATH79_DEV_NFC
++       select ATH79_DEV_WMAC
++       select ATH79_DEV_USB
++       select ATH79_ROUTERBOOT
++       select RLE_DECOMPRESS
++
+ config ATH79_MACH_RB2011
+ 	bool "MikroTik RouterBOARD 2011 support"
+ 	select SOC_AR934x
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -71,6 +71,7 @@ obj-$(CONFIG_ATH79_MACH_PB44)		+= mach-p
+ obj-$(CONFIG_ATH79_MACH_PB92)		+= mach-pb92.o
+ obj-$(CONFIG_ATH79_MACH_RB4XX)		+= mach-rb4xx.o
+ obj-$(CONFIG_ATH79_MACH_RB750)		+= mach-rb750.o
++obj-$(CONFIG_ATH79_MACH_RB95X)		+= mach-rb95x.o
+ obj-$(CONFIG_ATH79_MACH_RB2011)		+= mach-rb2011.o
+ obj-$(CONFIG_ATH79_MACH_RW2458N)	+= mach-rw2458n.o
+ obj-$(CONFIG_ATH79_MACH_TEW_632BRP)	+= mach-tew-632brp.o
+--- a/arch/mips/ath79/prom.c
++++ b/arch/mips/ath79/prom.c
+@@ -182,6 +182,7 @@ void __init prom_init(void)
+ 	}
+ 
+ 	if (strstr(arcs_cmdline, "board=750Gr3") ||
++	    strstr(arcs_cmdline, "board=951G") ||
+ 	    strstr(arcs_cmdline, "board=2011L"))
+ 		ath79_prom_append_cmdline("console", "ttyS0,115200");
+ }
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/616-MIPS-ath79-TL-MR3420-v2-support.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/616-MIPS-ath79-TL-MR3420-v2-support.patch.svn-base
new file mode 100644
index 0000000..855bb96
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/616-MIPS-ath79-TL-MR3420-v2-support.patch.svn-base
@@ -0,0 +1,27 @@
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -585,12 +585,13 @@ config ATH79_MACH_TL_WR841N_V1
+ 	select ATH79_DEV_M25P80
+ 
+ config ATH79_MACH_TL_WR841N_V8
+-	bool "TP-LINK TL-WR841N/ND v8 support"
++	bool "TP-LINK TL-WR841N/ND v8/TL-MR3420 v2 support"
+ 	select SOC_AR934X
+ 	select ATH79_DEV_ETH
+ 	select ATH79_DEV_GPIO_BUTTONS
+ 	select ATH79_DEV_LEDS_GPIO
+ 	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
+ 	select ATH79_DEV_WMAC
+ 
+ config ATH79_MACH_TL_WR941ND
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -84,6 +84,7 @@ enum ath79_mach_type {
+ 	ATH79_MACH_TL_MR3220,		/* TP-LINK TL-MR3220 */
+ 	ATH79_MACH_TL_MR3220_V2,	/* TP-LINK TL-MR3220 v2 */
+ 	ATH79_MACH_TL_MR3420,		/* TP-LINK TL-MR3420 */
++	ATH79_MACH_TL_MR3420_V2,	/* TP-LINK TL-MR3420 v2 */
+ 	ATH79_MACH_TL_WA7510N_V1,	/* TP-LINK TL-WA7510N v1*/
+ 	ATH79_MACH_TL_WA901ND,		/* TP-LINK TL-WA901ND */
+ 	ATH79_MACH_TL_WA901ND_V2,	/* TP-LINK TL-WA901ND v2 */
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/901-mdio_bitbang_ignore_ta_value.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/901-mdio_bitbang_ignore_ta_value.patch.svn-base
new file mode 100644
index 0000000..39584aa
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/901-mdio_bitbang_ignore_ta_value.patch.svn-base
@@ -0,0 +1,20 @@
+--- a/drivers/net/phy/mdio-bitbang.c
++++ b/drivers/net/phy/mdio-bitbang.c
+@@ -165,16 +165,7 @@ static int mdiobb_read(struct mii_bus *b
+ 
+ 	ctrl->ops->set_mdio_dir(ctrl, 0);
+ 
+-	/* check the turnaround bit: the PHY should be driving it to zero */
+-	if (mdiobb_get_bit(ctrl) != 0) {
+-		/* PHY didn't drive TA low -- flush any bits it
+-		 * may be trying to send.
+-		 */
+-		for (i = 0; i < 32; i++)
+-			mdiobb_get_bit(ctrl);
+-
+-		return 0xffff;
+-	}
++	mdiobb_get_bit(ctrl);
+ 
+ 	ret = mdiobb_get_num(ctrl, 16);
+ 	mdiobb_get_bit(ctrl);
diff --git a/target/linux/ar71xx/patches-3.8/.svn/text-base/902-unaligned_access_hacks.patch.svn-base b/target/linux/ar71xx/patches-3.8/.svn/text-base/902-unaligned_access_hacks.patch.svn-base
new file mode 100644
index 0000000..2426e07
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/.svn/text-base/902-unaligned_access_hacks.patch.svn-base
@@ -0,0 +1,789 @@
+--- a/arch/mips/include/asm/checksum.h
++++ b/arch/mips/include/asm/checksum.h
+@@ -104,26 +104,30 @@ static inline __sum16 ip_fast_csum(const
+ 	const unsigned int *stop = word + ihl;
+ 	unsigned int csum;
+ 	int carry;
++	unsigned int w;
+ 
+-	csum = word[0];
+-	csum += word[1];
+-	carry = (csum < word[1]);
++	csum = net_hdr_word(word++);
++
++	w = net_hdr_word(word++);
++	csum += w;
++	carry = (csum < w);
+ 	csum += carry;
+ 
+-	csum += word[2];
+-	carry = (csum < word[2]);
++	w = net_hdr_word(word++);
++	csum += w;
++	carry = (csum < w);
+ 	csum += carry;
+ 
+-	csum += word[3];
+-	carry = (csum < word[3]);
++	w = net_hdr_word(word++);
++	csum += w;
++	carry = (csum < w);
+ 	csum += carry;
+ 
+-	word += 4;
+ 	do {
+-		csum += *word;
+-		carry = (csum < *word);
++		w = net_hdr_word(word++);
++		csum += w;
++		carry = (csum < w);
+ 		csum += carry;
+-		word++;
+ 	} while (word != stop);
+ 
+ 	return csum_fold(csum);
+@@ -192,69 +196,4 @@ static inline __sum16 ip_compute_csum(co
+ 	return csum_fold(csum_partial(buff, len, 0));
+ }
+ 
+-#define _HAVE_ARCH_IPV6_CSUM
+-static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
+-				          const struct in6_addr *daddr,
+-					  __u32 len, unsigned short proto,
+-					  __wsum sum)
+-{
+-	__asm__(
+-	"	.set	push		# csum_ipv6_magic\n"
+-	"	.set	noreorder	\n"
+-	"	.set	noat		\n"
+-	"	addu	%0, %5		# proto (long in network byte order)\n"
+-	"	sltu	$1, %0, %5	\n"
+-	"	addu	%0, $1		\n"
+-
+-	"	addu	%0, %6		# csum\n"
+-	"	sltu	$1, %0, %6	\n"
+-	"	lw	%1, 0(%2)	# four words source address\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	lw	%1, 4(%2)	\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	lw	%1, 8(%2)	\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	lw	%1, 12(%2)	\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	lw	%1, 0(%3)	\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	lw	%1, 4(%3)	\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	lw	%1, 8(%3)	\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	lw	%1, 12(%3)	\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	addu	%0, $1		# Add final carry\n"
+-	"	.set	pop"
+-	: "=r" (sum), "=r" (proto)
+-	: "r" (saddr), "r" (daddr),
+-	  "0" (htonl(len)), "1" (htonl(proto)), "r" (sum));
+-
+-	return csum_fold(sum);
+-}
+-
+ #endif /* _ASM_CHECKSUM_H */
+--- a/include/uapi/linux/ip.h
++++ b/include/uapi/linux/ip.h
+@@ -102,7 +102,7 @@ struct iphdr {
+ 	__be32	saddr;
+ 	__be32	daddr;
+ 	/*The options start here. */
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ 
+ struct ip_auth_hdr {
+--- a/include/uapi/linux/ipv6.h
++++ b/include/uapi/linux/ipv6.h
+@@ -123,7 +123,7 @@ struct ipv6hdr {
+ 
+ 	struct	in6_addr	saddr;
+ 	struct	in6_addr	daddr;
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ 
+ /* index values for the variables in ipv6_devconf */
+--- a/include/uapi/linux/tcp.h
++++ b/include/uapi/linux/tcp.h
+@@ -54,7 +54,7 @@ struct tcphdr {
+ 	__be16	window;
+ 	__sum16	check;
+ 	__be16	urg_ptr;
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ /*
+  *	The union cast uses a gcc extension to avoid aliasing problems
+@@ -64,7 +64,7 @@ struct tcphdr {
+ union tcp_word_hdr { 
+ 	struct tcphdr hdr;
+ 	__be32 		  words[5];
+-}; 
++} __attribute__((packed, aligned(2)));
+ 
+ #define tcp_flag_word(tp) ( ((union tcp_word_hdr *)(tp))->words [3]) 
+ 
+--- a/include/uapi/linux/udp.h
++++ b/include/uapi/linux/udp.h
+@@ -24,7 +24,7 @@ struct udphdr {
+ 	__be16	dest;
+ 	__be16	len;
+ 	__sum16	check;
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ /* UDP socket options */
+ #define UDP_CORK	1	/* Never send partially complete segments */
+--- a/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c
++++ b/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c
+@@ -39,8 +39,8 @@ static bool ipv4_pkt_to_tuple(const stru
+ 	if (ap == NULL)
+ 		return false;
+ 
+-	tuple->src.u3.ip = ap[0];
+-	tuple->dst.u3.ip = ap[1];
++	tuple->src.u3.ip = net_hdr_word(ap++);
++	tuple->dst.u3.ip = net_hdr_word(ap);
+ 
+ 	return true;
+ }
+--- a/include/uapi/linux/icmp.h
++++ b/include/uapi/linux/icmp.h
+@@ -80,7 +80,7 @@ struct icmphdr {
+ 		__be16	mtu;
+ 	} frag;
+   } un;
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ 
+ /*
+--- a/net/ipv4/tcp_input.c
++++ b/net/ipv4/tcp_input.c
+@@ -3871,13 +3871,14 @@ static bool tcp_parse_aligned_timestamp(
+ {
+ 	const __be32 *ptr = (const __be32 *)(th + 1);
+ 
+-	if (*ptr == htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16)
+-			  | (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) {
++	if (net_hdr_word(ptr) ==
++	    htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
++	    (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) {
+ 		tp->rx_opt.saw_tstamp = 1;
+ 		++ptr;
+-		tp->rx_opt.rcv_tsval = ntohl(*ptr);
++		tp->rx_opt.rcv_tsval = get_unaligned_be32(ptr);
+ 		++ptr;
+-		tp->rx_opt.rcv_tsecr = ntohl(*ptr);
++		tp->rx_opt.rcv_tsecr = get_unaligned_be32(ptr);
+ 		return true;
+ 	}
+ 	return false;
+--- a/include/uapi/linux/in6.h
++++ b/include/uapi/linux/in6.h
+@@ -36,7 +36,7 @@ struct in6_addr {
+ #define s6_addr			in6_u.u6_addr8
+ #define s6_addr16		in6_u.u6_addr16
+ #define s6_addr32		in6_u.u6_addr32
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ /* IPv6 Wildcard Address (::) and Loopback Address (::1) defined in RFC2553
+  * NOTE: Be aware the IN6ADDR_* constants and in6addr_* externals are defined
+--- a/net/ipv6/af_inet6.c
++++ b/net/ipv6/af_inet6.c
+@@ -61,6 +61,7 @@
+ #endif
+ 
+ #include <asm/uaccess.h>
++#include <asm/unaligned.h>
+ #include <linux/mroute6.h>
+ 
+ MODULE_AUTHOR("Cast of dozens");
+@@ -688,7 +689,7 @@ bool ipv6_opt_accepted(const struct sock
+ 		if ((opt->hop && (np->rxopt.bits.hopopts ||
+ 				  np->rxopt.bits.ohopopts)) ||
+ 		    ((IPV6_FLOWINFO_MASK &
+-		      *(__be32 *)skb_network_header(skb)) &&
++		      net_hdr_word(skb_network_header(skb))) &&
+ 		     np->rxopt.bits.rxflow) ||
+ 		    (opt->srcrt && (np->rxopt.bits.srcrt ||
+ 		     np->rxopt.bits.osrcrt)) ||
+--- a/net/ipv6/route.c
++++ b/net/ipv6/route.c
+@@ -995,7 +995,7 @@ void ip6_route_input(struct sk_buff *skb
+ 		.flowi6_iif = skb->dev->ifindex,
+ 		.daddr = iph->daddr,
+ 		.saddr = iph->saddr,
+-		.flowlabel = (* (__be32 *) iph) & IPV6_FLOWINFO_MASK,
++		.flowlabel = net_hdr_word(iph) & IPV6_FLOWINFO_MASK,
+ 		.flowi6_mark = skb->mark,
+ 		.flowi6_proto = iph->nexthdr,
+ 	};
+@@ -1159,7 +1159,7 @@ void ip6_update_pmtu(struct sk_buff *skb
+ 	fl6.flowi6_flags = 0;
+ 	fl6.daddr = iph->daddr;
+ 	fl6.saddr = iph->saddr;
+-	fl6.flowlabel = (*(__be32 *) iph) & IPV6_FLOWINFO_MASK;
++	fl6.flowlabel = net_hdr_word(iph) & IPV6_FLOWINFO_MASK,
+ 
+ 	dst = ip6_route_output(net, NULL, &fl6);
+ 	if (!dst->error)
+@@ -1187,7 +1187,7 @@ void ip6_redirect(struct sk_buff *skb, s
+ 	fl6.flowi6_flags = 0;
+ 	fl6.daddr = iph->daddr;
+ 	fl6.saddr = iph->saddr;
+-	fl6.flowlabel = (*(__be32 *) iph) & IPV6_FLOWINFO_MASK;
++	fl6.flowlabel = net_hdr_word(iph) & IPV6_FLOWINFO_MASK,
+ 
+ 	dst = ip6_route_output(net, NULL, &fl6);
+ 	if (!dst->error)
+--- a/net/ipv6/tcp_ipv6.c
++++ b/net/ipv6/tcp_ipv6.c
+@@ -64,6 +64,7 @@
+ #include <net/secure_seq.h>
+ #include <net/tcp_memcontrol.h>
+ 
++#include <asm/unaligned.h>
+ #include <asm/uaccess.h>
+ 
+ #include <linux/proc_fs.h>
+@@ -756,10 +757,10 @@ static void tcp_v6_send_response(struct
+ 	topt = (__be32 *)(t1 + 1);
+ 
+ 	if (ts) {
+-		*topt++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
+-				(TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP);
+-		*topt++ = htonl(tcp_time_stamp);
+-		*topt++ = htonl(ts);
++		put_unaligned_be32((TCPOPT_NOP << 24) |	(TCPOPT_NOP << 16) |
++			(TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP, topt++);
++		put_unaligned_be32(tcp_time_stamp, topt++);
++		put_unaligned_be32(ts, topt++);
+ 	}
+ 
+ #ifdef CONFIG_TCP_MD5SIG
+--- a/include/linux/ipv6.h
++++ b/include/linux/ipv6.h
+@@ -4,6 +4,7 @@
+ #include <uapi/linux/ipv6.h>
+ 
+ #define ipv6_optlen(p)  (((p)->hdrlen+1) << 3)
++
+ /*
+  * This structure contains configuration options per IPv6 link.
+  */
+--- a/net/ipv6/datagram.c
++++ b/net/ipv6/datagram.c
+@@ -360,12 +360,12 @@ int ipv6_recv_error(struct sock *sk, str
+ 				*(struct in6_addr *)(nh + serr->addr_offset);
+ 			if (np->sndflow)
+ 				sin->sin6_flowinfo =
+-					(*(__be32 *)(nh + serr->addr_offset - 24) &
+-					 IPV6_FLOWINFO_MASK);
++					net_hdr_word(nh + serr->addr_offset - 24) &
++					 IPV6_FLOWINFO_MASK;
+ 			if (ipv6_addr_type(&sin->sin6_addr) & IPV6_ADDR_LINKLOCAL)
+ 				sin->sin6_scope_id = IP6CB(skb)->iif;
+ 		} else {
+-			ipv6_addr_set_v4mapped(*(__be32 *)(nh + serr->addr_offset),
++			ipv6_addr_set_v4mapped(net_hdr_word(nh + serr->addr_offset),
+ 					       &sin->sin6_addr);
+ 		}
+ 	}
+@@ -493,9 +493,10 @@ int ip6_datagram_recv_ctl(struct sock *s
+ 		put_cmsg(msg, SOL_IPV6, IPV6_TCLASS, sizeof(tclass), &tclass);
+ 	}
+ 
+-	if (np->rxopt.bits.rxflow && (*(__be32 *)nh & IPV6_FLOWINFO_MASK)) {
+-		__be32 flowinfo = *(__be32 *)nh & IPV6_FLOWINFO_MASK;
+-		put_cmsg(msg, SOL_IPV6, IPV6_FLOWINFO, sizeof(flowinfo), &flowinfo);
++	if (np->rxopt.bits.rxflow) {
++		__be32 flowinfo = net_hdr_word(nh) & IPV6_FLOWINFO_MASK;
++		if (flowinfo)
++			put_cmsg(msg, SOL_IPV6, IPV6_FLOWINFO, sizeof(flowinfo), &flowinfo);
+ 	}
+ 
+ 	/* HbH is allowed only once */
+@@ -682,12 +683,12 @@ int ip6_datagram_send_ctl(struct net *ne
+ 			}
+ 
+ 			if (fl6->flowlabel&IPV6_FLOWINFO_MASK) {
+-				if ((fl6->flowlabel^*(__be32 *)CMSG_DATA(cmsg))&~IPV6_FLOWINFO_MASK) {
++				if ((fl6->flowlabel^net_hdr_word(CMSG_DATA(cmsg)))&~IPV6_FLOWINFO_MASK) {
+ 					err = -EINVAL;
+ 					goto exit_f;
+ 				}
+ 			}
+-			fl6->flowlabel = IPV6_FLOWINFO_MASK & *(__be32 *)CMSG_DATA(cmsg);
++			fl6->flowlabel = IPV6_FLOWINFO_MASK & net_hdr_word(CMSG_DATA(cmsg));
+ 			break;
+ 
+ 		case IPV6_2292HOPOPTS:
+--- a/net/ipv6/ip6_gre.c
++++ b/net/ipv6/ip6_gre.c
+@@ -430,7 +430,7 @@ static void ip6gre_err(struct sk_buff *s
+ 
+ 	t = ip6gre_tunnel_lookup(skb->dev, &ipv6h->daddr, &ipv6h->saddr,
+ 				flags & GRE_KEY ?
+-				*(((__be32 *)p) + (grehlen / 4) - 1) : 0,
++				net_hdr_word(((__be32 *)p) + (grehlen / 4) - 1) : 0,
+ 				p[1]);
+ 	if (t == NULL)
+ 		return;
+@@ -522,11 +522,11 @@ static int ip6gre_rcv(struct sk_buff *sk
+ 			offset += 4;
+ 		}
+ 		if (flags&GRE_KEY) {
+-			key = *(__be32 *)(h + offset);
++			key = net_hdr_word(h + offset);
+ 			offset += 4;
+ 		}
+ 		if (flags&GRE_SEQ) {
+-			seqno = ntohl(*(__be32 *)(h + offset));
++			seqno = ntohl(net_hdr_word(h + offset));
+ 			offset += 4;
+ 		}
+ 	}
+@@ -772,7 +772,7 @@ static netdev_tx_t ip6gre_xmit2(struct s
+ 	 *	Push down and install the IP header.
+ 	 */
+ 	ipv6h = ipv6_hdr(skb);
+-	*(__be32 *)ipv6h = fl6->flowlabel | htonl(0x60000000);
++	net_hdr_word(ipv6h) = fl6->flowlabel | htonl(0x60000000);
+ 	dsfield = INET_ECN_encapsulate(0, dsfield);
+ 	ipv6_change_dsfield(ipv6h, ~INET_ECN_MASK, dsfield);
+ 	ipv6h->hop_limit = tunnel->parms.hop_limit;
+@@ -789,7 +789,7 @@ static netdev_tx_t ip6gre_xmit2(struct s
+ 
+ 		if (tunnel->parms.o_flags&GRE_SEQ) {
+ 			++tunnel->o_seqno;
+-			*ptr = htonl(tunnel->o_seqno);
++			net_hdr_word(ptr) = htonl(tunnel->o_seqno);
+ 			ptr--;
+ 		}
+ 		if (tunnel->parms.o_flags&GRE_KEY) {
+@@ -897,9 +897,9 @@ static inline int ip6gre_xmit_ipv6(struc
+ 
+ 	dsfield = ipv6_get_dsfield(ipv6h);
+ 	if (t->parms.flags & IP6_TNL_F_USE_ORIG_TCLASS)
+-		fl6.flowlabel |= (*(__be32 *) ipv6h & IPV6_TCLASS_MASK);
++		fl6.flowlabel |= net_hdr_word(ipv6h) & IPV6_TCLASS_MASK;
+ 	if (t->parms.flags & IP6_TNL_F_USE_ORIG_FLOWLABEL)
+-		fl6.flowlabel |= (*(__be32 *) ipv6h & IPV6_FLOWLABEL_MASK);
++		fl6.flowlabel |= net_hdr_word(ipv6h) & IPV6_FLOWLABEL_MASK;
+ 	if (t->parms.flags & IP6_TNL_F_USE_ORIG_FWMARK)
+ 		fl6.flowi6_mark = skb->mark;
+ 
+@@ -1240,7 +1240,7 @@ static int ip6gre_header(struct sk_buff
+ 	struct ipv6hdr *ipv6h = (struct ipv6hdr *)skb_push(skb, t->hlen);
+ 	__be16 *p = (__be16 *)(ipv6h+1);
+ 
+-	*(__be32 *)ipv6h = t->fl.u.ip6.flowlabel | htonl(0x60000000);
++	net_hdr_word(ipv6h) = t->fl.u.ip6.flowlabel | htonl(0x60000000);
+ 	ipv6h->hop_limit = t->parms.hop_limit;
+ 	ipv6h->nexthdr = NEXTHDR_GRE;
+ 	ipv6h->saddr = t->parms.laddr;
+--- a/net/ipv6/ip6_output.c
++++ b/net/ipv6/ip6_output.c
+@@ -216,7 +216,7 @@ int ip6_xmit(struct sock *sk, struct sk_
+ 	if (hlimit < 0)
+ 		hlimit = ip6_dst_hoplimit(dst);
+ 
+-	*(__be32 *)hdr = htonl(0x60000000 | (tclass << 20)) | fl6->flowlabel;
++	net_hdr_word(hdr) = htonl(0x60000000 | (tclass << 20)) | fl6->flowlabel;
+ 
+ 	hdr->payload_len = htons(seg_len);
+ 	hdr->nexthdr = proto;
+--- a/net/ipv6/ip6_tunnel.c
++++ b/net/ipv6/ip6_tunnel.c
+@@ -1136,9 +1136,9 @@ ip6ip6_tnl_xmit(struct sk_buff *skb, str
+ 
+ 	dsfield = ipv6_get_dsfield(ipv6h);
+ 	if (t->parms.flags & IP6_TNL_F_USE_ORIG_TCLASS)
+-		fl6.flowlabel |= (*(__be32 *) ipv6h & IPV6_TCLASS_MASK);
++		fl6.flowlabel |= net_hdr_word(ipv6h) & IPV6_TCLASS_MASK;
+ 	if (t->parms.flags & IP6_TNL_F_USE_ORIG_FLOWLABEL)
+-		fl6.flowlabel |= (*(__be32 *) ipv6h & IPV6_FLOWLABEL_MASK);
++		fl6.flowlabel |= net_hdr_word(ipv6h) & IPV6_FLOWLABEL_MASK;
+ 	if (t->parms.flags & IP6_TNL_F_USE_ORIG_FWMARK)
+ 		fl6.flowi6_mark = skb->mark;
+ 
+--- a/net/ipv6/exthdrs.c
++++ b/net/ipv6/exthdrs.c
+@@ -578,7 +578,7 @@ static bool ipv6_hop_jumbo(struct sk_buf
+ 		goto drop;
+ 	}
+ 
+-	pkt_len = ntohl(*(__be32 *)(nh + optoff + 2));
++	pkt_len = ntohl(net_hdr_word(nh + optoff + 2));
+ 	if (pkt_len <= IPV6_MAXPLEN) {
+ 		IP6_INC_STATS_BH(net, ipv6_skb_idev(skb),
+ 				 IPSTATS_MIB_INHDRERRORS);
+--- a/include/linux/types.h
++++ b/include/linux/types.h
+@@ -212,5 +212,11 @@ struct callback_head {
+ };
+ #define rcu_head callback_head
+ 
++struct net_hdr_word {
++       u32 words[1];
++} __attribute__((packed, aligned(2)));
++
++#define net_hdr_word(_p) (((struct net_hdr_word *) (_p))->words[0])
++
+ #endif /*  __ASSEMBLY__ */
+ #endif /* _LINUX_TYPES_H */
+--- a/net/ipv4/af_inet.c
++++ b/net/ipv4/af_inet.c
+@@ -1396,8 +1396,8 @@ static struct sk_buff **inet_gro_receive
+ 	if (unlikely(ip_fast_csum((u8 *)iph, 5)))
+ 		goto out_unlock;
+ 
+-	id = ntohl(*(__be32 *)&iph->id);
+-	flush = (u16)((ntohl(*(__be32 *)iph) ^ skb_gro_len(skb)) | (id ^ IP_DF));
++	id = ntohl(net_hdr_word(&iph->id));
++	flush = (u16)((ntohl(net_hdr_word(iph)) ^ skb_gro_len(skb)) | (id ^ IP_DF));
+ 	id >>= 16;
+ 
+ 	for (p = *head; p; p = p->next) {
+--- a/net/ipv4/route.c
++++ b/net/ipv4/route.c
+@@ -465,7 +465,7 @@ static struct neighbour *ipv4_neigh_look
+ 	else if (skb)
+ 		pkey = &ip_hdr(skb)->daddr;
+ 
+-	n = __ipv4_neigh_lookup(dev, *(__force u32 *)pkey);
++	n = __ipv4_neigh_lookup(dev, net_hdr_word(pkey));
+ 	if (n)
+ 		return n;
+ 	return neigh_create(&arp_tbl, pkey, dev);
+--- a/net/ipv4/tcp_output.c
++++ b/net/ipv4/tcp_output.c
+@@ -456,15 +456,17 @@ static void tcp_options_write(__be32 *pt
+ 	 */
+ 	if (unlikely(OPTION_MD5 & options)) {
+ 		if (unlikely(OPTION_COOKIE_EXTENSION & options)) {
+-			*ptr++ = htonl((TCPOPT_COOKIE << 24) |
+-				       (TCPOLEN_COOKIE_BASE << 16) |
+-				       (TCPOPT_MD5SIG << 8) |
+-				       TCPOLEN_MD5SIG);
++			net_hdr_word(ptr++) =
++				htonl((TCPOPT_COOKIE << 24) |
++				      (TCPOLEN_COOKIE_BASE << 16) |
++				      (TCPOPT_MD5SIG << 8) |
++				      TCPOLEN_MD5SIG);
+ 		} else {
+-			*ptr++ = htonl((TCPOPT_NOP << 24) |
+-				       (TCPOPT_NOP << 16) |
+-				       (TCPOPT_MD5SIG << 8) |
+-				       TCPOLEN_MD5SIG);
++			net_hdr_word(ptr++) =
++				htonl((TCPOPT_NOP << 24) |
++				      (TCPOPT_NOP << 16) |
++				      (TCPOPT_MD5SIG << 8) |
++				      TCPOLEN_MD5SIG);
+ 		}
+ 		options &= ~OPTION_COOKIE_EXTENSION;
+ 		/* overload cookie hash location */
+@@ -473,26 +475,28 @@ static void tcp_options_write(__be32 *pt
+ 	}
+ 
+ 	if (unlikely(opts->mss)) {
+-		*ptr++ = htonl((TCPOPT_MSS << 24) |
+-			       (TCPOLEN_MSS << 16) |
+-			       opts->mss);
++		net_hdr_word(ptr++) =
++			htonl((TCPOPT_MSS << 24) | (TCPOLEN_MSS << 16) |
++			      opts->mss);
+ 	}
+ 
+ 	if (likely(OPTION_TS & options)) {
+ 		if (unlikely(OPTION_SACK_ADVERTISE & options)) {
+-			*ptr++ = htonl((TCPOPT_SACK_PERM << 24) |
+-				       (TCPOLEN_SACK_PERM << 16) |
+-				       (TCPOPT_TIMESTAMP << 8) |
+-				       TCPOLEN_TIMESTAMP);
++			net_hdr_word(ptr++) =
++				htonl((TCPOPT_SACK_PERM << 24) |
++				      (TCPOLEN_SACK_PERM << 16) |
++				      (TCPOPT_TIMESTAMP << 8) |
++				      TCPOLEN_TIMESTAMP);
+ 			options &= ~OPTION_SACK_ADVERTISE;
+ 		} else {
+-			*ptr++ = htonl((TCPOPT_NOP << 24) |
+-				       (TCPOPT_NOP << 16) |
+-				       (TCPOPT_TIMESTAMP << 8) |
+-				       TCPOLEN_TIMESTAMP);
++			net_hdr_word(ptr++) =
++				htonl((TCPOPT_NOP << 24) |
++				      (TCPOPT_NOP << 16) |
++				      (TCPOPT_TIMESTAMP << 8) |
++				      TCPOLEN_TIMESTAMP);
+ 		}
+-		*ptr++ = htonl(opts->tsval);
+-		*ptr++ = htonl(opts->tsecr);
++		net_hdr_word(ptr++) = htonl(opts->tsval);
++		net_hdr_word(ptr++) = htonl(opts->tsecr);
+ 	}
+ 
+ 	/* Specification requires after timestamp, so do it now.
+@@ -512,19 +516,20 @@ static void tcp_options_write(__be32 *pt
+ 			__u8 *p = (__u8 *)ptr;
+ 
+ 			/* 16-bit multiple */
+-			*p++ = TCPOPT_COOKIE;
+-			*p++ = TCPOLEN_COOKIE_BASE + cookie_size;
+-			*p++ = *cookie_copy++;
+-			*p++ = *cookie_copy++;
++			net_hdr_word(p++) = TCPOPT_COOKIE;
++			net_hdr_word(p++) = TCPOLEN_COOKIE_BASE + cookie_size;
++			net_hdr_word(p++) = *cookie_copy++;
++			net_hdr_word(p++) = *cookie_copy++;
+ 			ptr++;
+ 			cookie_size -= 2;
+ 		} else {
+ 			/* 32-bit multiple */
+-			*ptr++ = htonl(((TCPOPT_NOP << 24) |
+-					(TCPOPT_NOP << 16) |
+-					(TCPOPT_COOKIE << 8) |
+-					TCPOLEN_COOKIE_BASE) +
+-				       cookie_size);
++			net_hdr_word(ptr++) =
++				htonl(((TCPOPT_NOP << 24) |
++				       (TCPOPT_NOP << 16) |
++				       (TCPOPT_COOKIE << 8) |
++				       TCPOLEN_COOKIE_BASE) +
++				      cookie_size);
+ 		}
+ 
+ 		if (cookie_size > 0) {
+@@ -534,17 +539,19 @@ static void tcp_options_write(__be32 *pt
+ 	}
+ 
+ 	if (unlikely(OPTION_SACK_ADVERTISE & options)) {
+-		*ptr++ = htonl((TCPOPT_NOP << 24) |
+-			       (TCPOPT_NOP << 16) |
+-			       (TCPOPT_SACK_PERM << 8) |
+-			       TCPOLEN_SACK_PERM);
++		net_hdr_word(ptr++) =
++			htonl((TCPOPT_NOP << 24) |
++			      (TCPOPT_NOP << 16) |
++			      (TCPOPT_SACK_PERM << 8) |
++			      TCPOLEN_SACK_PERM);
+ 	}
+ 
+ 	if (unlikely(OPTION_WSCALE & options)) {
+-		*ptr++ = htonl((TCPOPT_NOP << 24) |
+-			       (TCPOPT_WINDOW << 16) |
+-			       (TCPOLEN_WINDOW << 8) |
+-			       opts->ws);
++		net_hdr_word(ptr++) =
++			htonl((TCPOPT_NOP << 24) |
++			      (TCPOPT_WINDOW << 16) |
++			      (TCPOLEN_WINDOW << 8) |
++			      opts->ws);
+ 	}
+ 
+ 	if (unlikely(opts->num_sack_blocks)) {
+@@ -552,16 +559,17 @@ static void tcp_options_write(__be32 *pt
+ 			tp->duplicate_sack : tp->selective_acks;
+ 		int this_sack;
+ 
+-		*ptr++ = htonl((TCPOPT_NOP  << 24) |
+-			       (TCPOPT_NOP  << 16) |
+-			       (TCPOPT_SACK <<  8) |
+-			       (TCPOLEN_SACK_BASE + (opts->num_sack_blocks *
++		net_hdr_word(ptr++) =
++			htonl((TCPOPT_NOP << 24) |
++			      (TCPOPT_NOP << 16) |
++			      (TCPOPT_SACK << 8) |
++			      (TCPOLEN_SACK_BASE + (opts->num_sack_blocks *
+ 						     TCPOLEN_SACK_PERBLOCK)));
+ 
+ 		for (this_sack = 0; this_sack < opts->num_sack_blocks;
+ 		     ++this_sack) {
+-			*ptr++ = htonl(sp[this_sack].start_seq);
+-			*ptr++ = htonl(sp[this_sack].end_seq);
++			net_hdr_word(ptr++) = htonl(sp[this_sack].start_seq);
++			net_hdr_word(ptr++) = htonl(sp[this_sack].end_seq);
+ 		}
+ 
+ 		tp->rx_opt.dsack = 0;
+@@ -570,9 +578,10 @@ static void tcp_options_write(__be32 *pt
+ 	if (unlikely(OPTION_FAST_OPEN_COOKIE & options)) {
+ 		struct tcp_fastopen_cookie *foc = opts->fastopen_cookie;
+ 
+-		*ptr++ = htonl((TCPOPT_EXP << 24) |
+-			       ((TCPOLEN_EXP_FASTOPEN_BASE + foc->len) << 16) |
+-			       TCPOPT_FASTOPEN_MAGIC);
++		net_hdr_word(ptr++) =
++			htonl((TCPOPT_EXP << 24) |
++			      ((TCPOLEN_EXP_FASTOPEN_BASE + foc->len) << 16) |
++			      TCPOPT_FASTOPEN_MAGIC);
+ 
+ 		memcpy(ptr, foc->val, foc->len);
+ 		if ((foc->len & 3) == 2) {
+--- a/net/ipv4/igmp.c
++++ b/net/ipv4/igmp.c
+@@ -470,7 +470,7 @@ static struct sk_buff *add_grec(struct s
+ 		if (!skb)
+ 			return NULL;
+ 		psrc = (__be32 *)skb_put(skb, sizeof(__be32));
+-		*psrc = psf->sf_inaddr;
++		net_hdr_word(psrc) = psf->sf_inaddr;
+ 		scount++; stotal++;
+ 		if ((type == IGMPV3_ALLOW_NEW_SOURCES ||
+ 		     type == IGMPV3_BLOCK_OLD_SOURCES) && psf->sf_crcount) {
+--- a/net/ipv4/ip_gre.c
++++ b/net/ipv4/ip_gre.c
+@@ -518,7 +518,7 @@ static void ipgre_err(struct sk_buff *sk
+ 		return;
+ 
+ 	if (flags & GRE_KEY)
+-		key = *(((__be32 *)p) + (grehlen / 4) - 1);
++		key = net_hdr_word(((__be32 *)p) + (grehlen / 4) - 1);
+ 
+ 	switch (type) {
+ 	default:
+--- a/include/uapi/linux/igmp.h
++++ b/include/uapi/linux/igmp.h
+@@ -32,7 +32,7 @@ struct igmphdr {
+ 	__u8 code;		/* For newer IGMP */
+ 	__sum16 csum;
+ 	__be32 group;
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ /* V3 group record types [grec_type] */
+ #define IGMPV3_MODE_IS_INCLUDE		1
+@@ -48,7 +48,7 @@ struct igmpv3_grec {
+ 	__be16	grec_nsrcs;
+ 	__be32	grec_mca;
+ 	__be32	grec_src[0];
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ struct igmpv3_report {
+ 	__u8 type;
+@@ -57,7 +57,7 @@ struct igmpv3_report {
+ 	__be16 resv2;
+ 	__be16 ngrec;
+ 	struct igmpv3_grec grec[0];
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ struct igmpv3_query {
+ 	__u8 type;
+@@ -78,7 +78,7 @@ struct igmpv3_query {
+ 	__u8 qqic;
+ 	__be16 nsrcs;
+ 	__be32 srcs[0];
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ #define IGMP_HOST_MEMBERSHIP_QUERY	0x11	/* From RFC1112 */
+ #define IGMP_HOST_MEMBERSHIP_REPORT	0x12	/* Ditto */
+--- a/net/core/flow_dissector.c
++++ b/net/core/flow_dissector.c
+@@ -137,7 +137,7 @@ ipv6:
+ 		nhoff += poff;
+ 		ports = skb_header_pointer(skb, nhoff, sizeof(_ports), &_ports);
+ 		if (ports)
+-			flow->ports = *ports;
++			flow->ports = net_hdr_word(ports);
+ 	}
+ 
+ 	return true;
+--- a/include/uapi/linux/icmpv6.h
++++ b/include/uapi/linux/icmpv6.h
+@@ -76,7 +76,7 @@ struct icmp6hdr {
+ #define icmp6_addrconf_other	icmp6_dataun.u_nd_ra.other
+ #define icmp6_rt_lifetime	icmp6_dataun.u_nd_ra.rt_lifetime
+ #define icmp6_router_pref	icmp6_dataun.u_nd_ra.router_pref
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ 
+ #define ICMPV6_ROUTER_PREF_LOW		0x3
+--- a/include/net/ndisc.h
++++ b/include/net/ndisc.h
+@@ -142,10 +142,10 @@ static inline u32 ndisc_hashfn(const voi
+ {
+ 	const u32 *p32 = pkey;
+ 
+-	return (((p32[0] ^ hash32_ptr(dev)) * hash_rnd[0]) +
+-		(p32[1] * hash_rnd[1]) +
+-		(p32[2] * hash_rnd[2]) +
+-		(p32[3] * hash_rnd[3]));
++	return (((net_hdr_word(&p32[0]) ^ hash32_ptr(dev)) * hash_rnd[0]) +
++		(net_hdr_word(&p32[1]) * hash_rnd[1]) +
++		(net_hdr_word(&p32[2]) * hash_rnd[2]) +
++		(net_hdr_word(&p32[3]) * hash_rnd[3]));
+ }
+ 
+ static inline struct neighbour *__ipv6_neigh_lookup(struct neigh_table *tbl, struct net_device *dev, const void *pkey)
+--- a/net/sched/cls_u32.c
++++ b/net/sched/cls_u32.c
+@@ -142,7 +142,7 @@ next_knode:
+ 			data = skb_header_pointer(skb, toff, 4, &hdata);
+ 			if (!data)
+ 				goto out;
+-			if ((*data ^ key->val) & key->mask) {
++			if ((net_hdr_word(data) ^ key->val) & key->mask) {
+ 				n = n->next;
+ 				goto next_knode;
+ 			}
+@@ -193,8 +193,8 @@ check_terminal:
+ 						  &hdata);
+ 			if (!data)
+ 				goto out;
+-			sel = ht->divisor & u32_hash_fold(*data, &n->sel,
+-							  n->fshift);
++			sel = ht->divisor & u32_hash_fold(net_hdr_word(data),
++							  &n->sel, n->fshift);
+ 		}
+ 		if (!(n->sel.flags & (TC_U32_VAROFFSET | TC_U32_OFFSET | TC_U32_EAT)))
+ 			goto next_ht;
+--- a/net/ipv6/ip6_offload.c
++++ b/net/ipv6/ip6_offload.c
+@@ -200,7 +200,7 @@ static struct sk_buff **ipv6_gro_receive
+ 			continue;
+ 
+ 		iph2 = ipv6_hdr(p);
+-		first_word = *(__be32 *)iph ^ *(__be32 *)iph2 ;
++		first_word = net_hdr_word(iph) ^ net_hdr_word(iph2);
+ 
+ 		/* All fields must match except length and Traffic Class. */
+ 		if (nlen != skb_network_header_len(p) ||
diff --git a/target/linux/ar71xx/patches-3.8/001-spi-ath79-add-delay-between-SCK-changes.patch b/target/linux/ar71xx/patches-3.8/001-spi-ath79-add-delay-between-SCK-changes.patch
new file mode 100644
index 0000000..9a10622
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/001-spi-ath79-add-delay-between-SCK-changes.patch
@@ -0,0 +1,126 @@
+From 486c150478777ef53cfef6f0d46840b9406b0612 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 27 Dec 2012 10:42:24 +0100
+Subject: [PATCH] spi/ath79: add delay between SCK changes
+
+commit 440114fdb13cbc53ea734bcc05b86bcf5b1e430c upstream.
+
+The driver uses the "as fast as it can" approach
+to drive the SCK signal. However this does not
+work with certain low speed SPI chips (e.g. the
+PCF2123 RTC chip).
+
+The patch adds per-bit slowdowns in order to be
+able to use the driver with such chips as well.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+---
+ drivers/spi/spi-ath79.c |   44 +++++++++++++++++++++++++++++++++++++++++++-
+ 1 file changed, 43 insertions(+), 1 deletion(-)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -24,17 +24,24 @@
+ #include <linux/spi/spi_bitbang.h>
+ #include <linux/bitops.h>
+ #include <linux/gpio.h>
++#include <linux/clk.h>
++#include <linux/err.h>
+ 
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79_spi_platform.h>
+ 
+ #define DRV_NAME	"ath79-spi"
+ 
++#define ATH79_SPI_RRW_DELAY_FACTOR	12000
++#define MHZ				(1000 * 1000)
++
+ struct ath79_spi {
+ 	struct spi_bitbang	bitbang;
+ 	u32			ioc_base;
+ 	u32			reg_ctrl;
+ 	void __iomem		*base;
++	struct clk		*clk;
++	unsigned		rrw_delay;
+ };
+ 
+ static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
+@@ -52,6 +59,12 @@ static inline struct ath79_spi *ath79_sp
+ 	return spi_master_get_devdata(spi->master);
+ }
+ 
++static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs)
++{
++	if (nsecs > sp->rrw_delay)
++		ndelay(nsecs - sp->rrw_delay);
++}
++
+ static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
+ {
+ 	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+@@ -184,7 +197,9 @@ static u32 ath79_spi_txrx_mode0(struct s
+ 
+ 		/* setup MSB (to slave) on trailing edge */
+ 		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
++		ath79_spi_delay(sp, nsecs);
+ 		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
++		ath79_spi_delay(sp, nsecs);
+ 
+ 		word <<= 1;
+ 	}
+@@ -198,6 +213,7 @@ static int ath79_spi_probe(struct platfo
+ 	struct ath79_spi *sp;
+ 	struct ath79_spi_platform_data *pdata;
+ 	struct resource	*r;
++	unsigned long rate;
+ 	int ret;
+ 
+ 	master = spi_alloc_master(&pdev->dev, sizeof(*sp));
+@@ -236,12 +252,36 @@ static int ath79_spi_probe(struct platfo
+ 		goto err_put_master;
+ 	}
+ 
++	sp->clk = clk_get(&pdev->dev, "ahb");
++	if (IS_ERR(sp->clk)) {
++		ret = PTR_ERR(sp->clk);
++		goto err_unmap;
++	}
++
++	ret = clk_enable(sp->clk);
++	if (ret)
++		goto err_clk_put;
++
++	rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
++	if (!rate) {
++		ret = -EINVAL;
++		goto err_clk_disable;
++	}
++
++	sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
++	dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
++		sp->rrw_delay);
++
+ 	ret = spi_bitbang_start(&sp->bitbang);
+ 	if (ret)
+-		goto err_unmap;
++		goto err_clk_disable;
+ 
+ 	return 0;
+ 
++err_clk_disable:
++	clk_disable(sp->clk);
++err_clk_put:
++	clk_put(sp->clk);
+ err_unmap:
+ 	iounmap(sp->base);
+ err_put_master:
+@@ -256,6 +296,8 @@ static int ath79_spi_remove(struct platf
+ 	struct ath79_spi *sp = platform_get_drvdata(pdev);
+ 
+ 	spi_bitbang_stop(&sp->bitbang);
++	clk_disable(sp->clk);
++	clk_put(sp->clk);
+ 	iounmap(sp->base);
+ 	platform_set_drvdata(pdev, NULL);
+ 	spi_master_put(sp->bitbang.master);
diff --git a/target/linux/ar71xx/patches-3.8/002-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch b/target/linux/ar71xx/patches-3.8/002-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch
new file mode 100644
index 0000000..393ffa5
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/002-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch
@@ -0,0 +1,31 @@
+From c7c943b1e3813ff5764ee6417a14530cb7cd6f57 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 27 Dec 2012 10:42:25 +0100
+Subject: [PATCH] spi/ath79: add missing HIGH->LOW SCK transition
+
+commit 72611db0eef21f4456d79ba302af4b34ea384f30 upstream.
+
+The 'ath79_spi_txrx_mode0' function does not
+set the SCK signal to LOW at the end of a word
+transfer. This causes communications errors with
+certain devices (e.g. the PCF2123 RTC chip).
+
+The patch ensures that the SCK signal will be LOW.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+---
+ drivers/spi/spi-ath79.c |    2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -200,6 +200,8 @@ static u32 ath79_spi_txrx_mode0(struct s
+ 		ath79_spi_delay(sp, nsecs);
+ 		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
+ 		ath79_spi_delay(sp, nsecs);
++		if (bits == 1)
++			ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
+ 
+ 		word <<= 1;
+ 	}
diff --git a/target/linux/ar71xx/patches-3.8/003-spi-ath79-remove-superfluous-chip-select-code.patch b/target/linux/ar71xx/patches-3.8/003-spi-ath79-remove-superfluous-chip-select-code.patch
new file mode 100644
index 0000000..58272bd
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/003-spi-ath79-remove-superfluous-chip-select-code.patch
@@ -0,0 +1,33 @@
+From 622d87da7f99b29dde053881bf42c46de7572ce5 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 27 Dec 2012 10:42:26 +0100
+Subject: [PATCH] spi/ath79: remove superfluous chip select code
+
+commit f1e8fc9898fd8ca78b7438d3c2e60028d3ae2a34 upstream.
+
+The spi_bitbang driver calls the chipselect function
+of the driver from spi_bitbang_setup in order to
+deselect the given SPI chip, so we don't have to
+initialize the CS line here.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+---
+ drivers/spi/spi-ath79.c |    6 ------
+ 1 file changed, 6 deletions(-)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -128,12 +128,6 @@ static int ath79_spi_setup_cs(struct spi
+ 			gpio_free(cdata->gpio);
+ 			return status;
+ 		}
+-	} else {
+-		if (spi->mode & SPI_CS_HIGH)
+-			sp->ioc_base |= AR71XX_SPI_IOC_CS0;
+-		else
+-			sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
+-		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
+ 	}
+ 
+ 	return 0;
diff --git a/target/linux/ar71xx/patches-3.8/004-spi-ath79-use-gpio_request_one.patch b/target/linux/ar71xx/patches-3.8/004-spi-ath79-use-gpio_request_one.patch
new file mode 100644
index 0000000..ee81ecd
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/004-spi-ath79-use-gpio_request_one.patch
@@ -0,0 +1,59 @@
+From f0b166c931c9971f2ae9614881565d23f58b3178 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 27 Dec 2012 10:42:27 +0100
+Subject: [PATCH] spi/ath79: use gpio_request_one
+
+commit 95d79419feffb326a3d5cb50e2248129dec06bb0 upstream.
+
+Use gpio_request_one() instead of multiple gpiolib calls.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+---
+ drivers/spi/spi-ath79.c |   22 +++++++++++-----------
+ 1 file changed, 11 insertions(+), 11 deletions(-)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -100,6 +100,7 @@ static int ath79_spi_setup_cs(struct spi
+ {
+ 	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+ 	struct ath79_spi_controller_data *cdata;
++	int status;
+ 
+ 	cdata = spi->controller_data;
+ 	if (spi->chip_select && !cdata)
+@@ -115,22 +116,21 @@ static int ath79_spi_setup_cs(struct spi
+ 	/* TODO: setup speed? */
+ 	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
+ 
++	status = 0;
+ 	if (spi->chip_select) {
+-		int status = 0;
++		unsigned long flags;
+ 
+-		status = gpio_request(cdata->gpio, dev_name(&spi->dev));
+-		if (status)
+-			return status;
+-
+-		status = gpio_direction_output(cdata->gpio,
+-					       spi->mode & SPI_CS_HIGH);
+-		if (status) {
+-			gpio_free(cdata->gpio);
+-			return status;
+-		}
++		flags = GPIOF_DIR_OUT;
++		if (spi->mode & SPI_CS_HIGH)
++			flags |= GPIOF_INIT_HIGH;
++		else
++			flags |= GPIOF_INIT_LOW;
++
++		status = gpio_request_one(cdata->gpio, flags,
++					  dev_name(&spi->dev));
+ 	}
+ 
+-	return 0;
++	return status;
+ }
+ 
+ static void ath79_spi_cleanup_cs(struct spi_device *spi)
diff --git a/target/linux/ar71xx/patches-3.8/005-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch b/target/linux/ar71xx/patches-3.8/005-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch
new file mode 100644
index 0000000..8ad1dc3
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/005-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch
@@ -0,0 +1,112 @@
+From d731c08cf1d264fd6113b9a97790c5a3a86ea520 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 27 Dec 2012 10:42:28 +0100
+Subject: [PATCH] spi/ath79: avoid multiple initialization of the SPI
+ controller
+
+commit c4a31f43005512b366e8bfc346e7f14c1a7a1ba7 upstream.
+
+Currently we are initializing the SPI controller in
+the chip select line function, and that function is
+called once for each SPI device on the bus. If a
+board has multiple SPI devices, the controller will
+be initialized multiple times.
+
+Introduce ath79_spi_{en,dis}able helper functions,
+and call those from probe/response in order to avoid
+the mutliple initialization of the controller.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+---
+ drivers/spi/spi-ath79.c |   41 ++++++++++++++++++++++++-----------------
+ 1 file changed, 24 insertions(+), 17 deletions(-)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -96,16 +96,8 @@ static void ath79_spi_chipselect(struct
+ 
+ }
+ 
+-static int ath79_spi_setup_cs(struct spi_device *spi)
++static void ath79_spi_enable(struct ath79_spi *sp)
+ {
+-	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+-	struct ath79_spi_controller_data *cdata;
+-	int status;
+-
+-	cdata = spi->controller_data;
+-	if (spi->chip_select && !cdata)
+-		return -EINVAL;
+-
+ 	/* enable GPIO mode */
+ 	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
+ 
+@@ -115,6 +107,24 @@ static int ath79_spi_setup_cs(struct spi
+ 
+ 	/* TODO: setup speed? */
+ 	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
++}
++
++static void ath79_spi_disable(struct ath79_spi *sp)
++{
++	/* restore CTRL register */
++	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
++	/* disable GPIO mode */
++	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
++}
++
++static int ath79_spi_setup_cs(struct spi_device *spi)
++{
++	struct ath79_spi_controller_data *cdata;
++	int status;
++
++	cdata = spi->controller_data;
++	if (spi->chip_select && !cdata)
++		return -EINVAL;
+ 
+ 	status = 0;
+ 	if (spi->chip_select) {
+@@ -135,17 +145,10 @@ static int ath79_spi_setup_cs(struct spi
+ 
+ static void ath79_spi_cleanup_cs(struct spi_device *spi)
+ {
+-	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+-
+ 	if (spi->chip_select) {
+ 		struct ath79_spi_controller_data *cdata = spi->controller_data;
+ 		gpio_free(cdata->gpio);
+ 	}
+-
+-	/* restore CTRL register */
+-	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
+-	/* disable GPIO mode */
+-	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
+ }
+ 
+ static int ath79_spi_setup(struct spi_device *spi)
+@@ -268,12 +271,15 @@ static int ath79_spi_probe(struct platfo
+ 	dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
+ 		sp->rrw_delay);
+ 
++	ath79_spi_enable(sp);
+ 	ret = spi_bitbang_start(&sp->bitbang);
+ 	if (ret)
+-		goto err_clk_disable;
++		goto err_disable;
+ 
+ 	return 0;
+ 
++err_disable:
++	ath79_spi_disable(sp);
+ err_clk_disable:
+ 	clk_disable(sp->clk);
+ err_clk_put:
+@@ -292,6 +298,7 @@ static int ath79_spi_remove(struct platf
+ 	struct ath79_spi *sp = platform_get_drvdata(pdev);
+ 
+ 	spi_bitbang_stop(&sp->bitbang);
++	ath79_spi_disable(sp);
+ 	clk_disable(sp->clk);
+ 	clk_put(sp->clk);
+ 	iounmap(sp->base);
diff --git a/target/linux/ar71xx/patches-3.8/006-spi-ath79-add-shutdown-handler.patch b/target/linux/ar71xx/patches-3.8/006-spi-ath79-add-shutdown-handler.patch
new file mode 100644
index 0000000..6f59884
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/006-spi-ath79-add-shutdown-handler.patch
@@ -0,0 +1,54 @@
+From a32b0e7851320cba0144d20e87e5326ee81e1063 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Tue, 5 Feb 2013 20:57:55 +0100
+Subject: [PATCH] spi/ath79: add shutdown handler
+
+commit 7410e848583f9120dd5f9414629f01bb76b5ee5f upstream.
+
+The SPI controller of the AR7xxx/AR9xxx SoCs
+have a special mode which allows the SoC to
+directly read data from SPI flash chips. In
+this mode, the content of the SPI flash chip
+can be accessed via a memory mapped region.
+
+During early init time, the kernel expects
+that the flash chip is accessible through
+that memory region because it reads board
+specific values (e.g. MAC address, WiFi
+calibration data) from the flash on various
+boards.
+
+This is working if the kernel is loaded
+directly by the bootloader because that
+leaves the SPI controller in the special
+mode. However it is not working in a kexec'd
+kernel because the SPI driver does not restore
+the special mode during shutdown.
+
+The patch adds a shutdown handler to fix this
+issue.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+---
+ drivers/spi/spi-ath79.c |    6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -308,9 +308,15 @@ static int ath79_spi_remove(struct platf
+ 	return 0;
+ }
+ 
++static void ath79_spi_shutdown(struct platform_device *pdev)
++{
++	ath79_spi_remove(pdev);
++}
++
+ static struct platform_driver ath79_spi_driver = {
+ 	.probe		= ath79_spi_probe,
+ 	.remove		= ath79_spi_remove,
++	.shutdown	= ath79_spi_shutdown,
+ 	.driver		= {
+ 		.name	= DRV_NAME,
+ 		.owner	= THIS_MODULE,
diff --git a/target/linux/ar71xx/patches-3.8/007-MIPS-ath79-fix-GPIO-function-selection-for-AR934x-So.patch b/target/linux/ar71xx/patches-3.8/007-MIPS-ath79-fix-GPIO-function-selection-for-AR934x-So.patch
new file mode 100644
index 0000000..c1f1247
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/007-MIPS-ath79-fix-GPIO-function-selection-for-AR934x-So.patch
@@ -0,0 +1,110 @@
+From 2e6a41e0be6a09ed839e3afbe1fb413a015d8870 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Tue, 29 Jan 2013 08:19:12 +0000
+Subject: [PATCH] MIPS: ath79: fix GPIO function selection for AR934x SoCs
+
+commit 8838becdf5f7261d7f5dfbbe957fe9b9ed188aec upstream.
+
+GPIO function selection is not working on the AR934x
+SoCs because the offset of the function selection
+register is different on those.
+
+Add a helper routine which returns the correct
+register address based on the SoC type, and use
+that in the 'ath79_gpio_function_*' routines.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4870/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/gpio.c                         |   38 ++++++++++++++++--------
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    2 ++
+ 2 files changed, 28 insertions(+), 12 deletions(-)
+
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -137,47 +137,61 @@ static struct gpio_chip ath79_gpio_chip
+ 	.base			= 0,
+ };
+ 
++static void __iomem *ath79_gpio_get_function_reg(void)
++{
++	u32 reg = 0;
++
++	if (soc_is_ar71xx() ||
++	    soc_is_ar724x() ||
++	    soc_is_ar913x() ||
++	    soc_is_ar933x())
++		reg = AR71XX_GPIO_REG_FUNC;
++	else if (soc_is_ar934x())
++		reg = AR934X_GPIO_REG_FUNC;
++	else
++		BUG();
++
++	return ath79_gpio_base + reg;
++}
++
+ void ath79_gpio_function_enable(u32 mask)
+ {
+-	void __iomem *base = ath79_gpio_base;
++	void __iomem *reg = ath79_gpio_get_function_reg();
+ 	unsigned long flags;
+ 
+ 	spin_lock_irqsave(&ath79_gpio_lock, flags);
+ 
+-	__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) | mask,
+-		     base + AR71XX_GPIO_REG_FUNC);
++	__raw_writel(__raw_readl(reg) | mask, reg);
+ 	/* flush write */
+-	__raw_readl(base + AR71XX_GPIO_REG_FUNC);
++	__raw_readl(reg);
+ 
+ 	spin_unlock_irqrestore(&ath79_gpio_lock, flags);
+ }
+ 
+ void ath79_gpio_function_disable(u32 mask)
+ {
+-	void __iomem *base = ath79_gpio_base;
++	void __iomem *reg = ath79_gpio_get_function_reg();
+ 	unsigned long flags;
+ 
+ 	spin_lock_irqsave(&ath79_gpio_lock, flags);
+ 
+-	__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~mask,
+-		     base + AR71XX_GPIO_REG_FUNC);
++	__raw_writel(__raw_readl(reg) & ~mask, reg);
+ 	/* flush write */
+-	__raw_readl(base + AR71XX_GPIO_REG_FUNC);
++	__raw_readl(reg);
+ 
+ 	spin_unlock_irqrestore(&ath79_gpio_lock, flags);
+ }
+ 
+ void ath79_gpio_function_setup(u32 set, u32 clear)
+ {
+-	void __iomem *base = ath79_gpio_base;
++	void __iomem *reg = ath79_gpio_get_function_reg();
+ 	unsigned long flags;
+ 
+ 	spin_lock_irqsave(&ath79_gpio_lock, flags);
+ 
+-	__raw_writel((__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~clear) | set,
+-		     base + AR71XX_GPIO_REG_FUNC);
++	__raw_writel((__raw_readl(reg) & ~clear) | set, reg);
+ 	/* flush write */
+-	__raw_readl(base + AR71XX_GPIO_REG_FUNC);
++	__raw_readl(reg);
+ 
+ 	spin_unlock_irqrestore(&ath79_gpio_lock, flags);
+ }
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -401,6 +401,8 @@
+ #define AR71XX_GPIO_REG_INT_ENABLE	0x24
+ #define AR71XX_GPIO_REG_FUNC		0x28
+ 
++#define AR934X_GPIO_REG_FUNC		0x6c
++
+ #define AR71XX_GPIO_COUNT		16
+ #define AR7240_GPIO_COUNT		18
+ #define AR7241_GPIO_COUNT		20
diff --git a/target/linux/ar71xx/patches-3.8/008-MIPS-ath79-simplify-ath79_gpio_function_-routines.patch b/target/linux/ar71xx/patches-3.8/008-MIPS-ath79-simplify-ath79_gpio_function_-routines.patch
new file mode 100644
index 0000000..8606f3b
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/008-MIPS-ath79-simplify-ath79_gpio_function_-routines.patch
@@ -0,0 +1,72 @@
+From 6c888a88f2a9939182bf41151f079a6b59f1593c Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Tue, 29 Jan 2013 08:19:13 +0000
+Subject: [PATCH] MIPS: ath79: simplify ath79_gpio_function_* routines
+
+commit f160a289e0e8848391f5ec48ff1a014b9c04b162 upstream.
+
+Make ath79_gpio_function_{en,dis}able to be wrappers
+around ath79_gpio_function_setup.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4871/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/gpio.c |   30 ++++++------------------------
+ 1 file changed, 6 insertions(+), 24 deletions(-)
+
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -154,46 +154,28 @@ static void __iomem *ath79_gpio_get_func
+ 	return ath79_gpio_base + reg;
+ }
+ 
+-void ath79_gpio_function_enable(u32 mask)
++void ath79_gpio_function_setup(u32 set, u32 clear)
+ {
+ 	void __iomem *reg = ath79_gpio_get_function_reg();
+ 	unsigned long flags;
+ 
+ 	spin_lock_irqsave(&ath79_gpio_lock, flags);
+ 
+-	__raw_writel(__raw_readl(reg) | mask, reg);
++	__raw_writel((__raw_readl(reg) & ~clear) | set, reg);
+ 	/* flush write */
+ 	__raw_readl(reg);
+ 
+ 	spin_unlock_irqrestore(&ath79_gpio_lock, flags);
+ }
+ 
+-void ath79_gpio_function_disable(u32 mask)
++void ath79_gpio_function_enable(u32 mask)
+ {
+-	void __iomem *reg = ath79_gpio_get_function_reg();
+-	unsigned long flags;
+-
+-	spin_lock_irqsave(&ath79_gpio_lock, flags);
+-
+-	__raw_writel(__raw_readl(reg) & ~mask, reg);
+-	/* flush write */
+-	__raw_readl(reg);
+-
+-	spin_unlock_irqrestore(&ath79_gpio_lock, flags);
++	ath79_gpio_function_setup(mask, 0);
+ }
+ 
+-void ath79_gpio_function_setup(u32 set, u32 clear)
++void ath79_gpio_function_disable(u32 mask)
+ {
+-	void __iomem *reg = ath79_gpio_get_function_reg();
+-	unsigned long flags;
+-
+-	spin_lock_irqsave(&ath79_gpio_lock, flags);
+-
+-	__raw_writel((__raw_readl(reg) & ~clear) | set, reg);
+-	/* flush write */
+-	__raw_readl(reg);
+-
+-	spin_unlock_irqrestore(&ath79_gpio_lock, flags);
++	ath79_gpio_function_setup(0, mask);
+ }
+ 
+ void __init ath79_gpio_init(void)
diff --git a/target/linux/ar71xx/patches-3.8/009-MIPS-ath79-simplify-MISC-IRQ-handling.patch b/target/linux/ar71xx/patches-3.8/009-MIPS-ath79-simplify-MISC-IRQ-handling.patch
new file mode 100644
index 0000000..146bf25
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/009-MIPS-ath79-simplify-MISC-IRQ-handling.patch
@@ -0,0 +1,90 @@
+From 1690e8f8efdeedbd23bb34a3bc5803c34f2d3f66 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Tue, 29 Jan 2013 16:13:17 +0000
+Subject: [PATCH] MIPS: ath79: simplify MISC IRQ handling
+
+commit 9c099c4e79b67d5578ce8142e6214950be4fcf43 upstream.
+
+The current code uses multiple if statements for
+demultiplexing the different interrupt sources.
+Additionally, the MISC interrupt controller has
+32 interrupt sources and the current code does not
+handles all of them.
+
+Get rid of the if statements and process all interrupt
+sources in a loop to fix these issues.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4874/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/irq.c                  |   45 +++++++-------------------------
+ arch/mips/include/asm/mach-ath79/irq.h |    1 +
+ 2 files changed, 10 insertions(+), 36 deletions(-)
+
+--- a/arch/mips/ath79/irq.c
++++ b/arch/mips/ath79/irq.c
+@@ -35,44 +35,17 @@ static void ath79_misc_irq_handler(unsig
+ 	pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
+ 		  __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
+ 
+-	if (pending & MISC_INT_UART)
+-		generic_handle_irq(ATH79_MISC_IRQ_UART);
+-
+-	else if (pending & MISC_INT_DMA)
+-		generic_handle_irq(ATH79_MISC_IRQ_DMA);
+-
+-	else if (pending & MISC_INT_PERFC)
+-		generic_handle_irq(ATH79_MISC_IRQ_PERFC);
+-
+-	else if (pending & MISC_INT_TIMER)
+-		generic_handle_irq(ATH79_MISC_IRQ_TIMER);
+-
+-	else if (pending & MISC_INT_TIMER2)
+-		generic_handle_irq(ATH79_MISC_IRQ_TIMER2);
+-
+-	else if (pending & MISC_INT_TIMER3)
+-		generic_handle_irq(ATH79_MISC_IRQ_TIMER3);
+-
+-	else if (pending & MISC_INT_TIMER4)
+-		generic_handle_irq(ATH79_MISC_IRQ_TIMER4);
+-
+-	else if (pending & MISC_INT_OHCI)
+-		generic_handle_irq(ATH79_MISC_IRQ_OHCI);
+-
+-	else if (pending & MISC_INT_ERROR)
+-		generic_handle_irq(ATH79_MISC_IRQ_ERROR);
+-
+-	else if (pending & MISC_INT_GPIO)
+-		generic_handle_irq(ATH79_MISC_IRQ_GPIO);
+-
+-	else if (pending & MISC_INT_WDOG)
+-		generic_handle_irq(ATH79_MISC_IRQ_WDOG);
++	if (!pending) {
++		spurious_interrupt();
++		return;
++	}
+ 
+-	else if (pending & MISC_INT_ETHSW)
+-		generic_handle_irq(ATH79_MISC_IRQ_ETHSW);
++	while (pending) {
++		int bit = __ffs(pending);
+ 
+-	else
+-		spurious_interrupt();
++		generic_handle_irq(ATH79_MISC_IRQ(bit));
++		pending &= ~BIT(bit);
++	}
+ }
+ 
+ static void ar71xx_misc_irq_unmask(struct irq_data *d)
+--- a/arch/mips/include/asm/mach-ath79/irq.h
++++ b/arch/mips/include/asm/mach-ath79/irq.h
+@@ -14,6 +14,7 @@
+ 
+ #define ATH79_MISC_IRQ_BASE	8
+ #define ATH79_MISC_IRQ_COUNT	32
++#define ATH79_MISC_IRQ(_x)	(ATH79_MISC_IRQ_BASE + (_x))
+ 
+ #define ATH79_PCI_IRQ_BASE	(ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT)
+ #define ATH79_PCI_IRQ_COUNT	6
diff --git a/target/linux/ar71xx/patches-3.8/010-MIPS-pci-ar724x-convert-into-a-platform-driver.patch b/target/linux/ar71xx/patches-3.8/010-MIPS-pci-ar724x-convert-into-a-platform-driver.patch
new file mode 100644
index 0000000..e7b7b15
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/010-MIPS-pci-ar724x-convert-into-a-platform-driver.patch
@@ -0,0 +1,102 @@
+From 42541838d9fdbad8573141d69cf8e38831a6cbb6 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sat, 2 Feb 2013 11:40:42 +0000
+Subject: [PATCH] MIPS: pci-ar724x: convert into a platform driver
+
+commit 58d2e9bcd682d76bcb9575dc56c85f1d82a81bfa upstream.
+
+The patch converts the pci-ar724x driver into a
+platform driver. This makes it possible to register
+the PCI controller as a plain platform device.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4905/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/pci-ar724x.c |   57 ++++++++++++++++++++++++++++++++++++++++++--
+ 1 file changed, 55 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -11,6 +11,8 @@
+ 
+ #include <linux/irq.h>
+ #include <linux/pci.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/pci.h>
+@@ -262,7 +264,7 @@ static struct irq_chip ar724x_pci_irq_ch
+ 	.irq_mask_ack	= ar724x_pci_irq_mask,
+ };
+ 
+-static void __init ar724x_pci_irq_init(int irq)
++static void ar724x_pci_irq_init(int irq)
+ {
+ 	void __iomem *base;
+ 	int i;
+@@ -282,7 +284,7 @@ static void __init ar724x_pci_irq_init(i
+ 	irq_set_chained_handler(irq, ar724x_pci_irq_handler);
+ }
+ 
+-int __init ar724x_pcibios_init(int irq)
++int ar724x_pcibios_init(int irq)
+ {
+ 	int ret;
+ 
+@@ -312,3 +314,54 @@ err_unmap_devcfg:
+ err:
+ 	return ret;
+ }
++
++static int ar724x_pci_probe(struct platform_device *pdev)
++{
++	struct resource *res;
++	int irq;
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base");
++	if (!res)
++		return -EINVAL;
++
++	ar724x_pci_ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
++	if (ar724x_pci_ctrl_base == NULL)
++		return -EBUSY;
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
++	if (!res)
++		return -EINVAL;
++
++	ar724x_pci_devcfg_base = devm_request_and_ioremap(&pdev->dev, res);
++	if (!ar724x_pci_devcfg_base)
++		return -EBUSY;
++
++	irq = platform_get_irq(pdev, 0);
++	if (irq < 0)
++		return -EINVAL;
++
++	ar724x_pci_link_up = ar724x_pci_check_link();
++	if (!ar724x_pci_link_up)
++		dev_warn(&pdev->dev, "PCIe link is down\n");
++
++	ar724x_pci_irq_init(irq);
++
++	register_pci_controller(&ar724x_pci_controller);
++
++	return 0;
++}
++
++static struct platform_driver ar724x_pci_driver = {
++	.probe = ar724x_pci_probe,
++	.driver = {
++		.name = "ar724x-pci",
++		.owner = THIS_MODULE,
++	},
++};
++
++static int __init ar724x_pci_init(void)
++{
++	return platform_driver_register(&ar724x_pci_driver);
++}
++
++postcore_initcall(ar724x_pci_init);
diff --git a/target/linux/ar71xx/patches-3.8/011-MIPS-pci-ar71xx-convert-into-a-platform-driver.patch b/target/linux/ar71xx/patches-3.8/011-MIPS-pci-ar71xx-convert-into-a-platform-driver.patch
new file mode 100644
index 0000000..e6bd8d0
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/011-MIPS-pci-ar71xx-convert-into-a-platform-driver.patch
@@ -0,0 +1,112 @@
+From 060c9a226a25e044167e877d9830ec53f836da9e Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sat, 2 Feb 2013 11:40:43 +0000
+Subject: [PATCH] MIPS: pci-ar71xx: convert into a platform driver
+
+commit fb167e891d5cc6386840dd092af2d461b38eb802 upstream.
+
+The patch converts the pci-ar71xx driver into a
+platform driver. This makes it possible to register
+the PCI controller as a plain platform device.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4906/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/pci-ar71xx.c |   60 +++++++++++++++++++++++++++++++++++++++++---
+ 1 file changed, 56 insertions(+), 4 deletions(-)
+
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -18,6 +18,8 @@
+ #include <linux/pci.h>
+ #include <linux/pci_regs.h>
+ #include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
+ 
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
+@@ -309,7 +311,7 @@ static struct irq_chip ar71xx_pci_irq_ch
+ 	.irq_mask_ack	= ar71xx_pci_irq_mask,
+ };
+ 
+-static __init void ar71xx_pci_irq_init(void)
++static void ar71xx_pci_irq_init(int irq)
+ {
+ 	void __iomem *base = ath79_reset_base;
+ 	int i;
+@@ -324,10 +326,10 @@ static __init void ar71xx_pci_irq_init(v
+ 		irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
+ 					 handle_level_irq);
+ 
+-	irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar71xx_pci_irq_handler);
++	irq_set_chained_handler(irq, ar71xx_pci_irq_handler);
+ }
+ 
+-static __init void ar71xx_pci_reset(void)
++static void ar71xx_pci_reset(void)
+ {
+ 	void __iomem *ddr_base = ath79_ddr_base;
+ 
+@@ -367,9 +369,59 @@ __init int ar71xx_pcibios_init(void)
+ 	/* clear bus errors */
+ 	ar71xx_pci_check_error(1);
+ 
+-	ar71xx_pci_irq_init();
++	ar71xx_pci_irq_init(ATH79_CPU_IRQ_IP2);
+ 
+ 	register_pci_controller(&ar71xx_pci_controller);
+ 
+ 	return 0;
+ }
++
++static int ar71xx_pci_probe(struct platform_device *pdev)
++{
++	struct resource *res;
++	int irq;
++	u32 t;
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
++	if (!res)
++		return -EINVAL;
++
++	ar71xx_pcicfg_base = devm_request_and_ioremap(&pdev->dev, res);
++	if (!ar71xx_pcicfg_base)
++		return -ENOMEM;
++
++	irq = platform_get_irq(pdev, 0);
++	if (irq < 0)
++		return -EINVAL;
++
++	ar71xx_pci_reset();
++
++	/* setup COMMAND register */
++	t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
++	  | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
++	ar71xx_pci_local_write(PCI_COMMAND, 4, t);
++
++	/* clear bus errors */
++	ar71xx_pci_check_error(1);
++
++	ar71xx_pci_irq_init(irq);
++
++	register_pci_controller(&ar71xx_pci_controller);
++
++	return 0;
++}
++
++static struct platform_driver ar71xx_pci_driver = {
++	.probe = ar71xx_pci_probe,
++	.driver = {
++		.name = "ar71xx-pci",
++		.owner = THIS_MODULE,
++	},
++};
++
++static int __init ar71xx_pci_init(void)
++{
++	return platform_driver_register(&ar71xx_pci_driver);
++}
++
++postcore_initcall(ar71xx_pci_init);
diff --git a/target/linux/ar71xx/patches-3.8/012-MIPS-ath79-move-global-PCI-defines-into-a-common-hea.patch b/target/linux/ar71xx/patches-3.8/012-MIPS-ath79-move-global-PCI-defines-into-a-common-hea.patch
new file mode 100644
index 0000000..eaff04b
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/012-MIPS-ath79-move-global-PCI-defines-into-a-common-hea.patch
@@ -0,0 +1,98 @@
+From 1dece618b107f5db28c8f63d4d32424dd18324d1 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 4 Feb 2013 11:56:53 +0100
+Subject: [PATCH] MIPS: ath79: move global PCI defines into a common header
+
+commit ad4ce92e919f7ad5561a2060deb58899de58b40c upstream.
+
+The constants will be used by a subsequent patch.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4907/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |   24 ++++++++++++++++++++++++
+ arch/mips/pci/pci-ar71xx.c                     |   16 ----------------
+ arch/mips/pci/pci-ar724x.c                     |    8 --------
+ 3 files changed, 24 insertions(+), 24 deletions(-)
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -41,11 +41,35 @@
+ #define AR71XX_RESET_BASE	(AR71XX_APB_BASE + 0x00060000)
+ #define AR71XX_RESET_SIZE	0x100
+ 
++#define AR71XX_PCI_MEM_BASE	0x10000000
++#define AR71XX_PCI_MEM_SIZE	0x07000000
++
++#define AR71XX_PCI_WIN0_OFFS	0x10000000
++#define AR71XX_PCI_WIN1_OFFS	0x11000000
++#define AR71XX_PCI_WIN2_OFFS	0x12000000
++#define AR71XX_PCI_WIN3_OFFS	0x13000000
++#define AR71XX_PCI_WIN4_OFFS	0x14000000
++#define AR71XX_PCI_WIN5_OFFS	0x15000000
++#define AR71XX_PCI_WIN6_OFFS	0x16000000
++#define AR71XX_PCI_WIN7_OFFS	0x07000000
++
++#define AR71XX_PCI_CFG_BASE	\
++	(AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
++#define AR71XX_PCI_CFG_SIZE	0x100
++
+ #define AR7240_USB_CTRL_BASE	(AR71XX_APB_BASE + 0x00030000)
+ #define AR7240_USB_CTRL_SIZE	0x100
+ #define AR7240_OHCI_BASE	0x1b000000
+ #define AR7240_OHCI_SIZE	0x1000
+ 
++#define AR724X_PCI_MEM_BASE	0x10000000
++#define AR724X_PCI_MEM_SIZE	0x04000000
++
++#define AR724X_PCI_CFG_BASE	0x14000000
++#define AR724X_PCI_CFG_SIZE	0x1000
++#define AR724X_PCI_CTRL_BASE	(AR71XX_APB_BASE + 0x000f0000)
++#define AR724X_PCI_CTRL_SIZE	0x100
++
+ #define AR724X_EHCI_BASE	0x1b000000
+ #define AR724X_EHCI_SIZE	0x1000
+ 
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -25,22 +25,6 @@
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/pci.h>
+ 
+-#define AR71XX_PCI_MEM_BASE	0x10000000
+-#define AR71XX_PCI_MEM_SIZE	0x07000000
+-
+-#define AR71XX_PCI_WIN0_OFFS		0x10000000
+-#define AR71XX_PCI_WIN1_OFFS		0x11000000
+-#define AR71XX_PCI_WIN2_OFFS		0x12000000
+-#define AR71XX_PCI_WIN3_OFFS		0x13000000
+-#define AR71XX_PCI_WIN4_OFFS		0x14000000
+-#define AR71XX_PCI_WIN5_OFFS		0x15000000
+-#define AR71XX_PCI_WIN6_OFFS		0x16000000
+-#define AR71XX_PCI_WIN7_OFFS		0x07000000
+-
+-#define AR71XX_PCI_CFG_BASE		\
+-	(AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
+-#define AR71XX_PCI_CFG_SIZE		0x100
+-
+ #define AR71XX_PCI_REG_CRP_AD_CBE	0x00
+ #define AR71XX_PCI_REG_CRP_WRDATA	0x04
+ #define AR71XX_PCI_REG_CRP_RDDATA	0x08
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -17,14 +17,6 @@
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/pci.h>
+ 
+-#define AR724X_PCI_CFG_BASE	0x14000000
+-#define AR724X_PCI_CFG_SIZE	0x1000
+-#define AR724X_PCI_CTRL_BASE	(AR71XX_APB_BASE + 0x000f0000)
+-#define AR724X_PCI_CTRL_SIZE	0x100
+-
+-#define AR724X_PCI_MEM_BASE	0x10000000
+-#define AR724X_PCI_MEM_SIZE	0x04000000
+-
+ #define AR724X_PCI_REG_RESET		0x18
+ #define AR724X_PCI_REG_INT_STATUS	0x4c
+ #define AR724X_PCI_REG_INT_MASK		0x50
diff --git a/target/linux/ar71xx/patches-3.8/013-MIPS-ath79-register-platform-devices-for-the-PCI-con.patch b/target/linux/ar71xx/patches-3.8/013-MIPS-ath79-register-platform-devices-for-the-PCI-con.patch
new file mode 100644
index 0000000..eee791e
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/013-MIPS-ath79-register-platform-devices-for-the-PCI-con.patch
@@ -0,0 +1,129 @@
+From 87cdbe4315e4c72c2bc8568d1258e1207e1c772b Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sat, 2 Feb 2013 11:44:24 +0000
+Subject: [PATCH] MIPS: ath79: register platform devices for the PCI
+ controllers
+
+commit 9fc1ca5b73a82daedffa2d1d5daa48dd2093c39a upstream.
+
+The pci-ar71xx and pci-ar724x drivers were converted
+into platform drivers. Register the corresponding
+platform devices for the PCI controllers instead
+of using the ar7{1x,24}x_pcibios_init functions.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4908/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/pci.c |   87 ++++++++++++++++++++++++++++++++++++++++++++-----
+ 1 file changed, 78 insertions(+), 9 deletions(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -14,6 +14,8 @@
+ 
+ #include <linux/init.h>
+ #include <linux/pci.h>
++#include <linux/resource.h>
++#include <linux/platform_device.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/irq.h>
+@@ -110,21 +112,88 @@ void __init ath79_pci_set_plat_dev_init(
+ 	ath79_pci_plat_dev_init = func;
+ }
+ 
+-int __init ath79_register_pci(void)
++static struct platform_device *
++ath79_register_pci_ar71xx(void)
+ {
+-	if (soc_is_ar71xx())
+-		return ar71xx_pcibios_init();
++	struct platform_device *pdev;
++	struct resource res[2];
++
++	memset(res, 0, sizeof(res));
+ 
+-	if (soc_is_ar724x())
+-		return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
++	res[0].name = "cfg_base";
++	res[0].flags = IORESOURCE_MEM;
++	res[0].start = AR71XX_PCI_CFG_BASE;
++	res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1;
++
++	res[1].flags = IORESOURCE_IRQ;
++	res[1].start = ATH79_CPU_IRQ_IP2;
++	res[1].end = ATH79_CPU_IRQ_IP2;
++
++	pdev = platform_device_register_simple("ar71xx-pci", -1,
++					       res, ARRAY_SIZE(res));
++	return pdev;
++}
+ 
+-	if (soc_is_ar9342() || soc_is_ar9344()) {
++static struct platform_device *
++ath79_register_pci_ar724x(int id,
++			  unsigned long cfg_base,
++			  unsigned long ctrl_base,
++			  int irq)
++{
++	struct platform_device *pdev;
++	struct resource res[3];
++
++	memset(res, 0, sizeof(res));
++
++	res[0].name = "cfg_base";
++	res[0].flags = IORESOURCE_MEM;
++	res[0].start = cfg_base;
++	res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1;
++
++	res[1].name = "ctrl_base";
++	res[1].flags = IORESOURCE_MEM;
++	res[1].start = ctrl_base;
++	res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1;
++
++	res[2].flags = IORESOURCE_IRQ;
++	res[2].start = irq;
++	res[2].end = irq;
++
++	pdev = platform_device_register_simple("ar724x-pci", id,
++					       res, ARRAY_SIZE(res));
++	return pdev;
++}
++
++int __init ath79_register_pci(void)
++{
++	struct platform_device *pdev = NULL;
++
++	if (soc_is_ar71xx()) {
++		pdev = ath79_register_pci_ar71xx();
++	} else if (soc_is_ar724x()) {
++		pdev = ath79_register_pci_ar724x(-1,
++						 AR724X_PCI_CFG_BASE,
++						 AR724X_PCI_CTRL_BASE,
++						 ATH79_CPU_IRQ_IP2);
++	} else if (soc_is_ar9342() ||
++		   soc_is_ar9344()) {
+ 		u32 bootstrap;
+ 
+ 		bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
+-		if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC)
+-			return ar724x_pcibios_init(ATH79_IP2_IRQ(0));
++		if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0)
++			return -ENODEV;
++
++		pdev = ath79_register_pci_ar724x(-1,
++						 AR724X_PCI_CFG_BASE,
++						 AR724X_PCI_CTRL_BASE,
++						 ATH79_IP2_IRQ(0));
++	} else {
++		/* No PCI support */
++		return -ENODEV;
+ 	}
+ 
+-	return -ENODEV;
++	if (!pdev)
++		pr_err("unable to register PCI controller device\n");
++
++	return pdev ? 0 : -ENODEV;
+ }
diff --git a/target/linux/ar71xx/patches-3.8/014-MIPS-ath79-remove-unused-ar7-1x-24-x_pcibios_init-fu.patch b/target/linux/ar71xx/patches-3.8/014-MIPS-ath79-remove-unused-ar7-1x-24-x_pcibios_init-fu.patch
new file mode 100644
index 0000000..978a33d
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/014-MIPS-ath79-remove-unused-ar7-1x-24-x_pcibios_init-fu.patch
@@ -0,0 +1,152 @@
+From db36c9d6a6be232bdee245407fc8ccde53ea69c6 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 4 Feb 2013 11:58:49 +0100
+Subject: [PATCH] MIPS: ath79: remove unused ar7{1x,24}x_pcibios_init
+ functions
+
+commit 6e783865b4e60f2ecf7708f8ea24db5c5ea07ced upstream.
+
+The functions are unused now, so remove them.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4909/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/pci.c                  |    1 -
+ arch/mips/include/asm/mach-ath79/pci.h |   28 ----------------------------
+ arch/mips/pci/pci-ar71xx.c             |   26 --------------------------
+ arch/mips/pci/pci-ar724x.c             |   32 --------------------------------
+ 4 files changed, 87 deletions(-)
+ delete mode 100644 arch/mips/include/asm/mach-ath79/pci.h
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -19,7 +19,6 @@
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/irq.h>
+-#include <asm/mach-ath79/pci.h>
+ #include "pci.h"
+ 
+ static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
+--- a/arch/mips/include/asm/mach-ath79/pci.h
++++ /dev/null
+@@ -1,28 +0,0 @@
+-/*
+- *  Atheros AR71XX/AR724X PCI support
+- *
+- *  Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
+- *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+- *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+- *
+- *  This program is free software; you can redistribute it and/or modify it
+- *  under the terms of the GNU General Public License version 2 as published
+- *  by the Free Software Foundation.
+- */
+-
+-#ifndef __ASM_MACH_ATH79_PCI_H
+-#define __ASM_MACH_ATH79_PCI_H
+-
+-#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX)
+-int ar71xx_pcibios_init(void);
+-#else
+-static inline int ar71xx_pcibios_init(void) { return 0; }
+-#endif
+-
+-#if defined(CONFIG_PCI_AR724X)
+-int ar724x_pcibios_init(int irq);
+-#else
+-static inline int ar724x_pcibios_init(int irq) { return 0; }
+-#endif
+-
+-#endif /* __ASM_MACH_ATH79_PCI_H */
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -23,7 +23,6 @@
+ 
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
+-#include <asm/mach-ath79/pci.h>
+ 
+ #define AR71XX_PCI_REG_CRP_AD_CBE	0x00
+ #define AR71XX_PCI_REG_CRP_WRDATA	0x04
+@@ -335,31 +334,6 @@ static void ar71xx_pci_reset(void)
+ 	mdelay(100);
+ }
+ 
+-__init int ar71xx_pcibios_init(void)
+-{
+-	u32 t;
+-
+-	ar71xx_pcicfg_base = ioremap(AR71XX_PCI_CFG_BASE, AR71XX_PCI_CFG_SIZE);
+-	if (ar71xx_pcicfg_base == NULL)
+-		return -ENOMEM;
+-
+-	ar71xx_pci_reset();
+-
+-	/* setup COMMAND register */
+-	t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
+-	  | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
+-	ar71xx_pci_local_write(PCI_COMMAND, 4, t);
+-
+-	/* clear bus errors */
+-	ar71xx_pci_check_error(1);
+-
+-	ar71xx_pci_irq_init(ATH79_CPU_IRQ_IP2);
+-
+-	register_pci_controller(&ar71xx_pci_controller);
+-
+-	return 0;
+-}
+-
+ static int ar71xx_pci_probe(struct platform_device *pdev)
+ {
+ 	struct resource *res;
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -15,7 +15,6 @@
+ #include <linux/platform_device.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
+-#include <asm/mach-ath79/pci.h>
+ 
+ #define AR724X_PCI_REG_RESET		0x18
+ #define AR724X_PCI_REG_INT_STATUS	0x4c
+@@ -276,37 +275,6 @@ static void ar724x_pci_irq_init(int irq)
+ 	irq_set_chained_handler(irq, ar724x_pci_irq_handler);
+ }
+ 
+-int ar724x_pcibios_init(int irq)
+-{
+-	int ret;
+-
+-	ret = -ENOMEM;
+-
+-	ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE,
+-					 AR724X_PCI_CFG_SIZE);
+-	if (ar724x_pci_devcfg_base == NULL)
+-		goto err;
+-
+-	ar724x_pci_ctrl_base = ioremap(AR724X_PCI_CTRL_BASE,
+-				       AR724X_PCI_CTRL_SIZE);
+-	if (ar724x_pci_ctrl_base == NULL)
+-		goto err_unmap_devcfg;
+-
+-	ar724x_pci_link_up = ar724x_pci_check_link();
+-	if (!ar724x_pci_link_up)
+-		pr_warn("ar724x: PCIe link is down\n");
+-
+-	ar724x_pci_irq_init(irq);
+-	register_pci_controller(&ar724x_pci_controller);
+-
+-	return PCIBIOS_SUCCESSFUL;
+-
+-err_unmap_devcfg:
+-	iounmap(ar724x_pci_devcfg_base);
+-err:
+-	return ret;
+-}
+-
+ static int ar724x_pci_probe(struct platform_device *pdev)
+ {
+ 	struct resource *res;
diff --git a/target/linux/ar71xx/patches-3.8/015-MIPS-avoid-possible-resource-conflict-in-register_pc.patch b/target/linux/ar71xx/patches-3.8/015-MIPS-avoid-possible-resource-conflict-in-register_pc.patch
new file mode 100644
index 0000000..613c7ad
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/015-MIPS-avoid-possible-resource-conflict-in-register_pc.patch
@@ -0,0 +1,52 @@
+From 4da85831c8eaf2de2cadae6723e8231068c313b7 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sat, 2 Feb 2013 13:18:54 +0000
+Subject: [PATCH] MIPS: avoid possible resource conflict in
+ register_pci_controller
+
+commit 222831787704c9ad9215f6b56f975b233968607c upstream.
+
+The IO and memory resources of a PCI controller
+might already have a parent resource set when
+they are passed to 'register_pci_controller'.
+
+If the parent resource is set, the request_resource
+call will fail due to resource conflict and the
+current code will not be able to register the
+PCI controller.
+
+Use the parent resource if it is available in the
+request_resource call to avoid the isssue.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4910/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/pci.c |   15 +++++++++++++--
+ 1 file changed, 13 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/pci/pci.c
++++ b/arch/mips/pci/pci.c
+@@ -175,9 +175,20 @@ static DEFINE_MUTEX(pci_scan_mutex);
+ 
+ void register_pci_controller(struct pci_controller *hose)
+ {
+-	if (request_resource(&iomem_resource, hose->mem_resource) < 0)
++	struct resource *parent;
++
++	parent = hose->mem_resource->parent;
++	if (!parent)
++		parent = &iomem_resource;
++
++	if (request_resource(parent, hose->mem_resource) < 0)
+ 		goto out;
+-	if (request_resource(&ioport_resource, hose->io_resource) < 0) {
++
++	parent = hose->io_resource->parent;
++	if (!parent)
++		parent = &ioport_resource;
++
++	if (request_resource(parent, hose->io_resource) < 0) {
+ 		release_resource(hose->mem_resource);
+ 		goto out;
+ 	}
diff --git a/target/linux/ar71xx/patches-3.8/016-MIPS-ath79-allow-to-specify-bus-number-in-PCI-IRQ-ma.patch b/target/linux/ar71xx/patches-3.8/016-MIPS-ath79-allow-to-specify-bus-number-in-PCI-IRQ-ma.patch
new file mode 100644
index 0000000..477bddb
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/016-MIPS-ath79-allow-to-specify-bus-number-in-PCI-IRQ-ma.patch
@@ -0,0 +1,40 @@
+From 53ba4919664636487155c810fb49781169780e0c Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 3 Feb 2013 09:58:37 +0000
+Subject: [PATCH] MIPS: ath79: allow to specify bus number in PCI IRQ maps
+
+commit 617fed41e98417f3ea3e9974be251e125c8796f2 upstream.
+
+This is needed for multiple PCI bus support.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4913/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/pci.c |    4 +++-
+ arch/mips/ath79/pci.h |    1 +
+ 2 files changed, 4 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -75,7 +75,9 @@ int __init pcibios_map_irq(const struct
+ 		const struct ath79_pci_irq *entry;
+ 
+ 		entry = &ath79_pci_irq_map[i];
+-		if (entry->slot == slot && entry->pin == pin) {
++		if (entry->bus == dev->bus->number &&
++		    entry->slot == slot &&
++		    entry->pin == pin) {
+ 			irq = entry->irq;
+ 			break;
+ 		}
+--- a/arch/mips/ath79/pci.h
++++ b/arch/mips/ath79/pci.h
+@@ -14,6 +14,7 @@
+ #define _ATH79_PCI_H
+ 
+ struct ath79_pci_irq {
++	int	bus;
+ 	u8	slot;
+ 	u8	pin;
+ 	int	irq;
diff --git a/target/linux/ar71xx/patches-3.8/017-MIPS-pci-ar724x-use-dynamically-allocated-PCI-contro.patch b/target/linux/ar71xx/patches-3.8/017-MIPS-pci-ar724x-use-dynamically-allocated-PCI-contro.patch
new file mode 100644
index 0000000..a960cb3
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/017-MIPS-pci-ar724x-use-dynamically-allocated-PCI-contro.patch
@@ -0,0 +1,321 @@
+From 21b3cafae425cf2e317a22292a9a5773ff0e2e5e Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 3 Feb 2013 09:58:38 +0000
+Subject: [PATCH] MIPS: pci-ar724x: use dynamically allocated PCI controller
+ structure
+
+commit 908339ef25b1d5e80f1c6fab22b9958174708b4a upstream.
+
+The current code uses static variables to store the
+PCI controller specific data. This works if the system
+contains one PCI controller only, however it becomes
+impractical when multiple PCI controllers are present.
+
+Move the variables into a dynamically allocated controller
+specific structure, and use that instead of the static
+variables.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4912/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/pci-ar724x.c |  129 ++++++++++++++++++++++++++++----------------
+ 1 file changed, 82 insertions(+), 47 deletions(-)
+
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -9,6 +9,7 @@
+  *  by the Free Software Foundation.
+  */
+ 
++#include <linux/spinlock.h>
+ #include <linux/irq.h>
+ #include <linux/pci.h>
+ #include <linux/module.h>
+@@ -28,38 +29,56 @@
+ 
+ #define AR7240_BAR0_WAR_VALUE	0xffff
+ 
+-static DEFINE_SPINLOCK(ar724x_pci_lock);
+-static void __iomem *ar724x_pci_devcfg_base;
+-static void __iomem *ar724x_pci_ctrl_base;
+-
+-static u32 ar724x_pci_bar0_value;
+-static bool ar724x_pci_bar0_is_cached;
+-static bool ar724x_pci_link_up;
++struct ar724x_pci_controller {
++	void __iomem *devcfg_base;
++	void __iomem *ctrl_base;
+ 
+-static inline bool ar724x_pci_check_link(void)
++	int irq;
++
++	bool link_up;
++	bool bar0_is_cached;
++	u32  bar0_value;
++
++	spinlock_t lock;
++
++	struct pci_controller pci_controller;
++};
++
++static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
+ {
+ 	u32 reset;
+ 
+-	reset = __raw_readl(ar724x_pci_ctrl_base + AR724X_PCI_REG_RESET);
++	reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET);
+ 	return reset & AR724X_PCI_RESET_LINK_UP;
+ }
+ 
++static inline struct ar724x_pci_controller *
++pci_bus_to_ar724x_controller(struct pci_bus *bus)
++{
++	struct pci_controller *hose;
++
++	hose = (struct pci_controller *) bus->sysdata;
++	return container_of(hose, struct ar724x_pci_controller, pci_controller);
++}
++
+ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+ 			    int size, uint32_t *value)
+ {
++	struct ar724x_pci_controller *apc;
+ 	unsigned long flags;
+ 	void __iomem *base;
+ 	u32 data;
+ 
+-	if (!ar724x_pci_link_up)
++	apc = pci_bus_to_ar724x_controller(bus);
++	if (!apc->link_up)
+ 		return PCIBIOS_DEVICE_NOT_FOUND;
+ 
+ 	if (devfn)
+ 		return PCIBIOS_DEVICE_NOT_FOUND;
+ 
+-	base = ar724x_pci_devcfg_base;
++	base = apc->devcfg_base;
+ 
+-	spin_lock_irqsave(&ar724x_pci_lock, flags);
++	spin_lock_irqsave(&apc->lock, flags);
+ 	data = __raw_readl(base + (where & ~3));
+ 
+ 	switch (size) {
+@@ -78,17 +97,17 @@ static int ar724x_pci_read(struct pci_bu
+ 	case 4:
+ 		break;
+ 	default:
+-		spin_unlock_irqrestore(&ar724x_pci_lock, flags);
++		spin_unlock_irqrestore(&apc->lock, flags);
+ 
+ 		return PCIBIOS_BAD_REGISTER_NUMBER;
+ 	}
+ 
+-	spin_unlock_irqrestore(&ar724x_pci_lock, flags);
++	spin_unlock_irqrestore(&apc->lock, flags);
+ 
+ 	if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
+-	    ar724x_pci_bar0_is_cached) {
++	    apc->bar0_is_cached) {
+ 		/* use the cached value */
+-		*value = ar724x_pci_bar0_value;
++		*value = apc->bar0_value;
+ 	} else {
+ 		*value = data;
+ 	}
+@@ -99,12 +118,14 @@ static int ar724x_pci_read(struct pci_bu
+ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
+ 			     int size, uint32_t value)
+ {
++	struct ar724x_pci_controller *apc;
+ 	unsigned long flags;
+ 	void __iomem *base;
+ 	u32 data;
+ 	int s;
+ 
+-	if (!ar724x_pci_link_up)
++	apc = pci_bus_to_ar724x_controller(bus);
++	if (!apc->link_up)
+ 		return PCIBIOS_DEVICE_NOT_FOUND;
+ 
+ 	if (devfn)
+@@ -122,18 +143,18 @@ static int ar724x_pci_write(struct pci_b
+ 			 * BAR0 register in order to make the device memory
+ 			 * accessible.
+ 			 */
+-			ar724x_pci_bar0_is_cached = true;
+-			ar724x_pci_bar0_value = value;
++			apc->bar0_is_cached = true;
++			apc->bar0_value = value;
+ 
+ 			value = AR7240_BAR0_WAR_VALUE;
+ 		} else {
+-			ar724x_pci_bar0_is_cached = false;
++			apc->bar0_is_cached = false;
+ 		}
+ 	}
+ 
+-	base = ar724x_pci_devcfg_base;
++	base = apc->devcfg_base;
+ 
+-	spin_lock_irqsave(&ar724x_pci_lock, flags);
++	spin_lock_irqsave(&apc->lock, flags);
+ 	data = __raw_readl(base + (where & ~3));
+ 
+ 	switch (size) {
+@@ -151,7 +172,7 @@ static int ar724x_pci_write(struct pci_b
+ 		data = value;
+ 		break;
+ 	default:
+-		spin_unlock_irqrestore(&ar724x_pci_lock, flags);
++		spin_unlock_irqrestore(&apc->lock, flags);
+ 
+ 		return PCIBIOS_BAD_REGISTER_NUMBER;
+ 	}
+@@ -159,7 +180,7 @@ static int ar724x_pci_write(struct pci_b
+ 	__raw_writel(data, base + (where & ~3));
+ 	/* flush write */
+ 	__raw_readl(base + (where & ~3));
+-	spin_unlock_irqrestore(&ar724x_pci_lock, flags);
++	spin_unlock_irqrestore(&apc->lock, flags);
+ 
+ 	return PCIBIOS_SUCCESSFUL;
+ }
+@@ -183,18 +204,14 @@ static struct resource ar724x_mem_resour
+ 	.flags  = IORESOURCE_MEM,
+ };
+ 
+-static struct pci_controller ar724x_pci_controller = {
+-	.pci_ops        = &ar724x_pci_ops,
+-	.io_resource    = &ar724x_io_resource,
+-	.mem_resource	= &ar724x_mem_resource,
+-};
+-
+ static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
+ {
++	struct ar724x_pci_controller *apc;
+ 	void __iomem *base;
+ 	u32 pending;
+ 
+-	base = ar724x_pci_ctrl_base;
++	apc = irq_get_handler_data(irq);
++	base = apc->ctrl_base;
+ 
+ 	pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
+ 		  __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+@@ -208,10 +225,12 @@ static void ar724x_pci_irq_handler(unsig
+ 
+ static void ar724x_pci_irq_unmask(struct irq_data *d)
+ {
++	struct ar724x_pci_controller *apc;
+ 	void __iomem *base;
+ 	u32 t;
+ 
+-	base = ar724x_pci_ctrl_base;
++	apc = irq_data_get_irq_chip_data(d);
++	base = apc->ctrl_base;
+ 
+ 	switch (d->irq) {
+ 	case ATH79_PCI_IRQ(0):
+@@ -225,10 +244,12 @@ static void ar724x_pci_irq_unmask(struct
+ 
+ static void ar724x_pci_irq_mask(struct irq_data *d)
+ {
++	struct ar724x_pci_controller *apc;
+ 	void __iomem *base;
+ 	u32 t;
+ 
+-	base = ar724x_pci_ctrl_base;
++	apc = irq_data_get_irq_chip_data(d);
++	base = apc->ctrl_base;
+ 
+ 	switch (d->irq) {
+ 	case ATH79_PCI_IRQ(0):
+@@ -255,12 +276,12 @@ static struct irq_chip ar724x_pci_irq_ch
+ 	.irq_mask_ack	= ar724x_pci_irq_mask,
+ };
+ 
+-static void ar724x_pci_irq_init(int irq)
++static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc)
+ {
+ 	void __iomem *base;
+ 	int i;
+ 
+-	base = ar724x_pci_ctrl_base;
++	base = apc->ctrl_base;
+ 
+ 	__raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
+ 	__raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
+@@ -268,45 +289,59 @@ static void ar724x_pci_irq_init(int irq)
+ 	BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT);
+ 
+ 	for (i = ATH79_PCI_IRQ_BASE;
+-	     i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++)
++	     i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) {
+ 		irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
+ 					 handle_level_irq);
++		irq_set_chip_data(i, apc);
++	}
+ 
+-	irq_set_chained_handler(irq, ar724x_pci_irq_handler);
++	irq_set_handler_data(apc->irq, apc);
++	irq_set_chained_handler(apc->irq, ar724x_pci_irq_handler);
+ }
+ 
+ static int ar724x_pci_probe(struct platform_device *pdev)
+ {
++	struct ar724x_pci_controller *apc;
+ 	struct resource *res;
+-	int irq;
++
++	apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller),
++			    GFP_KERNEL);
++	if (!apc)
++		return -ENOMEM;
+ 
+ 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base");
+ 	if (!res)
+ 		return -EINVAL;
+ 
+-	ar724x_pci_ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
+-	if (ar724x_pci_ctrl_base == NULL)
++	apc->ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
++	if (apc->ctrl_base == NULL)
+ 		return -EBUSY;
+ 
+ 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
+ 	if (!res)
+ 		return -EINVAL;
+ 
+-	ar724x_pci_devcfg_base = devm_request_and_ioremap(&pdev->dev, res);
+-	if (!ar724x_pci_devcfg_base)
++	apc->devcfg_base = devm_request_and_ioremap(&pdev->dev, res);
++	if (!apc->devcfg_base)
+ 		return -EBUSY;
+ 
+-	irq = platform_get_irq(pdev, 0);
+-	if (irq < 0)
++	apc->irq = platform_get_irq(pdev, 0);
++	if (apc->irq < 0)
+ 		return -EINVAL;
+ 
+-	ar724x_pci_link_up = ar724x_pci_check_link();
+-	if (!ar724x_pci_link_up)
++	spin_lock_init(&apc->lock);
++
++	apc->pci_controller.pci_ops = &ar724x_pci_ops;
++	apc->pci_controller.io_resource = &ar724x_io_resource;
++	apc->pci_controller.mem_resource = &ar724x_mem_resource;
++
++	apc->link_up = ar724x_pci_check_link(apc);
++	if (!apc->link_up)
+ 		dev_warn(&pdev->dev, "PCIe link is down\n");
+ 
+-	ar724x_pci_irq_init(irq);
++	ar724x_pci_irq_init(apc);
+ 
+-	register_pci_controller(&ar724x_pci_controller);
++	register_pci_controller(&apc->pci_controller);
+ 
+ 	return 0;
+ }
diff --git a/target/linux/ar71xx/patches-3.8/018-MIPS-pci-ar724x-remove-static-PCI-IO-MEM-resources.patch b/target/linux/ar71xx/patches-3.8/018-MIPS-pci-ar724x-remove-static-PCI-IO-MEM-resources.patch
new file mode 100644
index 0000000..823488a
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/018-MIPS-pci-ar724x-remove-static-PCI-IO-MEM-resources.patch
@@ -0,0 +1,139 @@
+From d80b05d19c2772ded40403d578d8e90d38c85257 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 3 Feb 2013 09:59:45 +0000
+Subject: [PATCH] MIPS: pci-ar724x: remove static PCI IO/MEM resources
+
+commit 34b134aebda89888b6985b7a3139e9cbdf209236 upstream.
+
+Static resources become impractical when multiple
+PCI controllers are present. Move the resources
+into the platform device registration code and
+change the probe routine to get those from there
+platform device's resources.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4914/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/pci.c      |   21 ++++++++++++++++++++-
+ arch/mips/pci/pci-ar724x.c |   40 ++++++++++++++++++++++++----------------
+ 2 files changed, 44 insertions(+), 17 deletions(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -139,10 +139,13 @@ static struct platform_device *
+ ath79_register_pci_ar724x(int id,
+ 			  unsigned long cfg_base,
+ 			  unsigned long ctrl_base,
++			  unsigned long mem_base,
++			  unsigned long mem_size,
++			  unsigned long io_base,
+ 			  int irq)
+ {
+ 	struct platform_device *pdev;
+-	struct resource res[3];
++	struct resource res[5];
+ 
+ 	memset(res, 0, sizeof(res));
+ 
+@@ -160,6 +163,16 @@ ath79_register_pci_ar724x(int id,
+ 	res[2].start = irq;
+ 	res[2].end = irq;
+ 
++	res[3].name = "mem_base";
++	res[3].flags = IORESOURCE_MEM;
++	res[3].start = mem_base;
++	res[3].end = mem_base + mem_size - 1;
++
++	res[4].name = "io_base";
++	res[4].flags = IORESOURCE_IO;
++	res[4].start = io_base;
++	res[4].end = io_base;
++
+ 	pdev = platform_device_register_simple("ar724x-pci", id,
+ 					       res, ARRAY_SIZE(res));
+ 	return pdev;
+@@ -175,6 +188,9 @@ int __init ath79_register_pci(void)
+ 		pdev = ath79_register_pci_ar724x(-1,
+ 						 AR724X_PCI_CFG_BASE,
+ 						 AR724X_PCI_CTRL_BASE,
++						 AR724X_PCI_MEM_BASE,
++						 AR724X_PCI_MEM_SIZE,
++						 0,
+ 						 ATH79_CPU_IRQ_IP2);
+ 	} else if (soc_is_ar9342() ||
+ 		   soc_is_ar9344()) {
+@@ -187,6 +203,9 @@ int __init ath79_register_pci(void)
+ 		pdev = ath79_register_pci_ar724x(-1,
+ 						 AR724X_PCI_CFG_BASE,
+ 						 AR724X_PCI_CTRL_BASE,
++						 AR724X_PCI_MEM_BASE,
++						 AR724X_PCI_MEM_SIZE,
++						 0,
+ 						 ATH79_IP2_IRQ(0));
+ 	} else {
+ 		/* No PCI support */
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -42,6 +42,8 @@ struct ar724x_pci_controller {
+ 	spinlock_t lock;
+ 
+ 	struct pci_controller pci_controller;
++	struct resource io_res;
++	struct resource mem_res;
+ };
+ 
+ static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
+@@ -190,20 +192,6 @@ static struct pci_ops ar724x_pci_ops = {
+ 	.write	= ar724x_pci_write,
+ };
+ 
+-static struct resource ar724x_io_resource = {
+-	.name   = "PCI IO space",
+-	.start  = 0,
+-	.end    = 0,
+-	.flags  = IORESOURCE_IO,
+-};
+-
+-static struct resource ar724x_mem_resource = {
+-	.name   = "PCI memory space",
+-	.start  = AR724X_PCI_MEM_BASE,
+-	.end    = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1,
+-	.flags  = IORESOURCE_MEM,
+-};
+-
+ static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
+ {
+ 	struct ar724x_pci_controller *apc;
+@@ -331,9 +319,29 @@ static int ar724x_pci_probe(struct platf
+ 
+ 	spin_lock_init(&apc->lock);
+ 
++	res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
++	if (!res)
++		return -EINVAL;
++
++	apc->io_res.parent = res;
++	apc->io_res.name = "PCI IO space";
++	apc->io_res.start = res->start;
++	apc->io_res.end = res->end;
++	apc->io_res.flags = IORESOURCE_IO;
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
++	if (!res)
++		return -EINVAL;
++
++	apc->mem_res.parent = res;
++	apc->mem_res.name = "PCI memory space";
++	apc->mem_res.start = res->start;
++	apc->mem_res.end = res->end;
++	apc->mem_res.flags = IORESOURCE_MEM;
++
+ 	apc->pci_controller.pci_ops = &ar724x_pci_ops;
+-	apc->pci_controller.io_resource = &ar724x_io_resource;
+-	apc->pci_controller.mem_resource = &ar724x_mem_resource;
++	apc->pci_controller.io_resource = &apc->io_res;
++	apc->pci_controller.mem_resource = &apc->mem_res;
+ 
+ 	apc->link_up = ar724x_pci_check_link(apc);
+ 	if (!apc->link_up)
diff --git a/target/linux/ar71xx/patches-3.8/019-MIPS-pci-ar724x-use-per-controller-IRQ-base.patch b/target/linux/ar71xx/patches-3.8/019-MIPS-pci-ar724x-use-per-controller-IRQ-base.patch
new file mode 100644
index 0000000..0eabfb1
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/019-MIPS-pci-ar724x-use-per-controller-IRQ-base.patch
@@ -0,0 +1,117 @@
+From d85015ff3ab6df0e776c2aefc51f2da023c1edcf Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 3 Feb 2013 10:00:16 +0000
+Subject: [PATCH] MIPS: pci-ar724x: use per-controller IRQ base
+
+commit 8b66d461187ff61c5755001af7296e6edde48423 upstream.
+
+Change to the code to use per-controller IRQ base.
+This is needed for multiple PCI controller support.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4915/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/pci-ar724x.c |   31 +++++++++++++++++++++----------
+ 1 file changed, 21 insertions(+), 10 deletions(-)
+
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -34,6 +34,7 @@ struct ar724x_pci_controller {
+ 	void __iomem *ctrl_base;
+ 
+ 	int irq;
++	int irq_base;
+ 
+ 	bool link_up;
+ 	bool bar0_is_cached;
+@@ -205,7 +206,7 @@ static void ar724x_pci_irq_handler(unsig
+ 		  __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+ 
+ 	if (pending & AR724X_PCI_INT_DEV0)
+-		generic_handle_irq(ATH79_PCI_IRQ(0));
++		generic_handle_irq(apc->irq_base + 0);
+ 
+ 	else
+ 		spurious_interrupt();
+@@ -215,13 +216,15 @@ static void ar724x_pci_irq_unmask(struct
+ {
+ 	struct ar724x_pci_controller *apc;
+ 	void __iomem *base;
++	int offset;
+ 	u32 t;
+ 
+ 	apc = irq_data_get_irq_chip_data(d);
+ 	base = apc->ctrl_base;
++	offset = apc->irq_base - d->irq;
+ 
+-	switch (d->irq) {
+-	case ATH79_PCI_IRQ(0):
++	switch (offset) {
++	case 0:
+ 		t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+ 		__raw_writel(t | AR724X_PCI_INT_DEV0,
+ 			     base + AR724X_PCI_REG_INT_MASK);
+@@ -234,13 +237,15 @@ static void ar724x_pci_irq_mask(struct i
+ {
+ 	struct ar724x_pci_controller *apc;
+ 	void __iomem *base;
++	int offset;
+ 	u32 t;
+ 
+ 	apc = irq_data_get_irq_chip_data(d);
+ 	base = apc->ctrl_base;
++	offset = apc->irq_base - d->irq;
+ 
+-	switch (d->irq) {
+-	case ATH79_PCI_IRQ(0):
++	switch (offset) {
++	case 0:
+ 		t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+ 		__raw_writel(t & ~AR724X_PCI_INT_DEV0,
+ 			     base + AR724X_PCI_REG_INT_MASK);
+@@ -264,7 +269,8 @@ static struct irq_chip ar724x_pci_irq_ch
+ 	.irq_mask_ack	= ar724x_pci_irq_mask,
+ };
+ 
+-static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc)
++static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
++				int id)
+ {
+ 	void __iomem *base;
+ 	int i;
+@@ -274,10 +280,10 @@ static void ar724x_pci_irq_init(struct a
+ 	__raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
+ 	__raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
+ 
+-	BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT);
++	apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
+ 
+-	for (i = ATH79_PCI_IRQ_BASE;
+-	     i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) {
++	for (i = apc->irq_base;
++	     i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
+ 		irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
+ 					 handle_level_irq);
+ 		irq_set_chip_data(i, apc);
+@@ -291,6 +297,11 @@ static int ar724x_pci_probe(struct platf
+ {
+ 	struct ar724x_pci_controller *apc;
+ 	struct resource *res;
++	int id;
++
++	id = pdev->id;
++	if (id == -1)
++		id = 0;
+ 
+ 	apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller),
+ 			    GFP_KERNEL);
+@@ -347,7 +358,7 @@ static int ar724x_pci_probe(struct platf
+ 	if (!apc->link_up)
+ 		dev_warn(&pdev->dev, "PCIe link is down\n");
+ 
+-	ar724x_pci_irq_init(apc);
++	ar724x_pci_irq_init(apc, id);
+ 
+ 	register_pci_controller(&apc->pci_controller);
+ 
diff --git a/target/linux/ar71xx/patches-3.8/020-MIPS-pci-ar724x-setup-command-register-of-the-PCI-co.patch b/target/linux/ar71xx/patches-3.8/020-MIPS-pci-ar724x-setup-command-register-of-the-PCI-co.patch
new file mode 100644
index 0000000..301803c
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/020-MIPS-pci-ar724x-setup-command-register-of-the-PCI-co.patch
@@ -0,0 +1,178 @@
+From 5e079d9b7ac5dda3be9f215f8440333597f57b26 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 3 Feb 2013 14:52:47 +0000
+Subject: [PATCH] MIPS: pci-ar724x: setup command register of the PCI
+ controller
+
+commit 12401fc28d40aa5bf8bda6991a96b6d7a3dae3ac upstream.
+
+The command register of the PCI controller is
+not initialized correctly by the bootloader on
+some boards and this leads to non working PCI
+bus.
+
+Add code to initialize the command register
+from the Linux code to avoid this.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4916/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/pci.c                          |   10 +++-
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    2 +
+ arch/mips/pci/pci-ar724x.c                     |   63 ++++++++++++++++++++++++
+ 3 files changed, 74 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -139,13 +139,14 @@ static struct platform_device *
+ ath79_register_pci_ar724x(int id,
+ 			  unsigned long cfg_base,
+ 			  unsigned long ctrl_base,
++			  unsigned long crp_base,
+ 			  unsigned long mem_base,
+ 			  unsigned long mem_size,
+ 			  unsigned long io_base,
+ 			  int irq)
+ {
+ 	struct platform_device *pdev;
+-	struct resource res[5];
++	struct resource res[6];
+ 
+ 	memset(res, 0, sizeof(res));
+ 
+@@ -173,6 +174,11 @@ ath79_register_pci_ar724x(int id,
+ 	res[4].start = io_base;
+ 	res[4].end = io_base;
+ 
++	res[5].name = "crp_base";
++	res[5].flags = IORESOURCE_MEM;
++	res[5].start = crp_base;
++	res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1;
++
+ 	pdev = platform_device_register_simple("ar724x-pci", id,
+ 					       res, ARRAY_SIZE(res));
+ 	return pdev;
+@@ -188,6 +194,7 @@ int __init ath79_register_pci(void)
+ 		pdev = ath79_register_pci_ar724x(-1,
+ 						 AR724X_PCI_CFG_BASE,
+ 						 AR724X_PCI_CTRL_BASE,
++						 AR724X_PCI_CRP_BASE,
+ 						 AR724X_PCI_MEM_BASE,
+ 						 AR724X_PCI_MEM_SIZE,
+ 						 0,
+@@ -203,6 +210,7 @@ int __init ath79_register_pci(void)
+ 		pdev = ath79_register_pci_ar724x(-1,
+ 						 AR724X_PCI_CFG_BASE,
+ 						 AR724X_PCI_CTRL_BASE,
++						 AR724X_PCI_CRP_BASE,
+ 						 AR724X_PCI_MEM_BASE,
+ 						 AR724X_PCI_MEM_SIZE,
+ 						 0,
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -67,6 +67,8 @@
+ 
+ #define AR724X_PCI_CFG_BASE	0x14000000
+ #define AR724X_PCI_CFG_SIZE	0x1000
++#define AR724X_PCI_CRP_BASE	(AR71XX_APB_BASE + 0x000c0000)
++#define AR724X_PCI_CRP_SIZE	0x1000
+ #define AR724X_PCI_CTRL_BASE	(AR71XX_APB_BASE + 0x000f0000)
+ #define AR724X_PCI_CTRL_SIZE	0x100
+ 
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -29,9 +29,17 @@
+ 
+ #define AR7240_BAR0_WAR_VALUE	0xffff
+ 
++#define AR724X_PCI_CMD_INIT	(PCI_COMMAND_MEMORY |		\
++				 PCI_COMMAND_MASTER |		\
++				 PCI_COMMAND_INVALIDATE |	\
++				 PCI_COMMAND_PARITY |		\
++				 PCI_COMMAND_SERR |		\
++				 PCI_COMMAND_FAST_BACK)
++
+ struct ar724x_pci_controller {
+ 	void __iomem *devcfg_base;
+ 	void __iomem *ctrl_base;
++	void __iomem *crp_base;
+ 
+ 	int irq;
+ 	int irq_base;
+@@ -64,6 +72,51 @@ pci_bus_to_ar724x_controller(struct pci_
+ 	return container_of(hose, struct ar724x_pci_controller, pci_controller);
+ }
+ 
++static int ar724x_pci_local_write(struct ar724x_pci_controller *apc,
++				  int where, int size, u32 value)
++{
++	unsigned long flags;
++	void __iomem *base;
++	u32 data;
++	int s;
++
++	WARN_ON(where & (size - 1));
++
++	if (!apc->link_up)
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	base = apc->crp_base;
++
++	spin_lock_irqsave(&apc->lock, flags);
++	data = __raw_readl(base + (where & ~3));
++
++	switch (size) {
++	case 1:
++		s = ((where & 3) * 8);
++		data &= ~(0xff << s);
++		data |= ((value & 0xff) << s);
++		break;
++	case 2:
++		s = ((where & 2) * 8);
++		data &= ~(0xffff << s);
++		data |= ((value & 0xffff) << s);
++		break;
++	case 4:
++		data = value;
++		break;
++	default:
++		spin_unlock_irqrestore(&apc->lock, flags);
++		return PCIBIOS_BAD_REGISTER_NUMBER;
++	}
++
++	__raw_writel(data, base + (where & ~3));
++	/* flush write */
++	__raw_readl(base + (where & ~3));
++	spin_unlock_irqrestore(&apc->lock, flags);
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
+ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+ 			    int size, uint32_t *value)
+ {
+@@ -324,6 +377,14 @@ static int ar724x_pci_probe(struct platf
+ 	if (!apc->devcfg_base)
+ 		return -EBUSY;
+ 
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crp_base");
++	if (!res)
++		return -EINVAL;
++
++	apc->crp_base = devm_request_and_ioremap(&pdev->dev, res);
++	if (apc->crp_base == NULL)
++		return -EBUSY;
++
+ 	apc->irq = platform_get_irq(pdev, 0);
+ 	if (apc->irq < 0)
+ 		return -EINVAL;
+@@ -360,6 +421,8 @@ static int ar724x_pci_probe(struct platf
+ 
+ 	ar724x_pci_irq_init(apc, id);
+ 
++	ar724x_pci_local_write(apc, PCI_COMMAND, 4, AR724X_PCI_CMD_INIT);
++
+ 	register_pci_controller(&apc->pci_controller);
+ 
+ 	return 0;
diff --git a/target/linux/ar71xx/patches-3.8/021-MIPS-pci-ar71xx-use-dynamically-allocated-PCI-contro.patch b/target/linux/ar71xx/patches-3.8/021-MIPS-pci-ar71xx-use-dynamically-allocated-PCI-contro.patch
new file mode 100644
index 0000000..a8b53c8
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/021-MIPS-pci-ar71xx-use-dynamically-allocated-PCI-contro.patch
@@ -0,0 +1,226 @@
+From 0f0f7d810226c734141a20de85289dbb0dda8f96 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 7 Feb 2013 19:28:14 +0000
+Subject: [PATCH] MIPS: pci-ar71xx: use dynamically allocated PCI controller
+ structure
+
+commit f18118a868f1f7e7bdfea176a204fcc44fae2985 upstream.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4926/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/pci-ar71xx.c |   84 ++++++++++++++++++++++++++++----------------
+ 1 file changed, 53 insertions(+), 31 deletions(-)
+
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -48,8 +48,12 @@
+ 
+ #define AR71XX_PCI_IRQ_COUNT		5
+ 
+-static DEFINE_SPINLOCK(ar71xx_pci_lock);
+-static void __iomem *ar71xx_pcicfg_base;
++struct ar71xx_pci_controller {
++	void __iomem *cfg_base;
++	spinlock_t lock;
++	int irq;
++	struct pci_controller pci_ctrl;
++};
+ 
+ /* Byte lane enable bits */
+ static const u8 ar71xx_pci_ble_table[4][4] = {
+@@ -92,9 +96,18 @@ static inline u32 ar71xx_pci_bus_addr(st
+ 	return ret;
+ }
+ 
+-static int ar71xx_pci_check_error(int quiet)
++static inline struct ar71xx_pci_controller *
++pci_bus_to_ar71xx_controller(struct pci_bus *bus)
+ {
+-	void __iomem *base = ar71xx_pcicfg_base;
++	struct pci_controller *hose;
++
++	hose = (struct pci_controller *) bus->sysdata;
++	return container_of(hose, struct ar71xx_pci_controller, pci_ctrl);
++}
++
++static int ar71xx_pci_check_error(struct ar71xx_pci_controller *apc, int quiet)
++{
++	void __iomem *base = apc->cfg_base;
+ 	u32 pci_err;
+ 	u32 ahb_err;
+ 
+@@ -129,9 +142,10 @@ static int ar71xx_pci_check_error(int qu
+ 	return !!(ahb_err | pci_err);
+ }
+ 
+-static inline void ar71xx_pci_local_write(int where, int size, u32 value)
++static inline void ar71xx_pci_local_write(struct ar71xx_pci_controller *apc,
++					  int where, int size, u32 value)
+ {
+-	void __iomem *base = ar71xx_pcicfg_base;
++	void __iomem *base = apc->cfg_base;
+ 	u32 ad_cbe;
+ 
+ 	value = value << (8 * (where & 3));
+@@ -147,7 +161,8 @@ static inline int ar71xx_pci_set_cfgaddr
+ 					 unsigned int devfn,
+ 					 int where, int size, u32 cmd)
+ {
+-	void __iomem *base = ar71xx_pcicfg_base;
++	struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
++	void __iomem *base = apc->cfg_base;
+ 	u32 addr;
+ 
+ 	addr = ar71xx_pci_bus_addr(bus, devfn, where);
+@@ -156,13 +171,14 @@ static inline int ar71xx_pci_set_cfgaddr
+ 	__raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
+ 		     base + AR71XX_PCI_REG_CFG_CBE);
+ 
+-	return ar71xx_pci_check_error(1);
++	return ar71xx_pci_check_error(apc, 1);
+ }
+ 
+ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+ 				  int where, int size, u32 *value)
+ {
+-	void __iomem *base = ar71xx_pcicfg_base;
++	struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
++	void __iomem *base = apc->cfg_base;
+ 	unsigned long flags;
+ 	u32 data;
+ 	int err;
+@@ -171,7 +187,7 @@ static int ar71xx_pci_read_config(struct
+ 	ret = PCIBIOS_SUCCESSFUL;
+ 	data = ~0;
+ 
+-	spin_lock_irqsave(&ar71xx_pci_lock, flags);
++	spin_lock_irqsave(&apc->lock, flags);
+ 
+ 	err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
+ 				     AR71XX_PCI_CFG_CMD_READ);
+@@ -180,7 +196,7 @@ static int ar71xx_pci_read_config(struct
+ 	else
+ 		data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
+ 
+-	spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
++	spin_unlock_irqrestore(&apc->lock, flags);
+ 
+ 	*value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7];
+ 
+@@ -190,7 +206,8 @@ static int ar71xx_pci_read_config(struct
+ static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+ 				   int where, int size, u32 value)
+ {
+-	void __iomem *base = ar71xx_pcicfg_base;
++	struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
++	void __iomem *base = apc->cfg_base;
+ 	unsigned long flags;
+ 	int err;
+ 	int ret;
+@@ -198,7 +215,7 @@ static int ar71xx_pci_write_config(struc
+ 	value = value << (8 * (where & 3));
+ 	ret = PCIBIOS_SUCCESSFUL;
+ 
+-	spin_lock_irqsave(&ar71xx_pci_lock, flags);
++	spin_lock_irqsave(&apc->lock, flags);
+ 
+ 	err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
+ 				     AR71XX_PCI_CFG_CMD_WRITE);
+@@ -207,7 +224,7 @@ static int ar71xx_pci_write_config(struc
+ 	else
+ 		__raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
+ 
+-	spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
++	spin_unlock_irqrestore(&apc->lock, flags);
+ 
+ 	return ret;
+ }
+@@ -231,12 +248,6 @@ static struct resource ar71xx_pci_mem_re
+ 	.flags		= IORESOURCE_MEM
+ };
+ 
+-static struct pci_controller ar71xx_pci_controller = {
+-	.pci_ops	= &ar71xx_pci_ops,
+-	.mem_resource	= &ar71xx_pci_mem_resource,
+-	.io_resource	= &ar71xx_pci_io_resource,
+-};
+-
+ static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
+ {
+ 	void __iomem *base = ath79_reset_base;
+@@ -294,7 +305,7 @@ static struct irq_chip ar71xx_pci_irq_ch
+ 	.irq_mask_ack	= ar71xx_pci_irq_mask,
+ };
+ 
+-static void ar71xx_pci_irq_init(int irq)
++static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
+ {
+ 	void __iomem *base = ath79_reset_base;
+ 	int i;
+@@ -309,7 +320,7 @@ static void ar71xx_pci_irq_init(int irq)
+ 		irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
+ 					 handle_level_irq);
+ 
+-	irq_set_chained_handler(irq, ar71xx_pci_irq_handler);
++	irq_set_chained_handler(apc->irq, ar71xx_pci_irq_handler);
+ }
+ 
+ static void ar71xx_pci_reset(void)
+@@ -336,20 +347,27 @@ static void ar71xx_pci_reset(void)
+ 
+ static int ar71xx_pci_probe(struct platform_device *pdev)
+ {
++	struct ar71xx_pci_controller *apc;
+ 	struct resource *res;
+-	int irq;
+ 	u32 t;
+ 
++	apc = devm_kzalloc(&pdev->dev, sizeof(struct ar71xx_pci_controller),
++			   GFP_KERNEL);
++	if (!apc)
++		return -ENOMEM;
++
++	spin_lock_init(&apc->lock);
++
+ 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
+ 	if (!res)
+ 		return -EINVAL;
+ 
+-	ar71xx_pcicfg_base = devm_request_and_ioremap(&pdev->dev, res);
+-	if (!ar71xx_pcicfg_base)
++	apc->cfg_base = devm_request_and_ioremap(&pdev->dev, res);
++	if (!apc->cfg_base)
+ 		return -ENOMEM;
+ 
+-	irq = platform_get_irq(pdev, 0);
+-	if (irq < 0)
++	apc->irq = platform_get_irq(pdev, 0);
++	if (apc->irq < 0)
+ 		return -EINVAL;
+ 
+ 	ar71xx_pci_reset();
+@@ -357,14 +375,18 @@ static int ar71xx_pci_probe(struct platf
+ 	/* setup COMMAND register */
+ 	t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
+ 	  | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
+-	ar71xx_pci_local_write(PCI_COMMAND, 4, t);
++	ar71xx_pci_local_write(apc, PCI_COMMAND, 4, t);
+ 
+ 	/* clear bus errors */
+-	ar71xx_pci_check_error(1);
++	ar71xx_pci_check_error(apc, 1);
++
++	ar71xx_pci_irq_init(apc);
+ 
+-	ar71xx_pci_irq_init(irq);
++	apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
++	apc->pci_ctrl.mem_resource = &ar71xx_pci_mem_resource;
++	apc->pci_ctrl.io_resource = &ar71xx_pci_io_resource;
+ 
+-	register_pci_controller(&ar71xx_pci_controller);
++	register_pci_controller(&apc->pci_ctrl);
+ 
+ 	return 0;
+ }
diff --git a/target/linux/ar71xx/patches-3.8/022-MIPS-pci-ar71xx-remove-static-PCI-IO-MEM-resources.patch b/target/linux/ar71xx/patches-3.8/022-MIPS-pci-ar71xx-remove-static-PCI-IO-MEM-resources.patch
new file mode 100644
index 0000000..c7c4064
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/022-MIPS-pci-ar71xx-remove-static-PCI-IO-MEM-resources.patch
@@ -0,0 +1,113 @@
+From f073cb029873ed487e14784d3682b6aa25afe997 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 7 Feb 2013 19:28:15 +0000
+Subject: [PATCH] MIPS: pci-ar71xx: remove static PCI IO/MEM resources
+
+commit 42cb60d1fab4c81ef24876d985e08fc5bb899e41 upstream.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4927/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/pci.c      |   12 +++++++++++-
+ arch/mips/pci/pci-ar71xx.c |   40 ++++++++++++++++++++++++----------------
+ 2 files changed, 35 insertions(+), 17 deletions(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -117,7 +117,7 @@ static struct platform_device *
+ ath79_register_pci_ar71xx(void)
+ {
+ 	struct platform_device *pdev;
+-	struct resource res[2];
++	struct resource res[4];
+ 
+ 	memset(res, 0, sizeof(res));
+ 
+@@ -130,6 +130,16 @@ ath79_register_pci_ar71xx(void)
+ 	res[1].start = ATH79_CPU_IRQ_IP2;
+ 	res[1].end = ATH79_CPU_IRQ_IP2;
+ 
++	res[2].name = "io_base";
++	res[2].flags = IORESOURCE_IO;
++	res[2].start = 0;
++	res[2].end = 0;
++
++	res[3].name = "mem_base";
++	res[3].flags = IORESOURCE_MEM;
++	res[3].start = AR71XX_PCI_MEM_BASE;
++	res[3].end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1;
++
+ 	pdev = platform_device_register_simple("ar71xx-pci", -1,
+ 					       res, ARRAY_SIZE(res));
+ 	return pdev;
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -53,6 +53,8 @@ struct ar71xx_pci_controller {
+ 	spinlock_t lock;
+ 	int irq;
+ 	struct pci_controller pci_ctrl;
++	struct resource io_res;
++	struct resource mem_res;
+ };
+ 
+ /* Byte lane enable bits */
+@@ -234,20 +236,6 @@ static struct pci_ops ar71xx_pci_ops = {
+ 	.write	= ar71xx_pci_write_config,
+ };
+ 
+-static struct resource ar71xx_pci_io_resource = {
+-	.name		= "PCI IO space",
+-	.start		= 0,
+-	.end		= 0,
+-	.flags		= IORESOURCE_IO,
+-};
+-
+-static struct resource ar71xx_pci_mem_resource = {
+-	.name		= "PCI memory space",
+-	.start		= AR71XX_PCI_MEM_BASE,
+-	.end		= AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
+-	.flags		= IORESOURCE_MEM
+-};
+-
+ static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
+ {
+ 	void __iomem *base = ath79_reset_base;
+@@ -370,6 +358,26 @@ static int ar71xx_pci_probe(struct platf
+ 	if (apc->irq < 0)
+ 		return -EINVAL;
+ 
++	res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
++	if (!res)
++		return -EINVAL;
++
++	apc->io_res.parent = res;
++	apc->io_res.name = "PCI IO space";
++	apc->io_res.start = res->start;
++	apc->io_res.end = res->end;
++	apc->io_res.flags = IORESOURCE_IO;
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
++	if (!res)
++		return -EINVAL;
++
++	apc->mem_res.parent = res;
++	apc->mem_res.name = "PCI memory space";
++	apc->mem_res.start = res->start;
++	apc->mem_res.end = res->end;
++	apc->mem_res.flags = IORESOURCE_MEM;
++
+ 	ar71xx_pci_reset();
+ 
+ 	/* setup COMMAND register */
+@@ -383,8 +391,8 @@ static int ar71xx_pci_probe(struct platf
+ 	ar71xx_pci_irq_init(apc);
+ 
+ 	apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
+-	apc->pci_ctrl.mem_resource = &ar71xx_pci_mem_resource;
+-	apc->pci_ctrl.io_resource = &ar71xx_pci_io_resource;
++	apc->pci_ctrl.mem_resource = &apc->mem_res;
++	apc->pci_ctrl.io_resource = &apc->io_res;
+ 
+ 	register_pci_controller(&apc->pci_ctrl);
+ 
diff --git a/target/linux/ar71xx/patches-3.8/023-MIPS-pci-ar71xx-move-irq-base-to-the-controller-stru.patch b/target/linux/ar71xx/patches-3.8/023-MIPS-pci-ar71xx-move-irq-base-to-the-controller-stru.patch
new file mode 100644
index 0000000..78c2f07
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/023-MIPS-pci-ar71xx-move-irq-base-to-the-controller-stru.patch
@@ -0,0 +1,105 @@
+From bec8339e917651e51592dd57ed005f8ccd9b0e8d Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 7 Feb 2013 19:29:38 +0000
+Subject: [PATCH] MIPS: pci-ar71xx: move irq base to the controller structure
+
+commit 326e8d17d73fdf213f6334917ef46b2ba7b1354a upstream.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4928/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/pci-ar71xx.c |   32 ++++++++++++++++++++++++--------
+ 1 file changed, 24 insertions(+), 8 deletions(-)
+
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -52,6 +52,7 @@ struct ar71xx_pci_controller {
+ 	void __iomem *cfg_base;
+ 	spinlock_t lock;
+ 	int irq;
++	int irq_base;
+ 	struct pci_controller pci_ctrl;
+ 	struct resource io_res;
+ 	struct resource mem_res;
+@@ -238,23 +239,26 @@ static struct pci_ops ar71xx_pci_ops = {
+ 
+ static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
+ {
++	struct ar71xx_pci_controller *apc;
+ 	void __iomem *base = ath79_reset_base;
+ 	u32 pending;
+ 
++	apc = irq_get_handler_data(irq);
++
+ 	pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
+ 		  __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+ 
+ 	if (pending & AR71XX_PCI_INT_DEV0)
+-		generic_handle_irq(ATH79_PCI_IRQ(0));
++		generic_handle_irq(apc->irq_base + 0);
+ 
+ 	else if (pending & AR71XX_PCI_INT_DEV1)
+-		generic_handle_irq(ATH79_PCI_IRQ(1));
++		generic_handle_irq(apc->irq_base + 1);
+ 
+ 	else if (pending & AR71XX_PCI_INT_DEV2)
+-		generic_handle_irq(ATH79_PCI_IRQ(2));
++		generic_handle_irq(apc->irq_base + 2);
+ 
+ 	else if (pending & AR71XX_PCI_INT_CORE)
+-		generic_handle_irq(ATH79_PCI_IRQ(4));
++		generic_handle_irq(apc->irq_base + 4);
+ 
+ 	else
+ 		spurious_interrupt();
+@@ -262,10 +266,14 @@ static void ar71xx_pci_irq_handler(unsig
+ 
+ static void ar71xx_pci_irq_unmask(struct irq_data *d)
+ {
+-	unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE;
++	struct ar71xx_pci_controller *apc;
++	unsigned int irq;
+ 	void __iomem *base = ath79_reset_base;
+ 	u32 t;
+ 
++	apc = irq_data_get_irq_chip_data(d);
++	irq = d->irq - apc->irq_base;
++
+ 	t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+ 	__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+ 
+@@ -275,10 +283,14 @@ static void ar71xx_pci_irq_unmask(struct
+ 
+ static void ar71xx_pci_irq_mask(struct irq_data *d)
+ {
+-	unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE;
++	struct ar71xx_pci_controller *apc;
++	unsigned int irq;
+ 	void __iomem *base = ath79_reset_base;
+ 	u32 t;
+ 
++	apc = irq_data_get_irq_chip_data(d);
++	irq = d->irq - apc->irq_base;
++
+ 	t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+ 	__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+ 
+@@ -303,11 +315,15 @@ static void ar71xx_pci_irq_init(struct a
+ 
+ 	BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
+ 
+-	for (i = ATH79_PCI_IRQ_BASE;
+-	     i < ATH79_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++)
++	apc->irq_base = ATH79_PCI_IRQ_BASE;
++	for (i = apc->irq_base;
++	     i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) {
+ 		irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
+ 					 handle_level_irq);
++		irq_set_chip_data(i, apc);
++	}
+ 
++	irq_set_handler_data(apc->irq, apc);
+ 	irq_set_chained_handler(apc->irq, ar71xx_pci_irq_handler);
+ }
+ 
diff --git a/target/linux/ar71xx/patches-3.8/024-ath79-add-ATH79_CPU_IRQ-macro.patch b/target/linux/ar71xx/patches-3.8/024-ath79-add-ATH79_CPU_IRQ-macro.patch
new file mode 100644
index 0000000..3624433
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/024-ath79-add-ATH79_CPU_IRQ-macro.patch
@@ -0,0 +1,266 @@
+From 7377d32d37490f0804662c76a72b68d45d93966e Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 7 Feb 2013 19:32:23 +0000
+Subject: [PATCH] ath79: add ATH79_CPU_IRQ() macro
+
+commit 7e69c10a8ee1f201c040997c6742c27e915730ad upstream.
+
+Remove the individual ATH79_CPU_IRQ_* constants and
+use the new macro instead of those.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4929/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/dev-usb.c              |   12 ++++++------
+ arch/mips/ath79/dev-wmac.c             |    8 ++++----
+ arch/mips/ath79/irq.c                  |   32 ++++++++++++++++----------------
+ arch/mips/ath79/pci.c                  |    6 +++---
+ arch/mips/include/asm/mach-ath79/irq.h |    9 ++-------
+ 5 files changed, 31 insertions(+), 36 deletions(-)
+
+--- a/arch/mips/ath79/dev-usb.c
++++ b/arch/mips/ath79/dev-usb.c
+@@ -111,7 +111,7 @@ static void __init ath79_usb_setup(void)
+ 	platform_device_register(&ath79_ohci_device);
+ 
+ 	ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE,
+-				AR71XX_EHCI_SIZE, ATH79_CPU_IRQ_USB);
++				AR71XX_EHCI_SIZE, ATH79_CPU_IRQ(3));
+ 	ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1;
+ 	platform_device_register(&ath79_ehci_device);
+ }
+@@ -136,7 +136,7 @@ static void __init ar7240_usb_setup(void
+ 	iounmap(usb_ctrl_base);
+ 
+ 	ath79_usb_init_resource(ath79_ohci_resources, AR7240_OHCI_BASE,
+-				AR7240_OHCI_SIZE, ATH79_CPU_IRQ_USB);
++				AR7240_OHCI_SIZE, ATH79_CPU_IRQ(3));
+ 	platform_device_register(&ath79_ohci_device);
+ }
+ 
+@@ -152,7 +152,7 @@ static void __init ar724x_usb_setup(void
+ 	mdelay(10);
+ 
+ 	ath79_usb_init_resource(ath79_ehci_resources, AR724X_EHCI_BASE,
+-				AR724X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
++				AR724X_EHCI_SIZE, ATH79_CPU_IRQ(3));
+ 	ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
+ 	platform_device_register(&ath79_ehci_device);
+ }
+@@ -169,7 +169,7 @@ static void __init ar913x_usb_setup(void
+ 	mdelay(10);
+ 
+ 	ath79_usb_init_resource(ath79_ehci_resources, AR913X_EHCI_BASE,
+-				AR913X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
++				AR913X_EHCI_SIZE, ATH79_CPU_IRQ(3));
+ 	ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
+ 	platform_device_register(&ath79_ehci_device);
+ }
+@@ -186,7 +186,7 @@ static void __init ar933x_usb_setup(void
+ 	mdelay(10);
+ 
+ 	ath79_usb_init_resource(ath79_ehci_resources, AR933X_EHCI_BASE,
+-				AR933X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
++				AR933X_EHCI_SIZE, ATH79_CPU_IRQ(3));
+ 	ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
+ 	platform_device_register(&ath79_ehci_device);
+ }
+@@ -212,7 +212,7 @@ static void __init ar934x_usb_setup(void
+ 	udelay(1000);
+ 
+ 	ath79_usb_init_resource(ath79_ehci_resources, AR934X_EHCI_BASE,
+-				AR934X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
++				AR934X_EHCI_SIZE, ATH79_CPU_IRQ(3));
+ 	ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
+ 	platform_device_register(&ath79_ehci_device);
+ }
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -55,8 +55,8 @@ static void __init ar913x_wmac_setup(voi
+ 
+ 	ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
+ 	ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
+-	ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
+-	ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
++	ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
++	ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
+ }
+ 
+ 
+@@ -83,8 +83,8 @@ static void __init ar933x_wmac_setup(voi
+ 
+ 	ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
+ 	ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
+-	ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
+-	ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
++	ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
++	ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
+ 
+ 	t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
+ 	if (t & AR933X_BOOTSTRAP_REF_CLK_40)
+--- a/arch/mips/ath79/irq.c
++++ b/arch/mips/ath79/irq.c
+@@ -114,7 +114,7 @@ static void __init ath79_misc_irq_init(v
+ 					 handle_level_irq);
+ 	}
+ 
+-	irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
++	irq_set_chained_handler(ATH79_CPU_IRQ(6), ath79_misc_irq_handler);
+ }
+ 
+ static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
+@@ -147,7 +147,7 @@ static void ar934x_ip2_irq_init(void)
+ 		irq_set_chip_and_handler(i, &dummy_irq_chip,
+ 					 handle_level_irq);
+ 
+-	irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch);
++	irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
+ }
+ 
+ asmlinkage void plat_irq_dispatch(void)
+@@ -157,22 +157,22 @@ asmlinkage void plat_irq_dispatch(void)
+ 	pending = read_c0_status() & read_c0_cause() & ST0_IM;
+ 
+ 	if (pending & STATUSF_IP7)
+-		do_IRQ(ATH79_CPU_IRQ_TIMER);
++		do_IRQ(ATH79_CPU_IRQ(7));
+ 
+ 	else if (pending & STATUSF_IP2)
+ 		ath79_ip2_handler();
+ 
+ 	else if (pending & STATUSF_IP4)
+-		do_IRQ(ATH79_CPU_IRQ_GE0);
++		do_IRQ(ATH79_CPU_IRQ(4));
+ 
+ 	else if (pending & STATUSF_IP5)
+-		do_IRQ(ATH79_CPU_IRQ_GE1);
++		do_IRQ(ATH79_CPU_IRQ(5));
+ 
+ 	else if (pending & STATUSF_IP3)
+ 		ath79_ip3_handler();
+ 
+ 	else if (pending & STATUSF_IP6)
+-		do_IRQ(ATH79_CPU_IRQ_MISC);
++		do_IRQ(ATH79_CPU_IRQ(6));
+ 
+ 	else
+ 		spurious_interrupt();
+@@ -188,60 +188,60 @@ asmlinkage void plat_irq_dispatch(void)
+ static void ar71xx_ip2_handler(void)
+ {
+ 	ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI);
+-	do_IRQ(ATH79_CPU_IRQ_IP2);
++	do_IRQ(ATH79_CPU_IRQ(2));
+ }
+ 
+ static void ar724x_ip2_handler(void)
+ {
+ 	ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE);
+-	do_IRQ(ATH79_CPU_IRQ_IP2);
++	do_IRQ(ATH79_CPU_IRQ(2));
+ }
+ 
+ static void ar913x_ip2_handler(void)
+ {
+ 	ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC);
+-	do_IRQ(ATH79_CPU_IRQ_IP2);
++	do_IRQ(ATH79_CPU_IRQ(2));
+ }
+ 
+ static void ar933x_ip2_handler(void)
+ {
+ 	ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC);
+-	do_IRQ(ATH79_CPU_IRQ_IP2);
++	do_IRQ(ATH79_CPU_IRQ(2));
+ }
+ 
+ static void ar934x_ip2_handler(void)
+ {
+-	do_IRQ(ATH79_CPU_IRQ_IP2);
++	do_IRQ(ATH79_CPU_IRQ(2));
+ }
+ 
+ static void ar71xx_ip3_handler(void)
+ {
+ 	ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
+-	do_IRQ(ATH79_CPU_IRQ_USB);
++	do_IRQ(ATH79_CPU_IRQ(3));
+ }
+ 
+ static void ar724x_ip3_handler(void)
+ {
+ 	ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB);
+-	do_IRQ(ATH79_CPU_IRQ_USB);
++	do_IRQ(ATH79_CPU_IRQ(3));
+ }
+ 
+ static void ar913x_ip3_handler(void)
+ {
+ 	ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB);
+-	do_IRQ(ATH79_CPU_IRQ_USB);
++	do_IRQ(ATH79_CPU_IRQ(3));
+ }
+ 
+ static void ar933x_ip3_handler(void)
+ {
+ 	ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB);
+-	do_IRQ(ATH79_CPU_IRQ_USB);
++	do_IRQ(ATH79_CPU_IRQ(3));
+ }
+ 
+ static void ar934x_ip3_handler(void)
+ {
+ 	ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB);
+-	do_IRQ(ATH79_CPU_IRQ_USB);
++	do_IRQ(ATH79_CPU_IRQ(3));
+ }
+ 
+ void __init arch_init_irq(void)
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -127,8 +127,8 @@ ath79_register_pci_ar71xx(void)
+ 	res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1;
+ 
+ 	res[1].flags = IORESOURCE_IRQ;
+-	res[1].start = ATH79_CPU_IRQ_IP2;
+-	res[1].end = ATH79_CPU_IRQ_IP2;
++	res[1].start = ATH79_CPU_IRQ(2);
++	res[1].end = ATH79_CPU_IRQ(2);
+ 
+ 	res[2].name = "io_base";
+ 	res[2].flags = IORESOURCE_IO;
+@@ -208,7 +208,7 @@ int __init ath79_register_pci(void)
+ 						 AR724X_PCI_MEM_BASE,
+ 						 AR724X_PCI_MEM_SIZE,
+ 						 0,
+-						 ATH79_CPU_IRQ_IP2);
++						 ATH79_CPU_IRQ(2));
+ 	} else if (soc_is_ar9342() ||
+ 		   soc_is_ar9344()) {
+ 		u32 bootstrap;
+--- a/arch/mips/include/asm/mach-ath79/irq.h
++++ b/arch/mips/include/asm/mach-ath79/irq.h
+@@ -12,6 +12,8 @@
+ #define MIPS_CPU_IRQ_BASE	0
+ #define NR_IRQS			48
+ 
++#define ATH79_CPU_IRQ(_x)	(MIPS_CPU_IRQ_BASE + (_x))
++
+ #define ATH79_MISC_IRQ_BASE	8
+ #define ATH79_MISC_IRQ_COUNT	32
+ #define ATH79_MISC_IRQ(_x)	(ATH79_MISC_IRQ_BASE + (_x))
+@@ -24,13 +26,6 @@
+ #define ATH79_IP2_IRQ_COUNT	2
+ #define ATH79_IP2_IRQ(_x)	(ATH79_IP2_IRQ_BASE + (_x))
+ 
+-#define ATH79_CPU_IRQ_IP2	(MIPS_CPU_IRQ_BASE + 2)
+-#define ATH79_CPU_IRQ_USB	(MIPS_CPU_IRQ_BASE + 3)
+-#define ATH79_CPU_IRQ_GE0	(MIPS_CPU_IRQ_BASE + 4)
+-#define ATH79_CPU_IRQ_GE1	(MIPS_CPU_IRQ_BASE + 5)
+-#define ATH79_CPU_IRQ_MISC	(MIPS_CPU_IRQ_BASE + 6)
+-#define ATH79_CPU_IRQ_TIMER	(MIPS_CPU_IRQ_BASE + 7)
+-
+ #define ATH79_MISC_IRQ_TIMER	(ATH79_MISC_IRQ_BASE + 0)
+ #define ATH79_MISC_IRQ_ERROR	(ATH79_MISC_IRQ_BASE + 1)
+ #define ATH79_MISC_IRQ_GPIO	(ATH79_MISC_IRQ_BASE + 2)
diff --git a/target/linux/ar71xx/patches-3.8/025-ath79-remove-ATH79_MISC_IRQ_-defines.patch b/target/linux/ar71xx/patches-3.8/025-ath79-remove-ATH79_MISC_IRQ_-defines.patch
new file mode 100644
index 0000000..8278ad3
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/025-ath79-remove-ATH79_MISC_IRQ_-defines.patch
@@ -0,0 +1,85 @@
+From f4414336ae509d20c043264bc9f8f6bafb0e8a6f Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 7 Feb 2013 19:32:24 +0000
+Subject: [PATCH] ath79: remove ATH79_MISC_IRQ_* defines
+
+commit fd633cf1cfe978003888dc78ff94f926fbe7dd8a upstream.
+
+Use the ATH79_MISC_IRQ() macro instead.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4930/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/dev-common.c           |    6 +++---
+ arch/mips/ath79/dev-usb.c              |    2 +-
+ arch/mips/ath79/irq.c                  |    2 +-
+ arch/mips/include/asm/mach-ath79/irq.h |   13 -------------
+ 4 files changed, 5 insertions(+), 18 deletions(-)
+
+--- a/arch/mips/ath79/dev-common.c
++++ b/arch/mips/ath79/dev-common.c
+@@ -36,7 +36,7 @@ static struct resource ath79_uart_resour
+ static struct plat_serial8250_port ath79_uart_data[] = {
+ 	{
+ 		.mapbase	= AR71XX_UART_BASE,
+-		.irq		= ATH79_MISC_IRQ_UART,
++		.irq		= ATH79_MISC_IRQ(3),
+ 		.flags		= AR71XX_UART_FLAGS,
+ 		.iotype		= UPIO_MEM32,
+ 		.regshift	= 2,
+@@ -62,8 +62,8 @@ static struct resource ar933x_uart_resou
+ 		.flags	= IORESOURCE_MEM,
+ 	},
+ 	{
+-		.start	= ATH79_MISC_IRQ_UART,
+-		.end	= ATH79_MISC_IRQ_UART,
++		.start	= ATH79_MISC_IRQ(3),
++		.end	= ATH79_MISC_IRQ(3),
+ 		.flags	= IORESOURCE_IRQ,
+ 	},
+ };
+--- a/arch/mips/ath79/dev-usb.c
++++ b/arch/mips/ath79/dev-usb.c
+@@ -107,7 +107,7 @@ static void __init ath79_usb_setup(void)
+ 	mdelay(900);
+ 
+ 	ath79_usb_init_resource(ath79_ohci_resources, AR71XX_OHCI_BASE,
+-				AR71XX_OHCI_SIZE, ATH79_MISC_IRQ_OHCI);
++				AR71XX_OHCI_SIZE, ATH79_MISC_IRQ(6));
+ 	platform_device_register(&ath79_ohci_device);
+ 
+ 	ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE,
+--- a/arch/mips/ath79/irq.c
++++ b/arch/mips/ath79/irq.c
+@@ -265,7 +265,7 @@ void __init arch_init_irq(void)
+ 		BUG();
+ 	}
+ 
+-	cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC;
++	cp0_perfcount_irq = ATH79_MISC_IRQ(5);
+ 	mips_cpu_irq_init();
+ 	ath79_misc_irq_init();
+ 
+--- a/arch/mips/include/asm/mach-ath79/irq.h
++++ b/arch/mips/include/asm/mach-ath79/irq.h
+@@ -26,19 +26,6 @@
+ #define ATH79_IP2_IRQ_COUNT	2
+ #define ATH79_IP2_IRQ(_x)	(ATH79_IP2_IRQ_BASE + (_x))
+ 
+-#define ATH79_MISC_IRQ_TIMER	(ATH79_MISC_IRQ_BASE + 0)
+-#define ATH79_MISC_IRQ_ERROR	(ATH79_MISC_IRQ_BASE + 1)
+-#define ATH79_MISC_IRQ_GPIO	(ATH79_MISC_IRQ_BASE + 2)
+-#define ATH79_MISC_IRQ_UART	(ATH79_MISC_IRQ_BASE + 3)
+-#define ATH79_MISC_IRQ_WDOG	(ATH79_MISC_IRQ_BASE + 4)
+-#define ATH79_MISC_IRQ_PERFC	(ATH79_MISC_IRQ_BASE + 5)
+-#define ATH79_MISC_IRQ_OHCI	(ATH79_MISC_IRQ_BASE + 6)
+-#define ATH79_MISC_IRQ_DMA	(ATH79_MISC_IRQ_BASE + 7)
+-#define ATH79_MISC_IRQ_TIMER2	(ATH79_MISC_IRQ_BASE + 8)
+-#define ATH79_MISC_IRQ_TIMER3	(ATH79_MISC_IRQ_BASE + 9)
+-#define ATH79_MISC_IRQ_TIMER4	(ATH79_MISC_IRQ_BASE + 10)
+-#define ATH79_MISC_IRQ_ETHSW	(ATH79_MISC_IRQ_BASE + 12)
+-
+ #include_next <irq.h>
+ 
+ #endif /* __ASM_MACH_ATH79_IRQ_H */
diff --git a/target/linux/ar71xx/patches-3.8/026-MIPS-ath79-use-dynamically-allocated-USB-platform-de.patch b/target/linux/ar71xx/patches-3.8/026-MIPS-ath79-use-dynamically-allocated-USB-platform-de.patch
new file mode 100644
index 0000000..e7770cc
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/026-MIPS-ath79-use-dynamically-allocated-USB-platform-de.patch
@@ -0,0 +1,205 @@
+From 9c3c3f7be27c88b59359e743be0437eb6f9af41f Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sat, 9 Feb 2013 17:57:52 +0000
+Subject: [PATCH] MIPS: ath79: use dynamically allocated USB platform devices
+
+commit 90a938d1add4859ad3e43c3dd5ee54bd0627e42d upstream.
+
+The current code uses static resources and static platform
+device instances for the possible USB controllers in the
+system. These static variables contains initial values which
+leads to data segment pollution.
+
+Remove the static variables and use dynamically allocated
+structures instead.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4933/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/dev-usb.c |  111 +++++++++++++++++++++------------------------
+ 1 file changed, 51 insertions(+), 60 deletions(-)
+
+--- a/arch/mips/ath79/dev-usb.c
++++ b/arch/mips/ath79/dev-usb.c
+@@ -25,29 +25,11 @@
+ #include "common.h"
+ #include "dev-usb.h"
+ 
+-static struct resource ath79_ohci_resources[2];
+-
+-static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32);
++static u64 ath79_usb_dmamask = DMA_BIT_MASK(32);
+ 
+ static struct usb_ohci_pdata ath79_ohci_pdata = {
+ };
+ 
+-static struct platform_device ath79_ohci_device = {
+-	.name		= "ohci-platform",
+-	.id		= -1,
+-	.resource	= ath79_ohci_resources,
+-	.num_resources	= ARRAY_SIZE(ath79_ohci_resources),
+-	.dev = {
+-		.dma_mask		= &ath79_ohci_dmamask,
+-		.coherent_dma_mask	= DMA_BIT_MASK(32),
+-		.platform_data		= &ath79_ohci_pdata,
+-	},
+-};
+-
+-static struct resource ath79_ehci_resources[2];
+-
+-static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32);
+-
+ static struct usb_ehci_pdata ath79_ehci_pdata_v1 = {
+ 	.has_synopsys_hc_bug	= 1,
+ };
+@@ -57,22 +39,16 @@ static struct usb_ehci_pdata ath79_ehci_
+ 	.has_tt			= 1,
+ };
+ 
+-static struct platform_device ath79_ehci_device = {
+-	.name		= "ehci-platform",
+-	.id		= -1,
+-	.resource	= ath79_ehci_resources,
+-	.num_resources	= ARRAY_SIZE(ath79_ehci_resources),
+-	.dev = {
+-		.dma_mask		= &ath79_ehci_dmamask,
+-		.coherent_dma_mask	= DMA_BIT_MASK(32),
+-	},
+-};
+-
+-static void __init ath79_usb_init_resource(struct resource res[2],
+-					   unsigned long base,
+-					   unsigned long size,
+-					   int irq)
++static void __init ath79_usb_register(const char *name, int id,
++				      unsigned long base, unsigned long size,
++				      int irq, const void *data,
++				      size_t data_size)
+ {
++	struct resource res[2];
++	struct platform_device *pdev;
++
++	memset(res, 0, sizeof(res));
++
+ 	res[0].flags = IORESOURCE_MEM;
+ 	res[0].start = base;
+ 	res[0].end = base + size - 1;
+@@ -80,6 +56,19 @@ static void __init ath79_usb_init_resour
+ 	res[1].flags = IORESOURCE_IRQ;
+ 	res[1].start = irq;
+ 	res[1].end = irq;
++
++	pdev = platform_device_register_resndata(NULL, name, id,
++						 res, ARRAY_SIZE(res),
++						 data, data_size);
++
++	if (IS_ERR(pdev)) {
++		pr_err("ath79: unable to register USB at %08lx, err=%d\n",
++		       base, (int) PTR_ERR(pdev));
++		return;
++	}
++
++	pdev->dev.dma_mask = &ath79_usb_dmamask;
++	pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+ }
+ 
+ #define AR71XX_USB_RESET_MASK	(AR71XX_RESET_USB_HOST | \
+@@ -106,14 +95,15 @@ static void __init ath79_usb_setup(void)
+ 
+ 	mdelay(900);
+ 
+-	ath79_usb_init_resource(ath79_ohci_resources, AR71XX_OHCI_BASE,
+-				AR71XX_OHCI_SIZE, ATH79_MISC_IRQ(6));
+-	platform_device_register(&ath79_ohci_device);
+-
+-	ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE,
+-				AR71XX_EHCI_SIZE, ATH79_CPU_IRQ(3));
+-	ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1;
+-	platform_device_register(&ath79_ehci_device);
++	ath79_usb_register("ohci-platform", -1,
++			   AR71XX_OHCI_BASE, AR71XX_OHCI_SIZE,
++			   ATH79_MISC_IRQ(6),
++			   &ath79_ohci_pdata, sizeof(ath79_ohci_pdata));
++
++	ath79_usb_register("ehci-platform", -1,
++			   AR71XX_EHCI_BASE, AR71XX_EHCI_SIZE,
++			   ATH79_CPU_IRQ(3),
++			   &ath79_ehci_pdata_v1, sizeof(ath79_ehci_pdata_v1));
+ }
+ 
+ static void __init ar7240_usb_setup(void)
+@@ -135,9 +125,10 @@ static void __init ar7240_usb_setup(void
+ 
+ 	iounmap(usb_ctrl_base);
+ 
+-	ath79_usb_init_resource(ath79_ohci_resources, AR7240_OHCI_BASE,
+-				AR7240_OHCI_SIZE, ATH79_CPU_IRQ(3));
+-	platform_device_register(&ath79_ohci_device);
++	ath79_usb_register("ohci-platform", -1,
++			   AR7240_OHCI_BASE, AR7240_OHCI_SIZE,
++			   ATH79_CPU_IRQ(3),
++			   &ath79_ohci_pdata, sizeof(ath79_ohci_pdata));
+ }
+ 
+ static void __init ar724x_usb_setup(void)
+@@ -151,10 +142,10 @@ static void __init ar724x_usb_setup(void
+ 	ath79_device_reset_clear(AR724X_RESET_USB_PHY);
+ 	mdelay(10);
+ 
+-	ath79_usb_init_resource(ath79_ehci_resources, AR724X_EHCI_BASE,
+-				AR724X_EHCI_SIZE, ATH79_CPU_IRQ(3));
+-	ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
+-	platform_device_register(&ath79_ehci_device);
++	ath79_usb_register("ehci-platform", -1,
++			   AR724X_EHCI_BASE, AR724X_EHCI_SIZE,
++			   ATH79_CPU_IRQ(3),
++			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+ }
+ 
+ static void __init ar913x_usb_setup(void)
+@@ -168,10 +159,10 @@ static void __init ar913x_usb_setup(void
+ 	ath79_device_reset_clear(AR913X_RESET_USB_PHY);
+ 	mdelay(10);
+ 
+-	ath79_usb_init_resource(ath79_ehci_resources, AR913X_EHCI_BASE,
+-				AR913X_EHCI_SIZE, ATH79_CPU_IRQ(3));
+-	ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
+-	platform_device_register(&ath79_ehci_device);
++	ath79_usb_register("ehci-platform", -1,
++			   AR913X_EHCI_BASE, AR913X_EHCI_SIZE,
++			   ATH79_CPU_IRQ(3),
++			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+ }
+ 
+ static void __init ar933x_usb_setup(void)
+@@ -185,10 +176,10 @@ static void __init ar933x_usb_setup(void
+ 	ath79_device_reset_clear(AR933X_RESET_USB_PHY);
+ 	mdelay(10);
+ 
+-	ath79_usb_init_resource(ath79_ehci_resources, AR933X_EHCI_BASE,
+-				AR933X_EHCI_SIZE, ATH79_CPU_IRQ(3));
+-	ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
+-	platform_device_register(&ath79_ehci_device);
++	ath79_usb_register("ehci-platform", -1,
++			   AR933X_EHCI_BASE, AR933X_EHCI_SIZE,
++			   ATH79_CPU_IRQ(3),
++			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+ }
+ 
+ static void __init ar934x_usb_setup(void)
+@@ -211,10 +202,10 @@ static void __init ar934x_usb_setup(void
+ 	ath79_device_reset_clear(AR934X_RESET_USB_HOST);
+ 	udelay(1000);
+ 
+-	ath79_usb_init_resource(ath79_ehci_resources, AR934X_EHCI_BASE,
+-				AR934X_EHCI_SIZE, ATH79_CPU_IRQ(3));
+-	ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
+-	platform_device_register(&ath79_ehci_device);
++	ath79_usb_register("ehci-platform", -1,
++			   AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
++			   ATH79_CPU_IRQ(3),
++			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+ }
+ 
+ void __init ath79_register_usb(void)
diff --git a/target/linux/ar71xx/patches-3.8/027-MIPS-ath79-fix-WMAC-IRQ-resource-assignment.patch b/target/linux/ar71xx/patches-3.8/027-MIPS-ath79-fix-WMAC-IRQ-resource-assignment.patch
new file mode 100644
index 0000000..97065d5
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/027-MIPS-ath79-fix-WMAC-IRQ-resource-assignment.patch
@@ -0,0 +1,29 @@
+From acb28a2a03a93e351e26230511a9f38d0da62fdd Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 18:51:57 +0000
+Subject: [PATCH] MIPS: ath79: fix WMAC IRQ resource assignment
+
+commit e3b25cead4b58fbf60270ba73a1669bf9e5635f5 upstream.
+
+The '.start' field of the IRQ resource assigned twice
+in ar934x_wmac_setup(). The second assignment must
+set the '.end' field. Fix it.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4954/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/dev-wmac.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -107,7 +107,7 @@ static void ar934x_wmac_setup(void)
+ 	ath79_wmac_resources[0].start = AR934X_WMAC_BASE;
+ 	ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1;
+ 	ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
+-	ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
++	ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
+ 
+ 	t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
+ 	if (t & AR934X_BOOTSTRAP_REF_CLK_40)
diff --git a/target/linux/ar71xx/patches-3.8/028-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch b/target/linux/ar71xx/patches-3.8/028-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch
new file mode 100644
index 0000000..38d735b
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/028-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch
@@ -0,0 +1,43 @@
+From 8a4de56e3b7a6fbb777c78f87142bafc22c32ac2 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 13:38:15 +0000
+Subject: [PATCH] MIPS: ath79: add early printk support for the QCA955X SoCs
+
+commit 908987797076b848f01b32c21d61d0e152efc236 upstream.
+
+The patch allows to see kernel messages on the
+QCA955X SoCs in early boot stage.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4944/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/early_printk.c                 |    2 ++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    2 ++
+ 2 files changed, 4 insertions(+)
+
+--- a/arch/mips/ath79/early_printk.c
++++ b/arch/mips/ath79/early_printk.c
+@@ -74,6 +74,8 @@ static void prom_putchar_init(void)
+ 	case REV_ID_MAJOR_AR9341:
+ 	case REV_ID_MAJOR_AR9342:
+ 	case REV_ID_MAJOR_AR9344:
++	case REV_ID_MAJOR_QCA9556:
++	case REV_ID_MAJOR_QCA9558:
+ 		_prom_putchar = prom_putchar_ar71xx;
+ 		break;
+ 
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -370,6 +370,8 @@
+ #define REV_ID_MAJOR_AR9341		0x0120
+ #define REV_ID_MAJOR_AR9342		0x1120
+ #define REV_ID_MAJOR_AR9344		0x2120
++#define REV_ID_MAJOR_QCA9556		0x0130
++#define REV_ID_MAJOR_QCA9558		0x1130
+ 
+ #define AR71XX_REV_ID_MINOR_MASK	0x3
+ #define AR71XX_REV_ID_MINOR_AR7130	0x0
diff --git a/target/linux/ar71xx/patches-3.8/029-MIPS-ath79-add-SoC-detection-code-for-the-QCA955X-So.patch b/target/linux/ar71xx/patches-3.8/029-MIPS-ath79-add-SoC-detection-code-for-the-QCA955X-So.patch
new file mode 100644
index 0000000..5a60ffe
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/029-MIPS-ath79-add-SoC-detection-code-for-the-QCA955X-So.patch
@@ -0,0 +1,113 @@
+From f48780829e9de625cb7fa0850fc31d050da6adeb Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 13:38:16 +0000
+Subject: [PATCH] MIPS: ath79: add SoC detection code for the QCA955X SoCs
+
+commit 2e6c91e392fd7be2ef0ba1e9a20e0ebe8ab79cf3 upstream.
+
+Also add 'soc_is_qca955[68x]' helper functions
+and a Kconfig symbol for the SoC family.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4943/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/Kconfig                        |    4 ++++
+ arch/mips/ath79/setup.c                        |   18 +++++++++++++++++-
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    2 ++
+ arch/mips/include/asm/mach-ath79/ath79.h       |   17 +++++++++++++++++
+ 4 files changed, 40 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -88,6 +88,10 @@ config SOC_AR934X
+ 	select PCI_AR724X if PCI
+ 	def_bool n
+ 
++config SOC_QCA955X
++	select USB_ARCH_HAS_EHCI
++	def_bool n
++
+ config PCI_AR724X
+ 	def_bool n
+ 
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -164,13 +164,29 @@ static void __init ath79_detect_sys_type
+ 		rev = id & AR934X_REV_ID_REVISION_MASK;
+ 		break;
+ 
++	case REV_ID_MAJOR_QCA9556:
++		ath79_soc = ATH79_SOC_QCA9556;
++		chip = "9556";
++		rev = id & QCA955X_REV_ID_REVISION_MASK;
++		break;
++
++	case REV_ID_MAJOR_QCA9558:
++		ath79_soc = ATH79_SOC_QCA9558;
++		chip = "9558";
++		rev = id & QCA955X_REV_ID_REVISION_MASK;
++		break;
++
+ 	default:
+ 		panic("ath79: unknown SoC, id:0x%08x", id);
+ 	}
+ 
+ 	ath79_soc_rev = rev;
+ 
+-	sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
++	if (soc_is_qca955x())
++		sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
++			chip, rev);
++	else
++		sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
+ 	pr_info("SoC: %s\n", ath79_sys_type);
+ }
+ 
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -392,6 +392,8 @@
+ 
+ #define AR934X_REV_ID_REVISION_MASK     0xf
+ 
++#define QCA955X_REV_ID_REVISION_MASK	0xf
++
+ /*
+  * SPI block
+  */
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -32,6 +32,8 @@ enum ath79_soc_type {
+ 	ATH79_SOC_AR9341,
+ 	ATH79_SOC_AR9342,
+ 	ATH79_SOC_AR9344,
++	ATH79_SOC_QCA9556,
++	ATH79_SOC_QCA9558,
+ };
+ 
+ extern enum ath79_soc_type ath79_soc;
+@@ -98,6 +100,21 @@ static inline int soc_is_ar934x(void)
+ 	return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
+ }
+ 
++static inline int soc_is_qca9556(void)
++{
++	return ath79_soc == ATH79_SOC_QCA9556;
++}
++
++static inline int soc_is_qca9558(void)
++{
++	return ath79_soc == ATH79_SOC_QCA9558;
++}
++
++static inline int soc_is_qca955x(void)
++{
++	return soc_is_qca9556() || soc_is_qca9558();
++}
++
+ extern void __iomem *ath79_ddr_base;
+ extern void __iomem *ath79_pll_base;
+ extern void __iomem *ath79_reset_base;
diff --git a/target/linux/ar71xx/patches-3.8/030-MIPS-ath79-add-clock-setup-code-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.8/030-MIPS-ath79-add-clock-setup-code-for-the-QCA955X-SoCs.patch
new file mode 100644
index 0000000..e1d4bfc
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/030-MIPS-ath79-add-clock-setup-code-for-the-QCA955X-SoCs.patch
@@ -0,0 +1,177 @@
+From 64d8592fd1f7265de8b31dbf294928eaf9983db5 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 13:38:17 +0000
+Subject: [PATCH] MIPS: ath79: add clock setup code for the QCA955X SoCs
+
+commit 41583c05c15cd3adb848f9ee8316bf8084c961cb upstream.
+
+The patch adds code to get various clock frequencies
+from the PLLs used in the QCA955x SoCs.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4945/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/clock.c                        |   78 ++++++++++++++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |   39 ++++++++++++
+ 2 files changed, 117 insertions(+)
+
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -295,6 +295,82 @@ static void __init ar934x_clocks_init(vo
+ 	iounmap(dpll_base);
+ }
+ 
++static void __init qca955x_clocks_init(void)
++{
++	u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
++	u32 cpu_pll, ddr_pll;
++	u32 bootstrap;
++
++	bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
++	if (bootstrap &	QCA955X_BOOTSTRAP_REF_CLK_40)
++		ath79_ref_clk.rate = 40 * 1000 * 1000;
++	else
++		ath79_ref_clk.rate = 25 * 1000 * 1000;
++
++	pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
++	out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
++		  QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
++	ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
++		  QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
++	nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
++	       QCA955X_PLL_CPU_CONFIG_NINT_MASK;
++	frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
++	       QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
++
++	cpu_pll = nint * ath79_ref_clk.rate / ref_div;
++	cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6));
++	cpu_pll /= (1 << out_div);
++
++	pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
++	out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
++		  QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
++	ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
++		  QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
++	nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
++	       QCA955X_PLL_DDR_CONFIG_NINT_MASK;
++	frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
++	       QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
++
++	ddr_pll = nint * ath79_ref_clk.rate / ref_div;
++	ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10));
++	ddr_pll /= (1 << out_div);
++
++	clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
++
++	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
++		  QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
++
++	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
++		ath79_cpu_clk.rate = ath79_ref_clk.rate;
++	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
++		ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
++	else
++		ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
++
++	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
++		  QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
++
++	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
++		ath79_ddr_clk.rate = ath79_ref_clk.rate;
++	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
++		ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
++	else
++		ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
++
++	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
++		  QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
++
++	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
++		ath79_ahb_clk.rate = ath79_ref_clk.rate;
++	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
++		ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
++	else
++		ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
++
++	ath79_wdt_clk.rate = ath79_ref_clk.rate;
++	ath79_uart_clk.rate = ath79_ref_clk.rate;
++}
++
+ void __init ath79_clocks_init(void)
+ {
+ 	if (soc_is_ar71xx())
+@@ -307,6 +383,8 @@ void __init ath79_clocks_init(void)
+ 		ar933x_clocks_init();
+ 	else if (soc_is_ar934x())
+ 		ar934x_clocks_init();
++	else if (soc_is_qca955x())
++		qca955x_clocks_init();
+ 	else
+ 		BUG();
+ 
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -225,6 +225,41 @@
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL	BIT(21)
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL	BIT(24)
+ 
++#define QCA955X_PLL_CPU_CONFIG_REG		0x00
++#define QCA955X_PLL_DDR_CONFIG_REG		0x04
++#define QCA955X_PLL_CLK_CTRL_REG		0x08
++
++#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
++#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
++#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT	6
++#define QCA955X_PLL_CPU_CONFIG_NINT_MASK	0x3f
++#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT	12
++#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
++#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT	19
++#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK	0x3
++
++#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT	0
++#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK	0x3ff
++#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT	10
++#define QCA955X_PLL_DDR_CONFIG_NINT_MASK	0x3f
++#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT	16
++#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK	0x1f
++#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT	23
++#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK	0x7
++
++#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
++#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
++#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS		BIT(4)
++#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
++#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x1f
++#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
++#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x1f
++#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
++#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x1f
++#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL		BIT(20)
++#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL		BIT(21)
++#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)
++
+ /*
+  * USB_CONFIG block
+  */
+@@ -264,6 +299,8 @@
+ #define AR934X_RESET_REG_BOOTSTRAP		0xb0
+ #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS	0xac
+ 
++#define QCA955X_RESET_REG_BOOTSTRAP		0xb0
++
+ #define MISC_INT_ETHSW			BIT(12)
+ #define MISC_INT_TIMER4			BIT(10)
+ #define MISC_INT_TIMER3			BIT(9)
+@@ -341,6 +378,8 @@
+ #define AR934X_BOOTSTRAP_SDRAM_DISABLED	BIT(1)
+ #define AR934X_BOOTSTRAP_DDR1		BIT(0)
+ 
++#define QCA955X_BOOTSTRAP_REF_CLK_40	BIT(4)
++
+ #define AR934X_PCIE_WMAC_INT_WMAC_MISC		BIT(0)
+ #define AR934X_PCIE_WMAC_INT_WMAC_TX		BIT(1)
+ #define AR934X_PCIE_WMAC_INT_WMAC_RXLP		BIT(2)
diff --git a/target/linux/ar71xx/patches-3.8/031-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch b/target/linux/ar71xx/patches-3.8/031-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch
new file mode 100644
index 0000000..dd79fa9
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/031-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch
@@ -0,0 +1,246 @@
+From f1c0239d61d6d43469133d144e458f485b6cbda6 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 18:53:47 +0000
+Subject: [PATCH] MIPS: ath79: add IRQ handling code for the QCA955X SoCs
+
+commit 53330332f176eaa9567481c69bbad8b2176b4eb5 upstream.
+
+The IRQ routing in the QCA955x SoCs is slightly
+different from the routing implemented in the
+already supported SoCs.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4955/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/irq.c                          |  110 ++++++++++++++++++++++--
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |   32 +++++++
+ arch/mips/include/asm/mach-ath79/irq.h         |    6 +-
+ 3 files changed, 140 insertions(+), 8 deletions(-)
+
+--- a/arch/mips/ath79/irq.c
++++ b/arch/mips/ath79/irq.c
+@@ -103,7 +103,10 @@ static void __init ath79_misc_irq_init(v
+ 
+ 	if (soc_is_ar71xx() || soc_is_ar913x())
+ 		ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
+-	else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x())
++	else if (soc_is_ar724x() ||
++		 soc_is_ar933x() ||
++		 soc_is_ar934x() ||
++		 soc_is_qca955x())
+ 		ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
+ 	else
+ 		BUG();
+@@ -150,6 +153,88 @@ static void ar934x_ip2_irq_init(void)
+ 	irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
+ }
+ 
++static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
++{
++	u32 status;
++
++	disable_irq_nosync(irq);
++
++	status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
++	status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
++
++	if (status == 0) {
++		spurious_interrupt();
++		goto enable;
++	}
++
++	if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
++		/* TODO: flush DDR? */
++		generic_handle_irq(ATH79_IP2_IRQ(0));
++	}
++
++	if (status & QCA955X_EXT_INT_WMAC_ALL) {
++		/* TODO: flush DDR? */
++		generic_handle_irq(ATH79_IP2_IRQ(1));
++	}
++
++enable:
++	enable_irq(irq);
++}
++
++static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
++{
++	u32 status;
++
++	disable_irq_nosync(irq);
++
++	status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
++	status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
++		  QCA955X_EXT_INT_USB1 |
++		  QCA955X_EXT_INT_USB2;
++
++	if (status == 0) {
++		spurious_interrupt();
++		goto enable;
++	}
++
++	if (status & QCA955X_EXT_INT_USB1) {
++		/* TODO: flush DDR? */
++		generic_handle_irq(ATH79_IP3_IRQ(0));
++	}
++
++	if (status & QCA955X_EXT_INT_USB2) {
++		/* TODO: flush DDR? */
++		generic_handle_irq(ATH79_IP3_IRQ(1));
++	}
++
++	if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
++		/* TODO: flush DDR? */
++		generic_handle_irq(ATH79_IP3_IRQ(2));
++	}
++
++enable:
++	enable_irq(irq);
++}
++
++static void qca955x_irq_init(void)
++{
++	int i;
++
++	for (i = ATH79_IP2_IRQ_BASE;
++	     i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
++		irq_set_chip_and_handler(i, &dummy_irq_chip,
++					 handle_level_irq);
++
++	irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
++
++	for (i = ATH79_IP3_IRQ_BASE;
++	     i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
++		irq_set_chip_and_handler(i, &dummy_irq_chip,
++					 handle_level_irq);
++
++	irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
++}
++
+ asmlinkage void plat_irq_dispatch(void)
+ {
+ 	unsigned long pending;
+@@ -185,6 +270,17 @@ asmlinkage void plat_irq_dispatch(void)
+  * Issue a flush in the handlers to ensure that the driver sees
+  * the update.
+  */
++
++static void ath79_default_ip2_handler(void)
++{
++	do_IRQ(ATH79_CPU_IRQ(2));
++}
++
++static void ath79_default_ip3_handler(void)
++{
++	do_IRQ(ATH79_CPU_IRQ(3));
++}
++
+ static void ar71xx_ip2_handler(void)
+ {
+ 	ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI);
+@@ -209,11 +305,6 @@ static void ar933x_ip2_handler(void)
+ 	do_IRQ(ATH79_CPU_IRQ(2));
+ }
+ 
+-static void ar934x_ip2_handler(void)
+-{
+-	do_IRQ(ATH79_CPU_IRQ(2));
+-}
+-
+ static void ar71xx_ip3_handler(void)
+ {
+ 	ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
+@@ -259,8 +350,11 @@ void __init arch_init_irq(void)
+ 		ath79_ip2_handler = ar933x_ip2_handler;
+ 		ath79_ip3_handler = ar933x_ip3_handler;
+ 	} else if (soc_is_ar934x()) {
+-		ath79_ip2_handler = ar934x_ip2_handler;
++		ath79_ip2_handler = ath79_default_ip2_handler;
+ 		ath79_ip3_handler = ar934x_ip3_handler;
++	} else if (soc_is_qca955x()) {
++		ath79_ip2_handler = ath79_default_ip2_handler;
++		ath79_ip3_handler = ath79_default_ip3_handler;
+ 	} else {
+ 		BUG();
+ 	}
+@@ -271,4 +365,6 @@ void __init arch_init_irq(void)
+ 
+ 	if (soc_is_ar934x())
+ 		ar934x_ip2_irq_init();
++	else if (soc_is_qca955x())
++		qca955x_irq_init();
+ }
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -300,6 +300,7 @@
+ #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS	0xac
+ 
+ #define QCA955X_RESET_REG_BOOTSTRAP		0xb0
++#define QCA955X_RESET_REG_EXT_INT_STATUS	0xac
+ 
+ #define MISC_INT_ETHSW			BIT(12)
+ #define MISC_INT_TIMER4			BIT(10)
+@@ -398,6 +399,37 @@
+ 	 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
+ 	 AR934X_PCIE_WMAC_INT_PCIE_RC3)
+ 
++#define QCA955X_EXT_INT_WMAC_MISC		BIT(0)
++#define QCA955X_EXT_INT_WMAC_TX			BIT(1)
++#define QCA955X_EXT_INT_WMAC_RXLP		BIT(2)
++#define QCA955X_EXT_INT_WMAC_RXHP		BIT(3)
++#define QCA955X_EXT_INT_PCIE_RC1		BIT(4)
++#define QCA955X_EXT_INT_PCIE_RC1_INT0		BIT(5)
++#define QCA955X_EXT_INT_PCIE_RC1_INT1		BIT(6)
++#define QCA955X_EXT_INT_PCIE_RC1_INT2		BIT(7)
++#define QCA955X_EXT_INT_PCIE_RC1_INT3		BIT(8)
++#define QCA955X_EXT_INT_PCIE_RC2		BIT(12)
++#define QCA955X_EXT_INT_PCIE_RC2_INT0		BIT(13)
++#define QCA955X_EXT_INT_PCIE_RC2_INT1		BIT(14)
++#define QCA955X_EXT_INT_PCIE_RC2_INT2		BIT(15)
++#define QCA955X_EXT_INT_PCIE_RC2_INT3		BIT(16)
++#define QCA955X_EXT_INT_USB1			BIT(24)
++#define QCA955X_EXT_INT_USB2			BIT(28)
++
++#define QCA955X_EXT_INT_WMAC_ALL \
++	(QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
++	 QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
++
++#define QCA955X_EXT_INT_PCIE_RC1_ALL \
++	(QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
++	 QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
++	 QCA955X_EXT_INT_PCIE_RC1_INT3)
++
++#define QCA955X_EXT_INT_PCIE_RC2_ALL \
++	(QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
++	 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
++	 QCA955X_EXT_INT_PCIE_RC2_INT3)
++
+ #define REV_ID_MAJOR_MASK		0xfff0
+ #define REV_ID_MAJOR_AR71XX		0x00a0
+ #define REV_ID_MAJOR_AR913X		0x00b0
+--- a/arch/mips/include/asm/mach-ath79/irq.h
++++ b/arch/mips/include/asm/mach-ath79/irq.h
+@@ -10,7 +10,7 @@
+ #define __ASM_MACH_ATH79_IRQ_H
+ 
+ #define MIPS_CPU_IRQ_BASE	0
+-#define NR_IRQS			48
++#define NR_IRQS			51
+ 
+ #define ATH79_CPU_IRQ(_x)	(MIPS_CPU_IRQ_BASE + (_x))
+ 
+@@ -26,6 +26,10 @@
+ #define ATH79_IP2_IRQ_COUNT	2
+ #define ATH79_IP2_IRQ(_x)	(ATH79_IP2_IRQ_BASE + (_x))
+ 
++#define ATH79_IP3_IRQ_BASE	(ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT)
++#define ATH79_IP3_IRQ_COUNT     3
++#define ATH79_IP3_IRQ(_x)       (ATH79_IP3_IRQ_BASE + (_x))
++
+ #include_next <irq.h>
+ 
+ #endif /* __ASM_MACH_ATH79_IRQ_H */
diff --git a/target/linux/ar71xx/patches-3.8/032-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.8/032-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch
new file mode 100644
index 0000000..538da3c
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/032-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch
@@ -0,0 +1,50 @@
+From 8817bcbbaf64d54bd4d06659cc77d1bfc9e53dad Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 13:38:19 +0000
+Subject: [PATCH] MIPS: ath79: add GPIO setup code for the QCA955X SoCs
+
+commit f818ca3e6894d4a630a1ecc673c91df8fb6f6898 upstream.
+
+The existing code can handle the GPIO controller of
+the QCA955x SoCs. Add a minimal glue code to make it
+working.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4947/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/gpio.c                         |    4 +++-
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    1 +
+ 2 files changed, 4 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -194,12 +194,14 @@ void __init ath79_gpio_init(void)
+ 		ath79_gpio_count = AR933X_GPIO_COUNT;
+ 	else if (soc_is_ar934x())
+ 		ath79_gpio_count = AR934X_GPIO_COUNT;
++	else if (soc_is_qca955x())
++		ath79_gpio_count = QCA955X_GPIO_COUNT;
+ 	else
+ 		BUG();
+ 
+ 	ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
+ 	ath79_gpio_chip.ngpio = ath79_gpio_count;
+-	if (soc_is_ar934x()) {
++	if (soc_is_ar934x() || soc_is_qca955x()) {
+ 		ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
+ 		ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
+ 	}
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -510,6 +510,7 @@
+ #define AR913X_GPIO_COUNT		22
+ #define AR933X_GPIO_COUNT		30
+ #define AR934X_GPIO_COUNT		23
++#define QCA955X_GPIO_COUNT		24
+ 
+ /*
+  * SRIF block
diff --git a/target/linux/ar71xx/patches-3.8/033-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch b/target/linux/ar71xx/patches-3.8/033-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch
new file mode 100644
index 0000000..42877ff
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/033-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch
@@ -0,0 +1,53 @@
+From d3cc7a15c1e1a04e8d561c0b05d176434142bf9a Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 13:38:20 +0000
+Subject: [PATCH] MIPS: ath79: add QCA955X specific glue to
+ ath79_device_reset_{set, clear}
+
+commit 7d4c2af9bdbbe789fe4a93f32c5890d72cbf60a1 upstream.
+
+The ath79_device_reset_* are causing BUG when
+those are used on the QCA955x SoCs. The patch
+adds the required code to avoid that.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4948/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/common.c                       |    4 ++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    1 +
+ 2 files changed, 5 insertions(+)
+
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -72,6 +72,8 @@ void ath79_device_reset_set(u32 mask)
+ 		reg = AR933X_RESET_REG_RESET_MODULE;
+ 	else if (soc_is_ar934x())
+ 		reg = AR934X_RESET_REG_RESET_MODULE;
++	else if (soc_is_qca955x())
++		reg = QCA955X_RESET_REG_RESET_MODULE;
+ 	else
+ 		BUG();
+ 
+@@ -98,6 +100,8 @@ void ath79_device_reset_clear(u32 mask)
+ 		reg = AR933X_RESET_REG_RESET_MODULE;
+ 	else if (soc_is_ar934x())
+ 		reg = AR934X_RESET_REG_RESET_MODULE;
++	else if (soc_is_qca955x())
++		reg = QCA955X_RESET_REG_RESET_MODULE;
+ 	else
+ 		BUG();
+ 
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -299,6 +299,7 @@
+ #define AR934X_RESET_REG_BOOTSTRAP		0xb0
+ #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS	0xac
+ 
++#define QCA955X_RESET_REG_RESET_MODULE		0x1c
+ #define QCA955X_RESET_REG_BOOTSTRAP		0xb0
+ #define QCA955X_RESET_REG_EXT_INT_STATUS	0xac
+ 
diff --git a/target/linux/ar71xx/patches-3.8/034-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.8/034-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch
new file mode 100644
index 0000000..38acf45
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/034-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch
@@ -0,0 +1,34 @@
+From 25320dbceda508afc5b2de1986072caa9e04ad1b Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 13:38:21 +0000
+Subject: [PATCH] MIPS: ath79: register UART for the QCA955X SoCs
+
+commit 13992303fa705ae1e4acf4660c69687672996029 upstream.
+
+Similarly to the preceding SoCs, the QCA955X SoCs
+also have a built-in NS16650 compatible UART.
+Register the platform device for that to make
+it usable.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4949/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/dev-common.c |    3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ath79/dev-common.c
++++ b/arch/mips/ath79/dev-common.c
+@@ -90,7 +90,8 @@ void __init ath79_register_uart(void)
+ 	if (soc_is_ar71xx() ||
+ 	    soc_is_ar724x() ||
+ 	    soc_is_ar913x() ||
+-	    soc_is_ar934x()) {
++	    soc_is_ar934x() ||
++	    soc_is_qca955x()) {
+ 		ath79_uart_data[0].uartclk = clk_get_rate(clk);
+ 		platform_device_register(&ath79_uart_device);
+ 	} else if (soc_is_ar933x()) {
diff --git a/target/linux/ar71xx/patches-3.8/035-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch b/target/linux/ar71xx/patches-3.8/035-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch
new file mode 100644
index 0000000..d208fff
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/035-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch
@@ -0,0 +1,81 @@
+From cf40fbb509eaa53ff787dce41911b2545bd001ea Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 18:54:33 +0000
+Subject: [PATCH] MIPS: ath79: add WMAC registration code for the QCA955X SoCs
+
+commit e9c0d0aaa3a7a6e66135e8b44f3323143a635098 upstream.
+
+The SoC has a built-in wireless MAC. Register a platform
+device for that to make it usable with the ath9k driver.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4956/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/Kconfig                        |    2 +-
+ arch/mips/ath79/dev-wmac.c                     |   20 ++++++++++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    3 +++
+ 3 files changed, 24 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -108,7 +108,7 @@ config ATH79_DEV_USB
+ 	def_bool n
+ 
+ config ATH79_DEV_WMAC
+-	depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X)
++	depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
+ 	def_bool n
+ 
+ endif
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -116,6 +116,24 @@ static void ar934x_wmac_setup(void)
+ 		ath79_wmac_data.is_clk_25mhz = true;
+ }
+ 
++static void qca955x_wmac_setup(void)
++{
++	u32 t;
++
++	ath79_wmac_device.name = "qca955x_wmac";
++
++	ath79_wmac_resources[0].start = QCA955X_WMAC_BASE;
++	ath79_wmac_resources[0].end = QCA955X_WMAC_BASE + QCA955X_WMAC_SIZE - 1;
++	ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
++	ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
++
++	t = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
++	if (t & QCA955X_BOOTSTRAP_REF_CLK_40)
++		ath79_wmac_data.is_clk_25mhz = false;
++	else
++		ath79_wmac_data.is_clk_25mhz = true;
++}
++
+ void __init ath79_register_wmac(u8 *cal_data)
+ {
+ 	if (soc_is_ar913x())
+@@ -124,6 +142,8 @@ void __init ath79_register_wmac(u8 *cal_
+ 		ar933x_wmac_setup();
+ 	else if (soc_is_ar934x())
+ 		ar934x_wmac_setup();
++	else if (soc_is_qca955x())
++		qca955x_wmac_setup();
+ 	else
+ 		BUG();
+ 
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -94,6 +94,9 @@
+ #define AR934X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
+ #define AR934X_SRIF_SIZE	0x1000
+ 
++#define QCA955X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
++#define QCA955X_WMAC_SIZE	0x20000
++
+ /*
+  * DDR_CTRL block
+  */
diff --git a/target/linux/ar71xx/patches-3.8/036-MIPS-ath79-add-PCI-controller-registration-code-for-.patch b/target/linux/ar71xx/patches-3.8/036-MIPS-ath79-add-PCI-controller-registration-code-for-.patch
new file mode 100644
index 0000000..c431f94
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/036-MIPS-ath79-add-PCI-controller-registration-code-for-.patch
@@ -0,0 +1,115 @@
+From bc14333054c5ecee4bc7e8760d0ffbb730f32c54 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 13:38:23 +0000
+Subject: [PATCH] MIPS: ath79: add PCI controller registration code for the
+ QCA955X SoCs
+
+commit 0a5f3b1c9f20eb44142e3b37662de15c944f759d upstream.
+
+Add SoC specific PCI IRQ map, and register platform
+devices for the two built-in PCIe RCs.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4951/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/Kconfig                        |    2 ++
+ arch/mips/ath79/pci.c                          |   36 ++++++++++++++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |   13 +++++++++
+ 3 files changed, 51 insertions(+)
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -90,6 +90,8 @@ config SOC_AR934X
+ 
+ config SOC_QCA955X
+ 	select USB_ARCH_HAS_EHCI
++	select HW_HAS_PCI
++	select PCI_AR724X if PCI
+ 	def_bool n
+ 
+ config PCI_AR724X
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -49,6 +49,21 @@ static const struct ath79_pci_irq ar724x
+ 	}
+ };
+ 
++static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = {
++	{
++		.bus	= 0,
++		.slot	= 0,
++		.pin	= 1,
++		.irq	= ATH79_PCI_IRQ(0),
++	},
++	{
++		.bus	= 1,
++		.slot	= 0,
++		.pin	= 1,
++		.irq	= ATH79_PCI_IRQ(1),
++	},
++};
++
+ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
+ {
+ 	int irq = -1;
+@@ -64,6 +79,9 @@ int __init pcibios_map_irq(const struct
+ 			   soc_is_ar9344()) {
+ 			ath79_pci_irq_map = ar724x_pci_irq_map;
+ 			ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
++		} else if (soc_is_qca955x()) {
++			ath79_pci_irq_map = qca955x_pci_irq_map;
++			ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
+ 		} else {
+ 			pr_crit("pci %s: invalid irq map\n",
+ 				pci_name((struct pci_dev *) dev));
+@@ -225,6 +243,24 @@ int __init ath79_register_pci(void)
+ 						 AR724X_PCI_MEM_SIZE,
+ 						 0,
+ 						 ATH79_IP2_IRQ(0));
++	} else if (soc_is_qca9558()) {
++		pdev = ath79_register_pci_ar724x(0,
++						 QCA955X_PCI_CFG_BASE0,
++						 QCA955X_PCI_CTRL_BASE0,
++						 QCA955X_PCI_CRP_BASE0,
++						 QCA955X_PCI_MEM_BASE0,
++						 QCA955X_PCI_MEM_SIZE,
++						 0,
++						 ATH79_IP2_IRQ(0));
++
++		pdev = ath79_register_pci_ar724x(1,
++						 QCA955X_PCI_CFG_BASE1,
++						 QCA955X_PCI_CTRL_BASE1,
++						 QCA955X_PCI_CRP_BASE1,
++						 QCA955X_PCI_MEM_BASE1,
++						 QCA955X_PCI_MEM_SIZE,
++						 1,
++						 ATH79_IP3_IRQ(2));
+ 	} else {
+ 		/* No PCI support */
+ 		return -ENODEV;
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -94,6 +94,19 @@
+ #define AR934X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
+ #define AR934X_SRIF_SIZE	0x1000
+ 
++#define QCA955X_PCI_MEM_BASE0	0x10000000
++#define QCA955X_PCI_MEM_BASE1	0x12000000
++#define QCA955X_PCI_MEM_SIZE	0x02000000
++#define QCA955X_PCI_CFG_BASE0	0x14000000
++#define QCA955X_PCI_CFG_BASE1	0x16000000
++#define QCA955X_PCI_CFG_SIZE	0x1000
++#define QCA955X_PCI_CRP_BASE0	(AR71XX_APB_BASE + 0x000c0000)
++#define QCA955X_PCI_CRP_BASE1	(AR71XX_APB_BASE + 0x00250000)
++#define QCA955X_PCI_CRP_SIZE	0x1000
++#define QCA955X_PCI_CTRL_BASE0	(AR71XX_APB_BASE + 0x000f0000)
++#define QCA955X_PCI_CTRL_BASE1	(AR71XX_APB_BASE + 0x00280000)
++#define QCA955X_PCI_CTRL_SIZE	0x100
++
+ #define QCA955X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+ #define QCA955X_WMAC_SIZE	0x20000
+ 
diff --git a/target/linux/ar71xx/patches-3.8/037-MIPS-ath79-add-USB-controller-registration-code-for-.patch b/target/linux/ar71xx/patches-3.8/037-MIPS-ath79-add-USB-controller-registration-code-for-.patch
new file mode 100644
index 0000000..15b7c75
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/037-MIPS-ath79-add-USB-controller-registration-code-for-.patch
@@ -0,0 +1,65 @@
+From 281db30007b5836ce8acf5a45160fde6b176eda4 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 13:38:24 +0000
+Subject: [PATCH] MIPS: ath79: add USB controller registration code for the
+ QCA955X SoCs
+
+commit 82c46840ae6bd8a147c59cd51f636d913989324a upstream.
+
+Register platfom devices for the built-in USB
+controllers of the SoCs.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4952/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/dev-usb.c                      |   15 +++++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    3 +++
+ 2 files changed, 18 insertions(+)
+
+--- a/arch/mips/ath79/dev-usb.c
++++ b/arch/mips/ath79/dev-usb.c
+@@ -208,6 +208,19 @@ static void __init ar934x_usb_setup(void
+ 			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+ }
+ 
++static void __init qca955x_usb_setup(void)
++{
++	ath79_usb_register("ehci-platform", 0,
++			   QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
++			   ATH79_IP3_IRQ(0),
++			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
++
++	ath79_usb_register("ehci-platform", 1,
++			   QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE,
++			   ATH79_IP3_IRQ(1),
++			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
++}
++
+ void __init ath79_register_usb(void)
+ {
+ 	if (soc_is_ar71xx())
+@@ -222,6 +235,8 @@ void __init ath79_register_usb(void)
+ 		ar933x_usb_setup();
+ 	else if (soc_is_ar934x())
+ 		ar934x_usb_setup();
++	else if (soc_is_qca955x())
++		qca955x_usb_setup();
+ 	else
+ 		BUG();
+ }
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -109,6 +109,9 @@
+ 
+ #define QCA955X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+ #define QCA955X_WMAC_SIZE	0x20000
++#define QCA955X_EHCI0_BASE	0x1b000000
++#define QCA955X_EHCI1_BASE	0x1b400000
++#define QCA955X_EHCI_SIZE	0x1000
+ 
+ /*
+  * DDR_CTRL block
diff --git a/target/linux/ar71xx/patches-3.8/038-MIPS-ath79-add-support-for-the-Qualcomm-Atheros-AP13.patch b/target/linux/ar71xx/patches-3.8/038-MIPS-ath79-add-support-for-the-Qualcomm-Atheros-AP13.patch
new file mode 100644
index 0000000..e235570
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/038-MIPS-ath79-add-support-for-the-Qualcomm-Atheros-AP13.patch
@@ -0,0 +1,234 @@
+From 7f8c0c731409b9c3e62fa8a6eb4830ace8568769 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 13:38:25 +0000
+Subject: [PATCH] MIPS: ath79: add support for the Qualcomm Atheros AP136-010
+ board
+
+commit 27ea052acb9eaca98cc90bf1b8738b6d0ea5bc2f upstream.
+
+Also enable the board in the default configuration.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4953/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/Kconfig           |   12 +++
+ arch/mips/ath79/Makefile          |    1 +
+ arch/mips/ath79/mach-ap136.c      |  156 +++++++++++++++++++++++++++++++++++++
+ arch/mips/ath79/machtypes.h       |    1 +
+ arch/mips/configs/ath79_defconfig |    1 +
+ 5 files changed, 171 insertions(+)
+ create mode 100644 arch/mips/ath79/mach-ap136.c
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -14,6 +14,18 @@ config ATH79_MACH_AP121
+ 	  Say 'Y' here if you want your kernel to support the
+ 	  Atheros AP121 reference board.
+ 
++config ATH79_MACH_AP136
++	bool "Atheros AP136 reference board"
++	select SOC_QCA955X
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_SPI
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++	help
++	  Say 'Y' here if you want your kernel to support the
++	  Atheros AP136 reference board.
++
+ config ATH79_MACH_AP81
+ 	bool "Atheros AP81 reference board"
+ 	select SOC_AR913X
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -27,6 +27,7 @@ obj-$(CONFIG_ATH79_DEV_WMAC)		+= dev-wma
+ # Machines
+ #
+ obj-$(CONFIG_ATH79_MACH_AP121)		+= mach-ap121.o
++obj-$(CONFIG_ATH79_MACH_AP136)		+= mach-ap136.o
+ obj-$(CONFIG_ATH79_MACH_AP81)		+= mach-ap81.o
+ obj-$(CONFIG_ATH79_MACH_DB120)		+= mach-db120.o
+ obj-$(CONFIG_ATH79_MACH_PB44)		+= mach-pb44.o
+--- /dev/null
++++ b/arch/mips/ath79/mach-ap136.c
+@@ -0,0 +1,156 @@
++/*
++ * Qualcomm Atheros AP136 reference board support
++ *
++ * Copyright (c) 2012 Qualcomm Atheros
++ * Copyright (c) 2012-2013 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ *
++ */
++
++#include <linux/pci.h>
++#include <linux/ath9k_platform.h>
++
++#include "machtypes.h"
++#include "dev-gpio-buttons.h"
++#include "dev-leds-gpio.h"
++#include "dev-spi.h"
++#include "dev-usb.h"
++#include "dev-wmac.h"
++#include "pci.h"
++
++#define AP136_GPIO_LED_STATUS_RED	14
++#define AP136_GPIO_LED_STATUS_GREEN	19
++#define AP136_GPIO_LED_USB		4
++#define AP136_GPIO_LED_WLAN_2G		13
++#define AP136_GPIO_LED_WLAN_5G		12
++#define AP136_GPIO_LED_WPS_RED		15
++#define AP136_GPIO_LED_WPS_GREEN	20
++
++#define AP136_GPIO_BTN_WPS		16
++#define AP136_GPIO_BTN_RFKILL		21
++
++#define AP136_KEYS_POLL_INTERVAL	20	/* msecs */
++#define AP136_KEYS_DEBOUNCE_INTERVAL	(3 * AP136_KEYS_POLL_INTERVAL)
++
++#define AP136_WMAC_CALDATA_OFFSET 0x1000
++#define AP136_PCIE_CALDATA_OFFSET 0x5000
++
++static struct gpio_led ap136_leds_gpio[] __initdata = {
++	{
++		.name		= "qca:green:status",
++		.gpio		= AP136_GPIO_LED_STATUS_GREEN,
++		.active_low	= 1,
++	},
++	{
++		.name		= "qca:red:status",
++		.gpio		= AP136_GPIO_LED_STATUS_RED,
++		.active_low	= 1,
++	},
++	{
++		.name		= "qca:green:wps",
++		.gpio		= AP136_GPIO_LED_WPS_GREEN,
++		.active_low	= 1,
++	},
++	{
++		.name		= "qca:red:wps",
++		.gpio		= AP136_GPIO_LED_WPS_RED,
++		.active_low	= 1,
++	},
++	{
++		.name		= "qca:red:wlan-2g",
++		.gpio		= AP136_GPIO_LED_WLAN_2G,
++		.active_low	= 1,
++	},
++	{
++		.name		= "qca:red:usb",
++		.gpio		= AP136_GPIO_LED_USB,
++		.active_low	= 1,
++	}
++};
++
++static struct gpio_keys_button ap136_gpio_keys[] __initdata = {
++	{
++		.desc		= "WPS button",
++		.type		= EV_KEY,
++		.code		= KEY_WPS_BUTTON,
++		.debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL,
++		.gpio		= AP136_GPIO_BTN_WPS,
++		.active_low	= 1,
++	},
++	{
++		.desc		= "RFKILL button",
++		.type		= EV_KEY,
++		.code		= KEY_RFKILL,
++		.debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL,
++		.gpio		= AP136_GPIO_BTN_RFKILL,
++		.active_low	= 1,
++	},
++};
++
++static struct spi_board_info ap136_spi_info[] = {
++	{
++		.bus_num	= 0,
++		.chip_select	= 0,
++		.max_speed_hz	= 25000000,
++		.modalias	= "mx25l6405d",
++	}
++};
++
++static struct ath79_spi_platform_data ap136_spi_data = {
++	.bus_num	= 0,
++	.num_chipselect	= 1,
++};
++
++#ifdef CONFIG_PCI
++static struct ath9k_platform_data ap136_ath9k_data;
++
++static int ap136_pci_plat_dev_init(struct pci_dev *dev)
++{
++	if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
++		dev->dev.platform_data = &ap136_ath9k_data;
++
++	return 0;
++}
++
++static void __init ap136_pci_init(u8 *eeprom)
++{
++	memcpy(ap136_ath9k_data.eeprom_data, eeprom,
++	       sizeof(ap136_ath9k_data.eeprom_data));
++
++	ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
++	ath79_register_pci();
++}
++#else
++static inline void ap136_pci_init(void) {}
++#endif /* CONFIG_PCI */
++
++static void __init ap136_setup(void)
++{
++	u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
++
++	ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
++				 ap136_leds_gpio);
++	ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
++					ARRAY_SIZE(ap136_gpio_keys),
++					ap136_gpio_keys);
++	ath79_register_spi(&ap136_spi_data, ap136_spi_info,
++			   ARRAY_SIZE(ap136_spi_info));
++	ath79_register_usb();
++	ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
++	ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
++}
++
++MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
++	     "Atheros AP136-010 reference board",
++	     ap136_setup);
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -17,6 +17,7 @@
+ enum ath79_mach_type {
+ 	ATH79_MACH_GENERIC = 0,
+ 	ATH79_MACH_AP121,		/* Atheros AP121 reference board */
++	ATH79_MACH_AP136_010,		/* Atheros AP136-010 reference board */
+ 	ATH79_MACH_AP81,		/* Atheros AP81 reference board */
+ 	ATH79_MACH_DB120,		/* Atheros DB120 reference board */
+ 	ATH79_MACH_PB44,		/* Atheros PB44 reference board */
+--- a/arch/mips/configs/ath79_defconfig
++++ b/arch/mips/configs/ath79_defconfig
+@@ -1,5 +1,6 @@
+ CONFIG_ATH79=y
+ CONFIG_ATH79_MACH_AP121=y
++CONFIG_ATH79_MACH_AP136=y
+ CONFIG_ATH79_MACH_AP81=y
+ CONFIG_ATH79_MACH_DB120=y
+ CONFIG_ATH79_MACH_PB44=y
diff --git a/target/linux/ar71xx/patches-3.8/039-watchdog-ath79_wdt-convert-to-use-devm_clk_get.patch b/target/linux/ar71xx/patches-3.8/039-watchdog-ath79_wdt-convert-to-use-devm_clk_get.patch
new file mode 100644
index 0000000..e0b8d50
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/039-watchdog-ath79_wdt-convert-to-use-devm_clk_get.patch
@@ -0,0 +1,51 @@
+From 7ddf72f2337b5f7790994df966c26cd1180e1585 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 27 Dec 2012 15:38:24 +0100
+Subject: [PATCH] watchdog: ath79_wdt: convert to use devm_clk_get
+
+commit 5071a88475b758bf60191e53606463fe7290c71e upstream.
+
+Use the managed version of clk_get. This allows to
+simplify the probe/remove functions a bit.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
+---
+ drivers/watchdog/ath79_wdt.c |    7 ++-----
+ 1 file changed, 2 insertions(+), 5 deletions(-)
+
+--- a/drivers/watchdog/ath79_wdt.c
++++ b/drivers/watchdog/ath79_wdt.c
+@@ -229,13 +229,13 @@ static int ath79_wdt_probe(struct platfo
+ 	u32 ctrl;
+ 	int err;
+ 
+-	wdt_clk = clk_get(&pdev->dev, "wdt");
++	wdt_clk = devm_clk_get(&pdev->dev, "wdt");
+ 	if (IS_ERR(wdt_clk))
+ 		return PTR_ERR(wdt_clk);
+ 
+ 	err = clk_enable(wdt_clk);
+ 	if (err)
+-		goto err_clk_put;
++		return err;
+ 
+ 	wdt_freq = clk_get_rate(wdt_clk);
+ 	if (!wdt_freq) {
+@@ -265,8 +265,6 @@ static int ath79_wdt_probe(struct platfo
+ 
+ err_clk_disable:
+ 	clk_disable(wdt_clk);
+-err_clk_put:
+-	clk_put(wdt_clk);
+ 	return err;
+ }
+ 
+@@ -274,7 +272,6 @@ static int ath79_wdt_remove(struct platf
+ {
+ 	misc_deregister(&ath79_wdt_miscdev);
+ 	clk_disable(wdt_clk);
+-	clk_put(wdt_clk);
+ 	return 0;
+ }
+ 
diff --git a/target/linux/ar71xx/patches-3.8/040-MIPS-ath79-use-dynamically-allocated-watchdog-device.patch b/target/linux/ar71xx/patches-3.8/040-MIPS-ath79-use-dynamically-allocated-watchdog-device.patch
new file mode 100644
index 0000000..082195f
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/040-MIPS-ath79-use-dynamically-allocated-watchdog-device.patch
@@ -0,0 +1,35 @@
+From 5e25d5207d21e65b5a2e58b64aba6804653e95b8 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 27 Dec 2012 15:38:25 +0100
+Subject: [PATCH] MIPS: ath79: use dynamically allocated watchdog device
+
+commit 0f2ad9ed7c6fecb008372e8a709595a2a21059aa upstream.
+
+Remove the static watchdog device variable and use
+the 'platform_device_register_simple' helper to
+allocate and register the device in one step.
+
+This allows us to save a few bytes in the kernel image.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
+---
+ arch/mips/ath79/dev-common.c |    7 +------
+ 1 file changed, 1 insertion(+), 6 deletions(-)
+
+--- a/arch/mips/ath79/dev-common.c
++++ b/arch/mips/ath79/dev-common.c
+@@ -102,12 +102,7 @@ void __init ath79_register_uart(void)
+ 	}
+ }
+ 
+-static struct platform_device ath79_wdt_device = {
+-	.name		= "ath79-wdt",
+-	.id		= -1,
+-};
+-
+ void __init ath79_register_wdt(void)
+ {
+-	platform_device_register(&ath79_wdt_device);
++	platform_device_register_simple("ath79-wdt", -1, NULL, 0);
+ }
diff --git a/target/linux/ar71xx/patches-3.8/041-watchdog-ath79_wdt-get-register-base-from-platform-d.patch b/target/linux/ar71xx/patches-3.8/041-watchdog-ath79_wdt-get-register-base-from-platform-d.patch
new file mode 100644
index 0000000..b863829
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/041-watchdog-ath79_wdt-get-register-base-from-platform-d.patch
@@ -0,0 +1,151 @@
+From 9c0785757dacd1aaf9e6e58b4f559e345093f1d4 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 27 Dec 2012 15:38:26 +0100
+Subject: [PATCH] watchdog: ath79_wdt: get register base from platform
+ device's resources
+
+commit 09f5100a592d11dad06b218f41d560ff1f87f666 upstream.
+
+The ath79_wdt driver uses a fixed memory address
+currently. Although this is working with each
+currently supported SoCs, but this may change
+in the future. Additionally, the driver includes
+platform specific header files in order to be
+able to get the memory base of the watchdog
+device.
+
+The patch adds a memory resource to the platform
+device, and converts the driver to get the base
+address of the watchdog device from that.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
+---
+ arch/mips/ath79/dev-common.c |   10 ++++++++-
+ drivers/watchdog/ath79_wdt.c |   48 +++++++++++++++++++++++++++++++++---------
+ 2 files changed, 47 insertions(+), 11 deletions(-)
+
+--- a/arch/mips/ath79/dev-common.c
++++ b/arch/mips/ath79/dev-common.c
+@@ -104,5 +104,13 @@ void __init ath79_register_uart(void)
+ 
+ void __init ath79_register_wdt(void)
+ {
+-	platform_device_register_simple("ath79-wdt", -1, NULL, 0);
++	struct resource res;
++
++	memset(&res, 0, sizeof(res));
++
++	res.flags = IORESOURCE_MEM;
++	res.start = AR71XX_RESET_BASE + AR71XX_RESET_REG_WDOG_CTRL;
++	res.end = res.start + 0x8 - 1;
++
++	platform_device_register_simple("ath79-wdt", -1, &res, 1);
+ }
+--- a/drivers/watchdog/ath79_wdt.c
++++ b/drivers/watchdog/ath79_wdt.c
+@@ -23,6 +23,7 @@
+ #include <linux/errno.h>
+ #include <linux/fs.h>
+ #include <linux/init.h>
++#include <linux/io.h>
+ #include <linux/kernel.h>
+ #include <linux/miscdevice.h>
+ #include <linux/module.h>
+@@ -33,13 +34,13 @@
+ #include <linux/clk.h>
+ #include <linux/err.h>
+ 
+-#include <asm/mach-ath79/ath79.h>
+-#include <asm/mach-ath79/ar71xx_regs.h>
+-
+ #define DRIVER_NAME	"ath79-wdt"
+ 
+ #define WDT_TIMEOUT	15	/* seconds */
+ 
++#define WDOG_REG_CTRL		0x00
++#define WDOG_REG_TIMER		0x04
++
+ #define WDOG_CTRL_LAST_RESET	BIT(31)
+ #define WDOG_CTRL_ACTION_MASK	3
+ #define WDOG_CTRL_ACTION_NONE	0	/* no action */
+@@ -66,27 +67,38 @@ static struct clk *wdt_clk;
+ static unsigned long wdt_freq;
+ static int boot_status;
+ static int max_timeout;
++static void __iomem *wdt_base;
++
++static inline void ath79_wdt_wr(unsigned reg, u32 val)
++{
++	iowrite32(val, wdt_base + reg);
++}
++
++static inline u32 ath79_wdt_rr(unsigned reg)
++{
++	return ioread32(wdt_base + reg);
++}
+ 
+ static inline void ath79_wdt_keepalive(void)
+ {
+-	ath79_reset_wr(AR71XX_RESET_REG_WDOG, wdt_freq * timeout);
++	ath79_wdt_wr(WDOG_REG_TIMER, wdt_freq * timeout);
+ 	/* flush write */
+-	ath79_reset_rr(AR71XX_RESET_REG_WDOG);
++	ath79_wdt_rr(WDOG_REG_TIMER);
+ }
+ 
+ static inline void ath79_wdt_enable(void)
+ {
+ 	ath79_wdt_keepalive();
+-	ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR);
++	ath79_wdt_wr(WDOG_REG_CTRL, WDOG_CTRL_ACTION_FCR);
+ 	/* flush write */
+-	ath79_reset_rr(AR71XX_RESET_REG_WDOG_CTRL);
++	ath79_wdt_rr(WDOG_REG_CTRL);
+ }
+ 
+ static inline void ath79_wdt_disable(void)
+ {
+-	ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_NONE);
++	ath79_wdt_wr(WDOG_REG_CTRL, WDOG_CTRL_ACTION_NONE);
+ 	/* flush write */
+-	ath79_reset_rr(AR71XX_RESET_REG_WDOG_CTRL);
++	ath79_wdt_rr(WDOG_REG_CTRL);
+ }
+ 
+ static int ath79_wdt_set_timeout(int val)
+@@ -226,9 +238,25 @@ static struct miscdevice ath79_wdt_miscd
+ 
+ static int ath79_wdt_probe(struct platform_device *pdev)
+ {
++	struct resource *res;
+ 	u32 ctrl;
+ 	int err;
+ 
++	if (wdt_base)
++		return -EBUSY;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res) {
++		dev_err(&pdev->dev, "no memory resource found\n");
++		return -EINVAL;
++	}
++
++	wdt_base = devm_request_and_ioremap(&pdev->dev, res);
++	if (!wdt_base) {
++		dev_err(&pdev->dev, "unable to remap memory region\n");
++		return -ENOMEM;
++	}
++
+ 	wdt_clk = devm_clk_get(&pdev->dev, "wdt");
+ 	if (IS_ERR(wdt_clk))
+ 		return PTR_ERR(wdt_clk);
+@@ -251,7 +279,7 @@ static int ath79_wdt_probe(struct platfo
+ 			max_timeout, timeout);
+ 	}
+ 
+-	ctrl = ath79_reset_rr(AR71XX_RESET_REG_WDOG_CTRL);
++	ctrl = ath79_wdt_rr(WDOG_REG_CTRL);
+ 	boot_status = (ctrl & WDOG_CTRL_LAST_RESET) ? WDIOF_CARDRESET : 0;
+ 
+ 	err = misc_register(&ath79_wdt_miscdev);
diff --git a/target/linux/ar71xx/patches-3.8/206-spi-ath79-make-chipselect-logic-more-flexible.patch b/target/linux/ar71xx/patches-3.8/206-spi-ath79-make-chipselect-logic-more-flexible.patch
new file mode 100644
index 0000000..93df466
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/206-spi-ath79-make-chipselect-logic-more-flexible.patch
@@ -0,0 +1,310 @@
+From 7008284716403237f6bc7d7590b3ed073555bd56 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 11 Jan 2012 22:25:11 +0100
+Subject: [PATCH 34/34] spi/ath79: make chipselect logic more flexible
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/mach-ap121.c                       |    6 ++
+ arch/mips/ath79/mach-ap136.c                       |    6 ++
+ arch/mips/ath79/mach-ap81.c                        |    6 ++
+ arch/mips/ath79/mach-db120.c                       |    6 ++
+ arch/mips/ath79/mach-pb44.c                        |    6 ++
+ arch/mips/ath79/mach-ubnt-xm.c                     |    6 ++
+ .../include/asm/mach-ath79/ath79_spi_platform.h    |    8 ++-
+ drivers/spi/spi-ath79.c                            |   67 +++++++++++++-------
+ 8 files changed, 88 insertions(+), 23 deletions(-)
+
+--- a/arch/mips/ath79/mach-ap121.c
++++ b/arch/mips/ath79/mach-ap121.c
+@@ -58,12 +58,18 @@ static struct gpio_keys_button ap121_gpi
+ 	}
+ };
+ 
++static struct ath79_spi_controller_data ap121_spi0_data = {
++	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++	.cs_line = 0,
++};
++
+ static struct spi_board_info ap121_spi_info[] = {
+ 	{
+ 		.bus_num	= 0,
+ 		.chip_select	= 0,
+ 		.max_speed_hz	= 25000000,
+ 		.modalias	= "mx25l1606e",
++		.controller_data = &ap121_spi0_data,
+ 	}
+ };
+ 
+--- a/arch/mips/ath79/mach-ap136.c
++++ b/arch/mips/ath79/mach-ap136.c
+@@ -98,12 +98,18 @@ static struct gpio_keys_button ap136_gpi
+ 	},
+ };
+ 
++static struct ath79_spi_controller_data ap136_spi0_data = {
++	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++	.cs_line = 0,
++};
++
+ static struct spi_board_info ap136_spi_info[] = {
+ 	{
+ 		.bus_num	= 0,
+ 		.chip_select	= 0,
+ 		.max_speed_hz	= 25000000,
+ 		.modalias	= "mx25l6405d",
++		.controller_data = &ap136_spi0_data,
+ 	}
+ };
+ 
+--- a/arch/mips/ath79/mach-ap81.c
++++ b/arch/mips/ath79/mach-ap81.c
+@@ -67,12 +67,18 @@ static struct gpio_keys_button ap81_gpio
+ 	}
+ };
+ 
++static struct ath79_spi_controller_data ap81_spi0_data = {
++	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++	.cs_line = 0,
++};
++
+ static struct spi_board_info ap81_spi_info[] = {
+ 	{
+ 		.bus_num	= 0,
+ 		.chip_select	= 0,
+ 		.max_speed_hz	= 25000000,
+ 		.modalias	= "m25p64",
++		.controller_data = &ap81_spi0_data,
+ 	}
+ };
+ 
+--- a/arch/mips/ath79/mach-db120.c
++++ b/arch/mips/ath79/mach-db120.c
+@@ -76,12 +76,18 @@ static struct gpio_keys_button db120_gpi
+ 	},
+ };
+ 
++static struct ath79_spi_controller_data db120_spi0_data = {
++	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++	.cs_line = 0,
++};
++
+ static struct spi_board_info db120_spi_info[] = {
+ 	{
+ 		.bus_num	= 0,
+ 		.chip_select	= 0,
+ 		.max_speed_hz	= 25000000,
+ 		.modalias	= "s25sl064a",
++		.controller_data = &db120_spi0_data,
+ 	}
+ };
+ 
+--- a/arch/mips/ath79/mach-pb44.c
++++ b/arch/mips/ath79/mach-pb44.c
+@@ -87,12 +87,18 @@ static struct gpio_keys_button pb44_gpio
+ 	}
+ };
+ 
++static struct ath79_spi_controller_data pb44_spi0_data = {
++	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++	.cs_line = 0,
++};
++
+ static struct spi_board_info pb44_spi_info[] = {
+ 	{
+ 		.bus_num	= 0,
+ 		.chip_select	= 0,
+ 		.max_speed_hz	= 25000000,
+ 		.modalias	= "m25p64",
++		.controller_data = &pb44_spi0_data,
+ 	},
+ };
+ 
+--- a/arch/mips/ath79/mach-ubnt-xm.c
++++ b/arch/mips/ath79/mach-ubnt-xm.c
+@@ -65,12 +65,18 @@ static struct gpio_keys_button ubnt_xm_g
+ 	}
+ };
+ 
++static struct ath79_spi_controller_data ubnt_xm_spi0_data = {
++	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++	.cs_line = 0,
++};
++
+ static struct spi_board_info ubnt_xm_spi_info[] = {
+ 	{
+ 		.bus_num	= 0,
+ 		.chip_select	= 0,
+ 		.max_speed_hz	= 25000000,
+ 		.modalias	= "mx25l6405d",
++		.controller_data = &ubnt_xm_spi0_data,
+ 	}
+ };
+ 
+--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
++++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
+@@ -16,8 +16,14 @@ struct ath79_spi_platform_data {
+ 	unsigned	num_chipselect;
+ };
+ 
++enum ath79_spi_cs_type {
++	ATH79_SPI_CS_TYPE_INTERNAL,
++	ATH79_SPI_CS_TYPE_GPIO,
++};
++
+ struct ath79_spi_controller_data {
+-	unsigned	gpio;
++	enum ath79_spi_cs_type cs_type;
++	unsigned cs_line;
+ };
+ 
+ #endif /* _ATH79_SPI_PLATFORM_H */
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -35,6 +35,8 @@
+ #define ATH79_SPI_RRW_DELAY_FACTOR	12000
+ #define MHZ				(1000 * 1000)
+ 
++#define ATH79_SPI_CS_LINE_MAX		2
++
+ struct ath79_spi {
+ 	struct spi_bitbang	bitbang;
+ 	u32			ioc_base;
+@@ -69,6 +71,7 @@ static void ath79_spi_chipselect(struct
+ {
+ 	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+ 	int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
++	struct ath79_spi_controller_data *cdata = spi->controller_data;
+ 
+ 	if (is_active) {
+ 		/* set initial clock polarity */
+@@ -80,20 +83,24 @@ static void ath79_spi_chipselect(struct
+ 		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
+ 	}
+ 
+-	if (spi->chip_select) {
+-		struct ath79_spi_controller_data *cdata = spi->controller_data;
+-
+-		/* SPI is normally active-low */
+-		gpio_set_value(cdata->gpio, cs_high);
+-	} else {
++	switch (cdata->cs_type) {
++	case ATH79_SPI_CS_TYPE_INTERNAL:
+ 		if (cs_high)
+-			sp->ioc_base |= AR71XX_SPI_IOC_CS0;
++			sp->ioc_base |= AR71XX_SPI_IOC_CS(cdata->cs_line);
+ 		else
+-			sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
++			sp->ioc_base &= ~AR71XX_SPI_IOC_CS(cdata->cs_line);
+ 
+ 		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
+-	}
++		break;
+ 
++	case ATH79_SPI_CS_TYPE_GPIO:
++		/* SPI is normally active-low */
++		if (gpio_cansleep(cdata->cs_line))
++			gpio_set_value_cansleep(cdata->cs_line, cs_high);
++		else
++			gpio_set_value(cdata->cs_line, cs_high);
++		break;
++	}
+ }
+ 
+ static void ath79_spi_enable(struct ath79_spi *sp)
+@@ -120,24 +127,30 @@ static void ath79_spi_disable(struct ath
+ static int ath79_spi_setup_cs(struct spi_device *spi)
+ {
+ 	struct ath79_spi_controller_data *cdata;
++	unsigned long flags;
+ 	int status;
+ 
+ 	cdata = spi->controller_data;
+-	if (spi->chip_select && !cdata)
++	if (!cdata)
+ 		return -EINVAL;
+ 
+ 	status = 0;
+-	if (spi->chip_select) {
+-		unsigned long flags;
++	switch (cdata->cs_type) {
++	case ATH79_SPI_CS_TYPE_INTERNAL:
++		if (cdata->cs_line > ATH79_SPI_CS_LINE_MAX)
++			status = -EINVAL;
++		break;
+ 
++	case ATH79_SPI_CS_TYPE_GPIO:
+ 		flags = GPIOF_DIR_OUT;
+ 		if (spi->mode & SPI_CS_HIGH)
+ 			flags |= GPIOF_INIT_HIGH;
+ 		else
+ 			flags |= GPIOF_INIT_LOW;
+ 
+-		status = gpio_request_one(cdata->gpio, flags,
++		status = gpio_request_one(cdata->cs_line, flags,
+ 					  dev_name(&spi->dev));
++		break;
+ 	}
+ 
+ 	return status;
+@@ -145,9 +158,19 @@ static int ath79_spi_setup_cs(struct spi
+ 
+ static void ath79_spi_cleanup_cs(struct spi_device *spi)
+ {
+-	if (spi->chip_select) {
+-		struct ath79_spi_controller_data *cdata = spi->controller_data;
+-		gpio_free(cdata->gpio);
++	struct ath79_spi_controller_data *cdata;
++
++	cdata = spi->controller_data;
++	if (!cdata)
++		return;
++
++	switch (cdata->cs_type) {
++	case ATH79_SPI_CS_TYPE_INTERNAL:
++		/* nothing to do */
++		break;
++	case ATH79_SPI_CS_TYPE_GPIO:
++		gpio_free(cdata->cs_line);
++		break;
+ 	}
+ }
+ 
+@@ -155,6 +178,9 @@ static int ath79_spi_setup(struct spi_de
+ {
+ 	int status = 0;
+ 
++	if (spi->controller_data == NULL)
++		return -EINVAL;
++
+ 	if (spi->bits_per_word > 32)
+ 		return -EINVAL;
+ 
+@@ -215,6 +241,10 @@ static int ath79_spi_probe(struct platfo
+ 	unsigned long rate;
+ 	int ret;
+ 
++	pdata = pdev->dev.platform_data;
++	if (!pdata)
++		return -EINVAL;
++
+ 	master = spi_alloc_master(&pdev->dev, sizeof(*sp));
+ 	if (master == NULL) {
+ 		dev_err(&pdev->dev, "failed to allocate spi master\n");
+@@ -224,14 +254,10 @@ static int ath79_spi_probe(struct platfo
+ 	sp = spi_master_get_devdata(master);
+ 	platform_set_drvdata(pdev, sp);
+ 
+-	pdata = pdev->dev.platform_data;
+-
+ 	master->setup = ath79_spi_setup;
+ 	master->cleanup = ath79_spi_cleanup;
+-	if (pdata) {
+-		master->bus_num = pdata->bus_num;
+-		master->num_chipselect = pdata->num_chipselect;
+-	}
++	master->bus_num = pdata->bus_num;
++	master->num_chipselect = pdata->num_chipselect;
+ 
+ 	sp->bitbang.master = spi_master_get(master);
+ 	sp->bitbang.chipselect = ath79_spi_chipselect;
diff --git a/target/linux/ar71xx/patches-3.8/213-MIPS-ath79-fix-ar933x-wmac-reset.patch b/target/linux/ar71xx/patches-3.8/213-MIPS-ath79-fix-ar933x-wmac-reset.patch
new file mode 100644
index 0000000..e0821a7
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/213-MIPS-ath79-fix-ar933x-wmac-reset.patch
@@ -0,0 +1,31 @@
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -62,10 +62,27 @@ static void __init ar913x_wmac_setup(voi
+ 
+ static int ar933x_wmac_reset(void)
+ {
++	int retries = 20;
++
+ 	ath79_device_reset_set(AR933X_RESET_WMAC);
+ 	ath79_device_reset_clear(AR933X_RESET_WMAC);
+ 
+-	return 0;
++	while (1) {
++		u32 bootstrap;
++
++		bootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
++		if ((bootstrap & AR933X_BOOTSTRAP_EEPBUSY) == 0)
++			return 0;
++
++		if (retries-- == 0)
++			break;
++
++		udelay(10000);
++		retries++;
++	}
++
++	pr_err("ar933x: WMAC reset timed out");
++	return -ETIMEDOUT;
+ }
+ 
+ static int ar933x_r1_get_wmac_revision(void)
diff --git a/target/linux/ar71xx/patches-3.8/220-add_cpu_feature_overrides.patch b/target/linux/ar71xx/patches-3.8/220-add_cpu_feature_overrides.patch
new file mode 100644
index 0000000..05406f2
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/220-add_cpu_feature_overrides.patch
@@ -0,0 +1,28 @@
+--- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
++++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
+@@ -36,6 +36,7 @@
+ #define cpu_has_mdmx		0
+ #define cpu_has_mips3d		0
+ #define cpu_has_smartmips	0
++#define cpu_has_rixi		0
+ 
+ #define cpu_has_mips32r1	1
+ #define cpu_has_mips32r2	1
+@@ -45,6 +46,7 @@
+ #define cpu_has_dsp		0
+ #define cpu_has_dsp2		0
+ #define cpu_has_mipsmt		0
++#define cpu_has_userlocal	0
+ 
+ #define cpu_has_64bits		0
+ #define cpu_has_64bit_zero_reg	0
+@@ -53,5 +55,9 @@
+ 
+ #define cpu_dcache_line_size()	32
+ #define cpu_icache_line_size()	32
++#define cpu_has_vtag_icache	0
++#define cpu_has_dc_aliases	1
++#define cpu_has_ic_fills_f_dc	0
++#define cpu_has_pindexed_dcache	0
+ 
+ #endif /* __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H */
diff --git a/target/linux/ar71xx/patches-3.8/310-lib-add-rle-decompression.patch b/target/linux/ar71xx/patches-3.8/310-lib-add-rle-decompression.patch
new file mode 100644
index 0000000..d81fdd8
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/310-lib-add-rle-decompression.patch
@@ -0,0 +1,114 @@
+--- a/lib/Kconfig
++++ b/lib/Kconfig
+@@ -197,6 +197,9 @@ config LZMA_COMPRESS
+ config LZMA_DECOMPRESS
+     tristate
+ 
++config RLE_DECOMPRESS
++	tristate
++
+ #
+ # These all provide a common interface (hence the apparent duplication with
+ # ZLIB_INFLATE; DECOMPRESS_GZIP is just a wrapper.)
+--- a/lib/Makefile
++++ b/lib/Makefile
+@@ -86,6 +86,7 @@ obj-$(CONFIG_XZ_DEC) += xz/
+ obj-$(CONFIG_RAID6_PQ) += raid6/
+ obj-$(CONFIG_LZMA_COMPRESS) += lzma/
+ obj-$(CONFIG_LZMA_DECOMPRESS) += lzma/
++obj-$(CONFIG_RLE_DECOMPRESS) += rle.o
+ 
+ lib-$(CONFIG_DECOMPRESS_GZIP) += decompress_inflate.o
+ lib-$(CONFIG_DECOMPRESS_BZIP2) += decompress_bunzip2.o
+--- /dev/null
++++ b/include/linux/rle.h
+@@ -0,0 +1,8 @@
++#ifndef _RLE_H_
++#define _RLE_H_
++
++int rle_decode(const unsigned char *src, size_t srclen,
++	       unsigned char *dst, size_t dstlen,
++	       size_t *src_done, size_t *dst_done);
++
++#endif /* _RLE_H_ */
+--- /dev/null
++++ b/lib/rle.c
+@@ -0,0 +1,78 @@
++/*
++ *  RLE decoding routine
++ *
++ *  Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/rle.h>
++
++int rle_decode(const unsigned char *src, size_t srclen,
++	       unsigned char *dst, size_t dstlen,
++	       size_t *src_done, size_t *dst_done)
++{
++	size_t srcpos, dstpos;
++	int ret;
++
++	srcpos = 0;
++	dstpos = 0;
++	ret = -EINVAL;
++
++	/* sanity checks */
++	if (!src || !srclen || !dst || !dstlen)
++		goto out;
++
++	while (1) {
++		char count;
++
++		if (srcpos >= srclen)
++			break;
++
++		count = (char) src[srcpos++];
++		if (count == 0) {
++			ret = 0;
++			break;
++		}
++
++		if (count > 0) {
++			unsigned char c;
++
++			if (srcpos >= srclen)
++				break;
++
++			c = src[srcpos++];
++
++			while (count--) {
++				if (dstpos >= dstlen)
++					break;
++
++				dst[dstpos++] = c;
++			}
++		} else {
++			count *= -1;
++
++			while (count--) {
++				if (srcpos >= srclen)
++					break;
++				if (dstpos >= dstlen)
++					break;
++				dst[dstpos++] = src[srcpos++];
++			}
++		}
++	}
++
++out:
++	if (src_done)
++		*src_done = srcpos;
++	if (dst_done)
++		*dst_done = dstpos;
++
++	return ret;
++}
++
++EXPORT_SYMBOL_GPL(rle_decode);
diff --git a/target/linux/ar71xx/patches-3.8/401-mtd-physmap-add-lock-unlock.patch b/target/linux/ar71xx/patches-3.8/401-mtd-physmap-add-lock-unlock.patch
new file mode 100644
index 0000000..ead7685
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/401-mtd-physmap-add-lock-unlock.patch
@@ -0,0 +1,94 @@
+--- a/drivers/mtd/maps/physmap.c
++++ b/drivers/mtd/maps/physmap.c
+@@ -31,6 +31,66 @@ struct physmap_flash_info {
+ 	int			vpp_refcnt;
+ };
+ 
++static struct platform_device *physmap_map2pdev(struct map_info *map)
++{
++	return (struct platform_device *) map->map_priv_1;
++}
++
++static void physmap_lock(struct map_info *map)
++{
++	struct platform_device *pdev;
++	struct physmap_flash_data *physmap_data;
++
++	pdev = physmap_map2pdev(map);
++	physmap_data = pdev->dev.platform_data;
++	physmap_data->lock(pdev);
++}
++
++static void physmap_unlock(struct map_info *map)
++{
++	struct platform_device *pdev;
++	struct physmap_flash_data *physmap_data;
++
++	pdev = physmap_map2pdev(map);
++	physmap_data = pdev->dev.platform_data;
++	physmap_data->unlock(pdev);
++}
++
++static map_word physmap_flash_read_lock(struct map_info *map, unsigned long ofs)
++{
++	map_word ret;
++
++	physmap_lock(map);
++	ret = inline_map_read(map, ofs);
++	physmap_unlock(map);
++
++	return ret;
++}
++
++static void physmap_flash_write_lock(struct map_info *map, map_word d,
++				     unsigned long ofs)
++{
++	physmap_lock(map);
++	inline_map_write(map, d, ofs);
++	physmap_unlock(map);
++}
++
++static void physmap_flash_copy_from_lock(struct map_info *map, void *to,
++					 unsigned long from, ssize_t len)
++{
++	physmap_lock(map);
++	inline_map_copy_from(map, to, from, len);
++	physmap_unlock(map);
++}
++
++static void physmap_flash_copy_to_lock(struct map_info *map, unsigned long to,
++				       const void *from, ssize_t len)
++{
++	physmap_lock(map);
++	inline_map_copy_to(map, to, from, len);
++	physmap_unlock(map);
++}
++
+ static int physmap_flash_remove(struct platform_device *dev)
+ {
+ 	struct physmap_flash_info *info;
+@@ -157,6 +217,13 @@ static int physmap_flash_probe(struct pl
+ 
+ 		simple_map_init(&info->map[i]);
+ 
++		if (physmap_data->lock && physmap_data->unlock) {
++			info->map[i].read = physmap_flash_read_lock;
++			info->map[i].write = physmap_flash_write_lock;
++			info->map[i].copy_from = physmap_flash_copy_from_lock;
++			info->map[i].copy_to = physmap_flash_copy_to_lock;
++		}
++
+ 		probe_type = rom_probe_types;
+ 		if (physmap_data->probe_type == NULL) {
+ 			for (; info->mtd[i] == NULL && *probe_type != NULL; probe_type++)
+--- a/include/linux/mtd/physmap.h
++++ b/include/linux/mtd/physmap.h
+@@ -26,6 +26,8 @@ struct physmap_flash_data {
+ 	unsigned int		width;
+ 	int			(*init)(struct platform_device *);
+ 	void			(*exit)(struct platform_device *);
++	void			(*lock)(struct platform_device *);
++	void			(*unlock)(struct platform_device *);
+ 	void			(*set_vpp)(struct platform_device *, int);
+ 	unsigned int		nr_parts;
+ 	unsigned int		pfow_base;
diff --git a/target/linux/ar71xx/patches-3.8/402-mtd-SST39VF6401B-support.patch b/target/linux/ar71xx/patches-3.8/402-mtd-SST39VF6401B-support.patch
new file mode 100644
index 0000000..246abd5
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/402-mtd-SST39VF6401B-support.patch
@@ -0,0 +1,29 @@
+--- a/drivers/mtd/chips/jedec_probe.c
++++ b/drivers/mtd/chips/jedec_probe.c
+@@ -148,6 +148,7 @@
+ #define SST39LF160	0x2782
+ #define SST39VF1601	0x234b
+ #define SST39VF3201	0x235b
++#define SST39VF6401B	0x236d
+ #define SST39WF1601	0x274b
+ #define SST39WF1602	0x274a
+ #define SST39LF512	0x00D4
+@@ -1568,6 +1569,18 @@ static const struct amd_flash_info jedec
+ 			ERASEINFO(0x10000,64),
+ 		}
+ 	}, {
++		.mfr_id         = CFI_MFR_SST,
++		.dev_id         = SST39VF6401B,
++		.name           = "SST 39VF6401B",
++		.devtypes       = CFI_DEVICETYPE_X16,
++		.uaddr          = MTD_UADDR_0xAAAA_0x5555,
++		.dev_size       = SIZE_8MiB,
++		.cmd_set        = P_ID_AMD_STD,
++		.nr_regions     = 1,
++		.regions        = {
++			ERASEINFO(0x10000,128)
++		}
++	}, {
+ 		.mfr_id		= CFI_MFR_ST,
+ 		.dev_id		= M29F800AB,
+ 		.name		= "ST M29F800AB",
diff --git a/target/linux/ar71xx/patches-3.8/403-mtd_fix_cfi_cmdset_0002_status_check.patch b/target/linux/ar71xx/patches-3.8/403-mtd_fix_cfi_cmdset_0002_status_check.patch
new file mode 100644
index 0000000..e569fe1
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/403-mtd_fix_cfi_cmdset_0002_status_check.patch
@@ -0,0 +1,69 @@
+--- a/drivers/mtd/chips/cfi_cmdset_0002.c
++++ b/drivers/mtd/chips/cfi_cmdset_0002.c
+@@ -1288,8 +1288,8 @@ static int __xipram do_write_oneword(str
+ 			break;
+ 		}
+ 
+-		if (chip_ready(map, adr))
+-			break;
++		if (chip_good(map, adr, datum))
++			goto enable_xip;
+ 
+ 		/* Latency issues. Drop the lock, wait a while and retry */
+ 		UDELAY(map, chip, adr, 1);
+@@ -1305,6 +1305,8 @@ static int __xipram do_write_oneword(str
+ 
+ 		ret = -EIO;
+ 	}
++
++ enable_xip:
+ 	xip_enable(map, chip, adr);
+  op_done:
+ 	chip->state = FL_READY;
+@@ -1875,7 +1877,6 @@ static int cfi_amdstd_panic_write(struct
+ 	return 0;
+ }
+ 
+-
+ /*
+  * Handle devices with one erase region, that only implement
+  * the chip erase command.
+@@ -1939,8 +1940,8 @@ static int __xipram do_erase_chip(struct
+ 			chip->erase_suspended = 0;
+ 		}
+ 
+-		if (chip_ready(map, adr))
+-			break;
++		if (chip_good(map, adr, map_word_ff(map)))
++			goto op_done;
+ 
+ 		if (time_after(jiffies, timeo)) {
+ 			printk(KERN_WARNING "MTD %s(): software timeout\n",
+@@ -1960,6 +1961,7 @@ static int __xipram do_erase_chip(struct
+ 		ret = -EIO;
+ 	}
+ 
++ op_done:
+ 	chip->state = FL_READY;
+ 	xip_enable(map, chip, adr);
+ 	DISABLE_VPP(map);
+@@ -2028,9 +2030,9 @@ static int __xipram do_erase_oneblock(st
+ 			chip->erase_suspended = 0;
+ 		}
+ 
+-		if (chip_ready(map, adr)) {
++		if (chip_good(map, adr, map_word_ff(map))) {
+ 			xip_enable(map, chip, adr);
+-			break;
++			goto op_done;
+ 		}
+ 
+ 		if (time_after(jiffies, timeo)) {
+@@ -2052,6 +2054,7 @@ static int __xipram do_erase_oneblock(st
+ 		ret = -EIO;
+ 	}
+ 
++ op_done:
+ 	chip->state = FL_READY;
+ 	DISABLE_VPP(map);
+ 	put_chip(map, chip, adr);
diff --git a/target/linux/ar71xx/patches-3.8/404-mtd-wrt160nl-trx-parser.patch b/target/linux/ar71xx/patches-3.8/404-mtd-wrt160nl-trx-parser.patch
new file mode 100644
index 0000000..71798c4
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/404-mtd-wrt160nl-trx-parser.patch
@@ -0,0 +1,25 @@
+--- a/drivers/mtd/Kconfig
++++ b/drivers/mtd/Kconfig
+@@ -163,6 +163,12 @@ config MTD_BCM47XX_PARTS
+ 	  This provides partitions parser for devices based on BCM47xx
+ 	  boards.
+ 
++config MTD_WRT160NL_PARTS
++	tristate "Linksys WRT160NL partitioning support"
++	depends on MTD_PARTITIONS && ATH79_MACH_WRT160NL
++	---help---
++	   Linksys WRT160NL partitioning support
++
+ config MTD_MYLOADER_PARTS
+ 	tristate "MyLoader partition parsing"
+ 	depends on ADM5120 || ATHEROS_AR231X || ATHEROS_AR71XX || ATH79
+--- a/drivers/mtd/Makefile
++++ b/drivers/mtd/Makefile
+@@ -14,6 +14,7 @@ obj-$(CONFIG_MTD_AR7_PARTS)	+= ar7part.o
+ obj-$(CONFIG_MTD_BCM63XX_PARTS)	+= bcm63xxpart.o
+ obj-$(CONFIG_MTD_BCM47XX_PARTS)	+= bcm47xxpart.o
+ obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o
++obj-$(CONFIG_MTD_WRT160NL_PARTS) += wrt160nl_part.o
+ 
+ # 'Users' - code which presents functionality to userspace.
+ obj-$(CONFIG_MTD_CHAR)		+= mtdchar.o
diff --git a/target/linux/ar71xx/patches-3.8/405-mtd-tp-link-partition-parser.patch b/target/linux/ar71xx/patches-3.8/405-mtd-tp-link-partition-parser.patch
new file mode 100644
index 0000000..45676ec
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/405-mtd-tp-link-partition-parser.patch
@@ -0,0 +1,34 @@
+--- a/drivers/mtd/Kconfig
++++ b/drivers/mtd/Kconfig
+@@ -165,7 +165,7 @@ config MTD_BCM47XX_PARTS
+ 
+ config MTD_WRT160NL_PARTS
+ 	tristate "Linksys WRT160NL partitioning support"
+-	depends on MTD_PARTITIONS && ATH79_MACH_WRT160NL
++	depends on ATH79_MACH_WRT160NL
+ 	---help---
+ 	   Linksys WRT160NL partitioning support
+ 
+@@ -185,6 +185,12 @@ config MTD_MYLOADER_PARTS
+ 	  You will still need the parsing functions to be called by the driver
+ 	  for your particular device. It won't happen automatically.
+ 
++config MTD_TPLINK_PARTS
++	tristate "TP-Link AR7XXX/AR9XXX partitioning support"
++	depends on ATH79
++	---help---
++	  TBD.
++
+ comment "User Modules And Translation Layers"
+ 
+ config MTD_CHAR
+--- a/drivers/mtd/Makefile
++++ b/drivers/mtd/Makefile
+@@ -14,6 +14,7 @@ obj-$(CONFIG_MTD_AR7_PARTS)	+= ar7part.o
+ obj-$(CONFIG_MTD_BCM63XX_PARTS)	+= bcm63xxpart.o
+ obj-$(CONFIG_MTD_BCM47XX_PARTS)	+= bcm47xxpart.o
+ obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o
++obj-$(CONFIG_MTD_TPLINK_PARTS)	+= tplinkpart.o
+ obj-$(CONFIG_MTD_WRT160NL_PARTS) += wrt160nl_part.o
+ 
+ # 'Users' - code which presents functionality to userspace.
diff --git a/target/linux/ar71xx/patches-3.8/406-mtd-m25p80-allow-to-specify-max-read-size.patch b/target/linux/ar71xx/patches-3.8/406-mtd-m25p80-allow-to-specify-max-read-size.patch
new file mode 100644
index 0000000..be308c6
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/406-mtd-m25p80-allow-to-specify-max-read-size.patch
@@ -0,0 +1,109 @@
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -93,6 +93,7 @@ struct m25p {
+ 	u8			erase_opcode;
+ 	u8			*command;
+ 	bool			fast_read;
++	size_t			max_read_len;
+ };
+ 
+ static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
+@@ -344,6 +345,7 @@ static int m25p80_read(struct mtd_info *
+ 	struct spi_transfer t[2];
+ 	struct spi_message m;
+ 	uint8_t opcode;
++	loff_t ofs;
+ 
+ 	pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
+ 			__func__, (u32)from, len);
+@@ -359,19 +361,10 @@ static int m25p80_read(struct mtd_info *
+ 	t[0].len = m25p_cmdsz(flash) + (flash->fast_read ? 1 : 0);
+ 	spi_message_add_tail(&t[0], &m);
+ 
+-	t[1].rx_buf = buf;
+-	t[1].len = len;
+ 	spi_message_add_tail(&t[1], &m);
+ 
+ 	mutex_lock(&flash->lock);
+ 
+-	/* Wait till previous write/erase is done. */
+-	if (wait_till_ready(flash)) {
+-		/* REVISIT status return?? */
+-		mutex_unlock(&flash->lock);
+-		return 1;
+-	}
+-
+ 	/* FIXME switch to OPCODE_FAST_READ.  It's required for higher
+ 	 * clocks; and at this writing, every chip this driver handles
+ 	 * supports that opcode.
+@@ -380,13 +373,43 @@ static int m25p80_read(struct mtd_info *
+ 	/* Set up the write data buffer. */
+ 	opcode = flash->fast_read ? OPCODE_FAST_READ : OPCODE_NORM_READ;
+ 	flash->command[0] = opcode;
+-	m25p_addr2cmd(flash, from, flash->command);
++	ofs = 0;
++	while (len) {
++		size_t readlen;
++		size_t done;
++		int ret;
++
++		ret = wait_till_ready(flash);
++		if (ret) {
++			mutex_unlock(&flash->lock);
++			return 1;
++		}
++
++		if (flash->max_read_len > 0 &&
++		    flash->max_read_len < len)
++			readlen = flash->max_read_len;
++		else
++			readlen = len;
++
++		t[1].rx_buf = buf + ofs;
++		t[1].len = readlen;
++
++		m25p_addr2cmd(flash, from + ofs, flash->command);
++
++		spi_sync(flash->spi, &m);
+ 
+-	spi_sync(flash->spi, &m);
++		done = m.actual_length - m25p_cmdsz(flash) -
++		       (flash->fast_read ? 1 : 0);
++		if (done != readlen) {
++			mutex_unlock(&flash->lock);
++			return 1;
++		}
+ 
+-	*retlen = m.actual_length - m25p_cmdsz(flash) -
+-			(flash->fast_read ? 1 : 0);
++		ofs += done;
++		len -= done;
++	}
+ 
++	*retlen = ofs;
+ 	mutex_unlock(&flash->lock);
+ 
+ 	return 0;
+@@ -916,6 +939,12 @@ static int m25p_probe(struct spi_device
+ 	flash->mtd._erase = m25p80_erase;
+ 	flash->mtd._read = m25p80_read;
+ 
++	if (data && data->max_read_len) {
++		flash->max_read_len = data->max_read_len;
++		dev_warn(&spi->dev, "max_read_len set to %d bytes\n",
++			flash->max_read_len);
++	}
++
+ 	/* sst flash chips use AAI word program */
+ 	if (JEDEC_MFR(info->jedec_id) == CFI_MFR_SST)
+ 		flash->mtd._write = sst_write;
+--- a/include/linux/spi/flash.h
++++ b/include/linux/spi/flash.h
+@@ -25,6 +25,7 @@ struct flash_platform_data {
+ 
+ 	char		*type;
+ 
++	size_t		max_read_len;
+ 	/* we'll likely add more ... use JEDEC IDs, etc */
+ };
+ 
diff --git a/target/linux/ar71xx/patches-3.8/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch b/target/linux/ar71xx/patches-3.8/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch
new file mode 100644
index 0000000..db0a542
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch
@@ -0,0 +1,23 @@
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -1016,7 +1016,9 @@ static int m25p_probe(struct spi_device
+ 	/* partitions should match sector boundaries; and it may be good to
+ 	 * use readonly partitions for writeprotected sectors (BP2..BP0).
+ 	 */
+-	return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
++	return mtd_device_parse_register(&flash->mtd,
++			data ? data->part_probes : NULL,
++			&ppdata,
+ 			data ? data->parts : NULL,
+ 			data ? data->nr_parts : 0);
+ }
+--- a/include/linux/spi/flash.h
++++ b/include/linux/spi/flash.h
+@@ -24,6 +24,7 @@ struct flash_platform_data {
+ 	unsigned int	nr_parts;
+ 
+ 	char		*type;
++	const char	**part_probes;
+ 
+ 	size_t		max_read_len;
+ 	/* we'll likely add more ... use JEDEC IDs, etc */
diff --git a/target/linux/ar71xx/patches-3.8/408-mtd-redboot_partition_scan.patch b/target/linux/ar71xx/patches-3.8/408-mtd-redboot_partition_scan.patch
new file mode 100644
index 0000000..cd41e7c
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/408-mtd-redboot_partition_scan.patch
@@ -0,0 +1,44 @@
+--- a/drivers/mtd/redboot.c
++++ b/drivers/mtd/redboot.c
+@@ -76,12 +76,18 @@ static int parse_redboot_partitions(stru
+ 	static char nullstring[] = "unallocated";
+ #endif
+ 
++	buf = vmalloc(master->erasesize);
++	if (!buf)
++		return -ENOMEM;
++
++ restart:
+ 	if ( directory < 0 ) {
+ 		offset = master->size + directory * master->erasesize;
+ 		while (mtd_block_isbad(master, offset)) {
+ 			if (!offset) {
+ 			nogood:
+ 				printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n");
++				vfree(buf);
+ 				return -EIO;
+ 			}
+ 			offset -= master->erasesize;
+@@ -94,10 +100,6 @@ static int parse_redboot_partitions(stru
+ 				goto nogood;
+ 		}
+ 	}
+-	buf = vmalloc(master->erasesize);
+-
+-	if (!buf)
+-		return -ENOMEM;
+ 
+ 	printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n",
+ 	       master->name, offset);
+@@ -170,6 +172,11 @@ static int parse_redboot_partitions(stru
+ 	}
+ 	if (i == numslots) {
+ 		/* Didn't find it */
++		if (offset + master->erasesize < master->size) {
++			/* not at the end of the flash yet, maybe next block :) */
++			directory++;
++			goto restart;
++		}
+ 		printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
+ 		       master->name);
+ 		ret = 0;
diff --git a/target/linux/ar71xx/patches-3.8/409-mtd-rb4xx_nand_driver.patch b/target/linux/ar71xx/patches-3.8/409-mtd-rb4xx_nand_driver.patch
new file mode 100644
index 0000000..082df87
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/409-mtd-rb4xx_nand_driver.patch
@@ -0,0 +1,21 @@
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -575,4 +575,8 @@ config MTD_NAND_XWAY
+ 	  Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
+ 	  to the External Bus Unit (EBU).
+ 
++config MTD_NAND_RB4XX
++	tristate "NAND flash driver for RouterBoard 4xx series"
++	depends on MTD_NAND && ATH79_MACH_RB4XX
++
+ endif # MTD_NAND
+--- a/drivers/mtd/nand/Makefile
++++ b/drivers/mtd/nand/Makefile
+@@ -34,6 +34,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270)		+= cmx27
+ obj-$(CONFIG_MTD_NAND_PXA3xx)		+= pxa3xx_nand.o
+ obj-$(CONFIG_MTD_NAND_TMIO)		+= tmio_nand.o
+ obj-$(CONFIG_MTD_NAND_PLATFORM)		+= plat_nand.o
++obj-$(CONFIG_MTD_NAND_RB4XX)		+= rb4xx_nand.o
+ obj-$(CONFIG_MTD_ALAUDA)		+= alauda.o
+ obj-$(CONFIG_MTD_NAND_PASEMI)		+= pasemi_nand.o
+ obj-$(CONFIG_MTD_NAND_ORION)		+= orion_nand.o
diff --git a/target/linux/ar71xx/patches-3.8/410-mtd-rb750-nand-driver.patch b/target/linux/ar71xx/patches-3.8/410-mtd-rb750-nand-driver.patch
new file mode 100644
index 0000000..1247866
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/410-mtd-rb750-nand-driver.patch
@@ -0,0 +1,21 @@
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -579,4 +579,8 @@ config MTD_NAND_RB4XX
+ 	tristate "NAND flash driver for RouterBoard 4xx series"
+ 	depends on MTD_NAND && ATH79_MACH_RB4XX
+ 
++config MTD_NAND_RB750
++	tristate "NAND flash driver for the RouterBoard 750"
++	depends on MTD_NAND && ATH79_MACH_RB750
++
+ endif # MTD_NAND
+--- a/drivers/mtd/nand/Makefile
++++ b/drivers/mtd/nand/Makefile
+@@ -35,6 +35,7 @@ obj-$(CONFIG_MTD_NAND_PXA3xx)		+= pxa3xx
+ obj-$(CONFIG_MTD_NAND_TMIO)		+= tmio_nand.o
+ obj-$(CONFIG_MTD_NAND_PLATFORM)		+= plat_nand.o
+ obj-$(CONFIG_MTD_NAND_RB4XX)		+= rb4xx_nand.o
++obj-$(CONFIG_MTD_NAND_RB750)		+= rb750_nand.o
+ obj-$(CONFIG_MTD_ALAUDA)		+= alauda.o
+ obj-$(CONFIG_MTD_NAND_PASEMI)		+= pasemi_nand.o
+ obj-$(CONFIG_MTD_NAND_ORION)		+= orion_nand.o
diff --git a/target/linux/ar71xx/patches-3.8/411-mtd-cfi_cmdset_0002-force-word-write.patch b/target/linux/ar71xx/patches-3.8/411-mtd-cfi_cmdset_0002-force-word-write.patch
new file mode 100644
index 0000000..2d8e6e6
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/411-mtd-cfi_cmdset_0002-force-word-write.patch
@@ -0,0 +1,61 @@
+--- a/drivers/mtd/chips/cfi_cmdset_0002.c
++++ b/drivers/mtd/chips/cfi_cmdset_0002.c
+@@ -39,7 +39,7 @@
+ #include <linux/mtd/xip.h>
+ 
+ #define AMD_BOOTLOC_BUG
+-#define FORCE_WORD_WRITE 0
++#define FORCE_WORD_WRITE 1
+ 
+ #define MAX_WORD_RETRIES 3
+ 
+@@ -50,7 +50,9 @@
+ 
+ static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
+ static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
++#if !FORCE_WORD_WRITE
+ static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
++#endif
+ static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
+ static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
+ static void cfi_amdstd_sync (struct mtd_info *);
+@@ -186,6 +188,7 @@ static void fixup_amd_bootblock(struct m
+ }
+ #endif
+ 
++#if !FORCE_WORD_WRITE
+ static void fixup_use_write_buffers(struct mtd_info *mtd)
+ {
+ 	struct map_info *map = mtd->priv;
+@@ -195,6 +198,7 @@ static void fixup_use_write_buffers(stru
+ 		mtd->_write = cfi_amdstd_write_buffers;
+ 	}
+ }
++#endif /* !FORCE_WORD_WRITE */
+ 
+ /* Atmel chips don't use the same PRI format as AMD chips */
+ static void fixup_convert_atmel_pri(struct mtd_info *mtd)
+@@ -1445,6 +1449,7 @@ static int cfi_amdstd_write_words(struct
+ /*
+  * FIXME: interleaved mode not tested, and probably not supported!
+  */
++#if !FORCE_WORD_WRITE
+ static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
+ 				    unsigned long adr, const u_char *buf,
+ 				    int len)
+@@ -1569,7 +1574,6 @@ static int __xipram do_write_buffer(stru
+ 	return ret;
+ }
+ 
+-
+ static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
+ 				    size_t *retlen, const u_char *buf)
+ {
+@@ -1644,6 +1648,7 @@ static int cfi_amdstd_write_buffers(stru
+ 
+ 	return 0;
+ }
++#endif /* !FORCE_WORD_WRITE */
+ 
+ /*
+  * Wait for the flash chip to become ready to write data
diff --git a/target/linux/ar71xx/patches-3.8/412-mtd-m25p80-zero-partition-parser-data.patch b/target/linux/ar71xx/patches-3.8/412-mtd-m25p80-zero-partition-parser-data.patch
new file mode 100644
index 0000000..e9beb6b
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/412-mtd-m25p80-zero-partition-parser-data.patch
@@ -0,0 +1,10 @@
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -966,6 +966,7 @@ static int m25p_probe(struct spi_device
+ 	if (info->flags & M25P_NO_ERASE)
+ 		flash->mtd.flags |= MTD_NO_ERASE;
+ 
++	memset(&ppdata, '\0', sizeof(ppdata));
+ 	ppdata.of_node = spi->dev.of_node;
+ 	flash->mtd.dev.parent = &spi->dev;
+ 	flash->page_size = info->page_size;
diff --git a/target/linux/ar71xx/patches-3.8/413-mtd-ar934x-nand-driver.patch b/target/linux/ar71xx/patches-3.8/413-mtd-ar934x-nand-driver.patch
new file mode 100644
index 0000000..f8362cb
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/413-mtd-ar934x-nand-driver.patch
@@ -0,0 +1,21 @@
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -583,4 +583,8 @@ config MTD_NAND_RB750
+ 	tristate "NAND flash driver for the RouterBoard 750"
+ 	depends on MTD_NAND && ATH79_MACH_RB750
+ 
++config MTD_NAND_AR934X
++	tristate "NAND flash driver for the Qualcomm Atheros AR934x/QCA955x SoCs"
++	depends on (SOC_AR934X || SOC_QCA955X)
++
+ endif # MTD_NAND
+--- a/drivers/mtd/nand/Makefile
++++ b/drivers/mtd/nand/Makefile
+@@ -13,6 +13,7 @@ obj-$(CONFIG_MTD_NAND_AMS_DELTA)	+= ams-
+ obj-$(CONFIG_MTD_NAND_DENALI)		+= denali.o
+ obj-$(CONFIG_MTD_NAND_DENALI_PCI)	+= denali_pci.o
+ obj-$(CONFIG_MTD_NAND_DENALI_DT)	+= denali_dt.o
++obj-$(CONFIG_MTD_NAND_AR934X)		+= ar934x_nfc.o
+ obj-$(CONFIG_MTD_NAND_AU1550)		+= au1550nd.o
+ obj-$(CONFIG_MTD_NAND_BF5XX)		+= bf5xx_nand.o
+ obj-$(CONFIG_MTD_NAND_PPCHAMELEONEVB)	+= ppchameleonevb.o
diff --git a/target/linux/ar71xx/patches-3.8/420-net-ar71xx_mac_driver.patch b/target/linux/ar71xx/patches-3.8/420-net-ar71xx_mac_driver.patch
new file mode 100644
index 0000000..f117133
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/420-net-ar71xx_mac_driver.patch
@@ -0,0 +1,28 @@
+--- a/drivers/net/ethernet/atheros/Kconfig
++++ b/drivers/net/ethernet/atheros/Kconfig
+@@ -5,7 +5,7 @@
+ config NET_VENDOR_ATHEROS
+ 	bool "Atheros devices"
+ 	default y
+-	depends on PCI
++	depends on (PCI || ATH79)
+ 	---help---
+ 	  If you have a network (Ethernet) card belonging to this class, say Y
+ 	  and read the Ethernet-HOWTO, available from
+@@ -67,4 +67,6 @@ config ATL1C
+ 	  To compile this driver as a module, choose M here.  The module
+ 	  will be called atl1c.
+ 
++source drivers/net/ethernet/atheros/ag71xx/Kconfig
++
+ endif # NET_VENDOR_ATHEROS
+--- a/drivers/net/ethernet/atheros/Makefile
++++ b/drivers/net/ethernet/atheros/Makefile
+@@ -2,6 +2,7 @@
+ # Makefile for the Atheros network device drivers.
+ #
+ 
++obj-$(CONFIG_AG71XX) += ag71xx/
+ obj-$(CONFIG_ATL1) += atlx/
+ obj-$(CONFIG_ATL2) += atlx/
+ obj-$(CONFIG_ATL1E) += atl1e/
diff --git a/target/linux/ar71xx/patches-3.8/422-dsa-trailer-tag-validation-fix.patch b/target/linux/ar71xx/patches-3.8/422-dsa-trailer-tag-validation-fix.patch
new file mode 100644
index 0000000..3e3902b
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/422-dsa-trailer-tag-validation-fix.patch
@@ -0,0 +1,11 @@
+--- a/net/dsa/tag_trailer.c
++++ b/net/dsa/tag_trailer.c
+@@ -87,7 +87,7 @@ static int trailer_rcv(struct sk_buff *s
+ 
+ 	trailer = skb_tail_pointer(skb) - 4;
+ 	if (trailer[0] != 0x80 || (trailer[1] & 0xf8) != 0x00 ||
+-	    (trailer[3] & 0xef) != 0x00 || trailer[3] != 0x00)
++	    (trailer[2] & 0xef) != 0x00 || (trailer[3] & 0xfe) != 0x00)
+ 		goto out_drop;
+ 
+ 	source_port = trailer[1] & 7;
diff --git a/target/linux/ar71xx/patches-3.8/423-dsa-add-88e6063-driver.patch b/target/linux/ar71xx/patches-3.8/423-dsa-add-88e6063-driver.patch
new file mode 100644
index 0000000..1348cd9
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/423-dsa-add-88e6063-driver.patch
@@ -0,0 +1,24 @@
+--- a/drivers/net/dsa/Kconfig
++++ b/drivers/net/dsa/Kconfig
+@@ -13,6 +13,13 @@ config NET_DSA_MV88E6060
+ 	  This enables support for the Marvell 88E6060 ethernet switch
+ 	  chip.
+ 
++config NET_DSA_MV88E6063
++	bool "Marvell 88E6063 ethernet switch chip support"
++	select NET_DSA_TAG_TRAILER
++	---help---
++	  This enables support for the Marvell 88E6063 ethernet switch
++	  chip
++
+ config NET_DSA_MV88E6XXX_NEED_PPU
+ 	bool
+ 	default n
+--- a/drivers/net/dsa/Makefile
++++ b/drivers/net/dsa/Makefile
+@@ -1,4 +1,5 @@
+ obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
++obj-$(CONFIG_NET_DSA_MV88E6063) += mv88e6063.o
+ obj-$(CONFIG_NET_DSA_MV88E6XXX) += mv88e6xxx_drv.o
+ mv88e6xxx_drv-y += mv88e6xxx.o
+ ifdef CONFIG_NET_DSA_MV88E6123_61_65
diff --git a/target/linux/ar71xx/patches-3.8/430-drivers-link-spi-before-mtd.patch b/target/linux/ar71xx/patches-3.8/430-drivers-link-spi-before-mtd.patch
new file mode 100644
index 0000000..88d1457
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/430-drivers-link-spi-before-mtd.patch
@@ -0,0 +1,12 @@
+--- a/drivers/Makefile
++++ b/drivers/Makefile
+@@ -60,8 +60,8 @@ obj-$(CONFIG_IDE)		+= ide/
+ obj-$(CONFIG_SCSI)		+= scsi/
+ obj-$(CONFIG_ATA)		+= ata/
+ obj-$(CONFIG_TARGET_CORE)	+= target/
+-obj-$(CONFIG_MTD)		+= mtd/
+ obj-$(CONFIG_SPI)		+= spi/
++obj-$(CONFIG_MTD)		+= mtd/
+ obj-y				+= hsi/
+ obj-y				+= net/
+ obj-$(CONFIG_ATM)		+= atm/
diff --git a/target/linux/ar71xx/patches-3.8/431-spi-add-various-flags.patch b/target/linux/ar71xx/patches-3.8/431-spi-add-various-flags.patch
new file mode 100644
index 0000000..9f13db2
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/431-spi-add-various-flags.patch
@@ -0,0 +1,19 @@
+--- a/include/linux/spi/spi.h
++++ b/include/linux/spi/spi.h
+@@ -506,6 +506,8 @@ struct spi_transfer {
+ 	dma_addr_t	rx_dma;
+ 
+ 	unsigned	cs_change:1;
++	unsigned	verify:1;
++	unsigned	fast_write:1;
+ 	u8		bits_per_word;
+ 	u16		delay_usecs;
+ 	u32		speed_hz;
+@@ -547,6 +549,7 @@ struct spi_message {
+ 	struct spi_device	*spi;
+ 
+ 	unsigned		is_dma_mapped:1;
++	unsigned		fast_read:1;
+ 
+ 	/* REVISIT:  we might want a flag affecting the behavior of the
+ 	 * last transfer ... allowing things like "read 16 bit length L"
diff --git a/target/linux/ar71xx/patches-3.8/432-spi-rb4xx-spi-driver.patch b/target/linux/ar71xx/patches-3.8/432-spi-rb4xx-spi-driver.patch
new file mode 100644
index 0000000..1ff133c
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/432-spi-rb4xx-spi-driver.patch
@@ -0,0 +1,25 @@
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -324,6 +324,12 @@ config SPI_RSPI
+ 	help
+ 	  SPI driver for Renesas RSPI blocks.
+ 
++config SPI_RB4XX
++	tristate "Mikrotik RB4XX SPI master"
++	depends on SPI_MASTER && ATH79_MACH_RB4XX
++	help
++	  SPI controller driver for the Mikrotik RB4xx series boards.
++
+ config SPI_S3C24XX
+ 	tristate "Samsung S3C24XX series SPI"
+ 	depends on ARCH_S3C24XX && EXPERIMENTAL
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -50,6 +50,7 @@ obj-$(CONFIG_SPI_PL022)			+= spi-pl022.o
+ obj-$(CONFIG_SPI_PPC4xx)		+= spi-ppc4xx.o
+ obj-$(CONFIG_SPI_PXA2XX)		+= spi-pxa2xx.o
+ obj-$(CONFIG_SPI_PXA2XX_PCI)		+= spi-pxa2xx-pci.o
++obj-$(CONFIG_SPI_RB4XX)			+= spi-rb4xx.o
+ obj-$(CONFIG_SPI_RSPI)			+= spi-rspi.o
+ obj-$(CONFIG_SPI_S3C24XX)		+= spi-s3c24xx-hw.o
+ spi-s3c24xx-hw-y			:= spi-s3c24xx.o
diff --git a/target/linux/ar71xx/patches-3.8/433-spi-rb4xx-cpld-driver.patch b/target/linux/ar71xx/patches-3.8/433-spi-rb4xx-cpld-driver.patch
new file mode 100644
index 0000000..8fb9fa5
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/433-spi-rb4xx-cpld-driver.patch
@@ -0,0 +1,26 @@
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -509,6 +509,13 @@ config SPI_TLE62X0
+ 	  sysfs interface, with each line presented as a kind of GPIO
+ 	  exposing both switch control and diagnostic feedback.
+ 
++config SPI_RB4XX_CPLD
++	tristate "MikroTik RB4XX CPLD driver"
++	depends on ATH79_MACH_RB4XX
++	help
++	  SPI driver for the Xilinx CPLD chip present on the
++	  MikroTik RB4xx boards.
++
+ #
+ # Add new SPI protocol masters in alphabetical order above this line
+ #
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -51,6 +51,7 @@ obj-$(CONFIG_SPI_PPC4xx)		+= spi-ppc4xx.
+ obj-$(CONFIG_SPI_PXA2XX)		+= spi-pxa2xx.o
+ obj-$(CONFIG_SPI_PXA2XX_PCI)		+= spi-pxa2xx-pci.o
+ obj-$(CONFIG_SPI_RB4XX)			+= spi-rb4xx.o
++obj-$(CONFIG_SPI_RB4XX_CPLD)		+= spi-rb4xx-cpld.o
+ obj-$(CONFIG_SPI_RSPI)			+= spi-rspi.o
+ obj-$(CONFIG_SPI_S3C24XX)		+= spi-s3c24xx-hw.o
+ spi-s3c24xx-hw-y			:= spi-s3c24xx.o
diff --git a/target/linux/ar71xx/patches-3.8/434-spi-ap83_spi_controller.patch b/target/linux/ar71xx/patches-3.8/434-spi-ap83_spi_controller.patch
new file mode 100644
index 0000000..964ffe3
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/434-spi-ap83_spi_controller.patch
@@ -0,0 +1,27 @@
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -12,6 +12,7 @@ obj-$(CONFIG_SPI_SPIDEV)		+= spidev.o
+ # SPI master controller drivers (bus)
+ obj-$(CONFIG_SPI_ALTERA)		+= spi-altera.o
+ obj-$(CONFIG_SPI_ATMEL)			+= spi-atmel.o
++obj-$(CONFIG_SPI_AP83)			+= spi-ap83.o
+ obj-$(CONFIG_SPI_ATH79)			+= spi-ath79.o
+ obj-$(CONFIG_SPI_AU1550)		+= spi-au1550.o
+ obj-$(CONFIG_SPI_BCM63XX)		+= spi-bcm63xx.o
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -59,6 +59,14 @@ config SPI_ALTERA
+ 	help
+ 	  This is the driver for the Altera SPI Controller.
+ 
++config SPI_AP83
++	tristate "Atheros AP83 specific SPI Controller"
++	depends on SPI_MASTER && ATH79_MACH_AP83
++	select SPI_BITBANG
++	help
++	  This is a specific SPI controller driver for the Atheros AP83
++	  reference board.
++
+ config SPI_ATH79
+ 	tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver"
+ 	depends on ATH79 && GENERIC_GPIO
diff --git a/target/linux/ar71xx/patches-3.8/435-spi-vsc7385_driver.patch b/target/linux/ar71xx/patches-3.8/435-spi-vsc7385_driver.patch
new file mode 100644
index 0000000..c06ae53
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/435-spi-vsc7385_driver.patch
@@ -0,0 +1,23 @@
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -524,6 +524,11 @@ config SPI_RB4XX_CPLD
+ 	  SPI driver for the Xilinx CPLD chip present on the
+ 	  MikroTik RB4xx boards.
+ 
++config SPI_VSC7385
++	tristate "Vitesse VSC7385 ethernet switch driver"
++	help
++	  SPI driver for the Vitesse VSC7385 ethernet switch.
++
+ #
+ # Add new SPI protocol masters in alphabetical order above this line
+ #
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -70,5 +70,6 @@ obj-$(CONFIG_SPI_TI_SSP)		+= spi-ti-ssp.
+ obj-$(CONFIG_SPI_TLE62X0)		+= spi-tle62x0.o
+ obj-$(CONFIG_SPI_TOPCLIFF_PCH)		+= spi-topcliff-pch.o
+ obj-$(CONFIG_SPI_TXX9)			+= spi-txx9.o
++obj-$(CONFIG_SPI_VSC7385)		+= spi-vsc7385.o
+ obj-$(CONFIG_SPI_XCOMM)		+= spi-xcomm.o
+ obj-$(CONFIG_SPI_XILINX)		+= spi-xilinx.o
diff --git a/target/linux/ar71xx/patches-3.8/440-leds-wndr3700-usb-led-driver.patch b/target/linux/ar71xx/patches-3.8/440-leds-wndr3700-usb-led-driver.patch
new file mode 100644
index 0000000..e82277a
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/440-leds-wndr3700-usb-led-driver.patch
@@ -0,0 +1,26 @@
+--- a/drivers/leds/Kconfig
++++ b/drivers/leds/Kconfig
+@@ -467,6 +467,13 @@ config LEDS_TRIGGERS
+ 	  These triggers allow kernel events to drive the LEDs and can
+ 	  be configured via sysfs. If unsure, say Y.
+ 
++config LEDS_WNDR3700_USB
++	tristate "NETGEAR WNDR3700 USB LED driver"
++	depends on LEDS_CLASS && ATH79_MACH_WNDR3700
++	help
++	  This option enables support for the USB LED found on the
++	  NETGEAR WNDR3700 board.
++
+ comment "LED Triggers"
+ 
+ config LEDS_TRIGGER_TIMER
+--- a/drivers/leds/Makefile
++++ b/drivers/leds/Makefile
+@@ -38,6 +38,7 @@ obj-$(CONFIG_LEDS_DA9052)		+= leds-da905
+ obj-$(CONFIG_LEDS_WM831X_STATUS)	+= leds-wm831x-status.o
+ obj-$(CONFIG_LEDS_WM8350)		+= leds-wm8350.o
+ obj-$(CONFIG_LEDS_PWM)			+= leds-pwm.o
++obj-${CONFIG_LEDS_WNDR3700_USB}		+= leds-wndr3700-usb.o
+ obj-$(CONFIG_LEDS_REGULATOR)		+= leds-regulator.o
+ obj-$(CONFIG_LEDS_INTEL_SS4200)		+= leds-ss4200.o
+ obj-$(CONFIG_LEDS_LT3593)		+= leds-lt3593.o
diff --git a/target/linux/ar71xx/patches-3.8/441-leds-rb750-led-driver.patch b/target/linux/ar71xx/patches-3.8/441-leds-rb750-led-driver.patch
new file mode 100644
index 0000000..4eaa604
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/441-leds-rb750-led-driver.patch
@@ -0,0 +1,23 @@
+--- a/drivers/leds/Kconfig
++++ b/drivers/leds/Kconfig
+@@ -474,6 +474,10 @@ config LEDS_WNDR3700_USB
+ 	  This option enables support for the USB LED found on the
+ 	  NETGEAR WNDR3700 board.
+ 
++config LEDS_RB750
++	tristate "LED driver for the Mikrotik RouterBOARD 750"
++	depends on LEDS_CLASS && ATH79_MACH_RB750
++
+ comment "LED Triggers"
+ 
+ config LEDS_TRIGGER_TIMER
+--- a/drivers/leds/Makefile
++++ b/drivers/leds/Makefile
+@@ -45,6 +45,7 @@ obj-$(CONFIG_LEDS_LT3593)		+= leds-lt359
+ obj-$(CONFIG_LEDS_ADP5520)		+= leds-adp5520.o
+ obj-$(CONFIG_LEDS_DELL_NETBOOKS)	+= dell-led.o
+ obj-$(CONFIG_LEDS_MC13783)		+= leds-mc13783.o
++obj-$(CONFIG_LEDS_RB750)		+= leds-rb750.o
+ obj-$(CONFIG_LEDS_NS2)			+= leds-ns2.o
+ obj-$(CONFIG_LEDS_NETXBIG)		+= leds-netxbig.o
+ obj-$(CONFIG_LEDS_ASIC3)		+= leds-asic3.o
diff --git a/target/linux/ar71xx/patches-3.8/450-gpio-nxp-74hc153-gpio-chip-driver.patch b/target/linux/ar71xx/patches-3.8/450-gpio-nxp-74hc153-gpio-chip-driver.patch
new file mode 100644
index 0000000..97e15cd
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/450-gpio-nxp-74hc153-gpio-chip-driver.patch
@@ -0,0 +1,25 @@
+--- a/drivers/gpio/Kconfig
++++ b/drivers/gpio/Kconfig
+@@ -697,4 +697,12 @@ config GPIO_VIPERBOARD
+           River Tech's viperboard.h for detailed meaning
+           of the module parameters.
+ 
++comment "Other GPIO expanders"
++
++config GPIO_NXP_74HC153
++	tristate "NXP 74HC153 Dual 4-input multiplexer"
++	help
++	  Platform driver for NXP 74HC153 Dual 4-input Multiplexer. This
++	  provides a GPIO interface supporting input mode only.
++
+ endif
+--- a/drivers/gpio/Makefile
++++ b/drivers/gpio/Makefile
+@@ -48,6 +48,7 @@ obj-$(CONFIG_GPIO_MSM_V2)	+= gpio-msm-v2
+ obj-$(CONFIG_GPIO_MVEBU)        += gpio-mvebu.o
+ obj-$(CONFIG_GPIO_MXC)		+= gpio-mxc.o
+ obj-$(CONFIG_GPIO_MXS)		+= gpio-mxs.o
++obj-$(CONFIG_GPIO_NXP_74HC153)	+= gpio-nxp-74hc153.o
+ obj-$(CONFIG_ARCH_OMAP)		+= gpio-omap.o
+ obj-$(CONFIG_GPIO_PCA953X)	+= gpio-pca953x.o
+ obj-$(CONFIG_GPIO_PCF857X)	+= gpio-pcf857x.o
diff --git a/target/linux/ar71xx/patches-3.8/460-spi-bitbang-export-spi_bitbang_bufs.patch b/target/linux/ar71xx/patches-3.8/460-spi-bitbang-export-spi_bitbang_bufs.patch
new file mode 100644
index 0000000..919b85c
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/460-spi-bitbang-export-spi_bitbang_bufs.patch
@@ -0,0 +1,28 @@
+--- a/drivers/spi/spi-bitbang.c
++++ b/drivers/spi/spi-bitbang.c
+@@ -234,13 +234,14 @@ void spi_bitbang_cleanup(struct spi_devi
+ }
+ EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);
+ 
+-static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
++int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
+ {
+ 	struct spi_bitbang_cs	*cs = spi->controller_state;
+ 	unsigned		nsecs = cs->nsecs;
+ 
+ 	return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t);
+ }
++EXPORT_SYMBOL_GPL(spi_bitbang_bufs);
+ 
+ /*----------------------------------------------------------------------*/
+ 
+--- a/include/linux/spi/spi_bitbang.h
++++ b/include/linux/spi/spi_bitbang.h
+@@ -44,6 +44,7 @@ extern void spi_bitbang_cleanup(struct s
+ extern int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m);
+ extern int spi_bitbang_setup_transfer(struct spi_device *spi,
+ 				      struct spi_transfer *t);
++extern int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t);
+ 
+ /* start or stop queue processing */
+ extern int spi_bitbang_start(struct spi_bitbang *spi);
diff --git a/target/linux/ar71xx/patches-3.8/461-spi-add-type-field-to-spi_transfer.patch b/target/linux/ar71xx/patches-3.8/461-spi-add-type-field-to-spi_transfer.patch
new file mode 100644
index 0000000..d956499
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/461-spi-add-type-field-to-spi_transfer.patch
@@ -0,0 +1,23 @@
+--- a/include/linux/spi/spi.h
++++ b/include/linux/spi/spi.h
+@@ -409,6 +409,12 @@ extern struct spi_master *spi_busnum_to_
+ 
+ /*---------------------------------------------------------------------------*/
+ 
++enum spi_transfer_type {
++	SPI_TRANSFER_GENERIC = 0,
++	SPI_TRANSFER_FLASH_READ_CMD,
++	SPI_TRANSFER_FLASH_READ_DATA,
++};
++
+ /*
+  * I/O INTERFACE between SPI controller and protocol drivers
+  *
+@@ -511,6 +517,7 @@ struct spi_transfer {
+ 	u8		bits_per_word;
+ 	u16		delay_usecs;
+ 	u32		speed_hz;
++	enum spi_transfer_type type;
+ 
+ 	struct list_head transfer_list;
+ };
diff --git a/target/linux/ar71xx/patches-3.8/462-mtd-m25p80-set-spi-transfer-type.patch b/target/linux/ar71xx/patches-3.8/462-mtd-m25p80-set-spi-transfer-type.patch
new file mode 100644
index 0000000..e1ceb66
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/462-mtd-m25p80-set-spi-transfer-type.patch
@@ -0,0 +1,15 @@
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -357,10 +357,12 @@ static int m25p80_read(struct mtd_info *
+ 	 * OPCODE_FAST_READ (if available) is faster.
+ 	 * Should add 1 byte DUMMY_BYTE.
+ 	 */
++	t[0].type = SPI_TRANSFER_FLASH_READ_CMD;
+ 	t[0].tx_buf = flash->command;
+ 	t[0].len = m25p_cmdsz(flash) + (flash->fast_read ? 1 : 0);
+ 	spi_message_add_tail(&t[0], &m);
+ 
++	t[1].type = SPI_TRANSFER_FLASH_READ_DATA;
+ 	spi_message_add_tail(&t[1], &m);
+ 
+ 	mutex_lock(&flash->lock);
diff --git a/target/linux/ar71xx/patches-3.8/463-spi-ath79-add-fast-flash-read.patch b/target/linux/ar71xx/patches-3.8/463-spi-ath79-add-fast-flash-read.patch
new file mode 100644
index 0000000..e861644
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/463-spi-ath79-add-fast-flash-read.patch
@@ -0,0 +1,185 @@
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -37,6 +37,11 @@
+ 
+ #define ATH79_SPI_CS_LINE_MAX		2
+ 
++enum ath79_spi_state {
++	ATH79_SPI_STATE_WAIT_CMD = 0,
++	ATH79_SPI_STATE_WAIT_READ,
++};
++
+ struct ath79_spi {
+ 	struct spi_bitbang	bitbang;
+ 	u32			ioc_base;
+@@ -44,6 +49,11 @@ struct ath79_spi {
+ 	void __iomem		*base;
+ 	struct clk		*clk;
+ 	unsigned		rrw_delay;
++
++	enum ath79_spi_state	state;
++	u32			clk_div;
++	unsigned long 		read_addr;
++	unsigned long		ahb_rate;
+ };
+ 
+ static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
+@@ -111,9 +121,6 @@ static void ath79_spi_enable(struct ath7
+ 	/* save CTRL register */
+ 	sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
+ 	sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
+-
+-	/* TODO: setup speed? */
+-	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
+ }
+ 
+ static void ath79_spi_disable(struct ath79_spi *sp)
+@@ -232,6 +239,110 @@ static u32 ath79_spi_txrx_mode0(struct s
+ 	return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
+ }
+ 
++static int ath79_spi_do_read_flash_data(struct spi_device *spi,
++					struct spi_transfer *t)
++{
++	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
++
++	/* disable GPIO mode */
++	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
++
++	memcpy_fromio(t->rx_buf, sp->base + sp->read_addr, t->len);
++
++	/* enable GPIO mode */
++	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
++
++	/* restore IOC register */
++	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
++
++	return t->len;
++}
++
++static int ath79_spi_do_read_flash_cmd(struct spi_device *spi,
++				       struct spi_transfer *t)
++{
++	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
++	int len;
++	const u8 *p;
++
++	sp->read_addr = 0;
++
++	len = t->len - 1;
++	p = t->tx_buf;
++
++	while (len--) {
++		p++;
++		sp->read_addr <<= 8;
++		sp->read_addr |= *p;
++	}
++
++	return t->len;
++}
++
++static bool ath79_spi_is_read_cmd(struct spi_device *spi,
++				 struct spi_transfer *t)
++{
++	return t->type == SPI_TRANSFER_FLASH_READ_CMD;
++}
++
++static bool ath79_spi_is_data_read(struct spi_device *spi,
++				  struct spi_transfer *t)
++{
++	return t->type == SPI_TRANSFER_FLASH_READ_DATA;
++}
++
++static int ath79_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
++{
++	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
++	int ret;
++
++	switch (sp->state) {
++	case ATH79_SPI_STATE_WAIT_CMD:
++		if (ath79_spi_is_read_cmd(spi, t)) {
++			ret = ath79_spi_do_read_flash_cmd(spi, t);
++			sp->state = ATH79_SPI_STATE_WAIT_READ;
++		} else {
++			ret = spi_bitbang_bufs(spi, t);
++		}
++		break;
++
++	case ATH79_SPI_STATE_WAIT_READ:
++		if (ath79_spi_is_data_read(spi, t)) {
++			ret = ath79_spi_do_read_flash_data(spi, t);
++		} else {
++			dev_warn(&spi->dev, "flash data read expected\n");
++			ret = -EIO;
++		}
++		sp->state = ATH79_SPI_STATE_WAIT_CMD;
++		break;
++
++	default:
++		BUG();
++	}
++
++	return ret;
++}
++
++static int ath79_spi_setup_transfer(struct spi_device *spi,
++				    struct spi_transfer *t)
++{
++	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
++	struct ath79_spi_controller_data *cdata;
++	int ret;
++
++	ret = spi_bitbang_setup_transfer(spi, t);
++	if (ret)
++		return ret;
++
++	cdata = spi->controller_data;
++	if (cdata->is_flash)
++		sp->bitbang.txrx_bufs = ath79_spi_txrx_bufs;
++	else
++		sp->bitbang.txrx_bufs = spi_bitbang_bufs;
++
++	return ret;
++}
++
+ static int ath79_spi_probe(struct platform_device *pdev)
+ {
+ 	struct spi_master *master;
+@@ -254,6 +365,8 @@ static int ath79_spi_probe(struct platfo
+ 	sp = spi_master_get_devdata(master);
+ 	platform_set_drvdata(pdev, sp);
+ 
++	sp->state = ATH79_SPI_STATE_WAIT_CMD;
++
+ 	master->setup = ath79_spi_setup;
+ 	master->cleanup = ath79_spi_cleanup;
+ 	master->bus_num = pdata->bus_num;
+@@ -262,7 +375,7 @@ static int ath79_spi_probe(struct platfo
+ 	sp->bitbang.master = spi_master_get(master);
+ 	sp->bitbang.chipselect = ath79_spi_chipselect;
+ 	sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
+-	sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
++	sp->bitbang.setup_transfer = ath79_spi_setup_transfer;
+ 	sp->bitbang.flags = SPI_CS_HIGH;
+ 
+ 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+@@ -287,7 +400,8 @@ static int ath79_spi_probe(struct platfo
+ 	if (ret)
+ 		goto err_clk_put;
+ 
+-	rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
++	sp->ahb_rate = clk_get_rate(sp->clk);
++	rate = DIV_ROUND_UP(sp->ahb_rate, MHZ);
+ 	if (!rate) {
+ 		ret = -EINVAL;
+ 		goto err_clk_disable;
+--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
++++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
+@@ -24,6 +24,7 @@ enum ath79_spi_cs_type {
+ struct ath79_spi_controller_data {
+ 	enum ath79_spi_cs_type cs_type;
+ 	unsigned cs_line;
++	bool is_flash;
+ };
+ 
+ #endif /* _ATH79_SPI_PLATFORM_H */
diff --git a/target/linux/ar71xx/patches-3.8/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch b/target/linux/ar71xx/patches-3.8/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch
new file mode 100644
index 0000000..520c652
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch
@@ -0,0 +1,111 @@
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ath79/mangle-port.h
+@@ -0,0 +1,37 @@
++/*
++ *  Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
++ *
++ *  This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h
++ *      Copyright (C) 2003, 2004 Ralf Baechle
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ */
++
++#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H
++#define __ASM_MACH_ATH79_MANGLE_PORT_H
++
++#ifdef CONFIG_PCI
++extern unsigned long (ath79_pci_swizzle_b)(unsigned long port);
++extern unsigned long (ath79_pci_swizzle_w)(unsigned long port);
++#else
++#define ath79_pci_swizzle_b(port) (port)
++#define ath79_pci_swizzle_w(port) (port)
++#endif
++
++#define __swizzle_addr_b(port)	ath79_pci_swizzle_b(port)
++#define __swizzle_addr_w(port)	ath79_pci_swizzle_w(port)
++#define __swizzle_addr_l(port)	(port)
++#define __swizzle_addr_q(port)	(port)
++
++# define ioswabb(a, x)           (x)
++# define __mem_ioswabb(a, x)     (x)
++# define ioswabw(a, x)           (x)
++# define __mem_ioswabw(a, x)     cpu_to_le16(x)
++# define ioswabl(a, x)           (x)
++# define __mem_ioswabl(a, x)     cpu_to_le32(x)
++# define ioswabq(a, x)           (x)
++# define __mem_ioswabq(a, x)     cpu_to_le64(x)
++
++#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -13,6 +13,7 @@
+  */
+ 
+ #include <linux/init.h>
++#include <linux/export.h>
+ #include <linux/pci.h>
+ #include <linux/resource.h>
+ #include <linux/platform_device.h>
+@@ -25,6 +26,9 @@ static int (*ath79_pci_plat_dev_init)(st
+ static const struct ath79_pci_irq *ath79_pci_irq_map __initdata;
+ static unsigned ath79_pci_nr_irqs __initdata;
+ 
++static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port);
++static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port);
++
+ static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = {
+ 	{
+ 		.slot	= 17,
+@@ -212,12 +216,50 @@ ath79_register_pci_ar724x(int id,
+ 	return pdev;
+ }
+ 
++static inline bool ar71xx_is_pci_addr(unsigned long port)
++{
++	unsigned long phys = CPHYSADDR(port);
++
++	return (phys >= AR71XX_PCI_MEM_BASE &&
++		phys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE);
++}
++
++static unsigned long ar71xx_pci_swizzle_b(unsigned long port)
++{
++	return ar71xx_is_pci_addr(port) ? port ^ 3 : port;
++}
++
++static unsigned long ar71xx_pci_swizzle_w(unsigned long port)
++{
++	return ar71xx_is_pci_addr(port) ? port ^ 2 : port;
++}
++
++unsigned long ath79_pci_swizzle_b(unsigned long port)
++{
++	if (__ath79_pci_swizzle_b)
++		return __ath79_pci_swizzle_b(port);
++
++	return port;
++}
++EXPORT_SYMBOL(ath79_pci_swizzle_b);
++
++unsigned long ath79_pci_swizzle_w(unsigned long port)
++{
++	if (__ath79_pci_swizzle_w)
++		return __ath79_pci_swizzle_w(port);
++
++	return port;
++}
++EXPORT_SYMBOL(ath79_pci_swizzle_w);
++
+ int __init ath79_register_pci(void)
+ {
+ 	struct platform_device *pdev = NULL;
+ 
+ 	if (soc_is_ar71xx()) {
+ 		pdev = ath79_register_pci_ar71xx();
++		__ath79_pci_swizzle_b = ar71xx_pci_swizzle_b;
++		__ath79_pci_swizzle_w = ar71xx_pci_swizzle_w;
+ 	} else if (soc_is_ar724x()) {
+ 		pdev = ath79_register_pci_ar724x(-1,
+ 						 AR724X_PCI_CFG_BASE,
diff --git a/target/linux/ar71xx/patches-3.8/500-MIPS-fw-myloader.patch b/target/linux/ar71xx/patches-3.8/500-MIPS-fw-myloader.patch
new file mode 100644
index 0000000..421f6a9
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/500-MIPS-fw-myloader.patch
@@ -0,0 +1,22 @@
+--- a/arch/mips/Makefile
++++ b/arch/mips/Makefile
+@@ -182,6 +182,7 @@ endif
+ #
+ libs-$(CONFIG_FW_ARC)		+= arch/mips/fw/arc/
+ libs-$(CONFIG_FW_CFE)		+= arch/mips/fw/cfe/
++libs-$(CONFIG_MYLOADER)		+= arch/mips/fw/myloader/
+ libs-$(CONFIG_FW_SNIPROM)	+= arch/mips/fw/sni/
+ libs-y				+= arch/mips/fw/lib/
+ 
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -989,6 +989,9 @@ config MIPS_NILE4
+ config MIPS_DISABLE_OBSOLETE_IDE
+ 	bool
+ 
++config MYLOADER
++	bool
++
+ config SYNC_R4K
+ 	bool
+ 
diff --git a/target/linux/ar71xx/patches-3.8/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch b/target/linux/ar71xx/patches-3.8/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch
new file mode 100644
index 0000000..de0db9a
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch
@@ -0,0 +1,81 @@
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -15,6 +15,7 @@
+ #include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/irq.h>
++#include <linux/etherdevice.h>
+ #include <linux/platform_device.h>
+ #include <linux/ath9k_platform.h>
+ 
+@@ -22,6 +23,7 @@
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include "dev-wmac.h"
+ 
++static u8 ath79_wmac_mac[ETH_ALEN];
+ static struct ath9k_platform_data ath79_wmac_data;
+ 
+ static struct resource ath79_wmac_resources[] = {
+@@ -151,7 +153,7 @@ static void qca955x_wmac_setup(void)
+ 		ath79_wmac_data.is_clk_25mhz = true;
+ }
+ 
+-void __init ath79_register_wmac(u8 *cal_data)
++void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
+ {
+ 	if (soc_is_ar913x())
+ 		ar913x_wmac_setup();
+@@ -168,5 +170,10 @@ void __init ath79_register_wmac(u8 *cal_
+ 		memcpy(ath79_wmac_data.eeprom_data, cal_data,
+ 		       sizeof(ath79_wmac_data.eeprom_data));
+ 
++	if (mac_addr) {
++		memcpy(ath79_wmac_mac, mac_addr, sizeof(ath79_wmac_mac));
++		ath79_wmac_data.macaddr = ath79_wmac_mac;
++	}
++
+ 	platform_device_register(&ath79_wmac_device);
+ }
+--- a/arch/mips/ath79/dev-wmac.h
++++ b/arch/mips/ath79/dev-wmac.h
+@@ -12,6 +12,6 @@
+ #ifndef _ATH79_DEV_WMAC_H
+ #define _ATH79_DEV_WMAC_H
+ 
+-void ath79_register_wmac(u8 *cal_data);
++void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
+ 
+ #endif /* _ATH79_DEV_WMAC_H */
+--- a/arch/mips/ath79/mach-ap81.c
++++ b/arch/mips/ath79/mach-ap81.c
+@@ -98,7 +98,7 @@ static void __init ap81_setup(void)
+ 					ap81_gpio_keys);
+ 	ath79_register_spi(&ap81_spi_data, ap81_spi_info,
+ 			   ARRAY_SIZE(ap81_spi_info));
+-	ath79_register_wmac(cal_data);
++	ath79_register_wmac(cal_data, NULL);
+ 	ath79_register_usb();
+ }
+ 
+--- a/arch/mips/ath79/mach-db120.c
++++ b/arch/mips/ath79/mach-db120.c
+@@ -134,7 +134,7 @@ static void __init db120_setup(void)
+ 	ath79_register_spi(&db120_spi_data, db120_spi_info,
+ 			   ARRAY_SIZE(db120_spi_info));
+ 	ath79_register_usb();
+-	ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET);
++	ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
+ 	db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
+ }
+ 
+--- a/arch/mips/ath79/mach-ap121.c
++++ b/arch/mips/ath79/mach-ap121.c
+@@ -91,7 +91,7 @@ static void __init ap121_setup(void)
+ 	ath79_register_spi(&ap121_spi_data, ap121_spi_info,
+ 			   ARRAY_SIZE(ap121_spi_info));
+ 	ath79_register_usb();
+-	ath79_register_wmac(cal_data);
++	ath79_register_wmac(cal_data, NULL);
+ }
+ 
+ MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
diff --git a/target/linux/ar71xx/patches-3.8/502-MIPS-ath79-export-ath79_gpio_base.patch b/target/linux/ar71xx/patches-3.8/502-MIPS-ath79-export-ath79_gpio_base.patch
new file mode 100644
index 0000000..73eb8e1
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/502-MIPS-ath79-export-ath79_gpio_base.patch
@@ -0,0 +1,23 @@
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -25,7 +25,9 @@
+ #include <asm/mach-ath79/ath79.h>
+ #include "common.h"
+ 
+-static void __iomem *ath79_gpio_base;
++void __iomem *ath79_gpio_base;
++EXPORT_SYMBOL_GPL(ath79_gpio_base);
++
+ static unsigned long ath79_gpio_count;
+ static DEFINE_SPINLOCK(ath79_gpio_lock);
+ 
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -116,6 +116,7 @@ static inline int soc_is_qca955x(void)
+ }
+ 
+ extern void __iomem *ath79_ddr_base;
++extern void __iomem *ath79_gpio_base;
+ extern void __iomem *ath79_pll_base;
+ extern void __iomem *ath79_reset_base;
+ 
diff --git a/target/linux/ar71xx/patches-3.8/503-MIPS-ath79-add-flash-acquire-release.patch b/target/linux/ar71xx/patches-3.8/503-MIPS-ath79-add-flash-acquire-release.patch
new file mode 100644
index 0000000..06f7902
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/503-MIPS-ath79-add-flash-acquire-release.patch
@@ -0,0 +1,37 @@
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -22,6 +22,7 @@
+ #include "common.h"
+ 
+ static DEFINE_SPINLOCK(ath79_device_reset_lock);
++static DEFINE_MUTEX(ath79_flash_mutex);
+ 
+ u32 ath79_cpu_freq;
+ EXPORT_SYMBOL_GPL(ath79_cpu_freq);
+@@ -111,3 +112,16 @@ void ath79_device_reset_clear(u32 mask)
+ 	spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
+ }
+ EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
++
++void ath79_flash_acquire(void)
++{
++	mutex_lock(&ath79_flash_mutex);
++}
++EXPORT_SYMBOL_GPL(ath79_flash_acquire);
++
++void ath79_flash_release(void)
++{
++	mutex_unlock(&ath79_flash_mutex);
++}
++EXPORT_SYMBOL_GPL(ath79_flash_release);
++
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -143,4 +143,7 @@ static inline u32 ath79_reset_rr(unsigne
+ void ath79_device_reset_set(u32 mask);
+ void ath79_device_reset_clear(u32 mask);
+ 
++void ath79_flash_acquire(void);
++void ath79_flash_release(void);
++
+ #endif /* __ASM_MACH_ATH79_H */
diff --git a/target/linux/ar71xx/patches-3.8/504-MIPS-ath79-add-ath79_device_reset_get.patch b/target/linux/ar71xx/patches-3.8/504-MIPS-ath79-add-ath79_device_reset_get.patch
new file mode 100644
index 0000000..024a85d
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/504-MIPS-ath79-add-ath79_device_reset_get.patch
@@ -0,0 +1,45 @@
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -142,6 +142,7 @@ static inline u32 ath79_reset_rr(unsigne
+ 
+ void ath79_device_reset_set(u32 mask);
+ void ath79_device_reset_clear(u32 mask);
++u32 ath79_device_reset_get(u32 mask);
+ 
+ void ath79_flash_acquire(void);
+ void ath79_flash_release(void);
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -113,6 +113,32 @@ void ath79_device_reset_clear(u32 mask)
+ }
+ EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
+ 
++u32 ath79_device_reset_get(u32 mask)
++{
++	unsigned long flags;
++	u32 reg;
++	u32 ret;
++
++	if (soc_is_ar71xx())
++		reg = AR71XX_RESET_REG_RESET_MODULE;
++	else if (soc_is_ar724x())
++		reg = AR724X_RESET_REG_RESET_MODULE;
++	else if (soc_is_ar913x())
++		reg = AR913X_RESET_REG_RESET_MODULE;
++	else if (soc_is_ar933x())
++		reg = AR933X_RESET_REG_RESET_MODULE;
++	else if (soc_is_ar934x())
++		reg = AR934X_RESET_REG_RESET_MODULE;
++	else
++		BUG();
++
++	spin_lock_irqsave(&ath79_device_reset_lock, flags);
++	ret = ath79_reset_rr(reg);
++	spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
++	return ret;
++}
++EXPORT_SYMBOL_GPL(ath79_device_reset_get);
++
+ void ath79_flash_acquire(void)
+ {
+ 	mutex_lock(&ath79_flash_mutex);
diff --git a/target/linux/ar71xx/patches-3.8/505-MIPS-ath79-add-ath79_gpio_function_select.patch b/target/linux/ar71xx/patches-3.8/505-MIPS-ath79-add-ath79_gpio_function_select.patch
new file mode 100644
index 0000000..9e11381
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/505-MIPS-ath79-add-ath79_gpio_function_select.patch
@@ -0,0 +1,47 @@
+--- a/arch/mips/ath79/common.h
++++ b/arch/mips/ath79/common.h
+@@ -26,6 +26,7 @@ void ath79_ddr_wb_flush(unsigned int reg
+ void ath79_gpio_function_enable(u32 mask);
+ void ath79_gpio_function_disable(u32 mask);
+ void ath79_gpio_function_setup(u32 set, u32 clear);
++void ath79_gpio_output_select(unsigned gpio, u8 val);
+ void ath79_gpio_init(void);
+ 
+ #endif /* __ATH79_COMMON_H */
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -180,6 +180,34 @@ void ath79_gpio_function_disable(u32 mas
+ 	ath79_gpio_function_setup(0, mask);
+ }
+ 
++void __init ath79_gpio_output_select(unsigned gpio, u8 val)
++{
++	void __iomem *base = ath79_gpio_base;
++	unsigned long flags;
++	unsigned int reg;
++	u32 t, s;
++
++	BUG_ON(!soc_is_ar934x());
++
++	if (gpio >= AR934X_GPIO_COUNT)
++		return;
++
++	reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4);
++	s = 8 * (gpio % 4);
++
++	spin_lock_irqsave(&ath79_gpio_lock, flags);
++
++	t = __raw_readl(base + reg);
++	t &= ~(0xff << s);
++	t |= val << s;
++	__raw_writel(t, base + reg);
++
++	/* flush write */
++	(void) __raw_readl(base + reg);
++
++	spin_unlock_irqrestore(&ath79_gpio_lock, flags);
++}
++
+ void __init ath79_gpio_init(void)
+ {
+ 	int err;
diff --git a/target/linux/ar71xx/patches-3.8/506-MIPS-ath79-prom-parse-redboot-args.patch b/target/linux/ar71xx/patches-3.8/506-MIPS-ath79-prom-parse-redboot-args.patch
new file mode 100644
index 0000000..aab959b
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/506-MIPS-ath79-prom-parse-redboot-args.patch
@@ -0,0 +1,86 @@
+--- a/arch/mips/ath79/prom.c
++++ b/arch/mips/ath79/prom.c
+@@ -19,6 +19,8 @@
+ 
+ #include "common.h"
+ 
++static char ath79_cmdline_buf[COMMAND_LINE_SIZE] __initdata;
++
+ static inline int is_valid_ram_addr(void *addr)
+ {
+ 	if (((u32) addr > KSEG0) &&
+@@ -32,6 +34,41 @@ static inline int is_valid_ram_addr(void
+ 	return 0;
+ }
+ 
++static void __init ath79_prom_append_cmdline(const char *name,
++					      const char *value)
++{
++	snprintf(ath79_cmdline_buf, sizeof(ath79_cmdline_buf),
++		 " %s=%s", name, value);
++	strlcat(arcs_cmdline, ath79_cmdline_buf, sizeof(arcs_cmdline));
++}
++
++static const char * __init ath79_prom_find_env(char **envp, const char *name)
++{
++	const char *ret = NULL;
++	int len;
++	char **p;
++
++	if (!is_valid_ram_addr(envp))
++		return NULL;
++
++	len = strlen(name);
++	for (p = envp; is_valid_ram_addr(*p); p++) {
++		if (strncmp(name, *p, len) == 0 && (*p)[len] == '=') {
++			ret = *p + len + 1;
++			break;
++		}
++
++		/* RedBoot env comes in pointer pairs - key, value */
++		if (strncmp(name, *p, len) == 0 && (*p)[len] == 0)
++			if (is_valid_ram_addr(*(++p))) {
++				ret = *p;
++				break;
++			}
++	}
++
++	return ret;
++}
++
+ static __init void ath79_prom_init_cmdline(int argc, char **argv)
+ {
+ 	int i;
+@@ -48,7 +85,32 @@ static __init void ath79_prom_init_cmdli
+ 
+ void __init prom_init(void)
+ {
++	const char *env;
++	char **envp;
++
+ 	ath79_prom_init_cmdline(fw_arg0, (char **)fw_arg1);
++
++	envp = (char **)fw_arg2;
++	if (!strstr(arcs_cmdline, "ethaddr=")) {
++		env = ath79_prom_find_env(envp, "ethaddr");
++		if (env)
++			ath79_prom_append_cmdline("ethaddr", env);
++	}
++
++	if (!strstr(arcs_cmdline, "board=")) {
++		env = ath79_prom_find_env(envp, "board");
++		if (env) {
++			/* Workaround for buggy bootloaders */
++			if (strcmp(env, "RouterStation") == 0 ||
++			    strcmp(env, "Ubiquiti AR71xx-based board") == 0)
++				env = "UBNT-RS";
++
++			if (strcmp(env, "RouterStation PRO") == 0)
++				env = "UBNT-RSPRO";
++
++			ath79_prom_append_cmdline("board", env);
++		}
++	}
+ }
+ 
+ void __init prom_free_prom_memory(void)
diff --git a/target/linux/ar71xx/patches-3.8/507-MIPS-ath79-prom-add-myloader-support.patch b/target/linux/ar71xx/patches-3.8/507-MIPS-ath79-prom-add-myloader-support.patch
new file mode 100644
index 0000000..67c1faf
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/507-MIPS-ath79-prom-add-myloader-support.patch
@@ -0,0 +1,58 @@
+--- a/arch/mips/ath79/prom.c
++++ b/arch/mips/ath79/prom.c
+@@ -16,6 +16,7 @@
+ 
+ #include <asm/bootinfo.h>
+ #include <asm/addrspace.h>
++#include <asm/fw/myloader/myloader.h>
+ 
+ #include "common.h"
+ 
+@@ -69,6 +70,37 @@ static const char * __init ath79_prom_fi
+ 	return ret;
+ }
+ 
++static int __init ath79_prom_init_myloader(void)
++{
++	struct myloader_info *mylo;
++	char mac_buf[32];
++	unsigned char *mac;
++
++	mylo = myloader_get_info();
++	if (!mylo)
++		return 0;
++
++	switch (mylo->did) {
++	case DEVID_COMPEX_WP543:
++		ath79_prom_append_cmdline("board", "WP543");
++		break;
++	case DEVID_COMPEX_WPE72:
++		ath79_prom_append_cmdline("board", "WPE72");
++		break;
++	default:
++		pr_warn("prom: unknown device id: %x\n", mylo->did);
++		return 0;
++	}
++
++	mac = mylo->macs[0];
++	snprintf(mac_buf, sizeof(mac_buf), "%02x:%02x:%02x:%02x:%02x:%02x",
++		 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
++
++	ath79_prom_append_cmdline("ethaddr", mac_buf);
++
++	return 1;
++}
++
+ static __init void ath79_prom_init_cmdline(int argc, char **argv)
+ {
+ 	int i;
+@@ -88,6 +120,9 @@ void __init prom_init(void)
+ 	const char *env;
+ 	char **envp;
+ 
++	if (ath79_prom_init_myloader())
++		return;
++
+ 	ath79_prom_init_cmdline(fw_arg0, (char **)fw_arg1);
+ 
+ 	envp = (char **)fw_arg2;
diff --git a/target/linux/ar71xx/patches-3.8/508-MIPS-ath79-prom-image-command-line-hack.patch b/target/linux/ar71xx/patches-3.8/508-MIPS-ath79-prom-image-command-line-hack.patch
new file mode 100644
index 0000000..72a3b56
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/508-MIPS-ath79-prom-image-command-line-hack.patch
@@ -0,0 +1,57 @@
+--- a/arch/mips/ath79/prom.c
++++ b/arch/mips/ath79/prom.c
+@@ -70,6 +70,35 @@ static const char * __init ath79_prom_fi
+ 	return ret;
+ }
+ 
++#ifdef CONFIG_IMAGE_CMDLINE_HACK
++extern char __image_cmdline[];
++
++static int __init ath79_use_image_cmdline(void)
++{
++	char *p = __image_cmdline;
++	int replace = 0;
++
++	if (*p == '-') {
++		replace = 1;
++		p++;
++	}
++
++	if (*p == '\0')
++		return 0;
++
++	if (replace) {
++		strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline));
++	} else {
++		strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
++		strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
++	}
++
++	return 1;
++}
++#else
++static inline int ath79_use_image_cmdline(void) { return 0; }
++#endif
++
+ static int __init ath79_prom_init_myloader(void)
+ {
+ 	struct myloader_info *mylo;
+@@ -98,6 +127,8 @@ static int __init ath79_prom_init_myload
+ 
+ 	ath79_prom_append_cmdline("ethaddr", mac_buf);
+ 
++	ath79_use_image_cmdline();
++
+ 	return 1;
+ }
+ 
+@@ -105,6 +136,9 @@ static __init void ath79_prom_init_cmdli
+ {
+ 	int i;
+ 
++	if (ath79_use_image_cmdline())
++		return;
++
+ 	if (!is_valid_ram_addr(argv))
+ 		return;
+ 
diff --git a/target/linux/ar71xx/patches-3.8/509-MIPS-ath79-process-board-kernel-option.patch b/target/linux/ar71xx/patches-3.8/509-MIPS-ath79-process-board-kernel-option.patch
new file mode 100644
index 0000000..7858a90
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/509-MIPS-ath79-process-board-kernel-option.patch
@@ -0,0 +1,11 @@
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -231,6 +231,8 @@ void __init plat_time_init(void)
+ 	mips_hpt_frequency = clk_get_rate(clk) / 2;
+ }
+ 
++__setup("board=", mips_machtype_setup);
++
+ static int __init ath79_setup(void)
+ {
+ 	ath79_gpio_init();
diff --git a/target/linux/ar71xx/patches-3.8/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch b/target/linux/ar71xx/patches-3.8/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch
new file mode 100644
index 0000000..2d2235e
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch
@@ -0,0 +1,14 @@
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -24,7 +24,10 @@
+ #include "dev-wmac.h"
+ 
+ static u8 ath79_wmac_mac[ETH_ALEN];
+-static struct ath9k_platform_data ath79_wmac_data;
++
++static struct ath9k_platform_data ath79_wmac_data = {
++	.led_pin = -1,
++};
+ 
+ static struct resource ath79_wmac_resources[] = {
+ 	{
diff --git a/target/linux/ar71xx/patches-3.8/520-MIPS-ath79-enable-UART-function.patch b/target/linux/ar71xx/patches-3.8/520-MIPS-ath79-enable-UART-function.patch
new file mode 100644
index 0000000..1cb407f
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/520-MIPS-ath79-enable-UART-function.patch
@@ -0,0 +1,18 @@
+--- a/arch/mips/ath79/dev-common.c
++++ b/arch/mips/ath79/dev-common.c
+@@ -87,6 +87,15 @@ void __init ath79_register_uart(void)
+ 	if (IS_ERR(clk))
+ 		panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
+ 
++	if (soc_is_ar71xx())
++		ath79_gpio_function_enable(AR71XX_GPIO_FUNC_UART_EN);
++	else if (soc_is_ar724x())
++		ath79_gpio_function_enable(AR724X_GPIO_FUNC_UART_EN);
++	else if (soc_is_ar913x())
++		ath79_gpio_function_enable(AR913X_GPIO_FUNC_UART_EN);
++	else if (soc_is_ar933x())
++		ath79_gpio_function_enable(AR933X_GPIO_FUNC_UART_EN);
++
+ 	if (soc_is_ar71xx() ||
+ 	    soc_is_ar724x() ||
+ 	    soc_is_ar913x() ||
diff --git a/target/linux/ar71xx/patches-3.8/521-MIPS-ath79-enable-UART-for-early_serial.patch b/target/linux/ar71xx/patches-3.8/521-MIPS-ath79-enable-UART-for-early_serial.patch
new file mode 100644
index 0000000..3d6ddfe
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/521-MIPS-ath79-enable-UART-for-early_serial.patch
@@ -0,0 +1,61 @@
+--- a/arch/mips/ath79/early_printk.c
++++ b/arch/mips/ath79/early_printk.c
+@@ -56,6 +56,46 @@ static void prom_putchar_dummy(unsigned
+ 	/* nothing to do */
+ }
+ 
++static void prom_enable_uart(u32 id)
++{
++	void __iomem *gpio_base;
++	u32 uart_en;
++	u32 t;
++
++	switch (id) {
++	case REV_ID_MAJOR_AR71XX:
++		uart_en = AR71XX_GPIO_FUNC_UART_EN;
++		break;
++
++	case REV_ID_MAJOR_AR7240:
++	case REV_ID_MAJOR_AR7241:
++	case REV_ID_MAJOR_AR7242:
++		uart_en = AR724X_GPIO_FUNC_UART_EN;
++		break;
++
++	case REV_ID_MAJOR_AR913X:
++		uart_en = AR913X_GPIO_FUNC_UART_EN;
++		break;
++
++	case REV_ID_MAJOR_AR9330:
++	case REV_ID_MAJOR_AR9331:
++		uart_en = AR933X_GPIO_FUNC_UART_EN;
++		break;
++
++	case REV_ID_MAJOR_AR9341:
++	case REV_ID_MAJOR_AR9342:
++	case REV_ID_MAJOR_AR9344:
++		/* TODO */
++	default:
++		return;
++	}
++
++	gpio_base = (void __iomem *)(KSEG1ADDR(AR71XX_GPIO_BASE));
++	t = __raw_readl(gpio_base + AR71XX_GPIO_REG_FUNC);
++	t |= uart_en;
++	__raw_writel(t, gpio_base + AR71XX_GPIO_REG_FUNC);
++}
++
+ static void prom_putchar_init(void)
+ {
+ 	void __iomem *base;
+@@ -86,8 +126,10 @@ static void prom_putchar_init(void)
+ 
+ 	default:
+ 		_prom_putchar = prom_putchar_dummy;
+-		break;
++		return;
+ 	}
++
++	prom_enable_uart(id);
+ }
+ 
+ void prom_putchar(unsigned char ch)
diff --git a/target/linux/ar71xx/patches-3.8/522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch b/target/linux/ar71xx/patches-3.8/522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch
new file mode 100644
index 0000000..74309b6
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch
@@ -0,0 +1,21 @@
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -180,3 +180,9 @@ void __init ath79_register_wmac(u8 *cal_
+ 
+ 	platform_device_register(&ath79_wmac_device);
+ }
++
++void __init ath79_register_wmac_simple(void)
++{
++	ath79_register_wmac(NULL, NULL);
++	ath79_wmac_data.eeprom_name = "soc_wmac.eeprom";
++}
+--- a/arch/mips/ath79/dev-wmac.h
++++ b/arch/mips/ath79/dev-wmac.h
+@@ -13,5 +13,6 @@
+ #define _ATH79_DEV_WMAC_H
+ 
+ void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
++void ath79_register_wmac_simple(void);
+ 
+ #endif /* _ATH79_DEV_WMAC_H */
diff --git a/target/linux/ar71xx/patches-3.8/523-MIPS-ath79-OTP-support.patch b/target/linux/ar71xx/patches-3.8/523-MIPS-ath79-OTP-support.patch
new file mode 100644
index 0000000..84273d3
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/523-MIPS-ath79-OTP-support.patch
@@ -0,0 +1,166 @@
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -156,6 +156,137 @@ static void qca955x_wmac_setup(void)
+ 		ath79_wmac_data.is_clk_25mhz = true;
+ }
+ 
++static bool __init
++ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
++{
++	int timeout = 1000;
++	u32 val;
++
++	__raw_readl(base + AR9300_OTP_BASE + (4 * addr));
++	while (timeout--) {
++		val = __raw_readl(base + AR9300_OTP_STATUS);
++		if ((val & AR9300_OTP_STATUS_TYPE) == AR9300_OTP_STATUS_VALID)
++			break;
++
++		udelay(10);
++	}
++
++	if (!timeout)
++		return false;
++
++	*data = __raw_readl(base + AR9300_OTP_READ_DATA);
++	return true;
++}
++
++static bool __init
++ar93xx_wmac_otp_read(void __iomem *base, int addr, u8 *dest, int len)
++{
++	u32 data;
++	int i;
++
++	for (i = 0; i < len; i++) {
++		int offset = 8 * ((addr - i) % 4);
++
++		if (!ar93xx_wmac_otp_read_word(base, (addr - i) / 4, &data))
++			return false;
++
++		dest[i] = (data >> offset) & 0xff;
++	}
++
++	return true;
++}
++
++static bool __init
++ar93xx_wmac_otp_uncompress(void __iomem *base, int addr, int len, u8 *dest,
++			   int dest_start, int dest_len)
++{
++	int dest_bytes = 0;
++	int offset = 0;
++	int end = addr - len;
++	u8 hdr[2];
++
++	while (addr > end) {
++		if (!ar93xx_wmac_otp_read(base, addr, hdr, 2))
++			return false;
++
++		addr -= 2;
++		offset += hdr[0];
++
++		if (offset <= dest_start + dest_len &&
++		    offset + len >= dest_start) {
++			int data_offset = 0;
++			int dest_offset = 0;
++			int copy_len;
++
++			if (offset < dest_start)
++				data_offset = dest_start - offset;
++			else
++				dest_offset = offset - dest_start;
++
++			copy_len = len - data_offset;
++			if (copy_len > dest_len - dest_offset)
++				copy_len = dest_len - dest_offset;
++
++			ar93xx_wmac_otp_read(base, addr - data_offset,
++					     dest + dest_offset,
++					     copy_len);
++
++			dest_bytes += copy_len;
++		}
++		addr -= hdr[1];
++	}
++	return !!dest_bytes;
++}
++
++bool __init ar93xx_wmac_read_mac_address(u8 *dest)
++{
++	void __iomem *base;
++	bool ret = false;
++	int addr = 0x1ff;
++	unsigned int len;
++	u32 hdr_u32;
++	u8 *hdr = (u8 *) &hdr_u32;
++	u8 mac[6] = { 0x00, 0x02, 0x03, 0x04, 0x05, 0x06 };
++	int mac_start = 2, mac_end = 8;
++
++	BUG_ON(!soc_is_ar933x() && !soc_is_ar934x());
++	base = ioremap_nocache(AR933X_WMAC_BASE, AR933X_WMAC_SIZE);
++	while (addr > sizeof(hdr)) {
++		if (!ar93xx_wmac_otp_read(base, addr, hdr, sizeof(hdr)))
++			break;
++
++		if (hdr_u32 == 0 || hdr_u32 == ~0)
++			break;
++
++		len = (hdr[1] << 4) | (hdr[2] >> 4);
++		addr -= 4;
++
++		switch (hdr[0] >> 5) {
++		case 0:
++			if (len < mac_end)
++				break;
++
++			ar93xx_wmac_otp_read(base, addr - mac_start, mac, 6);
++			ret = true;
++			break;
++		case 3:
++			ret |= ar93xx_wmac_otp_uncompress(base, addr, len, mac,
++							  mac_start, 6);
++			break;
++		default:
++			break;
++		}
++
++		addr -= len + 2;
++	}
++
++	iounmap(base);
++	if (ret)
++		memcpy(dest, mac, 6);
++
++	return ret;
++}
++
+ void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
+ {
+ 	if (soc_is_ar913x())
+--- a/arch/mips/ath79/dev-wmac.h
++++ b/arch/mips/ath79/dev-wmac.h
+@@ -14,5 +14,6 @@
+ 
+ void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
+ void ath79_register_wmac_simple(void);
++bool ar93xx_wmac_read_mac_address(u8 *dest);
+ 
+ #endif /* _ATH79_DEV_WMAC_H */
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -113,6 +113,14 @@
+ #define QCA955X_EHCI1_BASE	0x1b400000
+ #define QCA955X_EHCI_SIZE	0x1000
+ 
++#define AR9300_OTP_BASE		0x14000
++#define AR9300_OTP_STATUS	0x15f18
++#define AR9300_OTP_STATUS_TYPE		0x7
++#define AR9300_OTP_STATUS_VALID		0x4
++#define AR9300_OTP_STATUS_ACCESS_BUSY	0x2
++#define AR9300_OTP_STATUS_SM_BUSY	0x1
++#define AR9300_OTP_READ_DATA	0x15f1c
++
+ /*
+  * DDR_CTRL block
+  */
diff --git a/target/linux/ar71xx/patches-3.8/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch b/target/linux/ar71xx/patches-3.8/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch
new file mode 100644
index 0000000..8c6fd40
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch
@@ -0,0 +1,31 @@
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -287,6 +287,16 @@ bool __init ar93xx_wmac_read_mac_address
+ 	return ret;
+ }
+ 
++void __init ath79_wmac_disable_2ghz(void)
++{
++	ath79_wmac_data.disable_2ghz = true;
++}
++
++void __init ath79_wmac_disable_5ghz(void)
++{
++	ath79_wmac_data.disable_5ghz = true;
++}
++
+ void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
+ {
+ 	if (soc_is_ar913x())
+--- a/arch/mips/ath79/dev-wmac.h
++++ b/arch/mips/ath79/dev-wmac.h
+@@ -14,6 +14,9 @@
+ 
+ void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
+ void ath79_register_wmac_simple(void);
++void ath79_wmac_disable_2ghz(void);
++void ath79_wmac_disable_5ghz(void);
++
+ bool ar93xx_wmac_read_mac_address(u8 *dest);
+ 
+ #endif /* _ATH79_DEV_WMAC_H */
diff --git a/target/linux/ar71xx/patches-3.8/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.8/601-MIPS-ath79-add-more-register-defines.patch
new file mode 100644
index 0000000..d9cdc9f
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/601-MIPS-ath79-add-more-register-defines.patch
@@ -0,0 +1,349 @@
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -21,6 +21,10 @@
+ #include <linux/bitops.h>
+ 
+ #define AR71XX_APB_BASE		0x18000000
++#define AR71XX_GE0_BASE		0x19000000
++#define AR71XX_GE0_SIZE		0x10000
++#define AR71XX_GE1_BASE		0x1a000000
++#define AR71XX_GE1_SIZE		0x10000
+ #define AR71XX_EHCI_BASE	0x1b000000
+ #define AR71XX_EHCI_SIZE	0x1000
+ #define AR71XX_OHCI_BASE	0x1c000000
+@@ -40,6 +44,8 @@
+ #define AR71XX_PLL_SIZE		0x100
+ #define AR71XX_RESET_BASE	(AR71XX_APB_BASE + 0x00060000)
+ #define AR71XX_RESET_SIZE	0x100
++#define AR71XX_MII_BASE		(AR71XX_APB_BASE + 0x00070000)
++#define AR71XX_MII_SIZE		0x100
+ 
+ #define AR71XX_PCI_MEM_BASE	0x10000000
+ #define AR71XX_PCI_MEM_SIZE	0x07000000
+@@ -82,15 +88,21 @@
+ 
+ #define AR933X_UART_BASE	(AR71XX_APB_BASE + 0x00020000)
+ #define AR933X_UART_SIZE	0x14
++#define AR933X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
++#define AR933X_GMAC_SIZE	0x04
+ #define AR933X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+ #define AR933X_WMAC_SIZE	0x20000
+ #define AR933X_EHCI_BASE	0x1b000000
+ #define AR933X_EHCI_SIZE	0x1000
+ 
++#define AR934X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
++#define AR934X_GMAC_SIZE	0x14
+ #define AR934X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+ #define AR934X_WMAC_SIZE	0x20000
+ #define AR934X_EHCI_BASE	0x1b000000
+ #define AR934X_EHCI_SIZE	0x200
++#define AR934X_NFC_BASE		0x1b000200
++#define AR934X_NFC_SIZE		0xb8
+ #define AR934X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
+ #define AR934X_SRIF_SIZE	0x1000
+ 
+@@ -107,11 +119,15 @@
+ #define QCA955X_PCI_CTRL_BASE1	(AR71XX_APB_BASE + 0x00280000)
+ #define QCA955X_PCI_CTRL_SIZE	0x100
+ 
++#define QCA955X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
++#define QCA955X_GMAC_SIZE	0x40
+ #define QCA955X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+ #define QCA955X_WMAC_SIZE	0x20000
+ #define QCA955X_EHCI0_BASE	0x1b000000
+ #define QCA955X_EHCI1_BASE	0x1b400000
+ #define QCA955X_EHCI_SIZE	0x1000
++#define QCA955X_NFC_BASE	0x1b800200
++#define QCA955X_NFC_SIZE	0xb8
+ 
+ #define AR9300_OTP_BASE		0x14000
+ #define AR9300_OTP_STATUS	0x15f18
+@@ -175,6 +191,9 @@
+ #define AR71XX_AHB_DIV_SHIFT		20
+ #define AR71XX_AHB_DIV_MASK		0x7
+ 
++#define AR71XX_ETH0_PLL_SHIFT		17
++#define AR71XX_ETH1_PLL_SHIFT		19
++
+ #define AR724X_PLL_REG_CPU_CONFIG	0x00
+ #define AR724X_PLL_REG_PCIE_CONFIG	0x18
+ 
+@@ -187,6 +206,8 @@
+ #define AR724X_DDR_DIV_SHIFT		22
+ #define AR724X_DDR_DIV_MASK		0x3
+ 
++#define AR7242_PLL_REG_ETH0_INT_CLOCK	0x2c
++
+ #define AR913X_PLL_REG_CPU_CONFIG	0x00
+ #define AR913X_PLL_REG_ETH_CONFIG	0x04
+ #define AR913X_PLL_REG_ETH0_INT_CLOCK	0x14
+@@ -199,6 +220,9 @@
+ #define AR913X_AHB_DIV_SHIFT		19
+ #define AR913X_AHB_DIV_MASK		0x1
+ 
++#define AR913X_ETH0_PLL_SHIFT		20
++#define AR913X_ETH1_PLL_SHIFT		22
++
+ #define AR933X_PLL_CPU_CONFIG_REG	0x00
+ #define AR933X_PLL_CLOCK_CTRL_REG	0x08
+ 
+@@ -220,6 +244,8 @@
+ #define AR934X_PLL_CPU_CONFIG_REG		0x00
+ #define AR934X_PLL_DDR_CONFIG_REG		0x04
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG		0x08
++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG	0x24
++#define AR934X_PLL_ETH_XMII_CONTROL_REG		0x2c
+ 
+ #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
+ #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
+@@ -252,9 +278,13 @@
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL	BIT(21)
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL	BIT(24)
+ 
++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL	BIT(6)
++
+ #define QCA955X_PLL_CPU_CONFIG_REG		0x00
+ #define QCA955X_PLL_DDR_CONFIG_REG		0x04
+ #define QCA955X_PLL_CLK_CTRL_REG		0x08
++#define QCA955X_PLL_ETH_XMII_CONTROL_REG	0x28
++#define QCA955X_PLL_ETH_SGMII_CONTROL_REG	0x48
+ 
+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
+@@ -379,16 +409,83 @@
+ #define AR913X_RESET_USB_HOST		BIT(5)
+ #define AR913X_RESET_USB_PHY		BIT(4)
+ 
++#define AR933X_RESET_GE1_MDIO		BIT(23)
++#define AR933X_RESET_GE0_MDIO		BIT(22)
++#define AR933X_RESET_GE1_MAC		BIT(13)
+ #define AR933X_RESET_WMAC		BIT(11)
++#define AR933X_RESET_GE0_MAC		BIT(9)
+ #define AR933X_RESET_USB_HOST		BIT(5)
+ #define AR933X_RESET_USB_PHY		BIT(4)
+ #define AR933X_RESET_USBSUS_OVERRIDE	BIT(3)
+ 
++#define AR934X_RESET_HOST		BIT(31)
++#define AR934X_RESET_SLIC		BIT(30)
++#define AR934X_RESET_HDMA		BIT(29)
++#define AR934X_RESET_EXTERNAL		BIT(28)
++#define AR934X_RESET_RTC		BIT(27)
++#define AR934X_RESET_PCIE_EP_INT	BIT(26)
++#define AR934X_RESET_CHKSUM_ACC		BIT(25)
++#define AR934X_RESET_FULL_CHIP		BIT(24)
++#define AR934X_RESET_GE1_MDIO		BIT(23)
++#define AR934X_RESET_GE0_MDIO		BIT(22)
++#define AR934X_RESET_CPU_NMI		BIT(21)
++#define AR934X_RESET_CPU_COLD		BIT(20)
++#define AR934X_RESET_HOST_RESET_INT	BIT(19)
++#define AR934X_RESET_PCIE_EP		BIT(18)
++#define AR934X_RESET_UART1		BIT(17)
++#define AR934X_RESET_DDR		BIT(16)
++#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
++#define AR934X_RESET_NANDF		BIT(14)
++#define AR934X_RESET_GE1_MAC		BIT(13)
++#define AR934X_RESET_ETH_SWITCH_ANALOG	BIT(12)
+ #define AR934X_RESET_USB_PHY_ANALOG	BIT(11)
++#define AR934X_RESET_HOST_DMA_INT	BIT(10)
++#define AR934X_RESET_GE0_MAC		BIT(9)
++#define AR934X_RESET_ETH_SWITCH		BIT(8)
++#define AR934X_RESET_PCIE_PHY		BIT(7)
++#define AR934X_RESET_PCIE		BIT(6)
+ #define AR934X_RESET_USB_HOST		BIT(5)
+ #define AR934X_RESET_USB_PHY		BIT(4)
+ #define AR934X_RESET_USBSUS_OVERRIDE	BIT(3)
++#define AR934X_RESET_LUT		BIT(2)
++#define AR934X_RESET_MBOX		BIT(1)
++#define AR934X_RESET_I2S		BIT(0)
++
++#define QCA955X_RESET_HOST		BIT(31)
++#define QCA955X_RESET_SLIC		BIT(30)
++#define QCA955X_RESET_HDMA		BIT(29)
++#define QCA955X_RESET_EXTERNAL		BIT(28)
++#define QCA955X_RESET_RTC		BIT(27)
++#define QCA955X_RESET_PCIE_EP_INT	BIT(26)
++#define QCA955X_RESET_CHKSUM_ACC	BIT(25)
++#define QCA955X_RESET_FULL_CHIP		BIT(24)
++#define QCA955X_RESET_GE1_MDIO		BIT(23)
++#define QCA955X_RESET_GE0_MDIO		BIT(22)
++#define QCA955X_RESET_CPU_NMI		BIT(21)
++#define QCA955X_RESET_CPU_COLD		BIT(20)
++#define QCA955X_RESET_HOST_RESET_INT	BIT(19)
++#define QCA955X_RESET_PCIE_EP		BIT(18)
++#define QCA955X_RESET_UART1		BIT(17)
++#define QCA955X_RESET_DDR		BIT(16)
++#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
++#define QCA955X_RESET_NANDF		BIT(14)
++#define QCA955X_RESET_GE1_MAC		BIT(13)
++#define QCA955X_RESET_SGMII_ANALOG	BIT(12)
++#define QCA955X_RESET_USB_PHY_ANALOG	BIT(11)
++#define QCA955X_RESET_HOST_DMA_INT	BIT(10)
++#define QCA955X_RESET_GE0_MAC		BIT(9)
++#define QCA955X_RESET_SGMII		BIT(8)
++#define QCA955X_RESET_PCIE_PHY		BIT(7)
++#define QCA955X_RESET_PCIE		BIT(6)
++#define QCA955X_RESET_USB_HOST		BIT(5)
++#define QCA955X_RESET_USB_PHY		BIT(4)
++#define QCA955X_RESET_USBSUS_OVERRIDE	BIT(3)
++#define QCA955X_RESET_LUT		BIT(2)
++#define QCA955X_RESET_MBOX		BIT(1)
++#define QCA955X_RESET_I2S		BIT(0)
+ 
++#define AR933X_BOOTSTRAP_MDIO_GPIO_EN	BIT(18)
++#define AR933X_BOOTSTRAP_EEPBUSY	BIT(4)
+ #define AR933X_BOOTSTRAP_REF_CLK_40	BIT(0)
+ 
+ #define AR934X_BOOTSTRAP_SW_OPTION8	BIT(23)
+@@ -530,6 +627,12 @@
+ #define AR71XX_GPIO_REG_INT_ENABLE	0x24
+ #define AR71XX_GPIO_REG_FUNC		0x28
+ 
++#define AR934X_GPIO_REG_OUT_FUNC0	0x2c
++#define AR934X_GPIO_REG_OUT_FUNC1	0x30
++#define AR934X_GPIO_REG_OUT_FUNC2	0x34
++#define AR934X_GPIO_REG_OUT_FUNC3	0x38
++#define AR934X_GPIO_REG_OUT_FUNC4	0x3c
++#define AR934X_GPIO_REG_OUT_FUNC5	0x40
+ #define AR934X_GPIO_REG_FUNC		0x6c
+ 
+ #define AR71XX_GPIO_COUNT		16
+@@ -561,4 +664,139 @@
+ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT	13
+ #define AR934X_SRIF_DPLL2_OUTDIV_MASK	0x7
+ 
++#define AR71XX_GPIO_FUNC_STEREO_EN		BIT(17)
++#define AR71XX_GPIO_FUNC_SLIC_EN		BIT(16)
++#define AR71XX_GPIO_FUNC_SPI_CS2_EN		BIT(13)
++#define AR71XX_GPIO_FUNC_SPI_CS1_EN		BIT(12)
++#define AR71XX_GPIO_FUNC_UART_EN		BIT(8)
++#define AR71XX_GPIO_FUNC_USB_OC_EN		BIT(4)
++#define AR71XX_GPIO_FUNC_USB_CLK_EN		BIT(0)
++
++#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN		BIT(19)
++#define AR724X_GPIO_FUNC_SPI_EN			BIT(18)
++#define AR724X_GPIO_FUNC_SPI_CS_EN2		BIT(14)
++#define AR724X_GPIO_FUNC_SPI_CS_EN1		BIT(13)
++#define AR724X_GPIO_FUNC_CLK_OBS5_EN		BIT(12)
++#define AR724X_GPIO_FUNC_CLK_OBS4_EN		BIT(11)
++#define AR724X_GPIO_FUNC_CLK_OBS3_EN		BIT(10)
++#define AR724X_GPIO_FUNC_CLK_OBS2_EN		BIT(9)
++#define AR724X_GPIO_FUNC_CLK_OBS1_EN		BIT(8)
++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN	BIT(7)
++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN	BIT(6)
++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN	BIT(5)
++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN	BIT(4)
++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN	BIT(3)
++#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN	BIT(2)
++#define AR724X_GPIO_FUNC_UART_EN		BIT(1)
++#define AR724X_GPIO_FUNC_JTAG_DISABLE		BIT(0)
++
++#define AR913X_GPIO_FUNC_WMAC_LED_EN		BIT(22)
++#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN		BIT(21)
++#define AR913X_GPIO_FUNC_I2S_REFCLKEN		BIT(20)
++#define AR913X_GPIO_FUNC_I2S_MCKEN		BIT(19)
++#define AR913X_GPIO_FUNC_I2S1_EN		BIT(18)
++#define AR913X_GPIO_FUNC_I2S0_EN		BIT(17)
++#define AR913X_GPIO_FUNC_SLIC_EN		BIT(16)
++#define AR913X_GPIO_FUNC_UART_RTSCTS_EN		BIT(9)
++#define AR913X_GPIO_FUNC_UART_EN		BIT(8)
++#define AR913X_GPIO_FUNC_USB_CLK_EN		BIT(4)
++
++#define AR933X_GPIO_FUNC_SPDIF2TCK		BIT(31)
++#define AR933X_GPIO_FUNC_SPDIF_EN		BIT(30)
++#define AR933X_GPIO_FUNC_I2SO_22_18_EN		BIT(29)
++#define AR933X_GPIO_FUNC_I2S_MCK_EN		BIT(27)
++#define AR933X_GPIO_FUNC_I2SO_EN		BIT(26)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL	BIT(25)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL	BIT(24)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT	BIT(23)
++#define AR933X_GPIO_FUNC_SPI_EN			BIT(18)
++#define AR933X_GPIO_FUNC_SPI_CS_EN2		BIT(14)
++#define AR933X_GPIO_FUNC_SPI_CS_EN1		BIT(13)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN	BIT(7)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN	BIT(6)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN	BIT(5)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN	BIT(4)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN	BIT(3)
++#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN	BIT(2)
++#define AR933X_GPIO_FUNC_UART_EN		BIT(1)
++#define AR933X_GPIO_FUNC_JTAG_DISABLE		BIT(0)
++
++#define AR934X_GPIO_FUNC_CLK_OBS7_EN		BIT(9)
++#define AR934X_GPIO_FUNC_CLK_OBS6_EN		BIT(8)
++#define AR934X_GPIO_FUNC_CLK_OBS5_EN		BIT(7)
++#define AR934X_GPIO_FUNC_CLK_OBS4_EN		BIT(6)
++#define AR934X_GPIO_FUNC_CLK_OBS3_EN		BIT(5)
++#define AR934X_GPIO_FUNC_CLK_OBS2_EN		BIT(4)
++#define AR934X_GPIO_FUNC_CLK_OBS1_EN		BIT(3)
++#define AR934X_GPIO_FUNC_CLK_OBS0_EN		BIT(2)
++#define AR934X_GPIO_FUNC_JTAG_DISABLE		BIT(1)
++
++#define AR934X_GPIO_OUT_GPIO		0x00
++
++/*
++ * MII_CTRL block
++ */
++#define AR71XX_MII_REG_MII0_CTRL	0x00
++#define AR71XX_MII_REG_MII1_CTRL	0x04
++
++#define AR71XX_MII_CTRL_IF_MASK		3
++#define AR71XX_MII_CTRL_SPEED_SHIFT	4
++#define AR71XX_MII_CTRL_SPEED_MASK	3
++#define AR71XX_MII_CTRL_SPEED_10	0
++#define AR71XX_MII_CTRL_SPEED_100	1
++#define AR71XX_MII_CTRL_SPEED_1000	2
++
++#define AR71XX_MII0_CTRL_IF_GMII	0
++#define AR71XX_MII0_CTRL_IF_MII		1
++#define AR71XX_MII0_CTRL_IF_RGMII	2
++#define AR71XX_MII0_CTRL_IF_RMII	3
++
++#define AR71XX_MII1_CTRL_IF_RGMII	0
++#define AR71XX_MII1_CTRL_IF_RMII	1
++
++/*
++ * AR933X GMAC interface
++ */
++#define AR933X_GMAC_REG_ETH_CFG		0x00
++
++#define AR933X_ETH_CFG_RGMII_GE0	BIT(0)
++#define AR933X_ETH_CFG_MII_GE0		BIT(1)
++#define AR933X_ETH_CFG_GMII_GE0		BIT(2)
++#define AR933X_ETH_CFG_MII_GE0_MASTER	BIT(3)
++#define AR933X_ETH_CFG_MII_GE0_SLAVE	BIT(4)
++#define AR933X_ETH_CFG_MII_GE0_ERR_EN	BIT(5)
++#define AR933X_ETH_CFG_SW_PHY_SWAP	BIT(7)
++#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP	BIT(8)
++#define AR933X_ETH_CFG_RMII_GE0		BIT(9)
++#define AR933X_ETH_CFG_RMII_GE0_SPD_10	0
++#define AR933X_ETH_CFG_RMII_GE0_SPD_100	BIT(10)
++
++/*
++ * AR934X GMAC Interface
++ */
++#define AR934X_GMAC_REG_ETH_CFG		0x00
++
++#define AR934X_ETH_CFG_RGMII_GMAC0	BIT(0)
++#define AR934X_ETH_CFG_MII_GMAC0	BIT(1)
++#define AR934X_ETH_CFG_GMII_GMAC0	BIT(2)
++#define AR934X_ETH_CFG_MII_GMAC0_MASTER	BIT(3)
++#define AR934X_ETH_CFG_MII_GMAC0_SLAVE	BIT(4)
++#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN	BIT(5)
++#define AR934X_ETH_CFG_SW_ONLY_MODE	BIT(6)
++#define AR934X_ETH_CFG_SW_PHY_SWAP	BIT(7)
++#define AR934X_ETH_CFG_SW_APB_ACCESS	BIT(9)
++#define AR934X_ETH_CFG_RMII_GMAC0	BIT(10)
++#define AR933X_ETH_CFG_MII_CNTL_SPEED	BIT(11)
++#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
++#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST	BIT(13)
++
++/*
++ * QCA955X GMAC Interface
++ */
++
++#define QCA955X_GMAC_REG_ETH_CFG	0x00
++
++#define QCA955X_ETH_CFG_RGMII_EN	BIT(0)
++#define QCA955X_ETH_CFG_GE0_SGMII	BIT(6)
++
+ #endif /* __ASM_MACH_AR71XX_REGS_H */
diff --git a/target/linux/ar71xx/patches-3.8/602-MIPS-ath79-add-openwrt-stuff.patch b/target/linux/ar71xx/patches-3.8/602-MIPS-ath79-add-openwrt-stuff.patch
new file mode 100644
index 0000000..da284e2
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/602-MIPS-ath79-add-openwrt-stuff.patch
@@ -0,0 +1,76 @@
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -106,6 +106,20 @@ config SOC_QCA955X
+ 	select PCI_AR724X if PCI
+ 	def_bool n
+ 
++config ATH79_DEV_M25P80
++	select ATH79_DEV_SPI
++	def_bool n
++
++config ATH79_DEV_AP9X_PCI
++	select ATH79_PCI_ATH9K_FIXUP
++	def_bool n
++
++config ATH79_DEV_DSA
++	def_bool n
++
++config ATH79_DEV_ETH
++	def_bool n
++
+ config PCI_AR724X
+ 	def_bool n
+ 
+@@ -115,6 +129,10 @@ config ATH79_DEV_GPIO_BUTTONS
+ config ATH79_DEV_LEDS_GPIO
+ 	def_bool n
+ 
++config ATH79_DEV_NFC
++	depends on (SOC_AR934X || SOC_QCA955X)
++	def_bool n
++
+ config ATH79_DEV_SPI
+ 	def_bool n
+ 
+@@ -125,4 +143,13 @@ config ATH79_DEV_WMAC
+ 	depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
+ 	def_bool n
+ 
++config ATH79_NVRAM
++	def_bool n
++
++config ATH79_PCI_ATH9K_FIXUP
++	def_bool n
++
++config ATH79_ROUTERBOOT
++	def_bool n
++
+ endif
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -17,13 +17,25 @@ obj-$(CONFIG_PCI)			+= pci.o
+ # Devices
+ #
+ obj-y					+= dev-common.o
++obj-$(CONFIG_ATH79_DEV_AP9X_PCI)	+= dev-ap9x-pci.o
++obj-$(CONFIG_ATH79_DEV_DSA)		+= dev-dsa.o
++obj-$(CONFIG_ATH79_DEV_ETH)		+= dev-eth.o
+ obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS)	+= dev-gpio-buttons.o
+ obj-$(CONFIG_ATH79_DEV_LEDS_GPIO)	+= dev-leds-gpio.o
++obj-$(CONFIG_ATH79_DEV_M25P80)		+= dev-m25p80.o
++obj-$(CONFIG_ATH79_DEV_NFC)		+= dev-nfc.o
+ obj-$(CONFIG_ATH79_DEV_SPI)		+= dev-spi.o
+ obj-$(CONFIG_ATH79_DEV_USB)		+= dev-usb.o
+ obj-$(CONFIG_ATH79_DEV_WMAC)		+= dev-wmac.o
+ 
+ #
++# Miscellaneous objects
++#
++obj-$(CONFIG_ATH79_NVRAM)		+= nvram.o
++obj-$(CONFIG_ATH79_PCI_ATH9K_FIXUP)	+= pci-ath9k-fixup.o
++obj-$(CONFIG_ATH79_ROUTERBOOT)		+= routerboot.o
++
++#
+ # Machines
+ #
+ obj-$(CONFIG_ATH79_MACH_AP121)		+= mach-ap121.o
diff --git a/target/linux/ar71xx/patches-3.8/603-MIPS-ath79-ap121-fixes.patch b/target/linux/ar71xx/patches-3.8/603-MIPS-ath79-ap121-fixes.patch
new file mode 100644
index 0000000..a51f587
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/603-MIPS-ath79-ap121-fixes.patch
@@ -0,0 +1,163 @@
+--- a/arch/mips/ath79/mach-ap121.c
++++ b/arch/mips/ath79/mach-ap121.c
+@@ -1,19 +1,21 @@
+ /*
+  *  Atheros AP121 board support
+  *
+- *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
++ *  Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+  *
+  *  This program is free software; you can redistribute it and/or modify it
+  *  under the terms of the GNU General Public License version 2 as published
+  *  by the Free Software Foundation.
+  */
+ 
+-#include "machtypes.h"
++#include "dev-eth.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
++#include "dev-m25p80.h"
+ #include "dev-spi.h"
+ #include "dev-usb.h"
+ #include "dev-wmac.h"
++#include "machtypes.h"
+ 
+ #define AP121_GPIO_LED_WLAN		0
+ #define AP121_GPIO_LED_USB		1
+@@ -24,7 +26,14 @@
+ #define AP121_KEYS_POLL_INTERVAL	20	/* msecs */
+ #define AP121_KEYS_DEBOUNCE_INTERVAL	(3 * AP121_KEYS_POLL_INTERVAL)
+ 
+-#define AP121_CAL_DATA_ADDR	0x1fff1000
++#define AP121_MAC0_OFFSET		0x0000
++#define AP121_MAC1_OFFSET		0x0006
++#define AP121_CALDATA_OFFSET		0x1000
++#define AP121_WMAC_MAC_OFFSET		0x1002
++
++#define AP121_MINI_GPIO_LED_WLAN	0
++#define AP121_MINI_GPIO_BTN_JUMPSTART	12
++#define AP121_MINI_GPIO_BTN_RESET	11
+ 
+ static struct gpio_led ap121_leds_gpio[] __initdata = {
+ 	{
+@@ -58,41 +67,78 @@ static struct gpio_keys_button ap121_gpi
+ 	}
+ };
+ 
+-static struct ath79_spi_controller_data ap121_spi0_data = {
+-	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+-	.cs_line = 0,
++static struct gpio_led ap121_mini_leds_gpio[] __initdata = {
++	{
++		.name		= "ap121:green:wlan",
++		.gpio		= AP121_MINI_GPIO_LED_WLAN,
++		.active_low	= 0,
++	},
+ };
+ 
+-static struct spi_board_info ap121_spi_info[] = {
++static struct gpio_keys_button ap121_mini_gpio_keys[] __initdata = {
+ 	{
+-		.bus_num	= 0,
+-		.chip_select	= 0,
+-		.max_speed_hz	= 25000000,
+-		.modalias	= "mx25l1606e",
+-		.controller_data = &ap121_spi0_data,
++		.desc		= "jumpstart button",
++		.type		= EV_KEY,
++		.code		= KEY_WPS_BUTTON,
++		.debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
++		.gpio		= AP121_MINI_GPIO_BTN_JUMPSTART,
++		.active_low	= 1,
++	},
++	{
++		.desc		= "reset button",
++		.type		= EV_KEY,
++		.code		= KEY_RESTART,
++		.debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
++		.gpio		= AP121_MINI_GPIO_BTN_RESET,
++		.active_low	= 1,
+ 	}
+ };
+ 
+-static struct ath79_spi_platform_data ap121_spi_data = {
+-	.bus_num	= 0,
+-	.num_chipselect	= 1,
+-};
++static void __init ap121_common_setup(void)
++{
++	u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
++
++	ath79_register_m25p80(NULL);
++	ath79_register_wmac(art + AP121_CALDATA_OFFSET,
++			    art + AP121_WMAC_MAC_OFFSET);
++
++	ath79_init_mac(ath79_eth0_data.mac_addr, art + AP121_MAC0_OFFSET, 0);
++	ath79_init_mac(ath79_eth1_data.mac_addr, art + AP121_MAC1_OFFSET, 0);
++
++	ath79_register_mdio(0, 0x0);
++
++	/* LAN ports */
++	ath79_register_eth(1);
++
++	/* WAN port */
++	ath79_register_eth(0);
++}
+ 
+ static void __init ap121_setup(void)
+ {
+-	u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR);
++	ap121_common_setup();
+ 
+ 	ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio),
+ 				 ap121_leds_gpio);
+ 	ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
+ 					ARRAY_SIZE(ap121_gpio_keys),
+ 					ap121_gpio_keys);
+-
+-	ath79_register_spi(&ap121_spi_data, ap121_spi_info,
+-			   ARRAY_SIZE(ap121_spi_info));
+ 	ath79_register_usb();
+-	ath79_register_wmac(cal_data, NULL);
+ }
+ 
+ MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
+ 	     ap121_setup);
++
++static void __init ap121_mini_setup(void)
++{
++	ap121_common_setup();
++
++	ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_mini_leds_gpio),
++				 ap121_mini_leds_gpio);
++	ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
++					ARRAY_SIZE(ap121_mini_gpio_keys),
++					ap121_mini_gpio_keys);
++}
++
++MIPS_MACHINE(ATH79_MACH_AP121_MINI, "AP121-MINI", "Atheros AP121-MINI",
++	     ap121_mini_setup);
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -5,9 +5,10 @@ menu "Atheros AR71XX/AR724X/AR913X machi
+ config ATH79_MACH_AP121
+ 	bool "Atheros AP121 reference board"
+ 	select SOC_AR933X
++	select ATH79_DEV_ETH
+ 	select ATH79_DEV_GPIO_BUTTONS
+ 	select ATH79_DEV_LEDS_GPIO
+-	select ATH79_DEV_SPI
++	select ATH79_DEV_M25P80
+ 	select ATH79_DEV_USB
+ 	select ATH79_DEV_WMAC
+ 	help
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -17,6 +17,7 @@
+ enum ath79_mach_type {
+ 	ATH79_MACH_GENERIC = 0,
+ 	ATH79_MACH_AP121,		/* Atheros AP121 reference board */
++	ATH79_MACH_AP121_MINI,		/* Atheros AP121-MINI reference board */
+ 	ATH79_MACH_AP136_010,		/* Atheros AP136-010 reference board */
+ 	ATH79_MACH_AP81,		/* Atheros AP81 reference board */
+ 	ATH79_MACH_DB120,		/* Atheros DB120 reference board */
diff --git a/target/linux/ar71xx/patches-3.8/604-MIPS-ath79-ap81-fixes.patch b/target/linux/ar71xx/patches-3.8/604-MIPS-ath79-ap81-fixes.patch
new file mode 100644
index 0000000..3cc012d
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/604-MIPS-ath79-ap81-fixes.patch
@@ -0,0 +1,128 @@
+--- a/arch/mips/ath79/mach-ap81.c
++++ b/arch/mips/ath79/mach-ap81.c
+@@ -9,12 +9,16 @@
+  *  by the Free Software Foundation.
+  */
+ 
+-#include "machtypes.h"
+-#include "dev-wmac.h"
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++
++#include "dev-eth.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
+-#include "dev-spi.h"
++#include "dev-m25p80.h"
+ #include "dev-usb.h"
++#include "dev-wmac.h"
++#include "machtypes.h"
+ 
+ #define AP81_GPIO_LED_STATUS	1
+ #define AP81_GPIO_LED_AOSS	3
+@@ -29,6 +33,37 @@
+ 
+ #define AP81_CAL_DATA_ADDR	0x1fff1000
+ 
++static struct mtd_partition ap81_partitions[] = {
++	{
++		.name		= "u-boot",
++		.offset		= 0,
++		.size		= 0x040000,
++		.mask_flags	= MTD_WRITEABLE,
++	}, {
++		.name		= "u-boot-env",
++		.offset		= 0x040000,
++		.size		= 0x010000,
++	}, {
++		.name		= "rootfs",
++		.offset		= 0x050000,
++		.size		= 0x500000,
++	}, {
++		.name		= "uImage",
++		.offset		= 0x550000,
++		.size		= 0x100000,
++	}, {
++		.name		= "ART",
++		.offset		= 0x650000,
++		.size		= 0x1b0000,
++		.mask_flags	= MTD_WRITEABLE,
++	}
++};
++
++static struct flash_platform_data ap81_flash_data = {
++	.parts		= ap81_partitions,
++	.nr_parts	= ARRAY_SIZE(ap81_partitions),
++};
++
+ static struct gpio_led ap81_leds_gpio[] __initdata = {
+ 	{
+ 		.name		= "ap81:green:status",
+@@ -67,26 +102,6 @@ static struct gpio_keys_button ap81_gpio
+ 	}
+ };
+ 
+-static struct ath79_spi_controller_data ap81_spi0_data = {
+-	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+-	.cs_line = 0,
+-};
+-
+-static struct spi_board_info ap81_spi_info[] = {
+-	{
+-		.bus_num	= 0,
+-		.chip_select	= 0,
+-		.max_speed_hz	= 25000000,
+-		.modalias	= "m25p64",
+-		.controller_data = &ap81_spi0_data,
+-	}
+-};
+-
+-static struct ath79_spi_platform_data ap81_spi_data = {
+-	.bus_num	= 0,
+-	.num_chipselect	= 1,
+-};
+-
+ static void __init ap81_setup(void)
+ {
+ 	u8 *cal_data = (u8 *) KSEG1ADDR(AP81_CAL_DATA_ADDR);
+@@ -96,10 +111,24 @@ static void __init ap81_setup(void)
+ 	ath79_register_gpio_keys_polled(-1, AP81_KEYS_POLL_INTERVAL,
+ 					ARRAY_SIZE(ap81_gpio_keys),
+ 					ap81_gpio_keys);
+-	ath79_register_spi(&ap81_spi_data, ap81_spi_info,
+-			   ARRAY_SIZE(ap81_spi_info));
++	ath79_register_m25p80(&ap81_flash_data);
+ 	ath79_register_wmac(cal_data, NULL);
+ 	ath79_register_usb();
++
++	ath79_register_mdio(0, 0x0);
++
++	ath79_init_mac(ath79_eth0_data.mac_addr, cal_data, 0);
++	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
++	ath79_eth0_data.speed = SPEED_100;
++	ath79_eth0_data.duplex = DUPLEX_FULL;
++	ath79_eth0_data.has_ar8216 = 1;
++
++	ath79_init_mac(ath79_eth1_data.mac_addr, cal_data, 1);
++	ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
++	ath79_eth1_data.phy_mask = 0x10;
++
++	ath79_register_eth(0);
++	ath79_register_eth(1);
+ }
+ 
+ MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board",
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -30,9 +30,10 @@ config ATH79_MACH_AP136
+ config ATH79_MACH_AP81
+ 	bool "Atheros AP81 reference board"
+ 	select SOC_AR913X
++	select ATH79_DEV_ETH
+ 	select ATH79_DEV_GPIO_BUTTONS
+ 	select ATH79_DEV_LEDS_GPIO
+-	select ATH79_DEV_SPI
++	select ATH79_DEV_M25P80
+ 	select ATH79_DEV_USB
+ 	select ATH79_DEV_WMAC
+ 	help
diff --git a/target/linux/ar71xx/patches-3.8/605-MIPS-ath79-db120-fixes.patch b/target/linux/ar71xx/patches-3.8/605-MIPS-ath79-db120-fixes.patch
new file mode 100644
index 0000000..0ca7861
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/605-MIPS-ath79-db120-fixes.patch
@@ -0,0 +1,209 @@
+--- a/arch/mips/ath79/mach-db120.c
++++ b/arch/mips/ath79/mach-db120.c
+@@ -2,7 +2,7 @@
+  * Atheros DB120 reference board support
+  *
+  * Copyright (c) 2011 Qualcomm Atheros
+- * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+  *
+  * Permission to use, copy, modify, and/or distribute this software for any
+  * purpose with or without fee is hereby granted, provided that the above
+@@ -19,16 +19,26 @@
+  */
+ 
+ #include <linux/pci.h>
++#include <linux/phy.h>
++#include <linux/platform_device.h>
+ #include <linux/ath9k_platform.h>
++#include <linux/ar8216_platform.h>
+ 
+-#include "machtypes.h"
++#include <asm/mach-ath79/ar71xx_regs.h>
++
++#include "common.h"
++#include "dev-ap9x-pci.h"
++#include "dev-eth.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
++#include "dev-m25p80.h"
++#include "dev-nfc.h"
+ #include "dev-spi.h"
+ #include "dev-usb.h"
+ #include "dev-wmac.h"
+-#include "pci.h"
++#include "machtypes.h"
+ 
++#define DB120_GPIO_LED_USB		11
+ #define DB120_GPIO_LED_WLAN_5G		12
+ #define DB120_GPIO_LED_WLAN_2G		13
+ #define DB120_GPIO_LED_STATUS		14
+@@ -39,8 +49,10 @@
+ #define DB120_KEYS_POLL_INTERVAL	20	/* msecs */
+ #define DB120_KEYS_DEBOUNCE_INTERVAL	(3 * DB120_KEYS_POLL_INTERVAL)
+ 
+-#define DB120_WMAC_CALDATA_OFFSET 0x1000
+-#define DB120_PCIE_CALDATA_OFFSET 0x5000
++#define DB120_MAC0_OFFSET		0
++#define DB120_MAC1_OFFSET		6
++#define DB120_WMAC_CALDATA_OFFSET	0x1000
++#define DB120_PCIE_CALDATA_OFFSET	0x5000
+ 
+ static struct gpio_led db120_leds_gpio[] __initdata = {
+ 	{
+@@ -63,6 +75,11 @@ static struct gpio_led db120_leds_gpio[]
+ 		.gpio		= DB120_GPIO_LED_WLAN_2G,
+ 		.active_low	= 1,
+ 	},
++	{
++		.name		= "db120:green:usb",
++		.gpio		= DB120_GPIO_LED_USB,
++		.active_low	= 1,
++	}
+ };
+ 
+ static struct gpio_keys_button db120_gpio_keys[] __initdata = {
+@@ -76,66 +93,85 @@ static struct gpio_keys_button db120_gpi
+ 	},
+ };
+ 
+-static struct ath79_spi_controller_data db120_spi0_data = {
+-	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+-	.cs_line = 0,
++static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = {
++	.mode = AR8327_PAD_MAC_RGMII,
++	.txclk_delay_en = true,
++	.rxclk_delay_en = true,
++	.txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
++	.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
+ };
+ 
+-static struct spi_board_info db120_spi_info[] = {
+-	{
+-		.bus_num	= 0,
+-		.chip_select	= 0,
+-		.max_speed_hz	= 25000000,
+-		.modalias	= "s25sl064a",
+-		.controller_data = &db120_spi0_data,
+-	}
++static struct ar8327_led_cfg db120_ar8327_led_cfg = {
++	.led_ctrl0 = 0x00000000,
++	.led_ctrl1 = 0xc737c737,
++	.led_ctrl2 = 0x00000000,
++	.led_ctrl3 = 0x00c30c00,
++	.open_drain = true,
+ };
+ 
+-static struct ath79_spi_platform_data db120_spi_data = {
+-	.bus_num	= 0,
+-	.num_chipselect	= 1,
++static struct ar8327_platform_data db120_ar8327_data = {
++	.pad0_cfg = &db120_ar8327_pad0_cfg,
++	.port0_cfg = {
++		.force_link = 1,
++		.speed = AR8327_PORT_SPEED_1000,
++		.duplex = 1,
++		.txpause = 1,
++		.rxpause = 1,
++	},
++	.led_cfg = &db120_ar8327_led_cfg,
+ };
+ 
+-#ifdef CONFIG_PCI
+-static struct ath9k_platform_data db120_ath9k_data;
+-
+-static int db120_pci_plat_dev_init(struct pci_dev *dev)
+-{
+-	switch (PCI_SLOT(dev->devfn)) {
+-	case 0:
+-		dev->dev.platform_data = &db120_ath9k_data;
+-		break;
+-	}
+-
+-	return 0;
+-}
+-
+-static void __init db120_pci_init(u8 *eeprom)
+-{
+-	memcpy(db120_ath9k_data.eeprom_data, eeprom,
+-	       sizeof(db120_ath9k_data.eeprom_data));
+-
+-	ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
+-	ath79_register_pci();
+-}
+-#else
+-static inline void db120_pci_init(void) {}
+-#endif /* CONFIG_PCI */
++static struct mdio_board_info db120_mdio0_info[] = {
++	{
++		.bus_id = "ag71xx-mdio.0",
++		.phy_addr = 0,
++		.platform_data = &db120_ar8327_data,
++	},
++};
+ 
+ static void __init db120_setup(void)
+ {
+ 	u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+ 
++	ath79_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO);
++	ath79_register_m25p80(NULL);
++
+ 	ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
+ 				 db120_leds_gpio);
+ 	ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
+ 					ARRAY_SIZE(db120_gpio_keys),
+ 					db120_gpio_keys);
+-	ath79_register_spi(&db120_spi_data, db120_spi_info,
+-			   ARRAY_SIZE(db120_spi_info));
+ 	ath79_register_usb();
+ 	ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
+-	db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
++	ap91_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL);
++
++	ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
++				   AR934X_ETH_CFG_SW_ONLY_MODE);
++
++	ath79_register_mdio(1, 0x0);
++	ath79_register_mdio(0, 0x0);
++
++	ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0);
++
++	mdiobus_register_board_info(db120_mdio0_info,
++				    ARRAY_SIZE(db120_mdio0_info));
++
++	/* GMAC0 is connected to an AR8327 switch */
++	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
++	ath79_eth0_data.phy_mask = BIT(0);
++	ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
++	ath79_eth0_pll_data.pll_1000 = 0x06000000;
++	ath79_register_eth(0);
++
++	/* GMAC1 is connected to the internal switch */
++	ath79_init_mac(ath79_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0);
++	ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
++	ath79_eth1_data.speed = SPEED_1000;
++	ath79_eth1_data.duplex = DUPLEX_FULL;
++
++	ath79_register_eth(1);
++
++	ath79_register_nfc();
+ }
+ 
+ MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -43,9 +43,12 @@ config ATH79_MACH_AP81
+ config ATH79_MACH_DB120
+ 	bool "Atheros DB120 reference board"
+ 	select SOC_AR934X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
+ 	select ATH79_DEV_GPIO_BUTTONS
+ 	select ATH79_DEV_LEDS_GPIO
+-	select ATH79_DEV_SPI
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_NFC
+ 	select ATH79_DEV_USB
+ 	select ATH79_DEV_WMAC
+ 	help
diff --git a/target/linux/ar71xx/patches-3.8/606-MIPS-ath79-pb44-fixes.patch b/target/linux/ar71xx/patches-3.8/606-MIPS-ath79-pb44-fixes.patch
new file mode 100644
index 0000000..f9ec775
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/606-MIPS-ath79-pb44-fixes.patch
@@ -0,0 +1,153 @@
+--- a/arch/mips/ath79/mach-pb44.c
++++ b/arch/mips/ath79/mach-pb44.c
+@@ -8,23 +8,48 @@
+  *  by the Free Software Foundation.
+  */
+ 
++#include <linux/delay.h>
+ #include <linux/init.h>
+ #include <linux/platform_device.h>
+ #include <linux/i2c.h>
+ #include <linux/i2c-gpio.h>
+ #include <linux/i2c/pcf857x.h>
++#include <linux/i2c/pcf857x.h>
++#include <linux/spi/flash.h>
++#include <linux/spi/vsc7385.h>
+ 
+-#include "machtypes.h"
++#include <asm/mach-ath79/ar71xx_regs.h>
++#include <asm/mach-ath79/ath79.h>
++
++#include "dev-eth.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
+ #include "dev-spi.h"
+ #include "dev-usb.h"
++#include "machtypes.h"
+ #include "pci.h"
+ 
+ #define PB44_GPIO_I2C_SCL	0
+ #define PB44_GPIO_I2C_SDA	1
+ 
++#define PB44_PCF8757_VSC7395_CS	0
++#define PB44_PCF8757_STEREO_CS	1
++#define PB44_PCF8757_SLIC_CS0	2
++#define PB44_PCF8757_SLIC_TEST	3
++#define PB44_PCF8757_SLIC_INT0	4
++#define PB44_PCF8757_SLIC_INT1	5
++#define PB44_PCF8757_SW_RESET	6
++#define PB44_PCF8757_SW_JUMP	8
++#define PB44_PCF8757_LED_JUMP1	9
++#define PB44_PCF8757_LED_JUMP2	10
++#define PB44_PCF8757_TP24	11
++#define PB44_PCF8757_TP25	12
++#define PB44_PCF8757_TP26	13
++#define PB44_PCF8757_TP27	14
++#define PB44_PCF8757_TP28	15
++
+ #define PB44_GPIO_EXP_BASE	16
++#define PB44_GPIO_VSC7395_CS	(PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS)
+ #define PB44_GPIO_SW_RESET	(PB44_GPIO_EXP_BASE + 6)
+ #define PB44_GPIO_SW_JUMP	(PB44_GPIO_EXP_BASE + 8)
+ #define PB44_GPIO_LED_JUMP1	(PB44_GPIO_EXP_BASE + 9)
+@@ -92,21 +117,66 @@ static struct ath79_spi_controller_data
+ 	.cs_line = 0,
+ };
+ 
++static struct ath79_spi_controller_data pb44_spi1_data = {
++	.cs_type = ATH79_SPI_CS_TYPE_GPIO,
++	.cs_line = PB44_GPIO_VSC7395_CS,
++};
++
++static void pb44_vsc7395_reset(void)
++{
++	ath79_device_reset_set(AR71XX_RESET_GE1_PHY);
++	udelay(10);
++	ath79_device_reset_clear(AR71XX_RESET_GE1_PHY);
++	mdelay(50);
++}
++
++static struct vsc7385_platform_data pb44_vsc7395_data = {
++	.reset		= pb44_vsc7395_reset,
++	.ucode_name	= "vsc7395_ucode_pb44.bin",
++	.mac_cfg = {
++		.tx_ipg		= 6,
++		.bit2		= 1,
++		.clk_sel	= 0,
++	},
++};
++
++static const char *pb44_part_probes[] = {
++	"RedBoot",
++	NULL,
++};
++
++static struct flash_platform_data pb44_flash_data = {
++	.part_probes	= pb44_part_probes,
++};
++
+ static struct spi_board_info pb44_spi_info[] = {
+ 	{
+ 		.bus_num	= 0,
+ 		.chip_select	= 0,
+ 		.max_speed_hz	= 25000000,
+ 		.modalias	= "m25p64",
++		.platform_data	= &pb44_flash_data,
+ 		.controller_data = &pb44_spi0_data,
+ 	},
++	{
++		.bus_num	= 0,
++		.chip_select	= 1,
++		.max_speed_hz	= 25000000,
++		.modalias	= "spi-vsc7385",
++		.platform_data	= &pb44_vsc7395_data,
++		.controller_data = &pb44_spi1_data,
++	}
+ };
+ 
+ static struct ath79_spi_platform_data pb44_spi_data = {
+ 	.bus_num		= 0,
+-	.num_chipselect		= 1,
++	.num_chipselect		= 2,
+ };
+ 
++#define PB44_WAN_PHYMASK	BIT(0)
++#define PB44_LAN_PHYMASK	0
++#define PB44_MDIO_PHYMASK	(PB44_LAN_PHYMASK | PB44_WAN_PHYMASK)
++
+ static void __init pb44_init(void)
+ {
+ 	i2c_register_board_info(0, pb44_i2c_board_info,
+@@ -122,6 +192,22 @@ static void __init pb44_init(void)
+ 			   ARRAY_SIZE(pb44_spi_info));
+ 	ath79_register_usb();
+ 	ath79_register_pci();
++
++	ath79_register_mdio(0, ~PB44_MDIO_PHYMASK);
++
++	ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
++	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
++	ath79_eth0_data.phy_mask = PB44_WAN_PHYMASK;
++
++	ath79_register_eth(0);
++
++	ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
++	ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
++	ath79_eth1_data.speed = SPEED_1000;
++	ath79_eth1_data.duplex = DUPLEX_FULL;
++	ath79_eth1_pll_data.pll_1000 = 0x110000;
++
++	ath79_register_eth(1);
+ }
+ 
+ MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -58,6 +58,7 @@ config ATH79_MACH_DB120
+ config ATH79_MACH_PB44
+ 	bool "Atheros PB44 reference board"
+ 	select SOC_AR71XX
++	select ATH79_DEV_ETH
+ 	select ATH79_DEV_GPIO_BUTTONS
+ 	select ATH79_DEV_LEDS_GPIO
+ 	select ATH79_DEV_SPI
diff --git a/target/linux/ar71xx/patches-3.8/607-MIPS-ath79-ubnt-xm-fixes.patch b/target/linux/ar71xx/patches-3.8/607-MIPS-ath79-ubnt-xm-fixes.patch
new file mode 100644
index 0000000..cbbe20b
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/607-MIPS-ath79-ubnt-xm-fixes.patch
@@ -0,0 +1,109 @@
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -70,9 +70,10 @@ config ATH79_MACH_PB44
+ config ATH79_MACH_UBNT_XM
+ 	bool "Ubiquiti Networks XM (rev 1.0) board"
+ 	select SOC_AR724X
++	select ATH79_DEV_AP9X_PCI if PCI
+ 	select ATH79_DEV_GPIO_BUTTONS
+ 	select ATH79_DEV_LEDS_GPIO
+-	select ATH79_DEV_SPI
++	select ATH79_DEV_M25P80
+ 	help
+ 	  Say 'Y' here if you want your kernel to support the
+ 	  Ubiquiti Networks XM (rev 1.0) board.
+--- a/arch/mips/ath79/mach-ubnt-xm.c
++++ b/arch/mips/ath79/mach-ubnt-xm.c
+@@ -16,10 +16,11 @@
+ 
+ #include <asm/mach-ath79/irq.h>
+ 
+-#include "machtypes.h"
++#include "dev-ap9x-pci.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
+-#include "dev-spi.h"
++#include "dev-m25p80.h"
++#include "machtypes.h"
+ #include "pci.h"
+ 
+ #define UBNT_XM_GPIO_LED_L1		0
+@@ -32,7 +33,7 @@
+ #define UBNT_XM_KEYS_POLL_INTERVAL	20
+ #define UBNT_XM_KEYS_DEBOUNCE_INTERVAL	(3 * UBNT_XM_KEYS_POLL_INTERVAL)
+ 
+-#define UBNT_XM_EEPROM_ADDR		(u8 *) KSEG1ADDR(0x1fff1000)
++#define UBNT_XM_EEPROM_ADDR		0x1fff1000
+ 
+ static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
+ 	{
+@@ -65,54 +66,10 @@ static struct gpio_keys_button ubnt_xm_g
+ 	}
+ };
+ 
+-static struct ath79_spi_controller_data ubnt_xm_spi0_data = {
+-	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+-	.cs_line = 0,
+-};
+-
+-static struct spi_board_info ubnt_xm_spi_info[] = {
+-	{
+-		.bus_num	= 0,
+-		.chip_select	= 0,
+-		.max_speed_hz	= 25000000,
+-		.modalias	= "mx25l6405d",
+-		.controller_data = &ubnt_xm_spi0_data,
+-	}
+-};
+-
+-static struct ath79_spi_platform_data ubnt_xm_spi_data = {
+-	.bus_num		= 0,
+-	.num_chipselect		= 1,
+-};
+-
+-#ifdef CONFIG_PCI
+-static struct ath9k_platform_data ubnt_xm_eeprom_data;
+-
+-static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev)
+-{
+-	switch (PCI_SLOT(dev->devfn)) {
+-	case 0:
+-		dev->dev.platform_data = &ubnt_xm_eeprom_data;
+-		break;
+-	}
+-
+-	return 0;
+-}
+-
+-static void __init ubnt_xm_pci_init(void)
+-{
+-	memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
+-	       sizeof(ubnt_xm_eeprom_data.eeprom_data));
+-
+-	ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init);
+-	ath79_register_pci();
+-}
+-#else
+-static inline void ubnt_xm_pci_init(void) {}
+-#endif /* CONFIG_PCI */
+-
+ static void __init ubnt_xm_init(void)
+ {
++	u8 *eeprom = (u8 *) KSEG1ADDR(UBNT_XM_EEPROM_ADDR);
++
+ 	ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
+ 				 ubnt_xm_leds_gpio);
+ 
+@@ -120,10 +77,8 @@ static void __init ubnt_xm_init(void)
+ 					ARRAY_SIZE(ubnt_xm_gpio_keys),
+ 					ubnt_xm_gpio_keys);
+ 
+-	ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info,
+-			   ARRAY_SIZE(ubnt_xm_spi_info));
+-
+-	ubnt_xm_pci_init();
++	ath79_register_m25p80(NULL);
++	ap91_pci_init(eeprom, NULL);
+ }
+ 
+ MIPS_MACHINE(ATH79_MACH_UBNT_XM,
diff --git a/target/linux/ar71xx/patches-3.8/608-MIPS-ath79-ubnt-xm-add-more-boards.patch b/target/linux/ar71xx/patches-3.8/608-MIPS-ath79-ubnt-xm-add-more-boards.patch
new file mode 100644
index 0000000..2e8fbdc
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/608-MIPS-ath79-ubnt-xm-add-more-boards.patch
@@ -0,0 +1,343 @@
+--- a/arch/mips/ath79/mach-ubnt-xm.c
++++ b/arch/mips/ath79/mach-ubnt-xm.c
+@@ -12,16 +12,22 @@
+ 
+ #include <linux/init.h>
+ #include <linux/pci.h>
++#include <linux/platform_device.h>
+ #include <linux/ath9k_platform.h>
++#include <linux/etherdevice.h>
++#include <linux/ar8216_platform.h>
+ 
+ #include <asm/mach-ath79/irq.h>
++#include <asm/mach-ath79/ar71xx_regs.h>
+ 
+ #include "dev-ap9x-pci.h"
++#include "dev-eth.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
+ #include "dev-m25p80.h"
++#include "dev-usb.h"
++#include "dev-wmac.h"
+ #include "machtypes.h"
+-#include "pci.h"
+ 
+ #define UBNT_XM_GPIO_LED_L1		0
+ #define UBNT_XM_GPIO_LED_L2		1
+@@ -37,19 +43,19 @@
+ 
+ static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
+ 	{
+-		.name		= "ubnt-xm:red:link1",
++		.name		= "ubnt:red:link1",
+ 		.gpio		= UBNT_XM_GPIO_LED_L1,
+ 		.active_low	= 0,
+ 	}, {
+-		.name		= "ubnt-xm:orange:link2",
++		.name		= "ubnt:orange:link2",
+ 		.gpio		= UBNT_XM_GPIO_LED_L2,
+ 		.active_low	= 0,
+ 	}, {
+-		.name		= "ubnt-xm:green:link3",
++		.name		= "ubnt:green:link3",
+ 		.gpio		= UBNT_XM_GPIO_LED_L3,
+ 		.active_low	= 0,
+ 	}, {
+-		.name		= "ubnt-xm:green:link4",
++		.name		= "ubnt:green:link4",
+ 		.gpio		= UBNT_XM_GPIO_LED_L4,
+ 		.active_low	= 0,
+ 	},
+@@ -66,9 +72,13 @@ static struct gpio_keys_button ubnt_xm_g
+ 	}
+ };
+ 
++#define UBNT_M_WAN_PHYMASK	BIT(4)
++
+ static void __init ubnt_xm_init(void)
+ {
+ 	u8 *eeprom = (u8 *) KSEG1ADDR(UBNT_XM_EEPROM_ADDR);
++	u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
++	u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN);
+ 
+ 	ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
+ 				 ubnt_xm_leds_gpio);
+@@ -79,9 +89,242 @@ static void __init ubnt_xm_init(void)
+ 
+ 	ath79_register_m25p80(NULL);
+ 	ap91_pci_init(eeprom, NULL);
++
++	ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK);
++	ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
++	ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
++	ath79_register_eth(0);
+ }
+ 
+ MIPS_MACHINE(ATH79_MACH_UBNT_XM,
+ 	     "UBNT-XM",
+ 	     "Ubiquiti Networks XM (rev 1.0) board",
+ 	     ubnt_xm_init);
++
++MIPS_MACHINE(ATH79_MACH_UBNT_BULLET_M, "UBNT-BM", "Ubiquiti Bullet M",
++	     ubnt_xm_init);
++
++static void __init ubnt_rocket_m_setup(void)
++{
++	ubnt_xm_init();
++	ath79_register_usb();
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_ROCKET_M, "UBNT-RM", "Ubiquiti Rocket M",
++	     ubnt_rocket_m_setup);
++
++static void __init ubnt_nano_m_setup(void)
++{
++	ubnt_xm_init();
++	ath79_register_eth(1);
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_NANO_M, "UBNT-NM", "Ubiquiti Nanostation M",
++	     ubnt_nano_m_setup);
++
++static struct gpio_led ubnt_airrouter_leds_gpio[] __initdata = {
++	{
++		.name		= "ubnt:green:globe",
++		.gpio		= 0,
++		.active_low	= 1,
++	}, {
++	        .name		= "ubnt:green:power",
++		.gpio		= 11,
++		.active_low	= 1,
++		.default_state  = LEDS_GPIO_DEFSTATE_ON,
++	}
++};
++
++static void __init ubnt_airrouter_setup(void)
++{
++	u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
++	u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
++
++	ath79_register_m25p80(NULL);
++	ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK);
++
++	ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
++	ath79_init_local_mac(ath79_eth1_data.mac_addr, mac1);
++
++	ath79_register_eth(1);
++	ath79_register_eth(0);
++	ath79_register_usb();
++
++	ap91_pci_init(ee, NULL);
++	ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_airrouter_leds_gpio),
++				 ubnt_airrouter_leds_gpio);
++
++	ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
++                                        ARRAY_SIZE(ubnt_xm_gpio_keys),
++                                        ubnt_xm_gpio_keys);
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_AIRROUTER, "UBNT-AR", "Ubiquiti AirRouter",
++	     ubnt_airrouter_setup);
++
++static struct gpio_led ubnt_unifi_leds_gpio[] __initdata = {
++	{
++		.name		= "ubnt:orange:dome",
++		.gpio		= 1,
++		.active_low	= 0,
++	}, {
++		.name		= "ubnt:green:dome",
++		.gpio		= 0,
++		.active_low	= 0,
++	}
++};
++
++static struct gpio_led ubnt_unifi_outdoor_leds_gpio[] __initdata = {
++	{
++		.name		= "ubnt:orange:front",
++		.gpio		= 1,
++		.active_low	= 0,
++	}, {
++		.name		= "ubnt:green:front",
++		.gpio		= 0,
++		.active_low	= 0,
++	}
++};
++
++static void __init ubnt_unifi_setup(void)
++{
++	u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000);
++	u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
++
++	ath79_register_m25p80(NULL);
++
++	ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK);
++
++	ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
++	ath79_register_eth(0);
++
++	ap91_pci_init(ee, NULL);
++
++	ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_leds_gpio),
++				 ubnt_unifi_leds_gpio);
++
++	ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
++                                        ARRAY_SIZE(ubnt_xm_gpio_keys),
++                                        ubnt_xm_gpio_keys);
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_UNIFI, "UBNT-UF", "Ubiquiti UniFi",
++	     ubnt_unifi_setup);
++
++
++#define UBNT_UNIFIOD_PRI_PHYMASK	BIT(4)
++#define UBNT_UNIFIOD_2ND_PHYMASK	(BIT(0) | BIT(1) | BIT(2) | BIT(3))
++
++static void __init ubnt_unifi_outdoor_setup(void)
++{
++	u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
++	u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN);
++	u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
++
++	ath79_register_m25p80(NULL);
++
++	ath79_register_mdio(0, ~(UBNT_UNIFIOD_PRI_PHYMASK |
++				 UBNT_UNIFIOD_2ND_PHYMASK));
++
++	ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
++	ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
++	ath79_register_eth(0);
++	ath79_register_eth(1);
++
++	ap91_pci_init(ee, NULL);
++
++	ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_outdoor_leds_gpio),
++				 ubnt_unifi_outdoor_leds_gpio);
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_UNIFI_OUTDOOR, "UBNT-U20",
++	     "Ubiquiti UniFiAP Outdoor",
++	     ubnt_unifi_outdoor_setup);
++
++static struct gpio_led ubnt_uap_pro_gpio_leds[] __initdata = {
++	{
++		.name		= "ubnt:white:dome",
++		.gpio		= 12,
++	}, {
++		.name		= "ubnt:blue:dome",
++		.gpio		= 13,
++	}
++};
++
++static struct gpio_keys_button uap_pro_gpio_keys[] __initdata = {
++	{
++		.desc			= "reset",
++		.type			= EV_KEY,
++		.code			= KEY_RESTART,
++		.debounce_interval	= UBNT_XM_KEYS_DEBOUNCE_INTERVAL,
++		.gpio			= 17,
++		.active_low		= 1,
++	}
++};
++
++static struct ar8327_pad_cfg uap_pro_ar8327_pad0_cfg = {
++	.mode = AR8327_PAD_MAC_RGMII,
++	.txclk_delay_en = true,
++	.rxclk_delay_en = true,
++	.txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
++	.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
++};
++
++static struct ar8327_platform_data uap_pro_ar8327_data = {
++	.pad0_cfg = &uap_pro_ar8327_pad0_cfg,
++	.port0_cfg = {
++		.force_link = 1,
++		.speed = AR8327_PORT_SPEED_1000,
++		.duplex = 1,
++		.txpause = 1,
++		.rxpause = 1,
++	},
++};
++
++static struct mdio_board_info uap_pro_mdio0_info[] = {
++	{
++		.bus_id = "ag71xx-mdio.0",
++		.phy_addr = 0,
++		.platform_data = &uap_pro_ar8327_data,
++	},
++};
++
++#define UAP_PRO_MAC0_OFFSET		0x0000
++#define UAP_PRO_MAC1_OFFSET		0x0006
++#define UAP_PRO_WMAC_CALDATA_OFFSET	0x1000
++#define UAP_PRO_PCI_CALDATA_OFFSET	0x5000
++
++static void __init ubnt_uap_pro_setup(void)
++{
++	u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000);
++
++	ath79_register_m25p80(NULL);
++
++	ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_uap_pro_gpio_leds),
++				 ubnt_uap_pro_gpio_leds);
++	ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
++                                        ARRAY_SIZE(uap_pro_gpio_keys),
++                                        uap_pro_gpio_keys);
++
++	ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL);
++	ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL);
++
++	ath79_register_mdio(0, 0x0);
++	mdiobus_register_board_info(uap_pro_mdio0_info,
++				    ARRAY_SIZE(uap_pro_mdio0_info));
++
++	ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
++	ath79_init_mac(ath79_eth0_data.mac_addr,
++		       eeprom + UAP_PRO_MAC0_OFFSET, 0);
++
++	/* GMAC0 is connected to an AR8327 switch */
++	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
++	ath79_eth0_data.phy_mask = BIT(0);
++	ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
++	ath79_eth0_pll_data.pll_1000 = 0x06000000;
++	ath79_register_eth(0);
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_UAP_PRO, "UAP-PRO", "Ubiquiti UniFi AP Pro",
++	     ubnt_uap_pro_setup);
++
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -68,12 +68,16 @@ config ATH79_MACH_PB44
+ 	  Atheros PB44 reference board.
+ 
+ config ATH79_MACH_UBNT_XM
+-	bool "Ubiquiti Networks XM (rev 1.0) board"
++	bool "Ubiquiti Networks XM/UniFi boards"
+ 	select SOC_AR724X
++	select SOC_AR934X
+ 	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
+ 	select ATH79_DEV_GPIO_BUTTONS
+ 	select ATH79_DEV_LEDS_GPIO
+ 	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
+ 	help
+ 	  Say 'Y' here if you want your kernel to support the
+ 	  Ubiquiti Networks XM (rev 1.0) board.
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -22,6 +22,13 @@ enum ath79_mach_type {
+ 	ATH79_MACH_AP81,		/* Atheros AP81 reference board */
+ 	ATH79_MACH_DB120,		/* Atheros DB120 reference board */
+ 	ATH79_MACH_PB44,		/* Atheros PB44 reference board */
++	ATH79_MACH_UBNT_AIRROUTER,	/* Ubiquiti AirRouter */
++	ATH79_MACH_UBNT_BULLET_M,	/* Ubiquiti Bullet M */
++	ATH79_MACH_UBNT_NANO_M, 	/* Ubiquiti NanoStation M */
++	ATH79_MACH_UBNT_ROCKET_M,	/* Ubiquiti Rocket M */
++	ATH79_MACH_UBNT_UAP_PRO,	/* Ubiquiti UniFi AP Pro */
++	ATH79_MACH_UBNT_UNIFI, 		/* Ubiquiti Unifi */
++	ATH79_MACH_UBNT_UNIFI_OUTDOOR,	/* Ubiquiti UnifiAP Outdoor */
+ 	ATH79_MACH_UBNT_XM,		/* Ubiquiti Networks XM board rev 1.0 */
+ };
+ 
diff --git a/target/linux/ar71xx/patches-3.8/609-MIPS-ath79-ap136-fixes.patch b/target/linux/ar71xx/patches-3.8/609-MIPS-ath79-ap136-fixes.patch
new file mode 100644
index 0000000..0a8fe0e
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/609-MIPS-ath79-ap136-fixes.patch
@@ -0,0 +1,317 @@
+--- a/arch/mips/ath79/mach-ap136.c
++++ b/arch/mips/ath79/mach-ap136.c
+@@ -18,23 +18,28 @@
+  *
+  */
+ 
+-#include <linux/pci.h>
+-#include <linux/ath9k_platform.h>
++#include <linux/platform_device.h>
++#include <linux/ar8216_platform.h>
+ 
+-#include "machtypes.h"
++#include <asm/mach-ath79/ar71xx_regs.h>
++
++#include "common.h"
++#include "dev-ap9x-pci.h"
+ #include "dev-gpio-buttons.h"
++#include "dev-eth.h"
+ #include "dev-leds-gpio.h"
+-#include "dev-spi.h"
++#include "dev-m25p80.h"
++#include "dev-nfc.h"
+ #include "dev-usb.h"
+ #include "dev-wmac.h"
+-#include "pci.h"
++#include "machtypes.h"
+ 
+-#define AP136_GPIO_LED_STATUS_RED	14
+-#define AP136_GPIO_LED_STATUS_GREEN	19
+ #define AP136_GPIO_LED_USB		4
+-#define AP136_GPIO_LED_WLAN_2G		13
+ #define AP136_GPIO_LED_WLAN_5G		12
++#define AP136_GPIO_LED_WLAN_2G		13
++#define AP136_GPIO_LED_STATUS_RED	14
+ #define AP136_GPIO_LED_WPS_RED		15
++#define AP136_GPIO_LED_STATUS_GREEN	19
+ #define AP136_GPIO_LED_WPS_GREEN	20
+ 
+ #define AP136_GPIO_BTN_WPS		16
+@@ -43,37 +48,39 @@
+ #define AP136_KEYS_POLL_INTERVAL	20	/* msecs */
+ #define AP136_KEYS_DEBOUNCE_INTERVAL	(3 * AP136_KEYS_POLL_INTERVAL)
+ 
+-#define AP136_WMAC_CALDATA_OFFSET 0x1000
+-#define AP136_PCIE_CALDATA_OFFSET 0x5000
++#define AP136_MAC0_OFFSET		0
++#define AP136_MAC1_OFFSET		6
++#define AP136_WMAC_CALDATA_OFFSET	0x1000
++#define AP136_PCIE_CALDATA_OFFSET	0x5000
+ 
+ static struct gpio_led ap136_leds_gpio[] __initdata = {
+ 	{
+-		.name		= "qca:green:status",
++		.name		= "ap136:green:status",
+ 		.gpio		= AP136_GPIO_LED_STATUS_GREEN,
+ 		.active_low	= 1,
+ 	},
+ 	{
+-		.name		= "qca:red:status",
++		.name		= "ap136:red:status",
+ 		.gpio		= AP136_GPIO_LED_STATUS_RED,
+ 		.active_low	= 1,
+ 	},
+ 	{
+-		.name		= "qca:green:wps",
++		.name		= "ap136:green:wps",
+ 		.gpio		= AP136_GPIO_LED_WPS_GREEN,
+ 		.active_low	= 1,
+ 	},
+ 	{
+-		.name		= "qca:red:wps",
++		.name		= "ap136:red:wps",
+ 		.gpio		= AP136_GPIO_LED_WPS_RED,
+ 		.active_low	= 1,
+ 	},
+ 	{
+-		.name		= "qca:red:wlan-2g",
++		.name		= "ap136:red:wlan-2g",
+ 		.gpio		= AP136_GPIO_LED_WLAN_2G,
+ 		.active_low	= 1,
+ 	},
+ 	{
+-		.name		= "qca:red:usb",
++		.name		= "ap136:red:usb",
+ 		.gpio		= AP136_GPIO_LED_USB,
+ 		.active_low	= 1,
+ 	}
+@@ -98,65 +105,158 @@ static struct gpio_keys_button ap136_gpi
+ 	},
+ };
+ 
+-static struct ath79_spi_controller_data ap136_spi0_data = {
+-	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+-	.cs_line = 0,
++static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg;
++static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg;
++
++static struct ar8327_platform_data ap136_ar8327_data = {
++	.pad0_cfg = &ap136_ar8327_pad0_cfg,
++	.pad6_cfg = &ap136_ar8327_pad6_cfg,
++	.port0_cfg = {
++		.force_link = 1,
++		.speed = AR8327_PORT_SPEED_1000,
++		.duplex = 1,
++		.txpause = 1,
++		.rxpause = 1,
++	},
++	.port6_cfg = {
++		.force_link = 1,
++		.speed = AR8327_PORT_SPEED_1000,
++		.duplex = 1,
++		.txpause = 1,
++		.rxpause = 1,
++	},
+ };
+ 
+-static struct spi_board_info ap136_spi_info[] = {
++static struct mdio_board_info ap136_mdio0_info[] = {
+ 	{
+-		.bus_num	= 0,
+-		.chip_select	= 0,
+-		.max_speed_hz	= 25000000,
+-		.modalias	= "mx25l6405d",
+-		.controller_data = &ap136_spi0_data,
+-	}
++		.bus_id = "ag71xx-mdio.0",
++		.phy_addr = 0,
++		.platform_data = &ap136_ar8327_data,
++	},
+ };
+ 
+-static struct ath79_spi_platform_data ap136_spi_data = {
+-	.bus_num	= 0,
+-	.num_chipselect	= 1,
+-};
++static void __init ap136_gmac_setup(void)
++{
++	void __iomem *base;
++	u32 t;
+ 
+-#ifdef CONFIG_PCI
+-static struct ath9k_platform_data ap136_ath9k_data;
++	base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
+ 
+-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
+-{
+-	if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
+-		dev->dev.platform_data = &ap136_ath9k_data;
++	t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
+ 
+-	return 0;
+-}
++	t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
++	t |= QCA955X_ETH_CFG_RGMII_EN;
+ 
+-static void __init ap136_pci_init(u8 *eeprom)
+-{
+-	memcpy(ap136_ath9k_data.eeprom_data, eeprom,
+-	       sizeof(ap136_ath9k_data.eeprom_data));
++	__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
+ 
+-	ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
+-	ath79_register_pci();
++	iounmap(base);
+ }
+-#else
+-static inline void ap136_pci_init(void) {}
+-#endif /* CONFIG_PCI */
+ 
+-static void __init ap136_setup(void)
++static void __init ap136_common_setup(void)
+ {
+ 	u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+ 
++	ath79_register_m25p80(NULL);
++
+ 	ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
+ 				 ap136_leds_gpio);
+ 	ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
+ 					ARRAY_SIZE(ap136_gpio_keys),
+ 					ap136_gpio_keys);
+-	ath79_register_spi(&ap136_spi_data, ap136_spi_info,
+-			   ARRAY_SIZE(ap136_spi_info));
++
+ 	ath79_register_usb();
+-	ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
+-	ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
++	ath79_register_nfc();
++
++	ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
++	ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
++
++	ap136_gmac_setup();
++
++	ath79_register_mdio(0, 0x0);
++
++	ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
++
++	mdiobus_register_board_info(ap136_mdio0_info,
++				    ARRAY_SIZE(ap136_mdio0_info));
++
++	/* GMAC0 is connected to the RMGII interface */
++	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
++	ath79_eth0_data.phy_mask = BIT(0);
++	ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
++
++	ath79_register_eth(0);
++
++	/* GMAC1 is connected tot eh SGMII interface */
++	ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
++	ath79_eth1_data.speed = SPEED_1000;
++	ath79_eth1_data.duplex = DUPLEX_FULL;
++
++	ath79_register_eth(1);
++}
++
++static void __init ap136_010_setup(void)
++{
++	/* GMAC0 of the AR8327 switch is connected to GMAC0 via RGMII */
++	ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII;
++	ap136_ar8327_pad0_cfg.txclk_delay_en = true;
++	ap136_ar8327_pad0_cfg.rxclk_delay_en = true;
++	ap136_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
++	ap136_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
++
++	/* GMAC6 of the AR8327 switch is connected to GMAC1 via SGMII */
++	ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
++	ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
++	ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0;
++
++	ath79_eth0_pll_data.pll_1000 = 0xa6000000;
++	ath79_eth1_pll_data.pll_1000 = 0x03000101;
++
++	ap136_common_setup();
+ }
+ 
+ MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
+ 	     "Atheros AP136-010 reference board",
+-	     ap136_setup);
++	     ap136_010_setup);
++
++static void __init ap136_020_setup(void)
++{
++	/* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */
++	ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII;
++	ap136_ar8327_pad0_cfg.sgmii_delay_en = true;
++
++	/* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */
++	ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII;
++	ap136_ar8327_pad6_cfg.txclk_delay_en = true;
++	ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
++	ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
++	ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
++
++	ath79_eth0_pll_data.pll_1000 = 0x56000000;
++	ath79_eth1_pll_data.pll_1000 = 0x03000101;
++
++	ap136_common_setup();
++}
++
++MIPS_MACHINE(ATH79_MACH_AP136_020, "AP136-020",
++	     "Atheros AP136-020 reference board",
++	     ap136_020_setup);
++
++/*
++ * AP135-020 is similar to AP136-020, any future AP135 specific init
++ * code can be added here.
++ */
++static void __init ap135_020_setup(void)
++{
++	ap136_leds_gpio[0].name = "ap135:green:status";
++	ap136_leds_gpio[1].name = "ap135:red:status";
++	ap136_leds_gpio[2].name = "ap135:green:wps";
++	ap136_leds_gpio[3].name = "ap135:red:wps";
++	ap136_leds_gpio[4].name = "ap135:red:wlan-2g";
++	ap136_leds_gpio[5].name = "ap135:red:usb";
++
++	ap136_020_setup();
++}
++
++MIPS_MACHINE(ATH79_MACH_AP135_020, "AP135-020",
++	     "Atheros AP135-020 reference board",
++	     ap135_020_setup);
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -18,7 +18,9 @@ enum ath79_mach_type {
+ 	ATH79_MACH_GENERIC = 0,
+ 	ATH79_MACH_AP121,		/* Atheros AP121 reference board */
+ 	ATH79_MACH_AP121_MINI,		/* Atheros AP121-MINI reference board */
++	ATH79_MACH_AP135_020,		/* Atheros AP135-020 reference board */
+ 	ATH79_MACH_AP136_010,		/* Atheros AP136-010 reference board */
++	ATH79_MACH_AP136_020,		/* Atheros AP136-020 reference board */
+ 	ATH79_MACH_AP81,		/* Atheros AP81 reference board */
+ 	ATH79_MACH_DB120,		/* Atheros DB120 reference board */
+ 	ATH79_MACH_PB44,		/* Atheros PB44 reference board */
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -16,16 +16,17 @@ config ATH79_MACH_AP121
+ 	  Atheros AP121 reference board.
+ 
+ config ATH79_MACH_AP136
+-	bool "Atheros AP136 reference board"
++	bool "Atheros AP136/AP135 reference board"
+ 	select SOC_QCA955X
+ 	select ATH79_DEV_GPIO_BUTTONS
+ 	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_NFC
+ 	select ATH79_DEV_SPI
+ 	select ATH79_DEV_USB
+ 	select ATH79_DEV_WMAC
+ 	help
+ 	  Say 'Y' here if you want your kernel to support the
+-	  Atheros AP136 reference board.
++	  Atheros AP136 or AP135 reference boards.
+ 
+ config ATH79_MACH_AP81
+ 	bool "Atheros AP81 reference board"
diff --git a/target/linux/ar71xx/patches-3.8/610-MIPS-ath79-openwrt-machines.patch b/target/linux/ar71xx/patches-3.8/610-MIPS-ath79-openwrt-machines.patch
new file mode 100644
index 0000000..73253bb
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/610-MIPS-ath79-openwrt-machines.patch
@@ -0,0 +1,854 @@
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -16,22 +16,112 @@
+ 
+ enum ath79_mach_type {
+ 	ATH79_MACH_GENERIC = 0,
++	ATH79_MACH_ALFA_AP96,		/* ALFA Network AP96 board */
++	ATH79_MACH_ALFA_NX,		/* ALFA Network N2/N5 board */
++	ATH79_MACH_ALL0258N,		/* Allnet ALL0258N */
++	ATH79_MACH_ALL0305,		/* Allnet ALL0305 */
++	ATH79_MACH_ALL0315N,		/* Allnet ALL0315N */
++	ATH79_MACH_AP113,		/* Atheros AP113 reference board */
+ 	ATH79_MACH_AP121,		/* Atheros AP121 reference board */
+ 	ATH79_MACH_AP121_MINI,		/* Atheros AP121-MINI reference board */
+ 	ATH79_MACH_AP135_020,		/* Atheros AP135-020 reference board */
+ 	ATH79_MACH_AP136_010,		/* Atheros AP136-010 reference board */
+ 	ATH79_MACH_AP136_020,		/* Atheros AP136-020 reference board */
+ 	ATH79_MACH_AP81,		/* Atheros AP81 reference board */
++	ATH79_MACH_AP83,		/* Atheros AP83 */
++	ATH79_MACH_AP96,		/* Atheros AP96 */
++	ATH79_MACH_AW_NR580,		/* AzureWave AW-NR580 */
++	ATH79_MACH_CAP4200AG,		/* Senao CAP4200AG */
+ 	ATH79_MACH_DB120,		/* Atheros DB120 reference board */
+ 	ATH79_MACH_PB44,		/* Atheros PB44 reference board */
++	ATH79_MACH_DIR_600_A1,		/* D-Link DIR-600 rev. A1 */
++	ATH79_MACH_DIR_615_C1,		/* D-Link DIR-615 rev. C1 */
++	ATH79_MACH_DIR_615_E4,		/* D-Link DIR-615 rev. E4 */
++	ATH79_MACH_DIR_825_B1,		/* D-Link DIR-825 rev. B1 */
++	ATH79_MACH_EW_DORIN,		/* embedded wireless Dorin Platform */
++	ATH79_MACH_EW_DORIN_ROUTER,	/* embedded wireless Dorin Router Platform */
++	ATH79_MACH_EAP7660D,		/* Senao EAP7660D */
++	ATH79_MACH_JA76PF,		/* jjPlus JA76PF */
++	ATH79_MACH_JA76PF2,		/* jjPlus JA76PF2 */
++	ATH79_MACH_JWAP003,		/* jjPlus JWAP003 */
++	ATH79_MACH_HORNET_UB,		/* ALFA Networks Hornet-UB */
++	ATH79_MACH_MR600,		/* OpenMesh MR600 */
++	ATH79_MACH_MZK_W04NU,		/* Planex MZK-W04NU */
++	ATH79_MACH_MZK_W300NH,		/* Planex MZK-W300NH */
++	ATH79_MACH_NBG460N,		/* Zyxel NBG460N/550N/550NH */
++	ATH79_MACH_OM2P_HS,		/* OpenMesh OM2P-HS */
++	ATH79_MACH_OM2P_LC,		/* OpenMesh OM2P-LC */
++	ATH79_MACH_OM2P,		/* OpenMesh OM2P */
++	ATH79_MACH_PB42,		/* Atheros PB42 */
++	ATH79_MACH_PB92,		/* Atheros PB92 */
++	ATH79_MACH_RB_411,		/* MikroTik RouterBOARD 411/411A/411AH */
++	ATH79_MACH_RB_411U,		/* MikroTik RouterBOARD 411U */
++	ATH79_MACH_RB_433,		/* MikroTik RouterBOARD 433/433AH */
++	ATH79_MACH_RB_433U,		/* MikroTik RouterBOARD 433UAH */
++	ATH79_MACH_RB_435G,		/* MikroTik RouterBOARD 435G */
++	ATH79_MACH_RB_450G,		/* MikroTik RouterBOARD 450G */
++	ATH79_MACH_RB_450,		/* MikroTik RouterBOARD 450 */
++	ATH79_MACH_RB_493,		/* Mikrotik RouterBOARD 493/493AH */
++	ATH79_MACH_RB_493G,		/* Mikrotik RouterBOARD 493G */
++	ATH79_MACH_RB_750,		/* MikroTik RouterBOARD 750 */
++	ATH79_MACH_RB_750G_R3,		/* MikroTik RouterBOARD 750GL */
++	ATH79_MACH_RB_751,		/* MikroTik RouterBOARD 751 */
++	ATH79_MACH_RB_751G,		/* Mikrotik RouterBOARD 751G */
++	ATH79_MACH_RB_2011G,		/* Mikrotik RouterBOARD 2011UAS-2HnD */
++	ATH79_MACH_RB_2011L,		/* Mikrotik RouterBOARD 2011L */
++	ATH79_MACH_RW2458N,		/* Redwave RW2458N */
++	ATH79_MACH_TEW_632BRP,		/* TRENDnet TEW-632BRP */
++	ATH79_MACH_TEW_673GRU,		/* TRENDnet TEW-673GRU */
++	ATH79_MACH_TEW_712BR,		/* TRENDnet TEW-712BR */
++	ATH79_MACH_TL_MR11U,		/* TP-LINK TL-MR11U */
++	ATH79_MACH_TL_MR3020,		/* TP-LINK TL-MR3020 */
++	ATH79_MACH_TL_MR3040,		/* TP-LINK TL-MR3040 */
++	ATH79_MACH_TL_MR3220,		/* TP-LINK TL-MR3220 */
++	ATH79_MACH_TL_MR3220_V2,	/* TP-LINK TL-MR3220 v2 */
++	ATH79_MACH_TL_MR3420,		/* TP-LINK TL-MR3420 */
++	ATH79_MACH_TL_WA7510N_V1,	/* TP-LINK TL-WA7510N v1*/
++	ATH79_MACH_TL_WA901ND,		/* TP-LINK TL-WA901ND */
++	ATH79_MACH_TL_WA901ND_V2,	/* TP-LINK TL-WA901ND v2 */
++	ATH79_MACH_TL_WDR4300,		/* TP-LINK TL-WDR4300 */
++	ATH79_MACH_TL_WR1041N_V2,	/* TP-LINK TL-WR1041N v2 */
++	ATH79_MACH_TL_WR1043ND,		/* TP-LINK TL-WR1043ND */
++	ATH79_MACH_TL_WR2543N,		/* TP-LINK TL-WR2543N/ND */
++	ATH79_MACH_TL_WR703N,		/* TP-LINK TL-WR703N */
++	ATH79_MACH_TL_WR741ND,		/* TP-LINK TL-WR741ND */
++	ATH79_MACH_TL_WR741ND_V4,	/* TP-LINK TL-WR741ND  v4*/
++	ATH79_MACH_TL_WR841N_V1,	/* TP-LINK TL-WR841N v1 */
++	ATH79_MACH_TL_WR841N_V7,	/* TP-LINK TL-WR841N/ND v7 */
++	ATH79_MACH_TL_WR841N_V8,	/* TP-LINK TL-WR841N/ND v8 */
++	ATH79_MACH_TL_WR941ND,		/* TP-LINK TL-WR941ND */
+ 	ATH79_MACH_UBNT_AIRROUTER,	/* Ubiquiti AirRouter */
+ 	ATH79_MACH_UBNT_BULLET_M,	/* Ubiquiti Bullet M */
++	ATH79_MACH_UBNT_LSSR71,		/* Ubiquiti LS-SR71 */
++	ATH79_MACH_UBNT_LSX,		/* Ubiquiti LSX */
+ 	ATH79_MACH_UBNT_NANO_M, 	/* Ubiquiti NanoStation M */
+ 	ATH79_MACH_UBNT_ROCKET_M,	/* Ubiquiti Rocket M */
++	ATH79_MACH_UBNT_RSPRO,		/* Ubiquiti RouterStation Pro */
++	ATH79_MACH_UBNT_RS,		/* Ubiquiti RouterStation */
+ 	ATH79_MACH_UBNT_UAP_PRO,	/* Ubiquiti UniFi AP Pro */
+ 	ATH79_MACH_UBNT_UNIFI, 		/* Ubiquiti Unifi */
+ 	ATH79_MACH_UBNT_UNIFI_OUTDOOR,	/* Ubiquiti UnifiAP Outdoor */
+ 	ATH79_MACH_UBNT_XM,		/* Ubiquiti Networks XM board rev 1.0 */
++	ATH79_MACH_WHR_G301N,		/* Buffalo WHR-G301N */
++	ATH79_MACH_WHR_HP_G300N,	/* Buffalo WHR-HP-G300N */
++	ATH79_MACH_WHR_HP_GN,		/* Buffalo WHR-HP-GN */
++	ATH79_MACH_WLAE_AG300N,		/* Buffalo WLAE-AG300N */
++	ATH79_MACH_WNDR3700,		/* NETGEAR WNDR3700/WNDR3800/WNDRMAC */
++	ATH79_MACH_WNDR4300,		/* NETGEAR WNDR4300 */
++	ATH79_MACH_WNR2000,		/* NETGEAR WNR2000 */
++	ATH79_MACH_WP543,		/* Compex WP543 */
++	ATH79_MACH_WPE72,		/* Compex WPE72 */
++	ATH79_MACH_WRT160NL,		/* Linksys WRT160NL */
++	ATH79_MACH_WRT400N,		/* Linksys WRT400N */
++	ATH79_MACH_WZR_HP_AG300H,	/* Buffalo WZR-HP-AG300H */
++	ATH79_MACH_WZR_HP_G300NH,	/* Buffalo WZR-HP-G300NH */
++	ATH79_MACH_WZR_HP_G300NH2,	/* Buffalo WZR-HP-G300NH2 */
++	ATH79_MACH_WZR_HP_G450H,	/* Buffalo WZR-HP-G450H */
++	ATH79_MACH_ZCN_1523H_2,		/* Zcomax ZCN-1523H-2-xx */
++	ATH79_MACH_ZCN_1523H_5,		/* Zcomax ZCN-1523H-5-xx */
+ };
+ 
+ #endif /* _ATH79_MACHTYPE_H */
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -2,6 +2,61 @@ if ATH79
+ 
+ menu "Atheros AR71XX/AR724X/AR913X machine selection"
+ 
++config ATH79_MACH_ALFA_AP96
++	bool "ALFA Network AP96 board support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_SPI
++	select ATH79_DEV_USB
++
++config ATH79_MACH_HORNET_UB
++	bool "ALFA Network Hornet-UB board support"
++	select SOC_AR933X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_ALFA_NX
++	bool "ALFA Network N2/N5 board support"
++	select SOC_AR724X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_ALL0258N
++	bool "Allnet ALL0258N support"
++	select SOC_AR724X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_ALL0315N
++	bool "Allnet ALL0315N support"
++	select SOC_AR724X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_AP113
++	bool "Atheros AP113 board support"
++	select SOC_AR724X
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_PB9X_PCI if PCI
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_USB
++	select ATH79_DEV_ETH
++
+ config ATH79_MACH_AP121
+ 	bool "Atheros AP121 reference board"
+ 	select SOC_AR933X
+@@ -41,6 +96,24 @@ config ATH79_MACH_AP81
+ 	  Say 'Y' here if you want your kernel to support the
+ 	  Atheros AP81 reference board.
+ 
++config ATH79_MACH_AP83
++	bool "Atheros AP83 board support"
++	select SOC_AR913X
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_AP96
++	bool "Atheros AP96 board support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
+ config ATH79_MACH_DB120
+ 	bool "Atheros DB120 reference board"
+ 	select SOC_AR934X
+@@ -56,6 +129,13 @@ config ATH79_MACH_DB120
+ 	  Say 'Y' here if you want your kernel to support the
+ 	  Atheros DB120 reference board.
+ 
++config ATH79_MACH_PB42
++	bool "Atheros PB42 board support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_M25P80
++
+ config ATH79_MACH_PB44
+ 	bool "Atheros PB44 reference board"
+ 	select SOC_AR71XX
+@@ -68,6 +148,488 @@ config ATH79_MACH_PB44
+ 	  Say 'Y' here if you want your kernel to support the
+ 	  Atheros PB44 reference board.
+ 
++config ATH79_MACH_PB92
++	bool "Atheros PB92 board support"
++	select SOC_AR724X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_PB9X_PCI if PCI
++	select ATH79_DEV_USB
++
++config ATH79_MACH_AW_NR580
++	bool "AzureWave AW-NR580 board support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_WHR_HP_G300N
++	bool "Buffalo WHR-HP-G300N board support"
++	select SOC_AR724X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_WLAE_AG300N
++	bool "Buffalo WLAE-AG300N board support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_WZR_HP_AG300H
++	bool "Buffalo WZR-HP-AG300H board support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
++config ATH79_MACH_WZR_HP_G300NH
++	bool "Buffalo WZR-HP-G300NH board support"
++	select SOC_AR913X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++	select RTL8366_SMI
++
++config ATH79_MACH_WZR_HP_G300NH2
++	bool "Buffalo WZR-HP-G300NH2 board support"
++	select SOC_AR724X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
++config ATH79_MACH_WZR_HP_G450H
++	bool "Buffalo WZR-HP-G450H board support"
++	select SOC_AR724X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
++config ATH79_MACH_WP543
++	bool "Compex WP543/WPJ543 board support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select MYLOADER
++
++config ATH79_MACH_WPE72
++	bool "Compex WPE72/WPE72NX board support"
++	select SOC_AR724X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select MYLOADER
++
++config ATH79_MACH_DIR_600_A1
++	bool "D-Link DIR-600 A1/DIR-615 E4 support"
++	select SOC_AR724X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_NVRAM
++
++config ATH79_MACH_DIR_615_C1
++	bool "D-Link DIR-615 rev. C1 support"
++	select SOC_AR913X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++	select ATH79_NVRAM
++
++config ATH79_MACH_DIR_825_B1
++	bool "D-Link DIR-825 rev. B1 board support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
++config ATH79_MACH_EW_DORIN
++	bool "embedded wireless Dorin Platform support"
++	select SOC_AR933X
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_WMAC
++	select ATH79_DEV_ETH
++	help
++	  Say 'Y' here if you want your kernel to support the
++	  Dorin Platform from www.80211.de .
++
++config ATH79_MACH_JA76PF
++	bool "jjPlus JA76PF board support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
++config ATH79_MACH_JWAP003
++	bool "jjPlus JWAP003 board support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
++config ATH79_MACH_WRT160NL
++	bool "Linksys WRT160NL board support"
++	select SOC_AR913X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++	select ATH79_NVRAM
++
++config ATH79_MACH_WRT400N
++	bool "Linksys WRT400N board support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_RB4XX
++	bool "MikroTik RouterBOARD 4xx series support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_USB
++
++config ATH79_MACH_RB750
++	bool "MikroTik RouterBOARD 750 support"
++	select SOC_AR724X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_USB
++	select ATH79_ROUTERBOOT
++	select RLE_DECOMPRESS
++
++config ATH79_MACH_RB2011
++	bool "MikroTik RouterBOARD 2011 support"
++	select SOC_AR934x
++	select ATH79_DEV_ETH
++	select ATH79_DEV_NFC
++	select ATH79_DEV_WMAC
++	select ATH79_ROUTERBOOT
++
++config ATH79_MACH_WNDR3700
++	bool "NETGEAR WNDR3700 board support"
++	select SOC_AR71XX
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
++config ATH79_MACH_WNDR4300
++	bool "NETGEAR WNDR4300 board support"
++	select SOC_AR934X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_NFC
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_WNR2000
++	bool "NETGEAR WNR2000 board support"
++	select SOC_AR913X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_OM2P
++	bool "OpenMesh OM2P board support"
++	select SOC_AR724X
++	select SOC_AR933X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_MR600
++	bool "OpenMesh MR600 board support"
++	select SOC_AR934X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_MZK_W04NU
++	bool "Planex MZK-W04NU board support"
++	select SOC_AR913X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_MZK_W300NH
++	bool "Planex MZK-W300NH board support"
++	select SOC_AR913X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_RW2458N
++	bool "Redwave RW2458N board support"
++	select SOC_AR724X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
++config ATH79_MACH_CAP4200AG
++	bool "Senao CAP4200AG support"
++	select SOC_AR934X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_EAP7660D
++	bool "Senao EAP7660D support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_TL_MR11U
++	bool "TP-LINK TL-MR11U/TL-MR3040 support"
++	select SOC_AR933X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_MR3020
++	bool "TP-LINK TL-MR3020 support"
++	select SOC_AR933X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_MR3X20
++	bool "TP-LINK TL-MR3220/3420 support"
++	select SOC_AR724X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
++config ATH79_MACH_TL_WA901ND
++	bool "TP-LINK TL-WA901ND/TL-WA7510N support"
++	select SOC_AR724X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_TL_WA901ND_V2
++	bool "TP-LINK TL-WA901ND v2 support"
++	select SOC_AR913X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WDR4300
++	bool "TP-LINK TL-WDR3600/4300/4310 board support"
++	select SOC_AR934X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR703N
++	bool "TP-LINK TL-WR703N support"
++	select SOC_AR933X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR741ND
++	bool "TP-LINK TL-WR741ND support"
++	select SOC_AR724X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_TL_WR741ND_V4
++	bool "TP-LINK TL-WR741ND v4/TL-MR3220 v2 support"
++	select SOC_AR933X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR841N_V1
++	bool "TP-LINK TL-WR841N v1 support"
++	select SOC_AR71XX
++	select ATH79_DEV_DSA
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_TL_WR841N_V8
++	bool "TP-LINK TL-WR841N/ND v8 support"
++	select SOC_AR934X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR941ND
++	bool "TP-LINK TL-WR941ND support"
++	select SOC_AR913X
++	select ATH79_DEV_DSA
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR1041N_V2
++	bool "TP-LINK TL-WR1041N v2 support"
++	select SOC_AR934X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR1043ND
++	bool "TP-LINK TL-WR1043ND support"
++	select SOC_AR913X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR2543N
++	bool "TP-LINK TL-WR2543N/ND support"
++	select SOC_AR724X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
++config ATH79_MACH_TEW_632BRP
++	bool "TRENDnet TEW-632BRP support"
++	select SOC_AR913X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++	select ATH79_NVRAM
++
++config ATH79_MACH_TEW_673GRU
++	bool "TRENDnet TEW-673GRU support"
++	select SOC_AR71XX
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_NVRAM
++
++config ATH79_MACH_TEW_712BR
++	bool "TRENDnet TEW-712BR support"
++	select SOC_AR933X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++	select ATH79_NVRAM
++
++config ATH79_MACH_UBNT
++	bool "Ubiquiti AR71xx based boards support"
++	select SOC_AR71XX
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++
+ config ATH79_MACH_UBNT_XM
+ 	bool "Ubiquiti Networks XM/UniFi boards"
+ 	select SOC_AR724X
+@@ -83,6 +645,24 @@ config ATH79_MACH_UBNT_XM
+ 	  Say 'Y' here if you want your kernel to support the
+ 	  Ubiquiti Networks XM (rev 1.0) board.
+ 
++config ATH79_MACH_ZCN_1523H
++	bool "Zcomax ZCN-1523H support"
++	select SOC_AR724X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++
++config ATH79_MACH_NBG460N
++	bool "Zyxel NBG460N/550N/550NH board support"
++	select SOC_AR913X
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_WMAC
++
+ endmenu
+ 
+ config SOC_AR71XX
+@@ -118,10 +698,6 @@ config SOC_QCA955X
+ 	select PCI_AR724X if PCI
+ 	def_bool n
+ 
+-config ATH79_DEV_M25P80
+-	select ATH79_DEV_SPI
+-	def_bool n
+-
+ config ATH79_DEV_AP9X_PCI
+ 	select ATH79_PCI_ATH9K_FIXUP
+ 	def_bool n
+@@ -132,7 +708,14 @@ config ATH79_DEV_DSA
+ config ATH79_DEV_ETH
+ 	def_bool n
+ 
+-config PCI_AR724X
++config ATH79_DEV_M25P80
++	select ATH79_DEV_SPI
++	def_bool n
++
++config ATH79_DEV_DSA
++	def_bool n
++
++config ATH79_DEV_ETH
+ 	def_bool n
+ 
+ config ATH79_DEV_GPIO_BUTTONS
+@@ -164,4 +747,7 @@ config ATH79_PCI_ATH9K_FIXUP
+ config ATH79_ROUTERBOOT
+ 	def_bool n
+ 
++config PCI_AR724X
++	def_bool n
++
+ endif
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -38,9 +38,71 @@ obj-$(CONFIG_ATH79_ROUTERBOOT)		+= route
+ #
+ # Machines
+ #
++obj-$(CONFIG_ATH79_MACH_ALFA_AP96)	+= mach-alfa-ap96.o
++obj-$(CONFIG_ATH79_MACH_ALFA_NX)	+= mach-alfa-nx.o
++obj-$(CONFIG_ATH79_MACH_ALL0258N)	+= mach-all0258n.o
++obj-$(CONFIG_ATH79_MACH_ALL0315N)	+= mach-all0315n.o
++obj-$(CONFIG_ATH79_MACH_AP113)		+= mach-ap113.o
+ obj-$(CONFIG_ATH79_MACH_AP121)		+= mach-ap121.o
+ obj-$(CONFIG_ATH79_MACH_AP136)		+= mach-ap136.o
+ obj-$(CONFIG_ATH79_MACH_AP81)		+= mach-ap81.o
++obj-$(CONFIG_ATH79_MACH_AP83)		+= mach-ap83.o
++obj-$(CONFIG_ATH79_MACH_AP96)		+= mach-ap96.o
++obj-$(CONFIG_ATH79_MACH_AW_NR580)	+= mach-aw-nr580.o
++obj-$(CONFIG_ATH79_MACH_CAP4200AG)	+= mach-cap4200ag.o
+ obj-$(CONFIG_ATH79_MACH_DB120)		+= mach-db120.o
++obj-$(CONFIG_ATH79_MACH_DIR_600_A1)	+= mach-dir-600-a1.o
++obj-$(CONFIG_ATH79_MACH_DIR_615_C1)	+= mach-dir-615-c1.o
++obj-$(CONFIG_ATH79_MACH_DIR_825_B1)	+= mach-dir-825-b1.o
++obj-$(CONFIG_ATH79_MACH_EW_DORIN)	+= mach-ew-dorin.o
++obj-$(CONFIG_ATH79_MACH_EAP7660D)	+= mach-eap7660d.o
++obj-$(CONFIG_ATH79_MACH_JA76PF)		+= mach-ja76pf.o
++obj-$(CONFIG_ATH79_MACH_JWAP003)	+= mach-jwap003.o
++obj-$(CONFIG_ATH79_MACH_HORNET_UB)	+= mach-hornet-ub.o
++obj-$(CONFIG_ATH79_MACH_MR600)		+= mach-mr600.o
++obj-$(CONFIG_ATH79_MACH_MZK_W04NU)	+= mach-mzk-w04nu.o
++obj-$(CONFIG_ATH79_MACH_MZK_W300NH)	+= mach-mzk-w300nh.o
++obj-$(CONFIG_ATH79_MACH_NBG460N)	+= mach-nbg460n.o
++obj-$(CONFIG_ATH79_MACH_OM2P)		+= mach-om2p.o
++obj-$(CONFIG_ATH79_MACH_PB42)		+= mach-pb42.o
+ obj-$(CONFIG_ATH79_MACH_PB44)		+= mach-pb44.o
++obj-$(CONFIG_ATH79_MACH_PB92)		+= mach-pb92.o
++obj-$(CONFIG_ATH79_MACH_RB4XX)		+= mach-rb4xx.o
++obj-$(CONFIG_ATH79_MACH_RB750)		+= mach-rb750.o
++obj-$(CONFIG_ATH79_MACH_RB2011)		+= mach-rb2011.o
++obj-$(CONFIG_ATH79_MACH_RW2458N)	+= mach-rw2458n.o
++obj-$(CONFIG_ATH79_MACH_TEW_632BRP)	+= mach-tew-632brp.o
++obj-$(CONFIG_ATH79_MACH_TEW_673GRU)	+= mach-tew-673gru.o
++obj-$(CONFIG_ATH79_MACH_TEW_712BR)	+= mach-tew-712br.o
++obj-$(CONFIG_ATH79_MACH_TL_MR11U)	+= mach-tl-mr11u.o
++obj-$(CONFIG_ATH79_MACH_TL_MR3020)	+= mach-tl-mr3020.o
++obj-$(CONFIG_ATH79_MACH_TL_MR3X20)	+= mach-tl-mr3x20.o
++obj-$(CONFIG_ATH79_MACH_TL_WA901ND)	+= mach-tl-wa901nd.o
++obj-$(CONFIG_ATH79_MACH_TL_WA901ND_V2)	+= mach-tl-wa901nd-v2.o
++obj-$(CONFIG_ATH79_MACH_TL_WDR4300)     += mach-tl-wdr4300.o
++obj-$(CONFIG_ATH79_MACH_TL_WR741ND)	+= mach-tl-wr741nd.o
++obj-$(CONFIG_ATH79_MACH_TL_WR741ND_V4)	+= mach-tl-wr741nd-v4.o
++obj-$(CONFIG_ATH79_MACH_TL_WR841N_V1)	+= mach-tl-wr841n.o
++obj-$(CONFIG_ATH79_MACH_TL_WR841N_V8)	+= mach-tl-wr841n-v8.o
++obj-$(CONFIG_ATH79_MACH_TL_WR941ND)	+= mach-tl-wr941nd.o
++obj-$(CONFIG_ATH79_MACH_TL_WR1041N_V2)	+= mach-tl-wr1041n-v2.o
++obj-$(CONFIG_ATH79_MACH_TL_WR1043ND)	+= mach-tl-wr1043nd.o
++obj-$(CONFIG_ATH79_MACH_TL_WR2543N)	+= mach-tl-wr2543n.o
++obj-$(CONFIG_ATH79_MACH_TL_WR703N)	+= mach-tl-wr703n.o
++obj-$(CONFIG_ATH79_MACH_UBNT)		+= mach-ubnt.o
+ obj-$(CONFIG_ATH79_MACH_UBNT_XM)	+= mach-ubnt-xm.o
++obj-$(CONFIG_ATH79_MACH_WHR_HP_G300N)	+= mach-whr-hp-g300n.o
++obj-$(CONFIG_ATH79_MACH_WLAE_AG300N)	+= mach-wlae-ag300n.o
++obj-$(CONFIG_ATH79_MACH_WNDR3700)	+= mach-wndr3700.o
++obj-$(CONFIG_ATH79_MACH_WNDR4300)	+= mach-wndr4300.o
++obj-$(CONFIG_ATH79_MACH_WNR2000)	+= mach-wnr2000.o
++obj-$(CONFIG_ATH79_MACH_WP543)		+= mach-wp543.o
++obj-$(CONFIG_ATH79_MACH_WPE72)		+= mach-wpe72.o
++obj-$(CONFIG_ATH79_MACH_WRT160NL)	+= mach-wrt160nl.o
++obj-$(CONFIG_ATH79_MACH_WRT400N)	+= mach-wrt400n.o
++obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH)	+= mach-wzr-hp-g300nh.o
++obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH2)	+= mach-wzr-hp-g300nh2.o
++obj-$(CONFIG_ATH79_MACH_WZR_HP_AG300H)	+= mach-wzr-hp-ag300h.o
++obj-$(CONFIG_ATH79_MACH_WZR_HP_G450H)	+= mach-wzr-hp-g450h.o
++obj-$(CONFIG_ATH79_MACH_ZCN_1523H)	+= mach-zcn-1523h.o
++
+--- a/arch/mips/ath79/prom.c
++++ b/arch/mips/ath79/prom.c
+@@ -180,6 +180,10 @@ void __init prom_init(void)
+ 			ath79_prom_append_cmdline("board", env);
+ 		}
+ 	}
++
++	if (strstr(arcs_cmdline, "board=750Gr3") ||
++	    strstr(arcs_cmdline, "board=2011L"))
++		ath79_prom_append_cmdline("console", "ttyS0,115200");
+ }
+ 
+ void __init prom_free_prom_memory(void)
diff --git a/target/linux/ar71xx/patches-3.8/611-MIPS-ath79-add-QCA9556-SoC-on-AP132.patch b/target/linux/ar71xx/patches-3.8/611-MIPS-ath79-add-QCA9556-SoC-on-AP132.patch
new file mode 100644
index 0000000..8479ea3
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/611-MIPS-ath79-add-QCA9556-SoC-on-AP132.patch
@@ -0,0 +1,41 @@
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -70,6 +70,18 @@ config ATH79_MACH_AP121
+ 	  Say 'Y' here if you want your kernel to support the
+ 	  Atheros AP121 reference board.
+ 
++config ATH79_MACH_AP132
++	bool "Atheros AP132 reference board"
++	select SOC_QCA955X
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_SPI
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++	help
++	  Say 'Y' here if you want your kernel to support the
++	  Atheros AP132 reference boards.
++
+ config ATH79_MACH_AP136
+ 	bool "Atheros AP136/AP135 reference board"
+ 	select SOC_QCA955X
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -24,6 +24,7 @@ enum ath79_mach_type {
+ 	ATH79_MACH_AP113,		/* Atheros AP113 reference board */
+ 	ATH79_MACH_AP121,		/* Atheros AP121 reference board */
+ 	ATH79_MACH_AP121_MINI,		/* Atheros AP121-MINI reference board */
++	ATH79_MACH_AP132,		/* Atheros AP132 reference board */
+ 	ATH79_MACH_AP135_020,		/* Atheros AP135-020 reference board */
+ 	ATH79_MACH_AP136_010,		/* Atheros AP136-010 reference board */
+ 	ATH79_MACH_AP136_020,		/* Atheros AP136-020 reference board */
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -44,6 +44,7 @@ obj-$(CONFIG_ATH79_MACH_ALL0258N)	+= mac
+ obj-$(CONFIG_ATH79_MACH_ALL0315N)	+= mach-all0315n.o
+ obj-$(CONFIG_ATH79_MACH_AP113)		+= mach-ap113.o
+ obj-$(CONFIG_ATH79_MACH_AP121)		+= mach-ap121.o
++obj-$(CONFIG_ATH79_MACH_AP132)		+= mach-ap132.o
+ obj-$(CONFIG_ATH79_MACH_AP136)		+= mach-ap136.o
+ obj-$(CONFIG_ATH79_MACH_AP81)		+= mach-ap81.o
+ obj-$(CONFIG_ATH79_MACH_AP83)		+= mach-ap83.o
diff --git a/target/linux/ar71xx/patches-3.8/612-MIPS-ath79-add-DIR-825-C1-support.patch b/target/linux/ar71xx/patches-3.8/612-MIPS-ath79-add-DIR-825-C1-support.patch
new file mode 100644
index 0000000..cacc2d3
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/612-MIPS-ath79-add-DIR-825-C1-support.patch
@@ -0,0 +1,41 @@
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -39,6 +39,8 @@ enum ath79_mach_type {
+ 	ATH79_MACH_DIR_615_C1,		/* D-Link DIR-615 rev. C1 */
+ 	ATH79_MACH_DIR_615_E4,		/* D-Link DIR-615 rev. E4 */
+ 	ATH79_MACH_DIR_825_B1,		/* D-Link DIR-825 rev. B1 */
++	ATH79_MACH_DIR_825_C1,		/* D-Link DIR-825 rev. C1 */
++	ATH79_MACH_DIR_835_A1,		/* D-Link DIR-835 rev. A1 */
+ 	ATH79_MACH_EW_DORIN,		/* embedded wireless Dorin Platform */
+ 	ATH79_MACH_EW_DORIN_ROUTER,	/* embedded wireless Dorin Router Platform */
+ 	ATH79_MACH_EAP7660D,		/* Senao EAP7660D */
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -283,6 +283,17 @@ config ATH79_MACH_DIR_825_B1
+ 	select ATH79_DEV_M25P80
+ 	select ATH79_DEV_USB
+ 
++config ATH79_MACH_DIR_825_C1
++	bool "D-Link DIR-825 rev. C1/DIR-835 rev. A1 board support"
++	select SOC_AR934X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
+ config ATH79_MACH_EW_DORIN
+ 	bool "embedded wireless Dorin Platform support"
+ 	select SOC_AR933X
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -55,6 +55,7 @@ obj-$(CONFIG_ATH79_MACH_DB120)		+= mach-
+ obj-$(CONFIG_ATH79_MACH_DIR_600_A1)	+= mach-dir-600-a1.o
+ obj-$(CONFIG_ATH79_MACH_DIR_615_C1)	+= mach-dir-615-c1.o
+ obj-$(CONFIG_ATH79_MACH_DIR_825_B1)	+= mach-dir-825-b1.o
++obj-$(CONFIG_ATH79_MACH_DIR_825_C1)	+= mach-dir-825-c1.o
+ obj-$(CONFIG_ATH79_MACH_EW_DORIN)	+= mach-ew-dorin.o
+ obj-$(CONFIG_ATH79_MACH_EAP7660D)	+= mach-eap7660d.o
+ obj-$(CONFIG_ATH79_MACH_JA76PF)		+= mach-ja76pf.o
diff --git a/target/linux/ar71xx/patches-3.8/613-MIPS-ath79-add-TL-WDR3500-support.patch b/target/linux/ar71xx/patches-3.8/613-MIPS-ath79-add-TL-WDR3500-support.patch
new file mode 100644
index 0000000..214e453
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/613-MIPS-ath79-add-TL-WDR3500-support.patch
@@ -0,0 +1,40 @@
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -85,6 +85,7 @@ enum ath79_mach_type {
+ 	ATH79_MACH_TL_WA7510N_V1,	/* TP-LINK TL-WA7510N v1*/
+ 	ATH79_MACH_TL_WA901ND,		/* TP-LINK TL-WA901ND */
+ 	ATH79_MACH_TL_WA901ND_V2,	/* TP-LINK TL-WA901ND v2 */
++	ATH79_MACH_TL_WDR3500,		/* TP-LINK TL-WDR3500 */
+ 	ATH79_MACH_TL_WDR4300,		/* TP-LINK TL-WDR4300 */
+ 	ATH79_MACH_TL_WR1041N_V2,	/* TP-LINK TL-WR1041N v2 */
+ 	ATH79_MACH_TL_WR1043ND,		/* TP-LINK TL-WR1043ND */
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -514,6 +514,17 @@ config ATH79_MACH_TL_WA901ND_V2
+ 	select ATH79_DEV_M25P80
+ 	select ATH79_DEV_WMAC
+ 
++config ATH79_MACH_TL_WDR3500
++	bool "TP-LINK TL-WDR3500 board support"
++	select SOC_AR934X
++	select ATH79_DEV_AP9X_PCI if PCI
++	select ATH79_DEV_ETH
++	select ATH79_DEV_GPIO_BUTTONS
++	select ATH79_DEV_LEDS_GPIO
++	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
++	select ATH79_DEV_WMAC
++
+ config ATH79_MACH_TL_WDR4300
+ 	bool "TP-LINK TL-WDR3600/4300/4310 board support"
+ 	select SOC_AR934X
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -81,6 +81,7 @@ obj-$(CONFIG_ATH79_MACH_TL_MR3020)	+= ma
+ obj-$(CONFIG_ATH79_MACH_TL_MR3X20)	+= mach-tl-mr3x20.o
+ obj-$(CONFIG_ATH79_MACH_TL_WA901ND)	+= mach-tl-wa901nd.o
+ obj-$(CONFIG_ATH79_MACH_TL_WA901ND_V2)	+= mach-tl-wa901nd-v2.o
++obj-$(CONFIG_ATH79_MACH_TL_WDR3500)     += mach-tl-wdr3500.o
+ obj-$(CONFIG_ATH79_MACH_TL_WDR4300)     += mach-tl-wdr4300.o
+ obj-$(CONFIG_ATH79_MACH_TL_WR741ND)	+= mach-tl-wr741nd.o
+ obj-$(CONFIG_ATH79_MACH_TL_WR741ND_V4)	+= mach-tl-wr741nd-v4.o
diff --git a/target/linux/ar71xx/patches-3.8/614-MIPS-ath79-MR600v2-support.patch b/target/linux/ar71xx/patches-3.8/614-MIPS-ath79-MR600v2-support.patch
new file mode 100644
index 0000000..cc89d81
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/614-MIPS-ath79-MR600v2-support.patch
@@ -0,0 +1,10 @@
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -48,6 +48,7 @@ enum ath79_mach_type {
+ 	ATH79_MACH_JA76PF2,		/* jjPlus JA76PF2 */
+ 	ATH79_MACH_JWAP003,		/* jjPlus JWAP003 */
+ 	ATH79_MACH_HORNET_UB,		/* ALFA Networks Hornet-UB */
++	ATH79_MACH_MR600V2,		/* OpenMesh MR600v2 */
+ 	ATH79_MACH_MR600,		/* OpenMesh MR600 */
+ 	ATH79_MACH_MZK_W04NU,		/* Planex MZK-W04NU */
+ 	ATH79_MACH_MZK_W300NH,		/* Planex MZK-W300NH */
diff --git a/target/linux/ar71xx/patches-3.8/615-MIPS-ath79-RB951G-support.patch b/target/linux/ar71xx/patches-3.8/615-MIPS-ath79-RB951G-support.patch
new file mode 100644
index 0000000..a2e558f
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/615-MIPS-ath79-RB951G-support.patch
@@ -0,0 +1,49 @@
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -71,6 +71,7 @@ enum ath79_mach_type {
+ 	ATH79_MACH_RB_750G_R3,		/* MikroTik RouterBOARD 750GL */
+ 	ATH79_MACH_RB_751,		/* MikroTik RouterBOARD 751 */
+ 	ATH79_MACH_RB_751G,		/* Mikrotik RouterBOARD 751G */
++	ATH79_MACH_RB_951G,		/* Mikrotik RouterBOARD 951G */
+ 	ATH79_MACH_RB_2011G,		/* Mikrotik RouterBOARD 2011UAS-2HnD */
+ 	ATH79_MACH_RB_2011L,		/* Mikrotik RouterBOARD 2011L */
+ 	ATH79_MACH_RW2458N,		/* Redwave RW2458N */
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -360,6 +360,16 @@ config ATH79_MACH_RB750
+ 	select ATH79_ROUTERBOOT
+ 	select RLE_DECOMPRESS
+ 
++config ATH79_MACH_RB95X
++       bool "MikroTik RouterBOARD 95X support"
++       select SOC_AR934x
++       select ATH79_DEV_ETH
++       select ATH79_DEV_NFC
++       select ATH79_DEV_WMAC
++       select ATH79_DEV_USB
++       select ATH79_ROUTERBOOT
++       select RLE_DECOMPRESS
++
+ config ATH79_MACH_RB2011
+ 	bool "MikroTik RouterBOARD 2011 support"
+ 	select SOC_AR934x
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -71,6 +71,7 @@ obj-$(CONFIG_ATH79_MACH_PB44)		+= mach-p
+ obj-$(CONFIG_ATH79_MACH_PB92)		+= mach-pb92.o
+ obj-$(CONFIG_ATH79_MACH_RB4XX)		+= mach-rb4xx.o
+ obj-$(CONFIG_ATH79_MACH_RB750)		+= mach-rb750.o
++obj-$(CONFIG_ATH79_MACH_RB95X)		+= mach-rb95x.o
+ obj-$(CONFIG_ATH79_MACH_RB2011)		+= mach-rb2011.o
+ obj-$(CONFIG_ATH79_MACH_RW2458N)	+= mach-rw2458n.o
+ obj-$(CONFIG_ATH79_MACH_TEW_632BRP)	+= mach-tew-632brp.o
+--- a/arch/mips/ath79/prom.c
++++ b/arch/mips/ath79/prom.c
+@@ -182,6 +182,7 @@ void __init prom_init(void)
+ 	}
+ 
+ 	if (strstr(arcs_cmdline, "board=750Gr3") ||
++	    strstr(arcs_cmdline, "board=951G") ||
+ 	    strstr(arcs_cmdline, "board=2011L"))
+ 		ath79_prom_append_cmdline("console", "ttyS0,115200");
+ }
diff --git a/target/linux/ar71xx/patches-3.8/616-MIPS-ath79-TL-MR3420-v2-support.patch b/target/linux/ar71xx/patches-3.8/616-MIPS-ath79-TL-MR3420-v2-support.patch
new file mode 100644
index 0000000..855bb96
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/616-MIPS-ath79-TL-MR3420-v2-support.patch
@@ -0,0 +1,27 @@
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -585,12 +585,13 @@ config ATH79_MACH_TL_WR841N_V1
+ 	select ATH79_DEV_M25P80
+ 
+ config ATH79_MACH_TL_WR841N_V8
+-	bool "TP-LINK TL-WR841N/ND v8 support"
++	bool "TP-LINK TL-WR841N/ND v8/TL-MR3420 v2 support"
+ 	select SOC_AR934X
+ 	select ATH79_DEV_ETH
+ 	select ATH79_DEV_GPIO_BUTTONS
+ 	select ATH79_DEV_LEDS_GPIO
+ 	select ATH79_DEV_M25P80
++	select ATH79_DEV_USB
+ 	select ATH79_DEV_WMAC
+ 
+ config ATH79_MACH_TL_WR941ND
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -84,6 +84,7 @@ enum ath79_mach_type {
+ 	ATH79_MACH_TL_MR3220,		/* TP-LINK TL-MR3220 */
+ 	ATH79_MACH_TL_MR3220_V2,	/* TP-LINK TL-MR3220 v2 */
+ 	ATH79_MACH_TL_MR3420,		/* TP-LINK TL-MR3420 */
++	ATH79_MACH_TL_MR3420_V2,	/* TP-LINK TL-MR3420 v2 */
+ 	ATH79_MACH_TL_WA7510N_V1,	/* TP-LINK TL-WA7510N v1*/
+ 	ATH79_MACH_TL_WA901ND,		/* TP-LINK TL-WA901ND */
+ 	ATH79_MACH_TL_WA901ND_V2,	/* TP-LINK TL-WA901ND v2 */
diff --git a/target/linux/ar71xx/patches-3.8/901-mdio_bitbang_ignore_ta_value.patch b/target/linux/ar71xx/patches-3.8/901-mdio_bitbang_ignore_ta_value.patch
new file mode 100644
index 0000000..39584aa
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/901-mdio_bitbang_ignore_ta_value.patch
@@ -0,0 +1,20 @@
+--- a/drivers/net/phy/mdio-bitbang.c
++++ b/drivers/net/phy/mdio-bitbang.c
+@@ -165,16 +165,7 @@ static int mdiobb_read(struct mii_bus *b
+ 
+ 	ctrl->ops->set_mdio_dir(ctrl, 0);
+ 
+-	/* check the turnaround bit: the PHY should be driving it to zero */
+-	if (mdiobb_get_bit(ctrl) != 0) {
+-		/* PHY didn't drive TA low -- flush any bits it
+-		 * may be trying to send.
+-		 */
+-		for (i = 0; i < 32; i++)
+-			mdiobb_get_bit(ctrl);
+-
+-		return 0xffff;
+-	}
++	mdiobb_get_bit(ctrl);
+ 
+ 	ret = mdiobb_get_num(ctrl, 16);
+ 	mdiobb_get_bit(ctrl);
diff --git a/target/linux/ar71xx/patches-3.8/902-unaligned_access_hacks.patch b/target/linux/ar71xx/patches-3.8/902-unaligned_access_hacks.patch
new file mode 100644
index 0000000..2426e07
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/902-unaligned_access_hacks.patch
@@ -0,0 +1,789 @@
+--- a/arch/mips/include/asm/checksum.h
++++ b/arch/mips/include/asm/checksum.h
+@@ -104,26 +104,30 @@ static inline __sum16 ip_fast_csum(const
+ 	const unsigned int *stop = word + ihl;
+ 	unsigned int csum;
+ 	int carry;
++	unsigned int w;
+ 
+-	csum = word[0];
+-	csum += word[1];
+-	carry = (csum < word[1]);
++	csum = net_hdr_word(word++);
++
++	w = net_hdr_word(word++);
++	csum += w;
++	carry = (csum < w);
+ 	csum += carry;
+ 
+-	csum += word[2];
+-	carry = (csum < word[2]);
++	w = net_hdr_word(word++);
++	csum += w;
++	carry = (csum < w);
+ 	csum += carry;
+ 
+-	csum += word[3];
+-	carry = (csum < word[3]);
++	w = net_hdr_word(word++);
++	csum += w;
++	carry = (csum < w);
+ 	csum += carry;
+ 
+-	word += 4;
+ 	do {
+-		csum += *word;
+-		carry = (csum < *word);
++		w = net_hdr_word(word++);
++		csum += w;
++		carry = (csum < w);
+ 		csum += carry;
+-		word++;
+ 	} while (word != stop);
+ 
+ 	return csum_fold(csum);
+@@ -192,69 +196,4 @@ static inline __sum16 ip_compute_csum(co
+ 	return csum_fold(csum_partial(buff, len, 0));
+ }
+ 
+-#define _HAVE_ARCH_IPV6_CSUM
+-static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
+-				          const struct in6_addr *daddr,
+-					  __u32 len, unsigned short proto,
+-					  __wsum sum)
+-{
+-	__asm__(
+-	"	.set	push		# csum_ipv6_magic\n"
+-	"	.set	noreorder	\n"
+-	"	.set	noat		\n"
+-	"	addu	%0, %5		# proto (long in network byte order)\n"
+-	"	sltu	$1, %0, %5	\n"
+-	"	addu	%0, $1		\n"
+-
+-	"	addu	%0, %6		# csum\n"
+-	"	sltu	$1, %0, %6	\n"
+-	"	lw	%1, 0(%2)	# four words source address\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	lw	%1, 4(%2)	\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	lw	%1, 8(%2)	\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	lw	%1, 12(%2)	\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	lw	%1, 0(%3)	\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	lw	%1, 4(%3)	\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	lw	%1, 8(%3)	\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	lw	%1, 12(%3)	\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	addu	%0, $1		# Add final carry\n"
+-	"	.set	pop"
+-	: "=r" (sum), "=r" (proto)
+-	: "r" (saddr), "r" (daddr),
+-	  "0" (htonl(len)), "1" (htonl(proto)), "r" (sum));
+-
+-	return csum_fold(sum);
+-}
+-
+ #endif /* _ASM_CHECKSUM_H */
+--- a/include/uapi/linux/ip.h
++++ b/include/uapi/linux/ip.h
+@@ -102,7 +102,7 @@ struct iphdr {
+ 	__be32	saddr;
+ 	__be32	daddr;
+ 	/*The options start here. */
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ 
+ struct ip_auth_hdr {
+--- a/include/uapi/linux/ipv6.h
++++ b/include/uapi/linux/ipv6.h
+@@ -123,7 +123,7 @@ struct ipv6hdr {
+ 
+ 	struct	in6_addr	saddr;
+ 	struct	in6_addr	daddr;
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ 
+ /* index values for the variables in ipv6_devconf */
+--- a/include/uapi/linux/tcp.h
++++ b/include/uapi/linux/tcp.h
+@@ -54,7 +54,7 @@ struct tcphdr {
+ 	__be16	window;
+ 	__sum16	check;
+ 	__be16	urg_ptr;
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ /*
+  *	The union cast uses a gcc extension to avoid aliasing problems
+@@ -64,7 +64,7 @@ struct tcphdr {
+ union tcp_word_hdr { 
+ 	struct tcphdr hdr;
+ 	__be32 		  words[5];
+-}; 
++} __attribute__((packed, aligned(2)));
+ 
+ #define tcp_flag_word(tp) ( ((union tcp_word_hdr *)(tp))->words [3]) 
+ 
+--- a/include/uapi/linux/udp.h
++++ b/include/uapi/linux/udp.h
+@@ -24,7 +24,7 @@ struct udphdr {
+ 	__be16	dest;
+ 	__be16	len;
+ 	__sum16	check;
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ /* UDP socket options */
+ #define UDP_CORK	1	/* Never send partially complete segments */
+--- a/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c
++++ b/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c
+@@ -39,8 +39,8 @@ static bool ipv4_pkt_to_tuple(const stru
+ 	if (ap == NULL)
+ 		return false;
+ 
+-	tuple->src.u3.ip = ap[0];
+-	tuple->dst.u3.ip = ap[1];
++	tuple->src.u3.ip = net_hdr_word(ap++);
++	tuple->dst.u3.ip = net_hdr_word(ap);
+ 
+ 	return true;
+ }
+--- a/include/uapi/linux/icmp.h
++++ b/include/uapi/linux/icmp.h
+@@ -80,7 +80,7 @@ struct icmphdr {
+ 		__be16	mtu;
+ 	} frag;
+   } un;
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ 
+ /*
+--- a/net/ipv4/tcp_input.c
++++ b/net/ipv4/tcp_input.c
+@@ -3871,13 +3871,14 @@ static bool tcp_parse_aligned_timestamp(
+ {
+ 	const __be32 *ptr = (const __be32 *)(th + 1);
+ 
+-	if (*ptr == htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16)
+-			  | (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) {
++	if (net_hdr_word(ptr) ==
++	    htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
++	    (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) {
+ 		tp->rx_opt.saw_tstamp = 1;
+ 		++ptr;
+-		tp->rx_opt.rcv_tsval = ntohl(*ptr);
++		tp->rx_opt.rcv_tsval = get_unaligned_be32(ptr);
+ 		++ptr;
+-		tp->rx_opt.rcv_tsecr = ntohl(*ptr);
++		tp->rx_opt.rcv_tsecr = get_unaligned_be32(ptr);
+ 		return true;
+ 	}
+ 	return false;
+--- a/include/uapi/linux/in6.h
++++ b/include/uapi/linux/in6.h
+@@ -36,7 +36,7 @@ struct in6_addr {
+ #define s6_addr			in6_u.u6_addr8
+ #define s6_addr16		in6_u.u6_addr16
+ #define s6_addr32		in6_u.u6_addr32
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ /* IPv6 Wildcard Address (::) and Loopback Address (::1) defined in RFC2553
+  * NOTE: Be aware the IN6ADDR_* constants and in6addr_* externals are defined
+--- a/net/ipv6/af_inet6.c
++++ b/net/ipv6/af_inet6.c
+@@ -61,6 +61,7 @@
+ #endif
+ 
+ #include <asm/uaccess.h>
++#include <asm/unaligned.h>
+ #include <linux/mroute6.h>
+ 
+ MODULE_AUTHOR("Cast of dozens");
+@@ -688,7 +689,7 @@ bool ipv6_opt_accepted(const struct sock
+ 		if ((opt->hop && (np->rxopt.bits.hopopts ||
+ 				  np->rxopt.bits.ohopopts)) ||
+ 		    ((IPV6_FLOWINFO_MASK &
+-		      *(__be32 *)skb_network_header(skb)) &&
++		      net_hdr_word(skb_network_header(skb))) &&
+ 		     np->rxopt.bits.rxflow) ||
+ 		    (opt->srcrt && (np->rxopt.bits.srcrt ||
+ 		     np->rxopt.bits.osrcrt)) ||
+--- a/net/ipv6/route.c
++++ b/net/ipv6/route.c
+@@ -995,7 +995,7 @@ void ip6_route_input(struct sk_buff *skb
+ 		.flowi6_iif = skb->dev->ifindex,
+ 		.daddr = iph->daddr,
+ 		.saddr = iph->saddr,
+-		.flowlabel = (* (__be32 *) iph) & IPV6_FLOWINFO_MASK,
++		.flowlabel = net_hdr_word(iph) & IPV6_FLOWINFO_MASK,
+ 		.flowi6_mark = skb->mark,
+ 		.flowi6_proto = iph->nexthdr,
+ 	};
+@@ -1159,7 +1159,7 @@ void ip6_update_pmtu(struct sk_buff *skb
+ 	fl6.flowi6_flags = 0;
+ 	fl6.daddr = iph->daddr;
+ 	fl6.saddr = iph->saddr;
+-	fl6.flowlabel = (*(__be32 *) iph) & IPV6_FLOWINFO_MASK;
++	fl6.flowlabel = net_hdr_word(iph) & IPV6_FLOWINFO_MASK,
+ 
+ 	dst = ip6_route_output(net, NULL, &fl6);
+ 	if (!dst->error)
+@@ -1187,7 +1187,7 @@ void ip6_redirect(struct sk_buff *skb, s
+ 	fl6.flowi6_flags = 0;
+ 	fl6.daddr = iph->daddr;
+ 	fl6.saddr = iph->saddr;
+-	fl6.flowlabel = (*(__be32 *) iph) & IPV6_FLOWINFO_MASK;
++	fl6.flowlabel = net_hdr_word(iph) & IPV6_FLOWINFO_MASK,
+ 
+ 	dst = ip6_route_output(net, NULL, &fl6);
+ 	if (!dst->error)
+--- a/net/ipv6/tcp_ipv6.c
++++ b/net/ipv6/tcp_ipv6.c
+@@ -64,6 +64,7 @@
+ #include <net/secure_seq.h>
+ #include <net/tcp_memcontrol.h>
+ 
++#include <asm/unaligned.h>
+ #include <asm/uaccess.h>
+ 
+ #include <linux/proc_fs.h>
+@@ -756,10 +757,10 @@ static void tcp_v6_send_response(struct
+ 	topt = (__be32 *)(t1 + 1);
+ 
+ 	if (ts) {
+-		*topt++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
+-				(TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP);
+-		*topt++ = htonl(tcp_time_stamp);
+-		*topt++ = htonl(ts);
++		put_unaligned_be32((TCPOPT_NOP << 24) |	(TCPOPT_NOP << 16) |
++			(TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP, topt++);
++		put_unaligned_be32(tcp_time_stamp, topt++);
++		put_unaligned_be32(ts, topt++);
+ 	}
+ 
+ #ifdef CONFIG_TCP_MD5SIG
+--- a/include/linux/ipv6.h
++++ b/include/linux/ipv6.h
+@@ -4,6 +4,7 @@
+ #include <uapi/linux/ipv6.h>
+ 
+ #define ipv6_optlen(p)  (((p)->hdrlen+1) << 3)
++
+ /*
+  * This structure contains configuration options per IPv6 link.
+  */
+--- a/net/ipv6/datagram.c
++++ b/net/ipv6/datagram.c
+@@ -360,12 +360,12 @@ int ipv6_recv_error(struct sock *sk, str
+ 				*(struct in6_addr *)(nh + serr->addr_offset);
+ 			if (np->sndflow)
+ 				sin->sin6_flowinfo =
+-					(*(__be32 *)(nh + serr->addr_offset - 24) &
+-					 IPV6_FLOWINFO_MASK);
++					net_hdr_word(nh + serr->addr_offset - 24) &
++					 IPV6_FLOWINFO_MASK;
+ 			if (ipv6_addr_type(&sin->sin6_addr) & IPV6_ADDR_LINKLOCAL)
+ 				sin->sin6_scope_id = IP6CB(skb)->iif;
+ 		} else {
+-			ipv6_addr_set_v4mapped(*(__be32 *)(nh + serr->addr_offset),
++			ipv6_addr_set_v4mapped(net_hdr_word(nh + serr->addr_offset),
+ 					       &sin->sin6_addr);
+ 		}
+ 	}
+@@ -493,9 +493,10 @@ int ip6_datagram_recv_ctl(struct sock *s
+ 		put_cmsg(msg, SOL_IPV6, IPV6_TCLASS, sizeof(tclass), &tclass);
+ 	}
+ 
+-	if (np->rxopt.bits.rxflow && (*(__be32 *)nh & IPV6_FLOWINFO_MASK)) {
+-		__be32 flowinfo = *(__be32 *)nh & IPV6_FLOWINFO_MASK;
+-		put_cmsg(msg, SOL_IPV6, IPV6_FLOWINFO, sizeof(flowinfo), &flowinfo);
++	if (np->rxopt.bits.rxflow) {
++		__be32 flowinfo = net_hdr_word(nh) & IPV6_FLOWINFO_MASK;
++		if (flowinfo)
++			put_cmsg(msg, SOL_IPV6, IPV6_FLOWINFO, sizeof(flowinfo), &flowinfo);
+ 	}
+ 
+ 	/* HbH is allowed only once */
+@@ -682,12 +683,12 @@ int ip6_datagram_send_ctl(struct net *ne
+ 			}
+ 
+ 			if (fl6->flowlabel&IPV6_FLOWINFO_MASK) {
+-				if ((fl6->flowlabel^*(__be32 *)CMSG_DATA(cmsg))&~IPV6_FLOWINFO_MASK) {
++				if ((fl6->flowlabel^net_hdr_word(CMSG_DATA(cmsg)))&~IPV6_FLOWINFO_MASK) {
+ 					err = -EINVAL;
+ 					goto exit_f;
+ 				}
+ 			}
+-			fl6->flowlabel = IPV6_FLOWINFO_MASK & *(__be32 *)CMSG_DATA(cmsg);
++			fl6->flowlabel = IPV6_FLOWINFO_MASK & net_hdr_word(CMSG_DATA(cmsg));
+ 			break;
+ 
+ 		case IPV6_2292HOPOPTS:
+--- a/net/ipv6/ip6_gre.c
++++ b/net/ipv6/ip6_gre.c
+@@ -430,7 +430,7 @@ static void ip6gre_err(struct sk_buff *s
+ 
+ 	t = ip6gre_tunnel_lookup(skb->dev, &ipv6h->daddr, &ipv6h->saddr,
+ 				flags & GRE_KEY ?
+-				*(((__be32 *)p) + (grehlen / 4) - 1) : 0,
++				net_hdr_word(((__be32 *)p) + (grehlen / 4) - 1) : 0,
+ 				p[1]);
+ 	if (t == NULL)
+ 		return;
+@@ -522,11 +522,11 @@ static int ip6gre_rcv(struct sk_buff *sk
+ 			offset += 4;
+ 		}
+ 		if (flags&GRE_KEY) {
+-			key = *(__be32 *)(h + offset);
++			key = net_hdr_word(h + offset);
+ 			offset += 4;
+ 		}
+ 		if (flags&GRE_SEQ) {
+-			seqno = ntohl(*(__be32 *)(h + offset));
++			seqno = ntohl(net_hdr_word(h + offset));
+ 			offset += 4;
+ 		}
+ 	}
+@@ -772,7 +772,7 @@ static netdev_tx_t ip6gre_xmit2(struct s
+ 	 *	Push down and install the IP header.
+ 	 */
+ 	ipv6h = ipv6_hdr(skb);
+-	*(__be32 *)ipv6h = fl6->flowlabel | htonl(0x60000000);
++	net_hdr_word(ipv6h) = fl6->flowlabel | htonl(0x60000000);
+ 	dsfield = INET_ECN_encapsulate(0, dsfield);
+ 	ipv6_change_dsfield(ipv6h, ~INET_ECN_MASK, dsfield);
+ 	ipv6h->hop_limit = tunnel->parms.hop_limit;
+@@ -789,7 +789,7 @@ static netdev_tx_t ip6gre_xmit2(struct s
+ 
+ 		if (tunnel->parms.o_flags&GRE_SEQ) {
+ 			++tunnel->o_seqno;
+-			*ptr = htonl(tunnel->o_seqno);
++			net_hdr_word(ptr) = htonl(tunnel->o_seqno);
+ 			ptr--;
+ 		}
+ 		if (tunnel->parms.o_flags&GRE_KEY) {
+@@ -897,9 +897,9 @@ static inline int ip6gre_xmit_ipv6(struc
+ 
+ 	dsfield = ipv6_get_dsfield(ipv6h);
+ 	if (t->parms.flags & IP6_TNL_F_USE_ORIG_TCLASS)
+-		fl6.flowlabel |= (*(__be32 *) ipv6h & IPV6_TCLASS_MASK);
++		fl6.flowlabel |= net_hdr_word(ipv6h) & IPV6_TCLASS_MASK;
+ 	if (t->parms.flags & IP6_TNL_F_USE_ORIG_FLOWLABEL)
+-		fl6.flowlabel |= (*(__be32 *) ipv6h & IPV6_FLOWLABEL_MASK);
++		fl6.flowlabel |= net_hdr_word(ipv6h) & IPV6_FLOWLABEL_MASK;
+ 	if (t->parms.flags & IP6_TNL_F_USE_ORIG_FWMARK)
+ 		fl6.flowi6_mark = skb->mark;
+ 
+@@ -1240,7 +1240,7 @@ static int ip6gre_header(struct sk_buff
+ 	struct ipv6hdr *ipv6h = (struct ipv6hdr *)skb_push(skb, t->hlen);
+ 	__be16 *p = (__be16 *)(ipv6h+1);
+ 
+-	*(__be32 *)ipv6h = t->fl.u.ip6.flowlabel | htonl(0x60000000);
++	net_hdr_word(ipv6h) = t->fl.u.ip6.flowlabel | htonl(0x60000000);
+ 	ipv6h->hop_limit = t->parms.hop_limit;
+ 	ipv6h->nexthdr = NEXTHDR_GRE;
+ 	ipv6h->saddr = t->parms.laddr;
+--- a/net/ipv6/ip6_output.c
++++ b/net/ipv6/ip6_output.c
+@@ -216,7 +216,7 @@ int ip6_xmit(struct sock *sk, struct sk_
+ 	if (hlimit < 0)
+ 		hlimit = ip6_dst_hoplimit(dst);
+ 
+-	*(__be32 *)hdr = htonl(0x60000000 | (tclass << 20)) | fl6->flowlabel;
++	net_hdr_word(hdr) = htonl(0x60000000 | (tclass << 20)) | fl6->flowlabel;
+ 
+ 	hdr->payload_len = htons(seg_len);
+ 	hdr->nexthdr = proto;
+--- a/net/ipv6/ip6_tunnel.c
++++ b/net/ipv6/ip6_tunnel.c
+@@ -1136,9 +1136,9 @@ ip6ip6_tnl_xmit(struct sk_buff *skb, str
+ 
+ 	dsfield = ipv6_get_dsfield(ipv6h);
+ 	if (t->parms.flags & IP6_TNL_F_USE_ORIG_TCLASS)
+-		fl6.flowlabel |= (*(__be32 *) ipv6h & IPV6_TCLASS_MASK);
++		fl6.flowlabel |= net_hdr_word(ipv6h) & IPV6_TCLASS_MASK;
+ 	if (t->parms.flags & IP6_TNL_F_USE_ORIG_FLOWLABEL)
+-		fl6.flowlabel |= (*(__be32 *) ipv6h & IPV6_FLOWLABEL_MASK);
++		fl6.flowlabel |= net_hdr_word(ipv6h) & IPV6_FLOWLABEL_MASK;
+ 	if (t->parms.flags & IP6_TNL_F_USE_ORIG_FWMARK)
+ 		fl6.flowi6_mark = skb->mark;
+ 
+--- a/net/ipv6/exthdrs.c
++++ b/net/ipv6/exthdrs.c
+@@ -578,7 +578,7 @@ static bool ipv6_hop_jumbo(struct sk_buf
+ 		goto drop;
+ 	}
+ 
+-	pkt_len = ntohl(*(__be32 *)(nh + optoff + 2));
++	pkt_len = ntohl(net_hdr_word(nh + optoff + 2));
+ 	if (pkt_len <= IPV6_MAXPLEN) {
+ 		IP6_INC_STATS_BH(net, ipv6_skb_idev(skb),
+ 				 IPSTATS_MIB_INHDRERRORS);
+--- a/include/linux/types.h
++++ b/include/linux/types.h
+@@ -212,5 +212,11 @@ struct callback_head {
+ };
+ #define rcu_head callback_head
+ 
++struct net_hdr_word {
++       u32 words[1];
++} __attribute__((packed, aligned(2)));
++
++#define net_hdr_word(_p) (((struct net_hdr_word *) (_p))->words[0])
++
+ #endif /*  __ASSEMBLY__ */
+ #endif /* _LINUX_TYPES_H */
+--- a/net/ipv4/af_inet.c
++++ b/net/ipv4/af_inet.c
+@@ -1396,8 +1396,8 @@ static struct sk_buff **inet_gro_receive
+ 	if (unlikely(ip_fast_csum((u8 *)iph, 5)))
+ 		goto out_unlock;
+ 
+-	id = ntohl(*(__be32 *)&iph->id);
+-	flush = (u16)((ntohl(*(__be32 *)iph) ^ skb_gro_len(skb)) | (id ^ IP_DF));
++	id = ntohl(net_hdr_word(&iph->id));
++	flush = (u16)((ntohl(net_hdr_word(iph)) ^ skb_gro_len(skb)) | (id ^ IP_DF));
+ 	id >>= 16;
+ 
+ 	for (p = *head; p; p = p->next) {
+--- a/net/ipv4/route.c
++++ b/net/ipv4/route.c
+@@ -465,7 +465,7 @@ static struct neighbour *ipv4_neigh_look
+ 	else if (skb)
+ 		pkey = &ip_hdr(skb)->daddr;
+ 
+-	n = __ipv4_neigh_lookup(dev, *(__force u32 *)pkey);
++	n = __ipv4_neigh_lookup(dev, net_hdr_word(pkey));
+ 	if (n)
+ 		return n;
+ 	return neigh_create(&arp_tbl, pkey, dev);
+--- a/net/ipv4/tcp_output.c
++++ b/net/ipv4/tcp_output.c
+@@ -456,15 +456,17 @@ static void tcp_options_write(__be32 *pt
+ 	 */
+ 	if (unlikely(OPTION_MD5 & options)) {
+ 		if (unlikely(OPTION_COOKIE_EXTENSION & options)) {
+-			*ptr++ = htonl((TCPOPT_COOKIE << 24) |
+-				       (TCPOLEN_COOKIE_BASE << 16) |
+-				       (TCPOPT_MD5SIG << 8) |
+-				       TCPOLEN_MD5SIG);
++			net_hdr_word(ptr++) =
++				htonl((TCPOPT_COOKIE << 24) |
++				      (TCPOLEN_COOKIE_BASE << 16) |
++				      (TCPOPT_MD5SIG << 8) |
++				      TCPOLEN_MD5SIG);
+ 		} else {
+-			*ptr++ = htonl((TCPOPT_NOP << 24) |
+-				       (TCPOPT_NOP << 16) |
+-				       (TCPOPT_MD5SIG << 8) |
+-				       TCPOLEN_MD5SIG);
++			net_hdr_word(ptr++) =
++				htonl((TCPOPT_NOP << 24) |
++				      (TCPOPT_NOP << 16) |
++				      (TCPOPT_MD5SIG << 8) |
++				      TCPOLEN_MD5SIG);
+ 		}
+ 		options &= ~OPTION_COOKIE_EXTENSION;
+ 		/* overload cookie hash location */
+@@ -473,26 +475,28 @@ static void tcp_options_write(__be32 *pt
+ 	}
+ 
+ 	if (unlikely(opts->mss)) {
+-		*ptr++ = htonl((TCPOPT_MSS << 24) |
+-			       (TCPOLEN_MSS << 16) |
+-			       opts->mss);
++		net_hdr_word(ptr++) =
++			htonl((TCPOPT_MSS << 24) | (TCPOLEN_MSS << 16) |
++			      opts->mss);
+ 	}
+ 
+ 	if (likely(OPTION_TS & options)) {
+ 		if (unlikely(OPTION_SACK_ADVERTISE & options)) {
+-			*ptr++ = htonl((TCPOPT_SACK_PERM << 24) |
+-				       (TCPOLEN_SACK_PERM << 16) |
+-				       (TCPOPT_TIMESTAMP << 8) |
+-				       TCPOLEN_TIMESTAMP);
++			net_hdr_word(ptr++) =
++				htonl((TCPOPT_SACK_PERM << 24) |
++				      (TCPOLEN_SACK_PERM << 16) |
++				      (TCPOPT_TIMESTAMP << 8) |
++				      TCPOLEN_TIMESTAMP);
+ 			options &= ~OPTION_SACK_ADVERTISE;
+ 		} else {
+-			*ptr++ = htonl((TCPOPT_NOP << 24) |
+-				       (TCPOPT_NOP << 16) |
+-				       (TCPOPT_TIMESTAMP << 8) |
+-				       TCPOLEN_TIMESTAMP);
++			net_hdr_word(ptr++) =
++				htonl((TCPOPT_NOP << 24) |
++				      (TCPOPT_NOP << 16) |
++				      (TCPOPT_TIMESTAMP << 8) |
++				      TCPOLEN_TIMESTAMP);
+ 		}
+-		*ptr++ = htonl(opts->tsval);
+-		*ptr++ = htonl(opts->tsecr);
++		net_hdr_word(ptr++) = htonl(opts->tsval);
++		net_hdr_word(ptr++) = htonl(opts->tsecr);
+ 	}
+ 
+ 	/* Specification requires after timestamp, so do it now.
+@@ -512,19 +516,20 @@ static void tcp_options_write(__be32 *pt
+ 			__u8 *p = (__u8 *)ptr;
+ 
+ 			/* 16-bit multiple */
+-			*p++ = TCPOPT_COOKIE;
+-			*p++ = TCPOLEN_COOKIE_BASE + cookie_size;
+-			*p++ = *cookie_copy++;
+-			*p++ = *cookie_copy++;
++			net_hdr_word(p++) = TCPOPT_COOKIE;
++			net_hdr_word(p++) = TCPOLEN_COOKIE_BASE + cookie_size;
++			net_hdr_word(p++) = *cookie_copy++;
++			net_hdr_word(p++) = *cookie_copy++;
+ 			ptr++;
+ 			cookie_size -= 2;
+ 		} else {
+ 			/* 32-bit multiple */
+-			*ptr++ = htonl(((TCPOPT_NOP << 24) |
+-					(TCPOPT_NOP << 16) |
+-					(TCPOPT_COOKIE << 8) |
+-					TCPOLEN_COOKIE_BASE) +
+-				       cookie_size);
++			net_hdr_word(ptr++) =
++				htonl(((TCPOPT_NOP << 24) |
++				       (TCPOPT_NOP << 16) |
++				       (TCPOPT_COOKIE << 8) |
++				       TCPOLEN_COOKIE_BASE) +
++				      cookie_size);
+ 		}
+ 
+ 		if (cookie_size > 0) {
+@@ -534,17 +539,19 @@ static void tcp_options_write(__be32 *pt
+ 	}
+ 
+ 	if (unlikely(OPTION_SACK_ADVERTISE & options)) {
+-		*ptr++ = htonl((TCPOPT_NOP << 24) |
+-			       (TCPOPT_NOP << 16) |
+-			       (TCPOPT_SACK_PERM << 8) |
+-			       TCPOLEN_SACK_PERM);
++		net_hdr_word(ptr++) =
++			htonl((TCPOPT_NOP << 24) |
++			      (TCPOPT_NOP << 16) |
++			      (TCPOPT_SACK_PERM << 8) |
++			      TCPOLEN_SACK_PERM);
+ 	}
+ 
+ 	if (unlikely(OPTION_WSCALE & options)) {
+-		*ptr++ = htonl((TCPOPT_NOP << 24) |
+-			       (TCPOPT_WINDOW << 16) |
+-			       (TCPOLEN_WINDOW << 8) |
+-			       opts->ws);
++		net_hdr_word(ptr++) =
++			htonl((TCPOPT_NOP << 24) |
++			      (TCPOPT_WINDOW << 16) |
++			      (TCPOLEN_WINDOW << 8) |
++			      opts->ws);
+ 	}
+ 
+ 	if (unlikely(opts->num_sack_blocks)) {
+@@ -552,16 +559,17 @@ static void tcp_options_write(__be32 *pt
+ 			tp->duplicate_sack : tp->selective_acks;
+ 		int this_sack;
+ 
+-		*ptr++ = htonl((TCPOPT_NOP  << 24) |
+-			       (TCPOPT_NOP  << 16) |
+-			       (TCPOPT_SACK <<  8) |
+-			       (TCPOLEN_SACK_BASE + (opts->num_sack_blocks *
++		net_hdr_word(ptr++) =
++			htonl((TCPOPT_NOP << 24) |
++			      (TCPOPT_NOP << 16) |
++			      (TCPOPT_SACK << 8) |
++			      (TCPOLEN_SACK_BASE + (opts->num_sack_blocks *
+ 						     TCPOLEN_SACK_PERBLOCK)));
+ 
+ 		for (this_sack = 0; this_sack < opts->num_sack_blocks;
+ 		     ++this_sack) {
+-			*ptr++ = htonl(sp[this_sack].start_seq);
+-			*ptr++ = htonl(sp[this_sack].end_seq);
++			net_hdr_word(ptr++) = htonl(sp[this_sack].start_seq);
++			net_hdr_word(ptr++) = htonl(sp[this_sack].end_seq);
+ 		}
+ 
+ 		tp->rx_opt.dsack = 0;
+@@ -570,9 +578,10 @@ static void tcp_options_write(__be32 *pt
+ 	if (unlikely(OPTION_FAST_OPEN_COOKIE & options)) {
+ 		struct tcp_fastopen_cookie *foc = opts->fastopen_cookie;
+ 
+-		*ptr++ = htonl((TCPOPT_EXP << 24) |
+-			       ((TCPOLEN_EXP_FASTOPEN_BASE + foc->len) << 16) |
+-			       TCPOPT_FASTOPEN_MAGIC);
++		net_hdr_word(ptr++) =
++			htonl((TCPOPT_EXP << 24) |
++			      ((TCPOLEN_EXP_FASTOPEN_BASE + foc->len) << 16) |
++			      TCPOPT_FASTOPEN_MAGIC);
+ 
+ 		memcpy(ptr, foc->val, foc->len);
+ 		if ((foc->len & 3) == 2) {
+--- a/net/ipv4/igmp.c
++++ b/net/ipv4/igmp.c
+@@ -470,7 +470,7 @@ static struct sk_buff *add_grec(struct s
+ 		if (!skb)
+ 			return NULL;
+ 		psrc = (__be32 *)skb_put(skb, sizeof(__be32));
+-		*psrc = psf->sf_inaddr;
++		net_hdr_word(psrc) = psf->sf_inaddr;
+ 		scount++; stotal++;
+ 		if ((type == IGMPV3_ALLOW_NEW_SOURCES ||
+ 		     type == IGMPV3_BLOCK_OLD_SOURCES) && psf->sf_crcount) {
+--- a/net/ipv4/ip_gre.c
++++ b/net/ipv4/ip_gre.c
+@@ -518,7 +518,7 @@ static void ipgre_err(struct sk_buff *sk
+ 		return;
+ 
+ 	if (flags & GRE_KEY)
+-		key = *(((__be32 *)p) + (grehlen / 4) - 1);
++		key = net_hdr_word(((__be32 *)p) + (grehlen / 4) - 1);
+ 
+ 	switch (type) {
+ 	default:
+--- a/include/uapi/linux/igmp.h
++++ b/include/uapi/linux/igmp.h
+@@ -32,7 +32,7 @@ struct igmphdr {
+ 	__u8 code;		/* For newer IGMP */
+ 	__sum16 csum;
+ 	__be32 group;
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ /* V3 group record types [grec_type] */
+ #define IGMPV3_MODE_IS_INCLUDE		1
+@@ -48,7 +48,7 @@ struct igmpv3_grec {
+ 	__be16	grec_nsrcs;
+ 	__be32	grec_mca;
+ 	__be32	grec_src[0];
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ struct igmpv3_report {
+ 	__u8 type;
+@@ -57,7 +57,7 @@ struct igmpv3_report {
+ 	__be16 resv2;
+ 	__be16 ngrec;
+ 	struct igmpv3_grec grec[0];
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ struct igmpv3_query {
+ 	__u8 type;
+@@ -78,7 +78,7 @@ struct igmpv3_query {
+ 	__u8 qqic;
+ 	__be16 nsrcs;
+ 	__be32 srcs[0];
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ #define IGMP_HOST_MEMBERSHIP_QUERY	0x11	/* From RFC1112 */
+ #define IGMP_HOST_MEMBERSHIP_REPORT	0x12	/* Ditto */
+--- a/net/core/flow_dissector.c
++++ b/net/core/flow_dissector.c
+@@ -137,7 +137,7 @@ ipv6:
+ 		nhoff += poff;
+ 		ports = skb_header_pointer(skb, nhoff, sizeof(_ports), &_ports);
+ 		if (ports)
+-			flow->ports = *ports;
++			flow->ports = net_hdr_word(ports);
+ 	}
+ 
+ 	return true;
+--- a/include/uapi/linux/icmpv6.h
++++ b/include/uapi/linux/icmpv6.h
+@@ -76,7 +76,7 @@ struct icmp6hdr {
+ #define icmp6_addrconf_other	icmp6_dataun.u_nd_ra.other
+ #define icmp6_rt_lifetime	icmp6_dataun.u_nd_ra.rt_lifetime
+ #define icmp6_router_pref	icmp6_dataun.u_nd_ra.router_pref
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ 
+ #define ICMPV6_ROUTER_PREF_LOW		0x3
+--- a/include/net/ndisc.h
++++ b/include/net/ndisc.h
+@@ -142,10 +142,10 @@ static inline u32 ndisc_hashfn(const voi
+ {
+ 	const u32 *p32 = pkey;
+ 
+-	return (((p32[0] ^ hash32_ptr(dev)) * hash_rnd[0]) +
+-		(p32[1] * hash_rnd[1]) +
+-		(p32[2] * hash_rnd[2]) +
+-		(p32[3] * hash_rnd[3]));
++	return (((net_hdr_word(&p32[0]) ^ hash32_ptr(dev)) * hash_rnd[0]) +
++		(net_hdr_word(&p32[1]) * hash_rnd[1]) +
++		(net_hdr_word(&p32[2]) * hash_rnd[2]) +
++		(net_hdr_word(&p32[3]) * hash_rnd[3]));
+ }
+ 
+ static inline struct neighbour *__ipv6_neigh_lookup(struct neigh_table *tbl, struct net_device *dev, const void *pkey)
+--- a/net/sched/cls_u32.c
++++ b/net/sched/cls_u32.c
+@@ -142,7 +142,7 @@ next_knode:
+ 			data = skb_header_pointer(skb, toff, 4, &hdata);
+ 			if (!data)
+ 				goto out;
+-			if ((*data ^ key->val) & key->mask) {
++			if ((net_hdr_word(data) ^ key->val) & key->mask) {
+ 				n = n->next;
+ 				goto next_knode;
+ 			}
+@@ -193,8 +193,8 @@ check_terminal:
+ 						  &hdata);
+ 			if (!data)
+ 				goto out;
+-			sel = ht->divisor & u32_hash_fold(*data, &n->sel,
+-							  n->fshift);
++			sel = ht->divisor & u32_hash_fold(net_hdr_word(data),
++							  &n->sel, n->fshift);
+ 		}
+ 		if (!(n->sel.flags & (TC_U32_VAROFFSET | TC_U32_OFFSET | TC_U32_EAT)))
+ 			goto next_ht;
+--- a/net/ipv6/ip6_offload.c
++++ b/net/ipv6/ip6_offload.c
+@@ -200,7 +200,7 @@ static struct sk_buff **ipv6_gro_receive
+ 			continue;
+ 
+ 		iph2 = ipv6_hdr(p);
+-		first_word = *(__be32 *)iph ^ *(__be32 *)iph2 ;
++		first_word = net_hdr_word(iph) ^ net_hdr_word(iph2);
+ 
+ 		/* All fields must match except length and Traffic Class. */
+ 		if (nlen != skb_network_header_len(p) ||