Content-Security-Policy: default-src 'none'
Content-Type: text/plain; charset=UTF-8
Content-Length: 480
Content-Disposition: inline; filename="940-ocf_kbuild_integration.patch"
Last-Modified: Sat, 26 Oct 2024 16:26:01 GMT
Expires: Tue, 24 Oct 2034 16:26:01 GMT
ETag: "b5cce90a1bc1269e1d2d6968fef7ce0003039a60"

--- a/crypto/Kconfig
+++ b/crypto/Kconfig
@@ -968,3 +968,6 @@ config CRYPTO_USER_API_SKCIPHER
 source "drivers/crypto/Kconfig"
 
 endif	# if CRYPTO
+
+source "crypto/ocf/Kconfig"
+
--- a/crypto/Makefile
+++ b/crypto/Makefile
@@ -92,6 +92,8 @@ obj-$(CONFIG_CRYPTO_USER_API) += af_alg.
 obj-$(CONFIG_CRYPTO_USER_API_HASH) += algif_hash.o
 obj-$(CONFIG_CRYPTO_USER_API_SKCIPHER) += algif_skcipher.o
 
+obj-$(CONFIG_OCF_OCF) += ocf/
+
 #
 # generic algorithms and the async_tx api
 #
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<span class="gi">+++ b/drivers/mtd/spi-nor/spi-nor.c</span>
<span class="gu">@@ -538,6 +538,7 @@ static const struct spi_device_id spi_no</span>
 	/* GigaDevice */
 	{ &quot;gd25q32&quot;, INFO(0xc84016, 0, 64 * 1024,  64, SECT_4K) },
 	{ &quot;gd25q64&quot;, INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
<span class="gi">+	{ &quot;gd25q128&quot;, INFO(0xc84018, 0, 64 * 1024, 256, SECT_4K) },</span>
 
 	/* Intel/Numonyx -- xxxs33b */
 	{ &quot;160s33b&quot;,  INFO(0x898911, 0, 64 * 1024,  32, 0) },
<span class="gu">@@ -560,14 +561,14 @@ static const struct spi_device_id spi_no</span>
 	{ &quot;mx66l1g55g&quot;,  INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
 
 	/* Micron */
<span class="gd">-	{ &quot;n25q032&quot;,	 INFO(0x20ba16, 0, 64 * 1024,   64, 0) },</span>
<span class="gd">-	{ &quot;n25q064&quot;,     INFO(0x20ba17, 0, 64 * 1024,  128, 0) },</span>
<span class="gd">-	{ &quot;n25q128a11&quot;,  INFO(0x20bb18, 0, 64 * 1024,  256, 0) },</span>
<span class="gd">-	{ &quot;n25q128a13&quot;,  INFO(0x20ba18, 0, 64 * 1024,  256, 0) },</span>
<span class="gd">-	{ &quot;n25q256a&quot;,    INFO(0x20ba19, 0, 64 * 1024,  512, SECT_4K) },</span>
<span class="gd">-	{ &quot;n25q512a&quot;,    INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },</span>
<span class="gd">-	{ &quot;n25q512ax3&quot;,  INFO(0x20ba20, 0, 64 * 1024, 1024, USE_FSR) },</span>
<span class="gd">-	{ &quot;n25q00&quot;,      INFO(0x20ba21, 0, 64 * 1024, 2048, USE_FSR) },</span>
<span class="gi">+	{ &quot;n25q032&quot;,	 INFO(0x20ba16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) },</span>
<span class="gi">+	{ &quot;n25q064&quot;,     INFO(0x20ba17, 0, 64 * 1024,  128, SPI_NOR_QUAD_READ) },</span>
<span class="gi">+	{ &quot;n25q128a11&quot;,  INFO(0x20bb18, 0, 64 * 1024,  256, SPI_NOR_QUAD_READ) },</span>
<span class="gi">+	{ &quot;n25q128a13&quot;,  INFO(0x20ba18, 0, 64 * 1024,  256, SPI_NOR_QUAD_READ) },</span>
<span class="gi">+	{ &quot;n25q256a&quot;,    INFO(0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ) },</span>
<span class="gi">+	{ &quot;n25q512a&quot;,    INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },</span>
<span class="gi">+	{ &quot;n25q512ax3&quot;,  INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },</span>
<span class="gi">+	{ &quot;n25q00&quot;,      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },</span>
 
 	/* PMC */
 	{ &quot;pm25lv512&quot;,   INFO(0,        0, 32 * 1024,    2, SECT_4K_PMC) },
<span class="gu">@@ -890,6 +891,45 @@ static int spansion_quad_enable(struct s</span>
 	return 0;
 }
 
<span class="gi">+static int micron_quad_enable(struct spi_nor *nor)</span>
<span class="gi">+{</span>
<span class="gi">+	int ret;</span>
<span class="gi">+	u8 val;</span>
<span class="gi">+</span>
<span class="gi">+	ret = nor-&gt;read_reg(nor, SPINOR_OP_RD_EVCR, &amp;val, 1);</span>
<span class="gi">+	if (ret &lt; 0) {</span>
<span class="gi">+		dev_err(nor-&gt;dev, &quot;error %d reading EVCR\n&quot;, ret);</span>
<span class="gi">+		return ret;</span>
<span class="gi">+	}</span>
<span class="gi">+</span>
<span class="gi">+	write_enable(nor);</span>
<span class="gi">+</span>
<span class="gi">+	/* set EVCR, enable quad I/O */</span>
<span class="gi">+	nor-&gt;cmd_buf[0] = val &amp; ~EVCR_QUAD_EN_MICRON;</span>
<span class="gi">+	ret = nor-&gt;write_reg(nor, SPINOR_OP_WD_EVCR, nor-&gt;cmd_buf, 1, 0);</span>
<span class="gi">+	if (ret &lt; 0) {</span>
<span class="gi">+		dev_err(nor-&gt;dev, &quot;error while writing EVCR register\n&quot;);</span>
<span class="gi">+		return ret;</span>
<span class="gi">+	}</span>
<span class="gi">+</span>
<span class="gi">+	ret = spi_nor_wait_till_ready(nor);</span>
<span class="gi">+	if (ret)</span>
<span class="gi">+		return ret;</span>
<span class="gi">+</span>
<span class="gi">+	/* read EVCR and check it */</span>
<span class="gi">+	ret = nor-&gt;read_reg(nor, SPINOR_OP_RD_EVCR, &amp;val, 1);</span>
<span class="gi">+	if (ret &lt; 0) {</span>
<span class="gi">+		dev_err(nor-&gt;dev, &quot;error %d reading EVCR\n&quot;, ret);</span>
<span class="gi">+		return ret;</span>
<span class="gi">+	}</span>
<span class="gi">+	if (val &amp; EVCR_QUAD_EN_MICRON) {</span>
<span class="gi">+		dev_err(nor-&gt;dev, &quot;Micron EVCR Quad bit not clear\n&quot;);</span>
<span class="gi">+		return -EINVAL;</span>
<span class="gi">+	}</span>
<span class="gi">+</span>
<span class="gi">+	return 0;</span>
<span class="gi">+}</span>
<span class="gi">+</span>
 static int set_quad_mode(struct spi_nor *nor, struct flash_info *info)
 {
 	int status;
<span class="gu">@@ -902,6 +942,13 @@ static int set_quad_mode(struct spi_nor</span>
 			return -EINVAL;
 		}
 		return status;
<span class="gi">+	case CFI_MFR_ST:</span>
<span class="gi">+		status = micron_quad_enable(nor);</span>
<span class="gi">+		if (status) {</span>
<span class="gi">+			dev_err(nor-&gt;dev, &quot;Micron quad-read not enabled\n&quot;);</span>
<span class="gi">+			return -EINVAL;</span>
<span class="gi">+		}</span>
<span class="gi">+		return status;</span>
 	default:
 		status = spansion_quad_enable(nor);
 		if (status) {
<span class="gd">--- a/include/linux/mtd/spi-nor.h</span>
<span class="gi">+++ b/include/linux/mtd/spi-nor.h</span>
<span class="gu">@@ -56,6 +56,10 @@</span>
 /* Used for Spansion flashes only. */
 #define SPINOR_OP_BRWR		0x17	/* Bank register write */
 
<span class="gi">+/* Used for Micron flashes only. */</span>
<span class="gi">+#define SPINOR_OP_RD_EVCR      0x65    /* Read EVCR register */</span>
<span class="gi">+#define SPINOR_OP_WD_EVCR      0x61    /* Write EVCR register */</span>
<span class="gi">+</span>
 /* Status Register bits. */
 #define SR_WIP			1	/* Write in progress */
 #define SR_WEL			2	/* Write enable latch */
<span class="gu">@@ -67,6 +71,9 @@</span>
 
 #define SR_QUAD_EN_MX		0x40	/* Macronix Quad I/O */
 
<span class="gi">+/* Enhanced Volatile Configuration Register bits */</span>
<span class="gi">+#define EVCR_QUAD_EN_MICRON    0x80    /* Micron Quad I/O */</span>
<span class="gi">+</span>
 /* Flag Status Register bits */
 #define FSR_READY		0x80
 
</pre></div>
</code></pre></td></tr></table>
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