aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/sunxi/patches-3.12/105-clk-sunxi_mod0.patch
diff options
context:
space:
mode:
Diffstat (limited to 'target/linux/sunxi/patches-3.12/105-clk-sunxi_mod0.patch')
-rw-r--r--target/linux/sunxi/patches-3.12/105-clk-sunxi_mod0.patch121
1 files changed, 121 insertions, 0 deletions
diff --git a/target/linux/sunxi/patches-3.12/105-clk-sunxi_mod0.patch b/target/linux/sunxi/patches-3.12/105-clk-sunxi_mod0.patch
new file mode 100644
index 0000000000..bbb8057f7c
--- /dev/null
+++ b/target/linux/sunxi/patches-3.12/105-clk-sunxi_mod0.patch
@@ -0,0 +1,121 @@
+From 3473e6acea4bd01ba2b334628970390207f9f4fd Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
+Date: Tue, 21 May 2013 21:25:05 -0300
+Subject: [PATCH] clk: sunxi: mod0 support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This commit implements support for the "module 0" type of clocks, as
+used by MMC, IR, NAND, SATA and other components.
+
+Signed-off-by: Emilio López <emilio@elopez.com.ar>
+---
+ Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
+ drivers/clk/sunxi/clk-sunxi.c | 57 +++++++++++++++++++++++
+ 2 files changed, 58 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
+index 773f3ae..ff3f61c 100644
+--- a/Documentation/devicetree/bindings/clock/sunxi.txt
++++ b/Documentation/devicetree/bindings/clock/sunxi.txt
+@@ -35,6 +35,7 @@ Required properties:
+ "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
+ "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
+ "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
++ "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
+
+ Required properties for all clocks:
+ - reg : shall be the control register address for the clock.
+diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
+index 6947ba9..96c01b2 100644
+--- a/drivers/clk/sunxi/clk-sunxi.c
++++ b/drivers/clk/sunxi/clk-sunxi.c
+@@ -287,6 +287,47 @@ static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
+
+
+ /**
++ * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
++ * MMC rate is calculated as follows
++ * rate = (parent_rate >> p) / (m + 1);
++ */
++
++static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
++ u8 *n, u8 *k, u8 *m, u8 *p)
++{
++ u8 div, calcm, calcp;
++
++ /* These clocks can only divide, so we will never be able to achieve
++ * frequencies higher than the parent frequency */
++ if (*freq > parent_rate)
++ *freq = parent_rate;
++
++ div = parent_rate / *freq;
++
++ if (div < 16)
++ calcp = 0;
++ else if (div / 2 < 16)
++ calcp = 1;
++ else if (div / 4 < 16)
++ calcp = 2;
++ else
++ calcp = 3;
++
++ calcm = DIV_ROUND_UP(div, 1 << calcp);
++
++ *freq = (parent_rate >> calcp) / calcm;
++
++ /* we were called to round the frequency, we can now return */
++ if (n == NULL)
++ return;
++
++ *m = calcm - 1;
++ *p = calcp;
++}
++
++
++
++/**
+ * sunxi_factors_clk_setup() - Setup function for factor clocks
+ */
+
+@@ -333,6 +374,14 @@ struct factors_data {
+ .pwidth = 2,
+ };
+
++/* user manual says "n" but it's really "p" */
++static struct clk_factors_config sun4i_mod0_config = {
++ .mshift = 0,
++ .mwidth = 4,
++ .pshift = 16,
++ .pwidth = 2,
++};
++
+ static const struct factors_data sun4i_pll1_data __initconst = {
+ .enable = 31,
+ .table = &sun4i_pll1_config,
+@@ -356,6 +405,13 @@ struct factors_data {
+ .getter = sun4i_get_apb1_factors,
+ };
+
++static const struct factors_data sun4i_mod0_data __initconst = {
++ .enable = 31,
++ .mux = 24,
++ .table = &sun4i_mod0_config,
++ .getter = sun4i_get_mod0_factors,
++};
++
+ static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
+ const struct factors_data *data)
+ {
+@@ -779,6 +835,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
+ {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
+ {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
+ {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
++ {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
+ {}
+ };
+
+--
+1.8.4
+