diff options
Diffstat (limited to 'target/linux/mvebu/patches-3.10/0164-ARM-mvebu-fix-register-length-for-Armada-XP-PMSU.patch')
| -rw-r--r-- | target/linux/mvebu/patches-3.10/0164-ARM-mvebu-fix-register-length-for-Armada-XP-PMSU.patch | 34 |
1 files changed, 0 insertions, 34 deletions
diff --git a/target/linux/mvebu/patches-3.10/0164-ARM-mvebu-fix-register-length-for-Armada-XP-PMSU.patch b/target/linux/mvebu/patches-3.10/0164-ARM-mvebu-fix-register-length-for-Armada-XP-PMSU.patch deleted file mode 100644 index 7b58f61a77..0000000000 --- a/target/linux/mvebu/patches-3.10/0164-ARM-mvebu-fix-register-length-for-Armada-XP-PMSU.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 10208caf7f0ebfb3d6b546aa2ae66e42462551e0 Mon Sep 17 00:00:00 2001 -From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> -Date: Wed, 4 Dec 2013 14:37:52 +0100 -Subject: [PATCH 164/203] ARM: mvebu: fix register length for Armada XP PMSU - -The per-CPU PMSU registers documented in the datasheet start at -0x22100 and the last register for CPU3 is at 0x22428. However, the DT -informations use <0x22100 0x430>, which makes the region end at -0x22530 and not 0x22430. - -Moreover, looking at the datasheet, we can see that the registers for -CPU0 start at 0x22100, for CPU1 at 0x22200, for CPU2 at 0x22300 and -for CPU3 at 0x22400. It seems clear that 0x100 bytes of registers have -been used per CPU. - -Therefore, this commit reduces the length of the PMSU per-CPU register -area from the incorrect 0x430 bytes to a more logical 0x400 bytes. - -Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> ---- - arch/arm/boot/dts/armada-xp.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/armada-xp.dtsi -+++ b/arch/arm/boot/dts/armada-xp.dtsi -@@ -48,7 +48,7 @@ - - armada-370-xp-pmsu@22000 { - compatible = "marvell,armada-370-xp-pmsu"; -- reg = <0x22100 0x430>, <0x20800 0x20>; -+ reg = <0x22100 0x400>, <0x20800 0x20>; - }; - - serial@12200 { |