diff options
Diffstat (limited to 'target/linux/generic/patches-2.6.31/941-ssb_update.patch')
| -rw-r--r-- | target/linux/generic/patches-2.6.31/941-ssb_update.patch | 2517 |
1 files changed, 2443 insertions, 74 deletions
diff --git a/target/linux/generic/patches-2.6.31/941-ssb_update.patch b/target/linux/generic/patches-2.6.31/941-ssb_update.patch index b8c8c0674c..42620a12a0 100644 --- a/target/linux/generic/patches-2.6.31/941-ssb_update.patch +++ b/target/linux/generic/patches-2.6.31/941-ssb_update.patch @@ -1,3 +1,104 @@ +--- a/drivers/ssb/Kconfig ++++ b/drivers/ssb/Kconfig +@@ -66,6 +66,20 @@ config SSB_PCMCIAHOST + + If unsure, say N + ++config SSB_SDIOHOST_POSSIBLE ++ bool ++ depends on SSB && (MMC = y || MMC = SSB) ++ default y ++ ++config SSB_SDIOHOST ++ bool "Support for SSB on SDIO-bus host" ++ depends on SSB_SDIOHOST_POSSIBLE ++ help ++ Support for a Sonics Silicon Backplane on top ++ of a SDIO device. ++ ++ If unsure, say N ++ + config SSB_SILENT + bool "No SSB kernel messages" + depends on SSB && EMBEDDED +--- a/drivers/ssb/Makefile ++++ b/drivers/ssb/Makefile +@@ -6,6 +6,7 @@ ssb-$(CONFIG_SSB_SPROM) += sprom.o + # host support + ssb-$(CONFIG_SSB_PCIHOST) += pci.o pcihost_wrapper.o + ssb-$(CONFIG_SSB_PCMCIAHOST) += pcmcia.o ++ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o + + # built-in drivers + ssb-y += driver_chipcommon.o +--- a/drivers/ssb/b43_pci_bridge.c ++++ b/drivers/ssb/b43_pci_bridge.c +@@ -24,6 +24,7 @@ static const struct pci_device_id b43_pc + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4312) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4315) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4318) }, ++ { PCI_DEVICE(PCI_VENDOR_ID_BCM_GVC, 0x4318) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) }, +--- a/drivers/ssb/driver_chipcommon.c ++++ b/drivers/ssb/driver_chipcommon.c +@@ -209,6 +209,24 @@ static void chipco_powercontrol_init(str + } + } + ++/* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */ ++static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc) ++{ ++ struct ssb_bus *bus = cc->dev->bus; ++ ++ switch (bus->chip_id) { ++ case 0x4312: ++ case 0x4322: ++ case 0x4328: ++ return 7000; ++ case 0x4325: ++ /* TODO: */ ++ default: ++ return 15000; ++ } ++} ++ ++/* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */ + static void calc_fast_powerup_delay(struct ssb_chipcommon *cc) + { + struct ssb_bus *bus = cc->dev->bus; +@@ -218,6 +236,12 @@ static void calc_fast_powerup_delay(stru + + if (bus->bustype != SSB_BUSTYPE_PCI) + return; ++ ++ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) { ++ cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc); ++ return; ++ } ++ + if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) + return; + +@@ -233,6 +257,9 @@ void ssb_chipcommon_init(struct ssb_chip + { + if (!cc->dev) + return; /* We don't have a ChipCommon */ ++ if (cc->dev->id.revision >= 11) ++ cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT); ++ ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status); + ssb_pmu_init(cc); + chipco_powercontrol_init(cc); + ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST); +@@ -370,6 +397,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c + { + return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value); + } ++EXPORT_SYMBOL(ssb_chipco_gpio_control); + + u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value) + { --- a/drivers/ssb/driver_chipcommon_pmu.c +++ b/drivers/ssb/driver_chipcommon_pmu.c @@ -28,6 +28,21 @@ static void ssb_chipco_pll_write(struct @@ -22,7 +123,57 @@ struct pmu0_plltab_entry { u16 freq; /* Crystal frequency in kHz.*/ u8 xf; /* Crystal frequency value for PMU control */ -@@ -506,3 +521,82 @@ void ssb_pmu_init(struct ssb_chipcommon +@@ -317,6 +332,12 @@ static void ssb_pmu_pll_init(struct ssb_ + case 0x5354: + ssb_pmu0_pllinit_r0(cc, crystalfreq); + break; ++ case 0x4322: ++ if (cc->pmu.rev == 2) { ++ chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A); ++ chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0); ++ } ++ break; + default: + ssb_printk(KERN_ERR PFX + "ERROR: PLL init unknown for device %04X\n", +@@ -402,6 +423,7 @@ static void ssb_pmu_resources_init(struc + + switch (bus->chip_id) { + case 0x4312: ++ case 0x4322: + /* We keep the default settings: + * min_msk = 0xCBB + * max_msk = 0x7FFFF +@@ -480,9 +502,9 @@ static void ssb_pmu_resources_init(struc + chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk); + } + ++/* http://bcm-v4.sipsolutions.net/802.11/SSB/PmuInit */ + void ssb_pmu_init(struct ssb_chipcommon *cc) + { +- struct ssb_bus *bus = cc->dev->bus; + u32 pmucap; + + if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU)) +@@ -494,15 +516,91 @@ void ssb_pmu_init(struct ssb_chipcommon + ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n", + cc->pmu.rev, pmucap); + +- if (cc->pmu.rev >= 1) { +- if ((bus->chip_id == 0x4325) && (bus->chip_rev < 2)) { +- chipco_mask32(cc, SSB_CHIPCO_PMU_CTL, +- ~SSB_CHIPCO_PMU_CTL_NOILPONW); +- } else { +- chipco_set32(cc, SSB_CHIPCO_PMU_CTL, +- SSB_CHIPCO_PMU_CTL_NOILPONW); +- } +- } ++ if (cc->pmu.rev == 1) ++ chipco_mask32(cc, SSB_CHIPCO_PMU_CTL, ++ ~SSB_CHIPCO_PMU_CTL_NOILPONW); ++ else ++ chipco_set32(cc, SSB_CHIPCO_PMU_CTL, ++ SSB_CHIPCO_PMU_CTL_NOILPONW); ssb_pmu_pll_init(cc); ssb_pmu_resources_init(cc); } @@ -105,18 +256,511 @@ + +EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage); +EXPORT_SYMBOL(ssb_pmu_set_ldo_paref); +--- a/drivers/ssb/driver_gige.c ++++ b/drivers/ssb/driver_gige.c +@@ -12,6 +12,7 @@ + #include <linux/ssb/ssb_driver_gige.h> + #include <linux/pci.h> + #include <linux/pci_regs.h> ++#include <linux/slab.h> + + + /* +--- a/drivers/ssb/driver_mipscore.c ++++ b/drivers/ssb/driver_mipscore.c +@@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco + set_irq(dev, irq++); + } + break; +- /* fallthrough */ + case SSB_DEV_PCI: + case SSB_DEV_ETHERNET: + case SSB_DEV_ETHERNET_GBIT: +@@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco + set_irq(dev, irq++); + break; + } ++ /* fallthrough */ ++ case SSB_DEV_EXTIF: ++ set_irq(dev, 0); ++ break; + } + } + ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n"); +--- a/drivers/ssb/driver_pcicore.c ++++ b/drivers/ssb/driver_pcicore.c +@@ -246,20 +246,12 @@ static struct pci_controller ssb_pcicore + .pci_ops = &ssb_pcicore_pciops, + .io_resource = &ssb_pcicore_io_resource, + .mem_resource = &ssb_pcicore_mem_resource, +- .mem_offset = 0x24000000, + }; + +-static u32 ssb_pcicore_pcibus_iobase = 0x100; +-static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA; +- + /* This function is called when doing a pci_enable_device(). + * We must first check if the device is a device on the PCI-core bridge. */ + int ssb_pcicore_plat_dev_init(struct pci_dev *d) + { +- struct resource *res; +- int pos, size; +- u32 *base; +- + if (d->bus->ops != &ssb_pcicore_pciops) { + /* This is not a device on the PCI-core bridge. */ + return -ENODEV; +@@ -268,27 +260,6 @@ int ssb_pcicore_plat_dev_init(struct pci + ssb_printk(KERN_INFO "PCI: Fixing up device %s\n", + pci_name(d)); + +- /* Fix up resource bases */ +- for (pos = 0; pos < 6; pos++) { +- res = &d->resource[pos]; +- if (res->flags & IORESOURCE_IO) +- base = &ssb_pcicore_pcibus_iobase; +- else +- base = &ssb_pcicore_pcibus_membase; +- res->flags |= IORESOURCE_PCI_FIXED; +- if (res->end) { +- size = res->end - res->start + 1; +- if (*base & (size - 1)) +- *base = (*base + size) & ~(size - 1); +- res->start = *base; +- res->end = res->start + size - 1; +- *base += size; +- pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start); +- } +- /* Fix up PCI bridge BAR0 only */ +- if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0) +- break; +- } + /* Fix up interrupt lines */ + d->irq = ssb_mips_irq(extpci_core->dev) + 2; + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq); +@@ -551,13 +522,13 @@ int ssb_pcicore_dev_irqvecs_enable(struc + might_sleep_if(pdev->id.coreid != SSB_DEV_PCI); + + /* Enable interrupts for this device. */ +- if (bus->host_pci && +- ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) { ++ if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) { + u32 coremask; + + /* Calculate the "coremask" for the device. */ + coremask = (1 << dev->core_index); + ++ SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI); + err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp); + if (err) + goto out; --- a/drivers/ssb/main.c +++ b/drivers/ssb/main.c -@@ -469,6 +469,8 @@ static int ssb_devices_register(struct s +@@ -17,6 +17,8 @@ + #include <linux/ssb/ssb_driver_gige.h> + #include <linux/dma-mapping.h> + #include <linux/pci.h> ++#include <linux/mmc/sdio_func.h> ++#include <linux/slab.h> + + #include <pcmcia/cs_types.h> + #include <pcmcia/cs.h> +@@ -88,6 +90,25 @@ found: + } + #endif /* CONFIG_SSB_PCMCIAHOST */ + ++#ifdef CONFIG_SSB_SDIOHOST ++struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func) ++{ ++ struct ssb_bus *bus; ++ ++ ssb_buses_lock(); ++ list_for_each_entry(bus, &buses, list) { ++ if (bus->bustype == SSB_BUSTYPE_SDIO && ++ bus->host_sdio == func) ++ goto found; ++ } ++ bus = NULL; ++found: ++ ssb_buses_unlock(); ++ ++ return bus; ++} ++#endif /* CONFIG_SSB_SDIOHOST */ ++ + int ssb_for_each_bus_call(unsigned long data, + int (*func)(struct ssb_bus *bus, unsigned long data)) + { +@@ -120,6 +141,19 @@ static void ssb_device_put(struct ssb_de + put_device(dev->dev); + } + ++static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv) ++{ ++ if (drv) ++ get_driver(&drv->drv); ++ return drv; ++} ++ ++static inline void ssb_driver_put(struct ssb_driver *drv) ++{ ++ if (drv) ++ put_driver(&drv->drv); ++} ++ + static int ssb_device_resume(struct device *dev) + { + struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); +@@ -190,90 +224,81 @@ int ssb_bus_suspend(struct ssb_bus *bus) + EXPORT_SYMBOL(ssb_bus_suspend); + + #ifdef CONFIG_SSB_SPROM +-int ssb_devices_freeze(struct ssb_bus *bus) ++/** ssb_devices_freeze - Freeze all devices on the bus. ++ * ++ * After freezing no device driver will be handling a device ++ * on this bus anymore. ssb_devices_thaw() must be called after ++ * a successful freeze to reactivate the devices. ++ * ++ * @bus: The bus. ++ * @ctx: Context structure. Pass this to ssb_devices_thaw(). ++ */ ++int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx) + { +- struct ssb_device *dev; +- struct ssb_driver *drv; +- int err = 0; +- int i; +- pm_message_t state = PMSG_FREEZE; ++ struct ssb_device *sdev; ++ struct ssb_driver *sdrv; ++ unsigned int i; ++ ++ memset(ctx, 0, sizeof(*ctx)); ++ ctx->bus = bus; ++ SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen)); + +- /* First check that we are capable to freeze all devices. */ + for (i = 0; i < bus->nr_devices; i++) { +- dev = &(bus->devices[i]); +- if (!dev->dev || +- !dev->dev->driver || +- !device_is_registered(dev->dev)) +- continue; +- drv = drv_to_ssb_drv(dev->dev->driver); +- if (!drv) ++ sdev = ssb_device_get(&bus->devices[i]); ++ ++ if (!sdev->dev || !sdev->dev->driver || ++ !device_is_registered(sdev->dev)) { ++ ssb_device_put(sdev); + continue; +- if (!drv->suspend) { +- /* Nope, can't suspend this one. */ +- return -EOPNOTSUPP; + } +- } +- /* Now suspend all devices */ +- for (i = 0; i < bus->nr_devices; i++) { +- dev = &(bus->devices[i]); +- if (!dev->dev || +- !dev->dev->driver || +- !device_is_registered(dev->dev)) ++ sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver)); ++ if (!sdrv || SSB_WARN_ON(!sdrv->remove)) { ++ ssb_device_put(sdev); + continue; +- drv = drv_to_ssb_drv(dev->dev->driver); +- if (!drv) +- continue; +- err = drv->suspend(dev, state); +- if (err) { +- ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n", +- dev_name(dev->dev)); +- goto err_unwind; + } ++ sdrv->remove(sdev); ++ ctx->device_frozen[i] = 1; + } + + return 0; +-err_unwind: +- for (i--; i >= 0; i--) { +- dev = &(bus->devices[i]); +- if (!dev->dev || +- !dev->dev->driver || +- !device_is_registered(dev->dev)) +- continue; +- drv = drv_to_ssb_drv(dev->dev->driver); +- if (!drv) +- continue; +- if (drv->resume) +- drv->resume(dev); +- } +- return err; + } + +-int ssb_devices_thaw(struct ssb_bus *bus) ++/** ssb_devices_thaw - Unfreeze all devices on the bus. ++ * ++ * This will re-attach the device drivers and re-init the devices. ++ * ++ * @ctx: The context structure from ssb_devices_freeze() ++ */ ++int ssb_devices_thaw(struct ssb_freeze_context *ctx) + { +- struct ssb_device *dev; +- struct ssb_driver *drv; +- int err; +- int i; ++ struct ssb_bus *bus = ctx->bus; ++ struct ssb_device *sdev; ++ struct ssb_driver *sdrv; ++ unsigned int i; ++ int err, result = 0; + + for (i = 0; i < bus->nr_devices; i++) { +- dev = &(bus->devices[i]); +- if (!dev->dev || +- !dev->dev->driver || +- !device_is_registered(dev->dev)) ++ if (!ctx->device_frozen[i]) + continue; +- drv = drv_to_ssb_drv(dev->dev->driver); +- if (!drv) ++ sdev = &bus->devices[i]; ++ ++ if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver)) + continue; +- if (SSB_WARN_ON(!drv->resume)) ++ sdrv = drv_to_ssb_drv(sdev->dev->driver); ++ if (SSB_WARN_ON(!sdrv || !sdrv->probe)) + continue; +- err = drv->resume(dev); ++ ++ err = sdrv->probe(sdev, &sdev->id); + if (err) { + ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n", +- dev_name(dev->dev)); ++ dev_name(sdev->dev)); ++ result = err; + } ++ ssb_driver_put(sdrv); ++ ssb_device_put(sdev); + } + +- return 0; ++ return result; + } + #endif /* CONFIG_SSB_SPROM */ + +@@ -360,6 +385,35 @@ static int ssb_device_uevent(struct devi + ssb_dev->id.revision); + } + ++#define ssb_config_attr(attrib, field, format_string) \ ++static ssize_t \ ++attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \ ++{ \ ++ return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \ ++} ++ ++ssb_config_attr(core_num, core_index, "%u\n") ++ssb_config_attr(coreid, id.coreid, "0x%04x\n") ++ssb_config_attr(vendor, id.vendor, "0x%04x\n") ++ssb_config_attr(revision, id.revision, "%u\n") ++ssb_config_attr(irq, irq, "%u\n") ++static ssize_t ++name_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%s\n", ++ ssb_core_name(dev_to_ssb_dev(dev)->id.coreid)); ++} ++ ++static struct device_attribute ssb_device_attrs[] = { ++ __ATTR_RO(name), ++ __ATTR_RO(core_num), ++ __ATTR_RO(coreid), ++ __ATTR_RO(vendor), ++ __ATTR_RO(revision), ++ __ATTR_RO(irq), ++ __ATTR_NULL, ++}; ++ + static struct bus_type ssb_bustype = { + .name = "ssb", + .match = ssb_bus_match, +@@ -369,6 +423,7 @@ static struct bus_type ssb_bustype = { + .suspend = ssb_device_suspend, + .resume = ssb_device_resume, + .uevent = ssb_device_uevent, ++ .dev_attrs = ssb_device_attrs, + }; + + static void ssb_buses_lock(void) +@@ -461,6 +516,7 @@ static int ssb_devices_register(struct s + #ifdef CONFIG_SSB_PCIHOST + sdev->irq = bus->host_pci->irq; + dev->parent = &bus->host_pci->dev; ++ sdev->dma_dev = dev->parent; + #endif + break; + case SSB_BUSTYPE_PCMCIA: +@@ -469,8 +525,14 @@ static int ssb_devices_register(struct s dev->parent = &bus->host_pcmcia->dev; #endif break; + case SSB_BUSTYPE_SDIO: ++#ifdef CONFIG_SSB_SDIOHOST ++ dev->parent = &bus->host_sdio->dev; ++#endif + break; case SSB_BUSTYPE_SSB: dev->dma_mask = &dev->coherent_dma_mask; ++ sdev->dma_dev = dev; break; -@@ -1358,8 +1360,10 @@ static int __init ssb_modinit(void) + } + +@@ -724,12 +786,18 @@ static int ssb_bus_register(struct ssb_b + err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); + if (err) + goto out; ++ ++ /* Init SDIO-host device (if any), before the scan */ ++ err = ssb_sdio_init(bus); ++ if (err) ++ goto err_disable_xtal; ++ + ssb_buses_lock(); + bus->busnumber = next_busnumber; + /* Scan for devices (cores) */ + err = ssb_bus_scan(bus, baseaddr); + if (err) +- goto err_disable_xtal; ++ goto err_sdio_exit; + + /* Init PCI-host device (if any) */ + err = ssb_pci_init(bus); +@@ -776,6 +844,8 @@ err_pci_exit: + ssb_pci_exit(bus); + err_unmap: + ssb_iounmap(bus); ++err_sdio_exit: ++ ssb_sdio_exit(bus); + err_disable_xtal: + ssb_buses_unlock(); + ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); +@@ -796,6 +866,9 @@ int ssb_bus_pcibus_register(struct ssb_b + if (!err) { + ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " + "PCI device %s\n", dev_name(&host_pci->dev)); ++ } else { ++ ssb_printk(KERN_ERR PFX "Failed to register PCI version" ++ " of SSB with error %d\n", err); + } + + return err; +@@ -825,6 +898,28 @@ int ssb_bus_pcmciabus_register(struct ss + EXPORT_SYMBOL(ssb_bus_pcmciabus_register); + #endif /* CONFIG_SSB_PCMCIAHOST */ + ++#ifdef CONFIG_SSB_SDIOHOST ++int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func, ++ unsigned int quirks) ++{ ++ int err; ++ ++ bus->bustype = SSB_BUSTYPE_SDIO; ++ bus->host_sdio = func; ++ bus->ops = &ssb_sdio_ops; ++ bus->quirks = quirks; ++ ++ err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0); ++ if (!err) { ++ ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " ++ "SDIO device %s\n", sdio_func_id(func)); ++ } ++ ++ return err; ++} ++EXPORT_SYMBOL(ssb_bus_sdiobus_register); ++#endif /* CONFIG_SSB_PCMCIAHOST */ ++ + int ssb_bus_ssbbus_register(struct ssb_bus *bus, + unsigned long baseaddr, + ssb_invariants_func_t get_invariants) +@@ -1099,10 +1194,10 @@ void ssb_device_enable(struct ssb_device + } + EXPORT_SYMBOL(ssb_device_enable); + +-/* Wait for a bit in a register to get set or unset. ++/* Wait for bitmask in a register to get set or cleared. + * timeout is in units of ten-microseconds */ +-static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask, +- int timeout, int set) ++static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask, ++ int timeout, int set) + { + int i; + u32 val; +@@ -1110,7 +1205,7 @@ static int ssb_wait_bit(struct ssb_devic + for (i = 0; i < timeout; i++) { + val = ssb_read32(dev, reg); + if (set) { +- if (val & bitmask) ++ if ((val & bitmask) == bitmask) + return 0; + } else { + if (!(val & bitmask)) +@@ -1127,20 +1222,38 @@ static int ssb_wait_bit(struct ssb_devic + + void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags) + { +- u32 reject; ++ u32 reject, val; + + if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET) + return; + + reject = ssb_tmslow_reject_bitmask(dev); +- ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK); +- ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1); +- ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0); +- ssb_write32(dev, SSB_TMSLOW, +- SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | +- reject | SSB_TMSLOW_RESET | +- core_specific_flags); +- ssb_flush_tmslow(dev); ++ ++ if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) { ++ ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK); ++ ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1); ++ ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0); ++ ++ if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) { ++ val = ssb_read32(dev, SSB_IMSTATE); ++ val |= SSB_IMSTATE_REJECT; ++ ssb_write32(dev, SSB_IMSTATE, val); ++ ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000, ++ 0); ++ } ++ ++ ssb_write32(dev, SSB_TMSLOW, ++ SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | ++ reject | SSB_TMSLOW_RESET | ++ core_specific_flags); ++ ssb_flush_tmslow(dev); ++ ++ if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) { ++ val = ssb_read32(dev, SSB_IMSTATE); ++ val &= ~SSB_IMSTATE_REJECT; ++ ssb_write32(dev, SSB_IMSTATE, val); ++ } ++ } + + ssb_write32(dev, SSB_TMSLOW, + reject | SSB_TMSLOW_RESET | +@@ -1358,8 +1471,10 @@ static int __init ssb_modinit(void) ssb_buses_lock(); err = ssb_attach_queued_buses(); ssb_buses_unlock(); @@ -128,7 +772,7 @@ err = b43_pci_ssb_bridge_init(); if (err) { -@@ -1375,7 +1379,7 @@ static int __init ssb_modinit(void) +@@ -1375,7 +1490,7 @@ static int __init ssb_modinit(void) /* don't fail SSB init because of this */ err = 0; } @@ -139,9 +783,20 @@ /* ssb must be initialized after PCI but before the ssb drivers. --- a/drivers/ssb/pci.c +++ b/drivers/ssb/pci.c -@@ -169,8 +169,14 @@ err_pci: +@@ -17,6 +17,7 @@ + + #include <linux/ssb/ssb.h> + #include <linux/ssb/ssb_regs.h> ++#include <linux/slab.h> + #include <linux/pci.h> + #include <linux/delay.h> + +@@ -167,10 +168,16 @@ err_pci: + } + /* Get the word-offset for a SSB_SPROM_XXX define. */ - #define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16)) +-#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16)) ++#define SPOFF(offset) ((offset) / sizeof(u16)) /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */ -#define SPEX(_outvar, _offset, _mask, _shift) \ +#define SPEX16(_outvar, _offset, _mask, _shift) \ @@ -155,7 +810,96 @@ static inline u8 ssb_crc8(u8 crc, u8 data) { -@@ -474,12 +480,14 @@ static void sprom_extract_r8(struct ssb_ +@@ -247,7 +254,7 @@ static int sprom_do_read(struct ssb_bus + int i; + + for (i = 0; i < bus->sprom_size; i++) +- sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2)); ++ sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2)); + + return 0; + } +@@ -278,7 +285,7 @@ static int sprom_do_write(struct ssb_bus + ssb_printk("75%%"); + else if (i % 2) + ssb_printk("."); +- writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2)); ++ writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2)); + mmiowb(); + msleep(20); + } +@@ -399,6 +406,46 @@ static void sprom_extract_r123(struct ss + out->antenna_gain.ghz5.a3 = gain; + } + ++/* Revs 4 5 and 8 have partially shared layout */ ++static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in) ++{ ++ SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, ++ SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT); ++ SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01, ++ SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT); ++ SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23, ++ SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT); ++ SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23, ++ SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT); ++ ++ SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01, ++ SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT); ++ SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01, ++ SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT); ++ SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23, ++ SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT); ++ SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23, ++ SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT); ++ ++ SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01, ++ SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT); ++ SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01, ++ SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT); ++ SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23, ++ SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT); ++ SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23, ++ SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT); ++ ++ SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01, ++ SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT); ++ SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01, ++ SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT); ++ SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23, ++ SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT); ++ SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23, ++ SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT); ++} ++ + static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in) + { + int i; +@@ -421,10 +468,14 @@ static void sprom_extract_r45(struct ssb + SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0); + SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0); + SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0); ++ SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0); ++ SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0); + } else { + SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0); + SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0); + SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0); ++ SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0); ++ SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0); + } + SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A, + SSB_SPROM4_ANTAVAIL_A_SHIFT); +@@ -464,6 +515,8 @@ static void sprom_extract_r45(struct ssb + memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24, + sizeof(out->antenna_gain.ghz5)); + ++ sprom_extract_r458(out, in); ++ + /* TODO - get remaining rev 4 stuff needed */ + } + +@@ -474,12 +527,14 @@ static void sprom_extract_r8(struct ssb_ /* extract the MAC address */ for (i = 0; i < 3; i++) { @@ -171,7 +915,7 @@ SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A, SSB_SPROM8_ANTAVAIL_A_SHIFT); SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG, -@@ -490,12 +498,55 @@ static void sprom_extract_r8(struct ssb_ +@@ -490,12 +545,55 @@ static void sprom_extract_r8(struct ssb_ SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0); SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A, SSB_SPROM8_ITSSI_A_SHIFT); @@ -227,35 +971,450 @@ /* Extract the antenna gain values. */ SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01, -@@ -549,6 +600,7 @@ static int sprom_extract(struct ssb_bus - ssb_printk(KERN_WARNING PFX "Unsupported SPROM" - " revision %d detected. Will extract" - " v1\n", out->revision); -+ out->revision = 1; - sprom_extract_r123(out, in); - } +@@ -509,6 +607,8 @@ static void sprom_extract_r8(struct ssb_ + memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24, + sizeof(out->antenna_gain.ghz5)); + ++ sprom_extract_r458(out, in); ++ + /* TODO - get remaining rev 8 stuff needed */ + } + +@@ -521,36 +621,34 @@ static int sprom_extract(struct ssb_bus + ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision); + memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */ + memset(out->et1mac, 0xFF, 6); ++ + if ((bus->chip_id & 0xFF00) == 0x4400) { + /* Workaround: The BCM44XX chip has a stupid revision + * number stored in the SPROM. + * Always extract r1. */ + out->revision = 1; ++ ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision); ++ } ++ ++ switch (out->revision) { ++ case 1: ++ case 2: ++ case 3: + sprom_extract_r123(out, in); +- } else if (bus->chip_id == 0x4321) { +- /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */ +- out->revision = 4; ++ break; ++ case 4: ++ case 5: + sprom_extract_r45(out, in); +- } else { +- switch (out->revision) { +- case 1: +- case 2: +- case 3: +- sprom_extract_r123(out, in); +- break; +- case 4: +- case 5: +- sprom_extract_r45(out, in); +- break; +- case 8: +- sprom_extract_r8(out, in); +- break; +- default: +- ssb_printk(KERN_WARNING PFX "Unsupported SPROM" +- " revision %d detected. Will extract" +- " v1\n", out->revision); +- sprom_extract_r123(out, in); +- } ++ break; ++ case 8: ++ sprom_extract_r8(out, in); ++ break; ++ default: ++ ssb_printk(KERN_WARNING PFX "Unsupported SPROM" ++ " revision %d detected. Will extract" ++ " v1\n", out->revision); ++ out->revision = 1; ++ sprom_extract_r123(out, in); } + + if (out->boardflags_lo == 0xFFFF) +@@ -565,12 +663,34 @@ static int ssb_pci_sprom_get(struct ssb_ + struct ssb_sprom *sprom) + { + const struct ssb_sprom *fallback; +- int err = -ENOMEM; ++ int err; + u16 *buf; + ++ if (!ssb_is_sprom_available(bus)) { ++ ssb_printk(KERN_ERR PFX "No SPROM available!\n"); ++ return -ENODEV; ++ } ++ if (bus->chipco.dev) { /* can be unavailible! */ ++ /* ++ * get SPROM offset: SSB_SPROM_BASE1 except for ++ * chipcommon rev >= 31 or chip ID is 0x4312 and ++ * chipcommon status & 3 == 2 ++ */ ++ if (bus->chipco.dev->id.revision >= 31) ++ bus->sprom_offset = SSB_SPROM_BASE31; ++ else if (bus->chip_id == 0x4312 && ++ (bus->chipco.status & 0x03) == 2) ++ bus->sprom_offset = SSB_SPROM_BASE31; ++ else ++ bus->sprom_offset = SSB_SPROM_BASE1; ++ } else { ++ bus->sprom_offset = SSB_SPROM_BASE1; ++ } ++ ssb_dprintk(KERN_INFO PFX "SPROM offset is 0x%x\n", bus->sprom_offset); ++ + buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL); + if (!buf) +- goto out; ++ return -ENOMEM; + bus->sprom_size = SSB_SPROMSIZE_WORDS_R123; + sprom_do_read(bus, buf); + err = sprom_check_crc(buf, bus->sprom_size); +@@ -580,7 +700,7 @@ static int ssb_pci_sprom_get(struct ssb_ + buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16), + GFP_KERNEL); + if (!buf) +- goto out; ++ return -ENOMEM; + bus->sprom_size = SSB_SPROMSIZE_WORDS_R4; + sprom_do_read(bus, buf); + err = sprom_check_crc(buf, bus->sprom_size); +@@ -602,7 +722,6 @@ static int ssb_pci_sprom_get(struct ssb_ + + out_free: + kfree(buf); +-out: + return err; + } + +--- a/drivers/ssb/pcihost_wrapper.c ++++ b/drivers/ssb/pcihost_wrapper.c +@@ -12,6 +12,7 @@ + */ + + #include <linux/pci.h> ++#include <linux/slab.h> + #include <linux/ssb/ssb.h> + + +@@ -58,6 +59,7 @@ static int ssb_pcihost_probe(struct pci_ + struct ssb_bus *ssb; + int err = -ENOMEM; + const char *name; ++ u32 val; + + ssb = kzalloc(sizeof(*ssb), GFP_KERNEL); + if (!ssb) +@@ -73,6 +75,12 @@ static int ssb_pcihost_probe(struct pci_ + goto err_pci_disable; + pci_set_master(dev); + ++ /* Disable the RETRY_TIMEOUT register (0x41) to keep ++ * PCI Tx retries from interfering with C3 CPU state */ ++ pci_read_config_dword(dev, 0x40, &val); ++ if ((val & 0x0000ff00) != 0) ++ pci_write_config_dword(dev, 0x40, val & 0xffff00ff); ++ + err = ssb_bus_pcibus_register(ssb, dev); + if (err) + goto err_pci_release_regions; +--- a/drivers/ssb/pcmcia.c ++++ b/drivers/ssb/pcmcia.c +@@ -617,136 +617,140 @@ static int ssb_pcmcia_sprom_check_crc(co + } \ + } while (0) + +-int ssb_pcmcia_get_invariants(struct ssb_bus *bus, +- struct ssb_init_invariants *iv) ++static int ssb_pcmcia_get_mac(struct pcmcia_device *p_dev, ++ tuple_t *tuple, ++ void *priv) + { +- tuple_t tuple; +- int res; +- unsigned char buf[32]; ++ struct ssb_sprom *sprom = priv; ++ ++ if (tuple->TupleData[0] != CISTPL_FUNCE_LAN_NODE_ID) ++ return -EINVAL; ++ if (tuple->TupleDataLen != ETH_ALEN + 2) ++ return -EINVAL; ++ if (tuple->TupleData[1] != ETH_ALEN) ++ return -EINVAL; ++ memcpy(sprom->il0mac, &tuple->TupleData[2], ETH_ALEN); ++ return 0; ++}; ++ ++static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev, ++ tuple_t *tuple, ++ void *priv) ++{ ++ struct ssb_init_invariants *iv = priv; + struct ssb_sprom *sprom = &iv->sprom; + struct ssb_boardinfo *bi = &iv->boardinfo; + const char *error_description; + ++ GOTO_ERROR_ON(tuple->TupleDataLen < 1, "VEN tpl < 1"); ++ switch (tuple->TupleData[0]) { ++ case SSB_PCMCIA_CIS_ID: ++ GOTO_ERROR_ON((tuple->TupleDataLen != 5) && ++ (tuple->TupleDataLen != 7), ++ "id tpl size"); ++ bi->vendor = tuple->TupleData[1] | ++ ((u16)tuple->TupleData[2] << 8); ++ break; ++ case SSB_PCMCIA_CIS_BOARDREV: ++ GOTO_ERROR_ON(tuple->TupleDataLen != 2, ++ "boardrev tpl size"); ++ sprom->board_rev = tuple->TupleData[1]; ++ break; ++ case SSB_PCMCIA_CIS_PA: ++ GOTO_ERROR_ON((tuple->TupleDataLen != 9) && ++ (tuple->TupleDataLen != 10), ++ "pa tpl size"); ++ sprom->pa0b0 = tuple->TupleData[1] | ++ ((u16)tuple->TupleData[2] << 8); ++ sprom->pa0b1 = tuple->TupleData[3] | ++ ((u16)tuple->TupleData[4] << 8); ++ sprom->pa0b2 = tuple->TupleData[5] | ++ ((u16)tuple->TupleData[6] << 8); ++ sprom->itssi_a = tuple->TupleData[7]; ++ sprom->itssi_bg = tuple->TupleData[7]; ++ sprom->maxpwr_a = tuple->TupleData[8]; ++ sprom->maxpwr_bg = tuple->TupleData[8]; ++ break; ++ case SSB_PCMCIA_CIS_OEMNAME: ++ /* We ignore this. */ ++ break; ++ case SSB_PCMCIA_CIS_CCODE: ++ GOTO_ERROR_ON(tuple->TupleDataLen != 2, ++ "ccode tpl size"); ++ sprom->country_code = tuple->TupleData[1]; ++ break; ++ case SSB_PCMCIA_CIS_ANTENNA: ++ GOTO_ERROR_ON(tuple->TupleDataLen != 2, ++ "ant tpl size"); ++ sprom->ant_available_a = tuple->TupleData[1]; ++ sprom->ant_available_bg = tuple->TupleData[1]; ++ break; ++ case SSB_PCMCIA_CIS_ANTGAIN: ++ GOTO_ERROR_ON(tuple->TupleDataLen != 2, ++ "antg tpl size"); ++ sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1]; ++ sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1]; ++ sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1]; ++ sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1]; ++ sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1]; ++ sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1]; ++ sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1]; ++ sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1]; ++ break; ++ case SSB_PCMCIA_CIS_BFLAGS: ++ GOTO_ERROR_ON((tuple->TupleDataLen != 3) && ++ (tuple->TupleDataLen != 5), ++ "bfl tpl size"); ++ sprom->boardflags_lo = tuple->TupleData[1] | ++ ((u16)tuple->TupleData[2] << 8); ++ break; ++ case SSB_PCMCIA_CIS_LEDS: ++ GOTO_ERROR_ON(tuple->TupleDataLen != 5, ++ "leds tpl size"); ++ sprom->gpio0 = tuple->TupleData[1]; ++ sprom->gpio1 = tuple->TupleData[2]; ++ sprom->gpio2 = tuple->TupleData[3]; ++ sprom->gpio3 = tuple->TupleData[4]; ++ break; ++ } ++ return -ENOSPC; /* continue with next entry */ ++ ++error: ++ ssb_printk(KERN_ERR PFX ++ "PCMCIA: Failed to fetch device invariants: %s\n", ++ error_description); ++ return -ENODEV; ++} ++ ++ ++int ssb_pcmcia_get_invariants(struct ssb_bus *bus, ++ struct ssb_init_invariants *iv) ++{ ++ struct ssb_sprom *sprom = &iv->sprom; ++ int res; ++ + memset(sprom, 0xFF, sizeof(*sprom)); + sprom->revision = 1; + sprom->boardflags_lo = 0; + sprom->boardflags_hi = 0; + + /* First fetch the MAC address. */ +- memset(&tuple, 0, sizeof(tuple)); +- tuple.DesiredTuple = CISTPL_FUNCE; +- tuple.TupleData = buf; +- tuple.TupleDataMax = sizeof(buf); +- res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple); +- GOTO_ERROR_ON(res != 0, "MAC first tpl"); +- res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple); +- GOTO_ERROR_ON(res != 0, "MAC first tpl data"); +- while (1) { +- GOTO_ERROR_ON(tuple.TupleDataLen < 1, "MAC tpl < 1"); +- if (tuple.TupleData[0] == CISTPL_FUNCE_LAN_NODE_ID) +- break; +- res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple); +- GOTO_ERROR_ON(res != 0, "MAC next tpl"); +- res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple); +- GOTO_ERROR_ON(res != 0, "MAC next tpl data"); ++ res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE, ++ ssb_pcmcia_get_mac, sprom); ++ if (res != 0) { ++ ssb_printk(KERN_ERR PFX ++ "PCMCIA: Failed to fetch MAC address\n"); ++ return -ENODEV; + } +- GOTO_ERROR_ON(tuple.TupleDataLen != ETH_ALEN + 2, "MAC tpl size"); +- memcpy(sprom->il0mac, &tuple.TupleData[2], ETH_ALEN); + + /* Fetch the vendor specific tuples. */ +- memset(&tuple, 0, sizeof(tuple)); +- tuple.DesiredTuple = SSB_PCMCIA_CIS; +- tuple.TupleData = buf; +- tuple.TupleDataMax = sizeof(buf); +- res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple); +- GOTO_ERROR_ON(res != 0, "VEN first tpl"); +- res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple); +- GOTO_ERROR_ON(res != 0, "VEN first tpl data"); +- while (1) { +- GOTO_ERROR_ON(tuple.TupleDataLen < 1, "VEN tpl < 1"); +- switch (tuple.TupleData[0]) { +- case SSB_PCMCIA_CIS_ID: +- GOTO_ERROR_ON((tuple.TupleDataLen != 5) && +- (tuple.TupleDataLen != 7), +- "id tpl size"); +- bi->vendor = tuple.TupleData[1] | +- ((u16)tuple.TupleData[2] << 8); +- break; +- case SSB_PCMCIA_CIS_BOARDREV: +- GOTO_ERROR_ON(tuple.TupleDataLen != 2, +- "boardrev tpl size"); +- sprom->board_rev = tuple.TupleData[1]; +- break; +- case SSB_PCMCIA_CIS_PA: +- GOTO_ERROR_ON((tuple.TupleDataLen != 9) && +- (tuple.TupleDataLen != 10), +- "pa tpl size"); +- sprom->pa0b0 = tuple.TupleData[1] | +- ((u16)tuple.TupleData[2] << 8); +- sprom->pa0b1 = tuple.TupleData[3] | +- ((u16)tuple.TupleData[4] << 8); +- sprom->pa0b2 = tuple.TupleData[5] | +- ((u16)tuple.TupleData[6] << 8); +- sprom->itssi_a = tuple.TupleData[7]; +- sprom->itssi_bg = tuple.TupleData[7]; +- sprom->maxpwr_a = tuple.TupleData[8]; +- sprom->maxpwr_bg = tuple.TupleData[8]; +- break; +- case SSB_PCMCIA_CIS_OEMNAME: +- /* We ignore this. */ +- break; +- case SSB_PCMCIA_CIS_CCODE: +- GOTO_ERROR_ON(tuple.TupleDataLen != 2, +- "ccode tpl size"); +- sprom->country_code = tuple.TupleData[1]; +- break; +- case SSB_PCMCIA_CIS_ANTENNA: +- GOTO_ERROR_ON(tuple.TupleDataLen != 2, +- "ant tpl size"); +- sprom->ant_available_a = tuple.TupleData[1]; +- sprom->ant_available_bg = tuple.TupleData[1]; +- break; +- case SSB_PCMCIA_CIS_ANTGAIN: +- GOTO_ERROR_ON(tuple.TupleDataLen != 2, +- "antg tpl size"); +- sprom->antenna_gain.ghz24.a0 = tuple.TupleData[1]; +- sprom->antenna_gain.ghz24.a1 = tuple.TupleData[1]; +- sprom->antenna_gain.ghz24.a2 = tuple.TupleData[1]; +- sprom->antenna_gain.ghz24.a3 = tuple.TupleData[1]; +- sprom->antenna_gain.ghz5.a0 = tuple.TupleData[1]; +- sprom->antenna_gain.ghz5.a1 = tuple.TupleData[1]; +- sprom->antenna_gain.ghz5.a2 = tuple.TupleData[1]; +- sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1]; +- break; +- case SSB_PCMCIA_CIS_BFLAGS: +- GOTO_ERROR_ON((tuple.TupleDataLen != 3) && +- (tuple.TupleDataLen != 5), +- "bfl tpl size"); +- sprom->boardflags_lo = tuple.TupleData[1] | +- ((u16)tuple.TupleData[2] << 8); +- break; +- case SSB_PCMCIA_CIS_LEDS: +- GOTO_ERROR_ON(tuple.TupleDataLen != 5, +- "leds tpl size"); +- sprom->gpio0 = tuple.TupleData[1]; +- sprom->gpio1 = tuple.TupleData[2]; +- sprom->gpio2 = tuple.TupleData[3]; +- sprom->gpio3 = tuple.TupleData[4]; +- break; +- } +- res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple); +- if (res == -ENOSPC) +- break; +- GOTO_ERROR_ON(res != 0, "VEN next tpl"); +- res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple); +- GOTO_ERROR_ON(res != 0, "VEN next tpl data"); +- } ++ res = pcmcia_loop_tuple(bus->host_pcmcia, SSB_PCMCIA_CIS, ++ ssb_pcmcia_do_get_invariants, iv); ++ if ((res == 0) || (res == -ENOSPC)) ++ return 0; + +- return 0; +-error: + ssb_printk(KERN_ERR PFX +- "PCMCIA: Failed to fetch device invariants: %s\n", +- error_description); ++ "PCMCIA: Failed to fetch device invariants\n"); + return -ENODEV; + } + --- a/drivers/ssb/scan.c +++ b/drivers/ssb/scan.c -@@ -175,6 +175,8 @@ static u32 scan_read32(struct ssb_bus *b +@@ -162,6 +162,8 @@ static u8 chipid_to_nrcores(u16 chipid) + static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx, + u16 offset) + { ++ u32 lo, hi; ++ + switch (bus->bustype) { + case SSB_BUSTYPE_SSB: + offset += current_coreidx * SSB_CORE_SIZE; +@@ -174,7 +176,12 @@ static u32 scan_read32(struct ssb_bus *b + offset -= 0x800; } else ssb_pcmcia_switch_segment(bus, 0); - break; +- break; ++ lo = readw(bus->mmio + offset); ++ hi = readw(bus->mmio + offset + 2); ++ return lo | (hi << 16); + case SSB_BUSTYPE_SDIO: -+ break; ++ offset += current_coreidx * SSB_CORE_SIZE; ++ return ssb_sdio_scan_read32(bus, offset); } return readl(bus->mmio + offset); } -@@ -188,6 +190,8 @@ static int scan_switchcore(struct ssb_bu +@@ -188,6 +195,8 @@ static int scan_switchcore(struct ssb_bu return ssb_pci_switch_coreidx(bus, coreidx); case SSB_BUSTYPE_PCMCIA: return ssb_pcmcia_switch_coreidx(bus, coreidx); + case SSB_BUSTYPE_SDIO: -+ break; ++ return ssb_sdio_scan_switch_coreidx(bus, coreidx); } return 0; } -@@ -206,6 +210,8 @@ void ssb_iounmap(struct ssb_bus *bus) +@@ -206,6 +215,8 @@ void ssb_iounmap(struct ssb_bus *bus) SSB_BUG_ON(1); /* Can't reach this code. */ #endif break; @@ -264,18 +1423,815 @@ } bus->mmio = NULL; bus->mapped_device = NULL; -@@ -230,6 +236,8 @@ static void __iomem *ssb_ioremap(struct +@@ -230,6 +241,10 @@ static void __iomem *ssb_ioremap(struct SSB_BUG_ON(1); /* Can't reach this code. */ #endif break; + case SSB_BUSTYPE_SDIO: ++ /* Nothing to ioremap in the SDIO case, just fake it */ ++ mmio = (void __iomem *)baseaddr; + break; } return mmio; +@@ -339,7 +354,7 @@ int ssb_bus_scan(struct ssb_bus *bus, + dev->bus = bus; + dev->ops = bus->ops; + +- ssb_dprintk(KERN_INFO PFX ++ printk(KERN_DEBUG PFX + "Core %d found: %s " + "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n", + i, ssb_core_name(dev->id.coreid), +@@ -407,6 +422,16 @@ int ssb_bus_scan(struct ssb_bus *bus, + bus->pcicore.dev = dev; + #endif /* CONFIG_SSB_DRIVER_PCICORE */ + break; ++ case SSB_DEV_ETHERNET: ++ if (bus->bustype == SSB_BUSTYPE_PCI) { ++ if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM && ++ (bus->host_pci->device & 0xFF00) == 0x4300) { ++ /* This is a dangling ethernet core on a ++ * wireless device. Ignore it. */ ++ continue; ++ } ++ } ++ break; + default: + break; + } +--- /dev/null ++++ b/drivers/ssb/sdio.c +@@ -0,0 +1,610 @@ ++/* ++ * Sonics Silicon Backplane ++ * SDIO-Hostbus related functions ++ * ++ * Copyright 2009 Albert Herranz <albert_herranz@yahoo.es> ++ * ++ * Based on drivers/ssb/pcmcia.c ++ * Copyright 2006 Johannes Berg <johannes@sipsolutions.net> ++ * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de> ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ * ++ */ ++ ++#include <linux/ssb/ssb.h> ++#include <linux/delay.h> ++#include <linux/io.h> ++#include <linux/etherdevice.h> ++#include <linux/mmc/sdio_func.h> ++ ++#include "ssb_private.h" ++ ++/* Define the following to 1 to enable a printk on each coreswitch. */ ++#define SSB_VERBOSE_SDIOCORESWITCH_DEBUG 0 ++ ++ ++/* Hardware invariants CIS tuples */ ++#define SSB_SDIO_CIS 0x80 ++#define SSB_SDIO_CIS_SROMREV 0x00 ++#define SSB_SDIO_CIS_ID 0x01 ++#define SSB_SDIO_CIS_BOARDREV 0x02 ++#define SSB_SDIO_CIS_PA 0x03 ++#define SSB_SDIO_CIS_PA_PA0B0_LO 0 ++#define SSB_SDIO_CIS_PA_PA0B0_HI 1 ++#define SSB_SDIO_CIS_PA_PA0B1_LO 2 ++#define SSB_SDIO_CIS_PA_PA0B1_HI 3 ++#define SSB_SDIO_CIS_PA_PA0B2_LO 4 ++#define SSB_SDIO_CIS_PA_PA0B2_HI 5 ++#define SSB_SDIO_CIS_PA_ITSSI 6 ++#define SSB_SDIO_CIS_PA_MAXPOW 7 ++#define SSB_SDIO_CIS_OEMNAME 0x04 ++#define SSB_SDIO_CIS_CCODE 0x05 ++#define SSB_SDIO_CIS_ANTENNA 0x06 ++#define SSB_SDIO_CIS_ANTGAIN 0x07 ++#define SSB_SDIO_CIS_BFLAGS 0x08 ++#define SSB_SDIO_CIS_LEDS 0x09 ++ ++#define CISTPL_FUNCE_LAN_NODE_ID 0x04 /* same as in PCMCIA */ ++ ++ ++/* ++ * Function 1 miscellaneous registers. ++ * ++ * Definitions match src/include/sbsdio.h from the ++ * Android Open Source Project ++ * http://android.git.kernel.org/?p=platform/system/wlan/broadcom.git ++ * ++ */ ++#define SBSDIO_FUNC1_SBADDRLOW 0x1000a /* SB Address window Low (b15) */ ++#define SBSDIO_FUNC1_SBADDRMID 0x1000b /* SB Address window Mid (b23-b16) */ ++#define SBSDIO_FUNC1_SBADDRHIGH 0x1000c /* SB Address window High (b24-b31) */ ++ ++/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */ ++#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid address bits in SBADDRLOW */ ++#define SBSDIO_SBADDRMID_MASK 0xff /* Valid address bits in SBADDRMID */ ++#define SBSDIO_SBADDRHIGH_MASK 0xff /* Valid address bits in SBADDRHIGH */ ++ ++#define SBSDIO_SB_OFT_ADDR_MASK 0x7FFF /* sb offset addr is <= 15 bits, 32k */ ++ ++/* REVISIT: this flag doesn't seem to matter */ ++#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x8000 /* forces 32-bit SB access */ ++ ++ ++/* ++ * Address map within the SDIO function address space (128K). ++ * ++ * Start End Description ++ * ------- ------- ------------------------------------------ ++ * 0x00000 0x0ffff selected backplane address window (64K) ++ * 0x10000 0x1ffff backplane control registers (max 64K) ++ * ++ * The current address window is configured by writing to registers ++ * SBADDRLOW, SBADDRMID and SBADDRHIGH. ++ * ++ * In order to access the contents of a 32-bit Silicon Backplane address ++ * the backplane address window must be first loaded with the highest ++ * 16 bits of the target address. Then, an access must be done to the ++ * SDIO function address space using the lower 15 bits of the address. ++ * Bit 15 of the address must be set when doing 32 bit accesses. ++ * ++ * 10987654321098765432109876543210 ++ * WWWWWWWWWWWWWWWWW SB Address Window ++ * OOOOOOOOOOOOOOOO Offset within SB Address Window ++ * a 32-bit access flag ++ */ ++ ++ ++/* ++ * SSB I/O via SDIO. ++ * ++ * NOTE: SDIO address @addr is 17 bits long (SDIO address space is 128K). ++ */ ++ ++static inline struct device *ssb_sdio_dev(struct ssb_bus *bus) ++{ ++ return &bus->host_sdio->dev; ++} ++ ++/* host claimed */ ++static int ssb_sdio_writeb(struct ssb_bus *bus, unsigned int addr, u8 val) ++{ ++ int error = 0; ++ ++ sdio_writeb(bus->host_sdio, val, addr, &error); ++ if (unlikely(error)) { ++ dev_dbg(ssb_sdio_dev(bus), "%08X <- %02x, error %d\n", ++ addr, val, error); ++ } ++ ++ return error; ++} ++ ++#if 0 ++static u8 ssb_sdio_readb(struct ssb_bus *bus, unsigned int addr) ++{ ++ u8 val; ++ int error = 0; ++ ++ val = sdio_readb(bus->host_sdio, addr, &error); ++ if (unlikely(error)) { ++ dev_dbg(ssb_sdio_dev(bus), "%08X -> %02x, error %d\n", ++ addr, val, error); ++ } ++ ++ return val; ++} ++#endif ++ ++/* host claimed */ ++static int ssb_sdio_set_sbaddr_window(struct ssb_bus *bus, u32 address) ++{ ++ int error; ++ ++ error = ssb_sdio_writeb(bus, SBSDIO_FUNC1_SBADDRLOW, ++ (address >> 8) & SBSDIO_SBADDRLOW_MASK); ++ if (error) ++ goto out; ++ error = ssb_sdio_writeb(bus, SBSDIO_FUNC1_SBADDRMID, ++ (address >> 16) & SBSDIO_SBADDRMID_MASK); ++ if (error) ++ goto out; ++ error = ssb_sdio_writeb(bus, SBSDIO_FUNC1_SBADDRHIGH, ++ (address >> 24) & SBSDIO_SBADDRHIGH_MASK); ++ if (error) ++ goto out; ++ bus->sdio_sbaddr = address; ++out: ++ if (error) { ++ dev_dbg(ssb_sdio_dev(bus), "failed to set address window" ++ " to 0x%08x, error %d\n", address, error); ++ } ++ ++ return error; ++} ++ ++/* for enumeration use only */ ++u32 ssb_sdio_scan_read32(struct ssb_bus *bus, u16 offset) ++{ ++ u32 val; ++ int error; ++ ++ sdio_claim_host(bus->host_sdio); ++ val = sdio_readl(bus->host_sdio, offset, &error); ++ sdio_release_host(bus->host_sdio); ++ if (unlikely(error)) { ++ dev_dbg(ssb_sdio_dev(bus), "%04X:%04X > %08x, error %d\n", ++ bus->sdio_sbaddr >> 16, offset, val, error); ++ } ++ ++ return val; ++} ++ ++/* for enumeration use only */ ++int ssb_sdio_scan_switch_coreidx(struct ssb_bus *bus, u8 coreidx) ++{ ++ u32 sbaddr; ++ int error; ++ ++ sbaddr = (coreidx * SSB_CORE_SIZE) + SSB_ENUM_BASE; ++ sdio_claim_host(bus->host_sdio); ++ error = ssb_sdio_set_sbaddr_window(bus, sbaddr); ++ sdio_release_host(bus->host_sdio); ++ if (error) { ++ dev_err(ssb_sdio_dev(bus), "failed to switch to core %u," ++ " error %d\n", coreidx, error); ++ goto out; ++ } ++out: ++ return error; ++} ++ ++/* host must be already claimed */ ++int ssb_sdio_switch_core(struct ssb_bus *bus, struct ssb_device *dev) ++{ ++ u8 coreidx = dev->core_index; ++ u32 sbaddr; ++ int error = 0; ++ ++ sbaddr = (coreidx * SSB_CORE_SIZE) + SSB_ENUM_BASE; ++ if (unlikely(bus->sdio_sbaddr != sbaddr)) { ++#if SSB_VERBOSE_SDIOCORESWITCH_DEBUG ++ dev_info(ssb_sdio_dev(bus), ++ "switching to %s core, index %d\n", ++ ssb_core_name(dev->id.coreid), coreidx); ++#endif ++ error = ssb_sdio_set_sbaddr_window(bus, sbaddr); ++ if (error) { ++ dev_dbg(ssb_sdio_dev(bus), "failed to switch to" ++ " core %u, error %d\n", coreidx, error); ++ goto out; ++ } ++ bus->mapped_device = dev; ++ } ++ ++out: ++ return error; ++} ++ ++static u8 ssb_sdio_read8(struct ssb_device *dev, u16 offset) ++{ ++ struct ssb_bus *bus = dev->bus; ++ u8 val = 0xff; ++ int error = 0; ++ ++ sdio_claim_host(bus->host_sdio); ++ if (unlikely(ssb_sdio_switch_core(bus, dev))) ++ goto out; ++ offset |= bus->sdio_sbaddr & 0xffff; ++ offset &= SBSDIO_SB_OFT_ADDR_MASK; ++ val = sdio_readb(bus->host_sdio, offset, &error); ++ if (error) { ++ dev_dbg(ssb_sdio_dev(bus), "%04X:%04X > %02x, error %d\n", ++ bus->sdio_sbaddr >> 16, offset, val, error); ++ } ++out: ++ sdio_release_host(bus->host_sdio); ++ ++ return val; ++} ++ ++static u16 ssb_sdio_read16(struct ssb_device *dev, u16 offset) ++{ ++ struct ssb_bus *bus = dev->bus; ++ u16 val = 0xffff; ++ int error = 0; ++ ++ sdio_claim_host(bus->host_sdio); ++ if (unlikely(ssb_sdio_switch_core(bus, dev))) ++ goto out; ++ offset |= bus->sdio_sbaddr & 0xffff; ++ offset &= SBSDIO_SB_OFT_ADDR_MASK; ++ val = sdio_readw(bus->host_sdio, offset, &error); ++ if (error) { ++ dev_dbg(ssb_sdio_dev(bus), "%04X:%04X > %04x, error %d\n", ++ bus->sdio_sbaddr >> 16, offset, val, error); ++ } ++out: ++ sdio_release_host(bus->host_sdio); ++ ++ return val; ++} ++ ++static u32 ssb_sdio_read32(struct ssb_device *dev, u16 offset) ++{ ++ struct ssb_bus *bus = dev->bus; ++ u32 val = 0xffffffff; ++ int error = 0; ++ ++ sdio_claim_host(bus->host_sdio); ++ if (unlikely(ssb_sdio_switch_core(bus, dev))) ++ goto out; ++ offset |= bus->sdio_sbaddr & 0xffff; ++ offset &= SBSDIO_SB_OFT_ADDR_MASK; ++ offset |= SBSDIO_SB_ACCESS_2_4B_FLAG; /* 32 bit data access */ ++ val = sdio_readl(bus->host_sdio, offset, &error); ++ if (error) { ++ dev_dbg(ssb_sdio_dev(bus), "%04X:%04X > %08x, error %d\n", ++ bus->sdio_sbaddr >> 16, offset, val, error); ++ } ++out: ++ sdio_release_host(bus->host_sdio); ++ ++ return val; ++} ++ ++#ifdef CONFIG_SSB_BLOCKIO ++static void ssb_sdio_block_read(struct ssb_device *dev, void *buffer, ++ size_t count, u16 offset, u8 reg_width) ++{ ++ size_t saved_count = count; ++ struct ssb_bus *bus = dev->bus; ++ int error = 0; ++ ++ sdio_claim_host(bus->host_sdio); ++ if (unlikely(ssb_sdio_switch_core(bus, dev))) { ++ error = -EIO; ++ memset(buffer, 0xff, count); ++ goto err_out; ++ } ++ offset |= bus->sdio_sbaddr & 0xffff; ++ offset &= SBSDIO_SB_OFT_ADDR_MASK; ++ ++ switch (reg_width) { ++ case sizeof(u8): { ++ error = sdio_readsb(bus->host_sdio, buffer, offset, count); ++ break; ++ } ++ case sizeof(u16): { ++ SSB_WARN_ON(count & 1); ++ error = sdio_readsb(bus->host_sdio, buffer, offset, count); ++ break; ++ } ++ case sizeof(u32): { ++ SSB_WARN_ON(count & 3); ++ offset |= SBSDIO_SB_ACCESS_2_4B_FLAG; /* 32 bit data access */ ++ error = sdio_readsb(bus->host_sdio, buffer, offset, count); ++ break; ++ } ++ default: ++ SSB_WARN_ON(1); ++ } ++ if (!error) ++ goto out; ++ ++err_out: ++ dev_dbg(ssb_sdio_dev(bus), "%04X:%04X (width=%u, len=%zu), error %d\n", ++ bus->sdio_sbaddr >> 16, offset, reg_width, saved_count, error); ++out: ++ sdio_release_host(bus->host_sdio); ++} ++#endif /* CONFIG_SSB_BLOCKIO */ ++ ++static void ssb_sdio_write8(struct ssb_device *dev, u16 offset, u8 val) ++{ ++ struct ssb_bus *bus = dev->bus; ++ int error = 0; ++ ++ sdio_claim_host(bus->host_sdio); ++ if (unlikely(ssb_sdio_switch_core(bus, dev))) ++ goto out; ++ offset |= bus->sdio_sbaddr & 0xffff; ++ offset &= SBSDIO_SB_OFT_ADDR_MASK; ++ sdio_writeb(bus->host_sdio, val, offset, &error); ++ if (error) { ++ dev_dbg(ssb_sdio_dev(bus), "%04X:%04X < %02x, error %d\n", ++ bus->sdio_sbaddr >> 16, offset, val, error); ++ } ++out: ++ sdio_release_host(bus->host_sdio); ++} ++ ++static void ssb_sdio_write16(struct ssb_device *dev, u16 offset, u16 val) ++{ ++ struct ssb_bus *bus = dev->bus; ++ int error = 0; ++ ++ sdio_claim_host(bus->host_sdio); ++ if (unlikely(ssb_sdio_switch_core(bus, dev))) ++ goto out; ++ offset |= bus->sdio_sbaddr & 0xffff; ++ offset &= SBSDIO_SB_OFT_ADDR_MASK; ++ sdio_writew(bus->host_sdio, val, offset, &error); ++ if (error) { ++ dev_dbg(ssb_sdio_dev(bus), "%04X:%04X < %04x, error %d\n", ++ bus->sdio_sbaddr >> 16, offset, val, error); ++ } ++out: ++ sdio_release_host(bus->host_sdio); ++} ++ ++static void ssb_sdio_write32(struct ssb_device *dev, u16 offset, u32 val) ++{ ++ struct ssb_bus *bus = dev->bus; ++ int error = 0; ++ ++ sdio_claim_host(bus->host_sdio); ++ if (unlikely(ssb_sdio_switch_core(bus, dev))) ++ goto out; ++ offset |= bus->sdio_sbaddr & 0xffff; ++ offset &= SBSDIO_SB_OFT_ADDR_MASK; ++ offset |= SBSDIO_SB_ACCESS_2_4B_FLAG; /* 32 bit data access */ ++ sdio_writel(bus->host_sdio, val, offset, &error); ++ if (error) { ++ dev_dbg(ssb_sdio_dev(bus), "%04X:%04X < %08x, error %d\n", ++ bus->sdio_sbaddr >> 16, offset, val, error); ++ } ++ if (bus->quirks & SSB_QUIRK_SDIO_READ_AFTER_WRITE32) ++ sdio_readl(bus->host_sdio, 0, &error); ++out: ++ sdio_release_host(bus->host_sdio); ++} ++ ++#ifdef CONFIG_SSB_BLOCKIO ++static void ssb_sdio_block_write(struct ssb_device *dev, const void *buffer, ++ size_t count, u16 offset, u8 reg_width) ++{ ++ size_t saved_count = count; ++ struct ssb_bus *bus = dev->bus; ++ int error = 0; ++ ++ sdio_claim_host(bus->host_sdio); ++ if (unlikely(ssb_sdio_switch_core(bus, dev))) { ++ error = -EIO; ++ memset((void *)buffer, 0xff, count); ++ goto err_out; ++ } ++ offset |= bus->sdio_sbaddr & 0xffff; ++ offset &= SBSDIO_SB_OFT_ADDR_MASK; ++ ++ switch (reg_width) { ++ case sizeof(u8): ++ error = sdio_writesb(bus->host_sdio, offset, ++ (void *)buffer, count); ++ break; ++ case sizeof(u16): ++ SSB_WARN_ON(count & 1); ++ error = sdio_writesb(bus->host_sdio, offset, ++ (void *)buffer, count); ++ break; ++ case sizeof(u32): ++ SSB_WARN_ON(count & 3); ++ offset |= SBSDIO_SB_ACCESS_2_4B_FLAG; /* 32 bit data access */ ++ error = sdio_writesb(bus->host_sdio, offset, ++ (void *)buffer, count); ++ break; ++ default: ++ SSB_WARN_ON(1); ++ } ++ if (!error) ++ goto out; ++ ++err_out: ++ dev_dbg(ssb_sdio_dev(bus), "%04X:%04X (width=%u, len=%zu), error %d\n", ++ bus->sdio_sbaddr >> 16, offset, reg_width, saved_count, error); ++out: ++ sdio_release_host(bus->host_sdio); ++} ++ ++#endif /* CONFIG_SSB_BLOCKIO */ ++ ++/* Not "static", as it's used in main.c */ ++const struct ssb_bus_ops ssb_sdio_ops = { ++ .read8 = ssb_sdio_read8, ++ .read16 = ssb_sdio_read16, ++ .read32 = ssb_sdio_read32, ++ .write8 = ssb_sdio_write8, ++ .write16 = ssb_sdio_write16, ++ .write32 = ssb_sdio_write32, ++#ifdef CONFIG_SSB_BLOCKIO ++ .block_read = ssb_sdio_block_read, ++ .block_write = ssb_sdio_block_write, ++#endif ++}; ++ ++#define GOTO_ERROR_ON(condition, description) do { \ ++ if (unlikely(condition)) { \ ++ error_description = description; \ ++ goto error; \ ++ } \ ++ } while (0) ++ ++int ssb_sdio_get_invariants(struct ssb_bus *bus, ++ struct ssb_init_invariants *iv) ++{ ++ struct ssb_sprom *sprom = &iv->sprom; ++ struct ssb_boardinfo *bi = &iv->boardinfo; ++ const char *error_description = "none"; ++ struct sdio_func_tuple *tuple; ++ void *mac; ++ ++ memset(sprom, 0xFF, sizeof(*sprom)); ++ sprom->boardflags_lo = 0; ++ sprom->boardflags_hi = 0; ++ ++ tuple = bus->host_sdio->tuples; ++ while (tuple) { ++ switch (tuple->code) { ++ case 0x22: /* extended function */ ++ switch (tuple->data[0]) { ++ case CISTPL_FUNCE_LAN_NODE_ID: ++ GOTO_ERROR_ON((tuple->size != 7) && ++ (tuple->data[1] != 6), ++ "mac tpl size"); ++ /* fetch the MAC address. */ ++ mac = tuple->data + 2; ++ memcpy(sprom->il0mac, mac, ETH_ALEN); ++ memcpy(sprom->et1mac, mac, ETH_ALEN); ++ break; ++ default: ++ break; ++ } ++ break; ++ case 0x80: /* vendor specific tuple */ ++ switch (tuple->data[0]) { ++ case SSB_SDIO_CIS_SROMREV: ++ GOTO_ERROR_ON(tuple->size != 2, ++ "sromrev tpl size"); ++ sprom->revision = tuple->data[1]; ++ break; ++ case SSB_SDIO_CIS_ID: ++ GOTO_ERROR_ON((tuple->size != 5) && ++ (tuple->size != 7), ++ "id tpl size"); ++ bi->vendor = tuple->data[1] | ++ (tuple->data[2]<<8); ++ break; ++ case SSB_SDIO_CIS_BOARDREV: ++ GOTO_ERROR_ON(tuple->size != 2, ++ "boardrev tpl size"); ++ sprom->board_rev = tuple->data[1]; ++ break; ++ case SSB_SDIO_CIS_PA: ++ GOTO_ERROR_ON((tuple->size != 9) && ++ (tuple->size != 10), ++ "pa tpl size"); ++ sprom->pa0b0 = tuple->data[1] | ++ ((u16)tuple->data[2] << 8); ++ sprom->pa0b1 = tuple->data[3] | ++ ((u16)tuple->data[4] << 8); ++ sprom->pa0b2 = tuple->data[5] | ++ ((u16)tuple->data[6] << 8); ++ sprom->itssi_a = tuple->data[7]; ++ sprom->itssi_bg = tuple->data[7]; ++ sprom->maxpwr_a = tuple->data[8]; ++ sprom->maxpwr_bg = tuple->data[8]; ++ break; ++ case SSB_SDIO_CIS_OEMNAME: ++ /* Not present */ ++ break; ++ case SSB_SDIO_CIS_CCODE: ++ GOTO_ERROR_ON(tuple->size != 2, ++ "ccode tpl size"); ++ sprom->country_code = tuple->data[1]; ++ break; ++ case SSB_SDIO_CIS_ANTENNA: ++ GOTO_ERROR_ON(tuple->size != 2, ++ "ant tpl size"); ++ sprom->ant_available_a = tuple->data[1]; ++ sprom->ant_available_bg = tuple->data[1]; ++ break; ++ case SSB_SDIO_CIS_ANTGAIN: ++ GOTO_ERROR_ON(tuple->size != 2, ++ "antg tpl size"); ++ sprom->antenna_gain.ghz24.a0 = tuple->data[1]; ++ sprom->antenna_gain.ghz24.a1 = tuple->data[1]; ++ sprom->antenna_gain.ghz24.a2 = tuple->data[1]; ++ sprom->antenna_gain.ghz24.a3 = tuple->data[1]; ++ sprom->antenna_gain.ghz5.a0 = tuple->data[1]; ++ sprom->antenna_gain.ghz5.a1 = tuple->data[1]; ++ sprom->antenna_gain.ghz5.a2 = tuple->data[1]; ++ sprom->antenna_gain.ghz5.a3 = tuple->data[1]; ++ break; ++ case SSB_SDIO_CIS_BFLAGS: ++ GOTO_ERROR_ON((tuple->size != 3) && ++ (tuple->size != 5), ++ "bfl tpl size"); ++ sprom->boardflags_lo = tuple->data[1] | ++ ((u16)tuple->data[2] << 8); ++ break; ++ case SSB_SDIO_CIS_LEDS: ++ GOTO_ERROR_ON(tuple->size != 5, ++ "leds tpl size"); ++ sprom->gpio0 = tuple->data[1]; ++ sprom->gpio1 = tuple->data[2]; ++ sprom->gpio2 = tuple->data[3]; ++ sprom->gpio3 = tuple->data[4]; ++ break; ++ default: ++ break; ++ } ++ break; ++ default: ++ break; ++ } ++ tuple = tuple->next; ++ } ++ ++ return 0; ++error: ++ dev_err(ssb_sdio_dev(bus), "failed to fetch device invariants: %s\n", ++ error_description); ++ return -ENODEV; ++} ++ ++void ssb_sdio_exit(struct ssb_bus *bus) ++{ ++ if (bus->bustype != SSB_BUSTYPE_SDIO) ++ return; ++ /* Nothing to do here. */ ++} ++ ++int ssb_sdio_init(struct ssb_bus *bus) ++{ ++ if (bus->bustype != SSB_BUSTYPE_SDIO) ++ return 0; ++ ++ bus->sdio_sbaddr = ~0; ++ ++ return 0; ++} +--- a/drivers/ssb/sprom.c ++++ b/drivers/ssb/sprom.c +@@ -14,6 +14,7 @@ + #include "ssb_private.h" + + #include <linux/ctype.h> ++#include <linux/slab.h> + + + static const struct ssb_sprom *fallback_sprom; +@@ -102,6 +103,7 @@ ssize_t ssb_attr_sprom_store(struct ssb_ + u16 *sprom; + int res = 0, err = -ENOMEM; + size_t sprom_size_words = bus->sprom_size; ++ struct ssb_freeze_context freeze; + + sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL); + if (!sprom) +@@ -123,18 +125,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_ + err = -ERESTARTSYS; + if (mutex_lock_interruptible(&bus->sprom_mutex)) + goto out_kfree; +- err = ssb_devices_freeze(bus); +- if (err == -EOPNOTSUPP) { +- ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. " +- "No suspend support. Is CONFIG_PM enabled?\n"); +- goto out_unlock; +- } ++ err = ssb_devices_freeze(bus, &freeze); + if (err) { + ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n"); + goto out_unlock; + } + res = sprom_write(bus, sprom); +- err = ssb_devices_thaw(bus); ++ err = ssb_devices_thaw(&freeze); + if (err) + ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n"); + out_unlock: +@@ -179,3 +176,18 @@ const struct ssb_sprom *ssb_get_fallback + { + return fallback_sprom; + } ++ ++/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */ ++bool ssb_is_sprom_available(struct ssb_bus *bus) ++{ ++ /* status register only exists on chipcomon rev >= 11 and we need check ++ for >= 31 only */ ++ /* this routine differs from specs as we do not access SPROM directly ++ on PCMCIA */ ++ if (bus->bustype == SSB_BUSTYPE_PCI && ++ bus->chipco.dev && /* can be unavailible! */ ++ bus->chipco.dev->id.revision >= 31) ++ return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM; ++ ++ return true; ++} +--- a/drivers/ssb/ssb_private.h ++++ b/drivers/ssb/ssb_private.h +@@ -114,6 +114,46 @@ static inline int ssb_pcmcia_init(struct + } + #endif /* CONFIG_SSB_PCMCIAHOST */ + ++/* sdio.c */ ++#ifdef CONFIG_SSB_SDIOHOST ++extern int ssb_sdio_get_invariants(struct ssb_bus *bus, ++ struct ssb_init_invariants *iv); ++ ++extern u32 ssb_sdio_scan_read32(struct ssb_bus *bus, u16 offset); ++extern int ssb_sdio_switch_core(struct ssb_bus *bus, struct ssb_device *dev); ++extern int ssb_sdio_scan_switch_coreidx(struct ssb_bus *bus, u8 coreidx); ++extern int ssb_sdio_hardware_setup(struct ssb_bus *bus); ++extern void ssb_sdio_exit(struct ssb_bus *bus); ++extern int ssb_sdio_init(struct ssb_bus *bus); ++ ++extern const struct ssb_bus_ops ssb_sdio_ops; ++#else /* CONFIG_SSB_SDIOHOST */ ++static inline u32 ssb_sdio_scan_read32(struct ssb_bus *bus, u16 offset) ++{ ++ return 0; ++} ++static inline int ssb_sdio_switch_core(struct ssb_bus *bus, ++ struct ssb_device *dev) ++{ ++ return 0; ++} ++static inline int ssb_sdio_scan_switch_coreidx(struct ssb_bus *bus, u8 coreidx) ++{ ++ return 0; ++} ++static inline int ssb_sdio_hardware_setup(struct ssb_bus *bus) ++{ ++ return 0; ++} ++static inline void ssb_sdio_exit(struct ssb_bus *bus) ++{ ++} ++static inline int ssb_sdio_init(struct ssb_bus *bus) ++{ ++ return 0; ++} ++#endif /* CONFIG_SSB_SDIOHOST */ ++ + + /* scan.c */ + extern const char *ssb_core_name(u16 coreid); +@@ -136,19 +176,27 @@ extern const struct ssb_sprom *ssb_get_f + + /* core.c */ + extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m); +-extern int ssb_devices_freeze(struct ssb_bus *bus); +-extern int ssb_devices_thaw(struct ssb_bus *bus); + extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev); + int ssb_for_each_bus_call(unsigned long data, + int (*func)(struct ssb_bus *bus, unsigned long data)); + extern struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev); + ++struct ssb_freeze_context { ++ /* Pointer to the bus */ ++ struct ssb_bus *bus; ++ /* Boolean list to indicate whether a device is frozen on this bus. */ ++ bool device_frozen[SSB_MAX_NR_CORES]; ++}; ++extern int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx); ++extern int ssb_devices_thaw(struct ssb_freeze_context *ctx); ++ ++ + + /* b43_pci_bridge.c */ + #ifdef CONFIG_SSB_B43_PCI_BRIDGE + extern int __init b43_pci_ssb_bridge_init(void); + extern void __exit b43_pci_ssb_bridge_exit(void); +-#else /* CONFIG_SSB_B43_PCI_BRIDGR */ ++#else /* CONFIG_SSB_B43_PCI_BRIDGE */ + static inline int b43_pci_ssb_bridge_init(void) + { + return 0; +@@ -156,6 +204,6 @@ static inline int b43_pci_ssb_bridge_ini + static inline void b43_pci_ssb_bridge_exit(void) + { + } +-#endif /* CONFIG_SSB_PCIHOST */ ++#endif /* CONFIG_SSB_B43_PCI_BRIDGE */ + + #endif /* LINUX_SSB_PRIVATE_H_ */ +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -2017,6 +2017,7 @@ + #define PCI_DEVICE_ID_AFAVLAB_P030 0x2182 + #define PCI_SUBDEVICE_ID_AFAVLAB_P061 0x2150 + ++#define PCI_VENDOR_ID_BCM_GVC 0x14a4 + #define PCI_VENDOR_ID_BROADCOM 0x14e4 + #define PCI_DEVICE_ID_TIGON3_5752 0x1600 + #define PCI_DEVICE_ID_TIGON3_5752M 0x1601 --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h -@@ -27,24 +27,54 @@ struct ssb_sprom { +@@ -27,24 +27,58 @@ struct ssb_sprom { u8 et1mdcport; /* MDIO for enet1 */ u8 board_rev; /* Board revision number from SPROM. */ u8 country_code; /* Country Code */ @@ -313,6 +2269,10 @@ + u8 tri5gl; /* 5.2GHz TX isolation */ + u8 tri5g; /* 5.3GHz TX isolation */ + u8 tri5gh; /* 5.8GHz TX isolation */ ++ u8 txpid2g[4]; /* 2GHz TX power index */ ++ u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */ ++ u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */ ++ u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */ + u8 rxpo2g; /* 2GHz RX power offset */ + u8 rxpo5g; /* 5GHz RX power offset */ + u8 rssisav2g; /* 2GHz RSSI params */ @@ -336,7 +2296,7 @@ /* Antenna gain values for up to 4 antennas * on each band. Values in dBm/4 (Q5.2). Negative gain means the -@@ -58,7 +88,7 @@ struct ssb_sprom { +@@ -58,7 +92,7 @@ struct ssb_sprom { } ghz5; /* 5GHz band */ } antenna_gain; @@ -345,7 +2305,16 @@ }; /* Information about the PCB the circuitry is soldered on. */ -@@ -208,6 +238,7 @@ enum ssb_bustype { +@@ -137,7 +171,7 @@ struct ssb_device { + * is an optimization. */ + const struct ssb_bus_ops *ops; + +- struct device *dev; ++ struct device *dev, *dma_dev; + + struct ssb_bus *bus; + struct ssb_device_id id; +@@ -208,6 +242,7 @@ enum ssb_bustype { SSB_BUSTYPE_SSB, /* This SSB bus is the system bus */ SSB_BUSTYPE_PCI, /* SSB is connected to PCI bus */ SSB_BUSTYPE_PCMCIA, /* SSB is connected to PCMCIA bus */ @@ -353,9 +2322,13 @@ }; /* board_vendor */ -@@ -240,8 +271,12 @@ struct ssb_bus { +@@ -238,20 +273,33 @@ struct ssb_bus { + + const struct ssb_bus_ops *ops; - /* The core in the basic address register window. (PCI bus only) */ +- /* The core in the basic address register window. (PCI bus only) */ ++ /* The core currently mapped into the MMIO window. ++ * Not valid on all host-buses. So don't use outside of SSB. */ struct ssb_device *mapped_device; - /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */ - u8 mapped_pcmcia_seg; @@ -368,19 +2341,38 @@ /* Lock for core and segment switching. * On PCMCIA-host busses this is used to protect the whole MMIO access. */ spinlock_t bar_lock; -@@ -252,6 +287,11 @@ struct ssb_bus { - struct pci_dev *host_pci; - /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */ - struct pcmcia_device *host_pcmcia; -+ /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */ -+ struct sdio_func *host_sdio; + +- /* The bus this backplane is running on. */ ++ /* The host-bus this backplane is running on. */ + enum ssb_bustype bustype; +- /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */ +- struct pci_dev *host_pci; +- /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */ +- struct pcmcia_device *host_pcmcia; ++ /* Pointers to the host-bus. Check bustype before using any of these pointers. */ ++ union { ++ /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */ ++ struct pci_dev *host_pci; ++ /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */ ++ struct pcmcia_device *host_pcmcia; ++ /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */ ++ struct sdio_func *host_sdio; ++ }; + + /* See enum ssb_quirks */ + unsigned int quirks; #ifdef CONFIG_SSB_SPROM /* Mutex to protect the SPROM writing. */ -@@ -306,6 +346,11 @@ struct ssb_bus { +@@ -261,6 +309,7 @@ struct ssb_bus { + /* ID information about the Chip. */ + u16 chip_id; + u16 chip_rev; ++ u16 sprom_offset; + u16 sprom_size; /* number of words in sprom */ + u8 chip_package; + +@@ -306,6 +355,11 @@ struct ssb_bus { #endif /* DEBUG */ }; @@ -392,9 +2384,71 @@ /* The initialization-invariants. */ struct ssb_init_invariants { /* Versioning information about the PCB. */ +@@ -336,9 +390,18 @@ extern int ssb_bus_pcmciabus_register(st + struct pcmcia_device *pcmcia_dev, + unsigned long baseaddr); + #endif /* CONFIG_SSB_PCMCIAHOST */ ++#ifdef CONFIG_SSB_SDIOHOST ++extern int ssb_bus_sdiobus_register(struct ssb_bus *bus, ++ struct sdio_func *sdio_func, ++ unsigned int quirks); ++#endif /* CONFIG_SSB_SDIOHOST */ ++ + + extern void ssb_bus_unregister(struct ssb_bus *bus); + ++/* Does the device have an SPROM? */ ++extern bool ssb_is_sprom_available(struct ssb_bus *bus); ++ + /* Set a fallback SPROM. + * See kdoc at the function definition for complete documentation. */ + extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom); --- a/include/linux/ssb/ssb_driver_chipcommon.h +++ b/include/linux/ssb/ssb_driver_chipcommon.h -@@ -629,5 +629,15 @@ extern int ssb_chipco_serial_init(struct +@@ -53,6 +53,7 @@ + #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */ + #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */ + #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */ ++#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */ + #define SSB_CHIPCO_CORECTL 0x0008 + #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */ + #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ +@@ -385,6 +386,7 @@ + + + /** Chip specific Chip-Status register contents. */ ++#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */ + #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003 + #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */ + #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */ +@@ -398,6 +400,18 @@ + #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4 + #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */ + ++/** Macros to determine SPROM presence based on Chip-Status register. */ ++#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \ ++ ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \ ++ SSB_CHIPCO_CHST_4325_OTP_SEL) ++#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \ ++ (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS) ++#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \ ++ (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \ ++ SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \ ++ ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \ ++ SSB_CHIPCO_CHST_4325_OTP_SEL)) ++ + + + /** Clockcontrol masks and values **/ +@@ -564,6 +578,7 @@ struct ssb_chipcommon_pmu { + struct ssb_chipcommon { + struct ssb_device *dev; + u32 capabilities; ++ u32 status; + /* Fast Powerup Delay constant */ + u16 fast_pwrup_delay; + struct ssb_chipcommon_pmu pmu; +@@ -629,5 +644,15 @@ extern int ssb_chipco_serial_init(struct /* PMU support */ extern void ssb_pmu_init(struct ssb_chipcommon *cc); @@ -412,7 +2466,16 @@ #endif /* LINUX_SSB_CHIPCO_H_ */ --- a/include/linux/ssb/ssb_regs.h +++ b/include/linux/ssb/ssb_regs.h -@@ -162,7 +162,7 @@ +@@ -85,6 +85,8 @@ + #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */ + #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */ + #define SSB_IMSTATE_TO 0x00040000 /* Timeout */ ++#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */ ++#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */ + #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */ + #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */ + #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */ +@@ -162,7 +164,7 @@ /* SPROM shadow area. If not otherwise noted, fields are * two bytes wide. Note that the SPROM can _only_ be read @@ -421,27 +2484,333 @@ */ #define SSB_SPROMSIZE_WORDS 64 #define SSB_SPROMSIZE_BYTES (SSB_SPROMSIZE_WORDS * sizeof(u16)) -@@ -327,8 +327,11 @@ +@@ -170,26 +172,27 @@ + #define SSB_SPROMSIZE_WORDS_R4 220 + #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16)) + #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16)) +-#define SSB_SPROM_BASE 0x1000 +-#define SSB_SPROM_REVISION 0x107E ++#define SSB_SPROM_BASE1 0x1000 ++#define SSB_SPROM_BASE31 0x0800 ++#define SSB_SPROM_REVISION 0x007E + #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */ + #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */ + #define SSB_SPROM_REVISION_CRC_SHIFT 8 + + /* SPROM Revision 1 */ +-#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */ +-#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */ +-#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */ +-#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */ +-#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */ +-#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */ +-#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */ ++#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */ ++#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */ ++#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */ ++#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */ ++#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */ ++#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */ ++#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */ + #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */ + #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */ + #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5 + #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ + #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ +-#define SSB_SPROM1_BINF 0x105C /* Board info */ ++#define SSB_SPROM1_BINF 0x005C /* Board info */ + #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */ + #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */ + #define SSB_SPROM1_BINF_CCODE_SHIFT 8 +@@ -197,63 +200,63 @@ + #define SSB_SPROM1_BINF_ANTBG_SHIFT 12 + #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */ + #define SSB_SPROM1_BINF_ANTA_SHIFT 14 +-#define SSB_SPROM1_PA0B0 0x105E +-#define SSB_SPROM1_PA0B1 0x1060 +-#define SSB_SPROM1_PA0B2 0x1062 +-#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */ ++#define SSB_SPROM1_PA0B0 0x005E ++#define SSB_SPROM1_PA0B1 0x0060 ++#define SSB_SPROM1_PA0B2 0x0062 ++#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */ + #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */ + #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */ + #define SSB_SPROM1_GPIOA_P1_SHIFT 8 +-#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */ ++#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */ + #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */ + #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */ + #define SSB_SPROM1_GPIOB_P3_SHIFT 8 +-#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */ ++#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */ + #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */ + #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */ + #define SSB_SPROM1_MAXPWR_A_SHIFT 8 +-#define SSB_SPROM1_PA1B0 0x106A +-#define SSB_SPROM1_PA1B1 0x106C +-#define SSB_SPROM1_PA1B2 0x106E +-#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */ ++#define SSB_SPROM1_PA1B0 0x006A ++#define SSB_SPROM1_PA1B1 0x006C ++#define SSB_SPROM1_PA1B2 0x006E ++#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */ + #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/ + #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */ + #define SSB_SPROM1_ITSSI_A_SHIFT 8 +-#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */ +-#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */ ++#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */ ++#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */ + #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */ + #define SSB_SPROM1_AGAIN_BG_SHIFT 0 + #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */ + #define SSB_SPROM1_AGAIN_A_SHIFT 8 + + /* SPROM Revision 2 (inherits from rev 1) */ +-#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */ +-#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */ ++#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */ ++#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */ + #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */ + #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */ + #define SSB_SPROM2_MAXP_A_LO_SHIFT 8 +-#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */ +-#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */ +-#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */ +-#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */ +-#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */ +-#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */ +-#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */ ++#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */ ++#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */ ++#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */ ++#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */ ++#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */ ++#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */ ++#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */ + #define SSB_SPROM2_OPO_VALUE 0x00FF + #define SSB_SPROM2_OPO_UNUSED 0xFF00 +-#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */ ++#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */ + + /* SPROM Revision 3 (inherits most data from rev 2) */ +-#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */ +-#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */ +-#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */ +-#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */ +-#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */ ++#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */ ++#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */ ++#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */ ++#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */ + #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */ + #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8 + #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */ + #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16 +-#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */ ++#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */ ++#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */ + #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */ + #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */ + #define SSB_SPROM3_CCKPO_2M_SHIFT 4 +@@ -264,104 +267,200 @@ + #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */ + + /* SPROM Revision 4 */ +-#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */ +-#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */ ++#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */ ++#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */ ++#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */ ++#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */ ++#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */ ++#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */ ++#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */ ++#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */ ++#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */ ++#define SSB_SPROM4_GPIOA_P1_SHIFT 8 ++#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */ ++#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */ ++#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */ ++#define SSB_SPROM4_GPIOB_P3_SHIFT 8 ++#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */ + #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */ + #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */ + #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5 + #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ + #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ +-#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */ +-#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */ +-#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */ +-#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0 +-#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */ +-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8 +-#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */ +-#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */ ++#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */ ++#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */ ++#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0 ++#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */ ++#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8 ++#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */ + #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */ + #define SSB_SPROM4_AGAIN0_SHIFT 0 + #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */ + #define SSB_SPROM4_AGAIN1_SHIFT 8 +-#define SSB_SPROM4_AGAIN23 0x1060 ++#define SSB_SPROM4_AGAIN23 0x0060 + #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */ + #define SSB_SPROM4_AGAIN2_SHIFT 0 + #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */ + #define SSB_SPROM4_AGAIN3_SHIFT 8 +-#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */ +-#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */ ++#define SSB_SPROM4_TXPID2G01 0x0062 /* TX Power Index 2GHz */ ++#define SSB_SPROM4_TXPID2G0 0x00FF ++#define SSB_SPROM4_TXPID2G0_SHIFT 0 ++#define SSB_SPROM4_TXPID2G1 0xFF00 ++#define SSB_SPROM4_TXPID2G1_SHIFT 8 ++#define SSB_SPROM4_TXPID2G23 0x0064 /* TX Power Index 2GHz */ ++#define SSB_SPROM4_TXPID2G2 0x00FF ++#define SSB_SPROM4_TXPID2G2_SHIFT 0 ++#define SSB_SPROM4_TXPID2G3 0xFF00 ++#define SSB_SPROM4_TXPID2G3_SHIFT 8 ++#define SSB_SPROM4_TXPID5G01 0x0066 /* TX Power Index 5GHz middle subband */ ++#define SSB_SPROM4_TXPID5G0 0x00FF ++#define SSB_SPROM4_TXPID5G0_SHIFT 0 ++#define SSB_SPROM4_TXPID5G1 0xFF00 ++#define SSB_SPROM4_TXPID5G1_SHIFT 8 ++#define SSB_SPROM4_TXPID5G23 0x0068 /* TX Power Index 5GHz middle subband */ ++#define SSB_SPROM4_TXPID5G2 0x00FF ++#define SSB_SPROM4_TXPID5G2_SHIFT 0 ++#define SSB_SPROM4_TXPID5G3 0xFF00 ++#define SSB_SPROM4_TXPID5G3_SHIFT 8 ++#define SSB_SPROM4_TXPID5GL01 0x006A /* TX Power Index 5GHz low subband */ ++#define SSB_SPROM4_TXPID5GL0 0x00FF ++#define SSB_SPROM4_TXPID5GL0_SHIFT 0 ++#define SSB_SPROM4_TXPID5GL1 0xFF00 ++#define SSB_SPROM4_TXPID5GL1_SHIFT 8 ++#define SSB_SPROM4_TXPID5GL23 0x006C /* TX Power Index 5GHz low subband */ ++#define SSB_SPROM4_TXPID5GL2 0x00FF ++#define SSB_SPROM4_TXPID5GL2_SHIFT 0 ++#define SSB_SPROM4_TXPID5GL3 0xFF00 ++#define SSB_SPROM4_TXPID5GL3_SHIFT 8 ++#define SSB_SPROM4_TXPID5GH01 0x006E /* TX Power Index 5GHz high subband */ ++#define SSB_SPROM4_TXPID5GH0 0x00FF ++#define SSB_SPROM4_TXPID5GH0_SHIFT 0 ++#define SSB_SPROM4_TXPID5GH1 0xFF00 ++#define SSB_SPROM4_TXPID5GH1_SHIFT 8 ++#define SSB_SPROM4_TXPID5GH23 0x0070 /* TX Power Index 5GHz high subband */ ++#define SSB_SPROM4_TXPID5GH2 0x00FF ++#define SSB_SPROM4_TXPID5GH2_SHIFT 0 ++#define SSB_SPROM4_TXPID5GH3 0xFF00 ++#define SSB_SPROM4_TXPID5GH3_SHIFT 8 ++#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */ + #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */ + #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ + #define SSB_SPROM4_ITSSI_BG_SHIFT 8 +-#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */ ++#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */ + #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */ + #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */ + #define SSB_SPROM4_ITSSI_A_SHIFT 8 +-#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */ +-#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */ +-#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */ +-#define SSB_SPROM4_GPIOA_P1_SHIFT 8 +-#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */ +-#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */ +-#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */ +-#define SSB_SPROM4_GPIOB_P3_SHIFT 8 +-#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */ +-#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */ +-#define SSB_SPROM4_PA0B2 0x1086 +-#define SSB_SPROM4_PA1B0 0x108E +-#define SSB_SPROM4_PA1B1 0x1090 +-#define SSB_SPROM4_PA1B2 0x1092 ++#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */ ++#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */ ++#define SSB_SPROM4_PA0B2 0x0086 ++#define SSB_SPROM4_PA1B0 0x008E ++#define SSB_SPROM4_PA1B1 0x0090 ++#define SSB_SPROM4_PA1B2 0x0092 + + /* SPROM Revision 5 (inherits most data from rev 4) */ +-#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */ +-#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */ +-#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */ +-#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */ +-#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */ ++#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */ ++#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */ ++#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */ ++#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */ ++#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */ ++#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */ ++#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */ + #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */ + #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */ + #define SSB_SPROM5_GPIOA_P1_SHIFT 8 +-#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */ ++#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */ + #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */ + #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */ #define SSB_SPROM5_GPIOB_P3_SHIFT 8 /* SPROM Revision 8 */ -#define SSB_SPROM8_BFLLO 0x1084 /* Boardflags (low 16 bits) */ -#define SSB_SPROM8_BFLHI 0x1086 /* Boardflags Hi */ -+#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */ -+#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */ -+#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */ -+#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */ -+#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */ - #define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */ - #define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */ - #define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/ -@@ -354,14 +357,63 @@ - #define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */ - #define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */ - #define SSB_SPROM8_GPIOB_P3_SHIFT 8 +-#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */ +-#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */ +-#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/ +-#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */ +-#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8 +-#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */ +-#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0 +-#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */ ++#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */ ++#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */ ++#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */ ++#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */ ++#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */ ++#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */ ++#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */ ++#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */ ++#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */ ++#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */ ++#define SSB_SPROM8_GPIOA_P1_SHIFT 8 ++#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */ ++#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */ ++#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */ ++#define SSB_SPROM8_GPIOB_P3_SHIFT 8 ++#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/ ++#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */ ++#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8 ++#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */ ++#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0 ++#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */ + #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */ + #define SSB_SPROM8_AGAIN0_SHIFT 0 + #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */ + #define SSB_SPROM8_AGAIN1_SHIFT 8 +-#define SSB_SPROM8_AGAIN23 0x10A0 ++#define SSB_SPROM8_AGAIN23 0x00A0 + #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */ + #define SSB_SPROM8_AGAIN2_SHIFT 0 + #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */ + #define SSB_SPROM8_AGAIN3_SHIFT 8 +-#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */ +-#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */ +-#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */ +-#define SSB_SPROM8_GPIOA_P1_SHIFT 8 +-#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */ +-#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */ +-#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */ +-#define SSB_SPROM8_GPIOB_P3_SHIFT 8 -#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power BG in path 1 */ -#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */ -+#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */ ++#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */ +#define SSB_SPROM8_RSSISMF2G 0x000F +#define SSB_SPROM8_RSSISMC2G 0x00F0 +#define SSB_SPROM8_RSSISMC2G_SHIFT 4 @@ -449,7 +2818,7 @@ +#define SSB_SPROM8_RSSISAV2G_SHIFT 8 +#define SSB_SPROM8_BXA2G 0x1800 +#define SSB_SPROM8_BXA2G_SHIFT 11 -+#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */ ++#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */ +#define SSB_SPROM8_RSSISMF5G 0x000F +#define SSB_SPROM8_RSSISMC5G 0x00F0 +#define SSB_SPROM8_RSSISMC5G_SHIFT 4 @@ -457,49 +2826,49 @@ +#define SSB_SPROM8_RSSISAV5G_SHIFT 8 +#define SSB_SPROM8_BXA5G 0x1800 +#define SSB_SPROM8_BXA5G_SHIFT 11 -+#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */ ++#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */ +#define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */ +#define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */ +#define SSB_SPROM8_TRI5G_SHIFT 8 -+#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */ ++#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */ +#define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */ +#define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */ +#define SSB_SPROM8_TRI5GH_SHIFT 8 -+#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */ ++#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */ +#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */ +#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */ +#define SSB_SPROM8_RXPO5G_SHIFT 8 -+#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */ ++#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */ +#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */ #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ #define SSB_SPROM8_ITSSI_BG_SHIFT 8 -#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power A in path 1 */ -#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power A */ -+#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */ -+#define SSB_SPROM8_PA0B1 0x10C4 -+#define SSB_SPROM8_PA0B2 0x10C6 -+#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */ ++#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */ ++#define SSB_SPROM8_PA0B1 0x00C4 ++#define SSB_SPROM8_PA0B2 0x00C6 ++#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */ +#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */ #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */ #define SSB_SPROM8_ITSSI_A_SHIFT 8 -+#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */ ++#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */ +#define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */ +#define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */ +#define SSB_SPROM8_MAXP_AL_SHIFT 8 -+#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */ -+#define SSB_SPROM8_PA1B1 0x10CE -+#define SSB_SPROM8_PA1B2 0x10D0 -+#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */ -+#define SSB_SPROM8_PA1LOB1 0x10D4 -+#define SSB_SPROM8_PA1LOB2 0x10D6 -+#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */ -+#define SSB_SPROM8_PA1HIB1 0x10DA -+#define SSB_SPROM8_PA1HIB2 0x10DC -+#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */ -+#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */ -+#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */ -+#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */ -+#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */ ++#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */ ++#define SSB_SPROM8_PA1B1 0x00CE ++#define SSB_SPROM8_PA1B2 0x00D0 ++#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */ ++#define SSB_SPROM8_PA1LOB1 0x00D4 ++#define SSB_SPROM8_PA1LOB2 0x00D6 ++#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */ ++#define SSB_SPROM8_PA1HIB1 0x00DA ++#define SSB_SPROM8_PA1HIB2 0x00DC ++#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */ ++#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */ ++#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */ ++#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */ ++#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */ /* Values for SSB_SPROM1_BINF_CCODE */ enum { |