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author | Felix Fietkau <nbd@openwrt.org> | 2015-03-13 03:01:04 +0000 |
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committer | Felix Fietkau <nbd@openwrt.org> | 2015-03-13 03:01:04 +0000 |
commit | c35ad669cbf80253d549967ac7039199f66557f1 (patch) | |
tree | 1a536a37126988396fdd8827c5bee31aafd24cb6 /target/sdk | |
parent | a24e0d1b97fc538d6def8dc0ba2ce6da8fff3cad (diff) | |
download | master-187ad058-c35ad669cbf80253d549967ac7039199f66557f1.tar.gz master-187ad058-c35ad669cbf80253d549967ac7039199f66557f1.tar.bz2 master-187ad058-c35ad669cbf80253d549967ac7039199f66557f1.zip |
atheros: v3.18: remap main SoC MMR memory
Honestly remap main SoC MMR mem and use accessor functions to
interact with registers. Now registers defined relatively to base
address (e.g. SDRAM controller base address).
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@44723 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/sdk')
0 files changed, 0 insertions, 0 deletions