diff options
| author | Felix Fietkau <nbd@openwrt.org> | 2015-09-11 16:32:45 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2015-09-11 16:32:45 +0000 |
| commit | 9329ffbe964357608c4f99bfc6f7bf41e14da7a0 (patch) | |
| tree | ce316408cc89b5ea495a0fcdbd49c50970d99a91 /target/linux | |
| parent | ab849f2d2d86ca04c7159969476bf100957b86cd (diff) | |
| download | master-187ad058-9329ffbe964357608c4f99bfc6f7bf41e14da7a0.tar.gz master-187ad058-9329ffbe964357608c4f99bfc6f7bf41e14da7a0.tar.bz2 master-187ad058-9329ffbe964357608c4f99bfc6f7bf41e14da7a0.zip | |
ar71xx: fix ar724x clock calculation
According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz
input clock as the REF_CLK instead of 5MHz.
The correct CPU PLL calculation procedure is as follows:
CPU_PLL = (DIV * REF_CLK) / REF_DIV / 2.
This patch is compatible with the current calculation procedure with default
DIV and REF_DIV values.
Test on both AR7240, AR7241 and AR7242.
Signed-off-by: Weijie Gao <hackpascal@gmail.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@46856 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux')
| -rw-r--r-- | target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch b/target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch new file mode 100644 index 0000000000..16d462137e --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -25,7 +25,7 @@ + #include "common.h" + + #define AR71XX_BASE_FREQ 40000000 +-#define AR724X_BASE_FREQ 5000000 ++#define AR724X_BASE_FREQ 40000000 + #define AR913X_BASE_FREQ 5000000 + + struct clk { +@@ -99,8 +99,8 @@ + div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); + freq = div * ref_rate; + +- div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); +- freq *= div; ++ div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2; ++ freq /= div; + + cpu_rate = freq; + |