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author | Luka Perkov <luka@openwrt.org> | 2016-05-10 22:37:09 +0000 |
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committer | Luka Perkov <luka@openwrt.org> | 2016-06-19 19:34:04 +0200 |
commit | 391b50e4bccfe30552f0837cc74300a343a37bec (patch) | |
tree | a58d81729c6857a557374a6f5c2df39ad4ae688a /target/linux/ramips | |
parent | 21e9ab7e0d9e76a11abad55bd5b3ad55f5717279 (diff) | |
download | master-187ad058-391b50e4bccfe30552f0837cc74300a343a37bec.tar.gz master-187ad058-391b50e4bccfe30552f0837cc74300a343a37bec.tar.bz2 master-187ad058-391b50e4bccfe30552f0837cc74300a343a37bec.zip |
ramips: mt7620: [UPSTREAM] fix USB frequency scaling
The logic for the SoC check got inverted. We need to check if it's
not a MT76x8.
Signed-off-by: D. Andrei Măceș <dmaces@nd.edu>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@49352 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips')
-rw-r--r-- | target/linux/ramips/patches-4.4/0080-MIPS-ralink-fix-USB-frequency-scaling.patch | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-4.4/0080-MIPS-ralink-fix-USB-frequency-scaling.patch b/target/linux/ramips/patches-4.4/0080-MIPS-ralink-fix-USB-frequency-scaling.patch new file mode 100644 index 0000000000..0f3129e931 --- /dev/null +++ b/target/linux/ramips/patches-4.4/0080-MIPS-ralink-fix-USB-frequency-scaling.patch @@ -0,0 +1,33 @@ +From ae28413b3b8901ea00af3571e1c90d0228976e16 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 4 Jan 2016 20:23:57 +0100 +Subject: [PATCH 80/81] MIPS: ralink: fix USB frequency scaling + +Commit 418d29c87061 ("MIPS: ralink: Unify SoC id handling") was not fully +correct. The logic for the SoC check got inverted. We need to check if it +is not a MT76x8. + +Signed-off-by: John Crispin <blogic@openwrt.org> +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/11992/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ralink/mt7620.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c +index dfb04fc..fc19932 100644 +--- a/arch/mips/ralink/mt7620.c ++++ b/arch/mips/ralink/mt7620.c +@@ -439,7 +439,7 @@ void __init ralink_clk_init(void) + ralink_clk_add("10000c00.uartlite", periph_rate); + ralink_clk_add("10180000.wmac", xtal_rate); + +- if (IS_ENABLED(CONFIG_USB) && is_mt76x8()) { ++ if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) { + /* + * When the CPU goes into sleep mode, the BUS clock will be + * too low for USB to function properly. Adjust the busses +-- +2.1.4 + |