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author | John Crispin <blogic@openwrt.org> | 2014-03-18 19:21:56 +0000 |
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committer | John Crispin <blogic@openwrt.org> | 2014-03-18 19:21:56 +0000 |
commit | de51ae36beb618be705b292e32610a2e3efae330 (patch) | |
tree | 5bd54a4e1462f1d3bd187b2af9d1f2d1d4f00d55 /target/linux/ramips/files/drivers/usb/host/mtk-phy.c | |
parent | 694bc2270f53c34cdf86d5067040481f37e44e00 (diff) | |
download | master-187ad058-de51ae36beb618be705b292e32610a2e3efae330.tar.gz master-187ad058-de51ae36beb618be705b292e32610a2e3efae330.tar.bz2 master-187ad058-de51ae36beb618be705b292e32610a2e3efae330.zip |
ralink: refresh patches
Signed-off-by: John Crispin <blogic@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39949 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips/files/drivers/usb/host/mtk-phy.c')
-rw-r--r-- | target/linux/ramips/files/drivers/usb/host/mtk-phy.c | 102 |
1 files changed, 0 insertions, 102 deletions
diff --git a/target/linux/ramips/files/drivers/usb/host/mtk-phy.c b/target/linux/ramips/files/drivers/usb/host/mtk-phy.c deleted file mode 100644 index 7ed8f015b8..0000000000 --- a/target/linux/ramips/files/drivers/usb/host/mtk-phy.c +++ /dev/null @@ -1,102 +0,0 @@ -#include <linux/gfp.h> -#include <linux/kernel.h> -#include <linux/slab.h> -#define U3_PHY_LIB -#include "mtk-phy.h" -#ifdef CONFIG_PROJECT_7621 -#include "mtk-phy-7621.h" -#endif -#ifdef CONFIG_PROJECT_PHY -static struct u3phy_operator project_operators = { - .init = phy_init, - .change_pipe_phase = phy_change_pipe_phase, - .eyescan_init = eyescan_init, - .eyescan = phy_eyescan, - .u2_slew_rate_calibration = u2_slew_rate_calibration, -}; -#endif - - -PHY_INT32 u3phy_init(){ -#ifndef CONFIG_PROJECT_PHY - PHY_INT32 u3phy_version; -#endif - - if(u3phy != NULL){ - return PHY_TRUE; - } - - u3phy = kmalloc(sizeof(struct u3phy_info), GFP_NOIO); -#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM) - u3phy_p1 = kmalloc(sizeof(struct u3phy_info), GFP_NOIO); -#endif -#ifdef CONFIG_U3_PHY_GPIO_SUPPORT - u3phy->phyd_version_addr = 0x2000e4; -#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM) - u3phy_p1->phyd_version_addr = 0x2000e4; -#endif -#else - u3phy->phyd_version_addr = U3_PHYD_B2_BASE + 0xe4; -#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM) - u3phy_p1->phyd_version_addr = U3_PHYD_B2_BASE_P1 + 0xe4; -#endif -#endif - -#ifdef CONFIG_PROJECT_PHY - - u3phy->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE; - u3phy->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE; - u3phy->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE; - u3phy->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE; - u3phy->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE; - u3phy->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE; - u3phy->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE; - u3phy_ops = &project_operators; - -#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM) - u3phy_p1->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE_P1; - u3phy_p1->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE_P1; - u3phy_p1->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE_P1; - u3phy_p1->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE_P1; - u3phy_p1->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE_P1; - u3phy_p1->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE; - u3phy_p1->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE; -#endif -#endif - - return PHY_TRUE; -} - -PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){ - PHY_INT8 cur_value; - PHY_INT8 new_value; - - cur_value = U3PhyReadReg8(addr); - new_value = (cur_value & (~mask)) | (value << offset); - //udelay(i2cdelayus); - U3PhyWriteReg8(addr, new_value); - return PHY_TRUE; -} - -PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){ - PHY_INT32 cur_value; - PHY_INT32 new_value; - - cur_value = U3PhyReadReg32(addr); - new_value = (cur_value & (~mask)) | ((value << offset) & mask); - U3PhyWriteReg32(addr, new_value); - //DRV_MDELAY(100); - - return PHY_TRUE; -} - -PHY_INT32 U3PhyReadField8(PHY_INT32 addr,PHY_INT32 offset,PHY_INT32 mask){ - - return ((U3PhyReadReg8(addr) & mask) >> offset); -} - -PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask){ - - return ((U3PhyReadReg32(addr) & mask) >> offset); -} - |