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| author | Gabor Juhos <juhosg@openwrt.org> | 2012-09-12 19:03:12 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2012-09-12 19:03:12 +0000 |
| commit | 88571c64d74163aabda3a6a9cbf1a8555536e65e (patch) | |
| tree | eb44f761ca9bbb580c94b1cb48bea748c1e3523a /target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c | |
| parent | 05f9a7de8063fb97d5229f267299df17950f7291 (diff) | |
| download | master-187ad058-88571c64d74163aabda3a6a9cbf1a8555536e65e.tar.gz master-187ad058-88571c64d74163aabda3a6a9cbf1a8555536e65e.tar.bz2 master-187ad058-88571c64d74163aabda3a6a9cbf1a8555536e65e.zip | |
ramips/rt305x: add initial support for Rt5350 SoC
Somehow detecting the RAM size in common/setup.c doesn't
work here, it always detects 64M and then crashes on devices
with less RAM.
Probably using MEMC_REG_SDRAM_CFG1 to know the RAM size is how
it could be, for now I use the mem=32M kernel parameter to get
stuff working.
Signed-off-by: Daniel Golle <dgolle@allnet.de>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33381 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c')
| -rw-r--r-- | target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c index 958547611b..c46a1747b5 100644 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c +++ b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c @@ -62,6 +62,27 @@ void __init rt305x_clocks_init(void) rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; rt305x_uart_clk.rate = 40000000; rt305x_wdt_clk.rate = rt305x_sys_clk.rate; + } else if (soc_is_rt5350()) { + t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & + RT5350_SYSCFG0_CPUCLK_MASK; + switch (t) { + case RT5350_SYSCFG0_CPUCLK_360: + rt305x_cpu_clk.rate = 360000000; + rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; + break; + case RT5350_SYSCFG0_CPUCLK_320: + rt305x_cpu_clk.rate = 320000000; + rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 4; + break; + case RT5350_SYSCFG0_CPUCLK_300: + rt305x_cpu_clk.rate = 300000000; + rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; + break; + default: + BUG(); + } + rt305x_uart_clk.rate = 40000000; + rt305x_wdt_clk.rate = rt305x_sys_clk.rate; } else { BUG(); } |