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author | Gabor Juhos <juhosg@openwrt.org> | 2011-01-26 20:48:35 +0000 |
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committer | Gabor Juhos <juhosg@openwrt.org> | 2011-01-26 20:48:35 +0000 |
commit | 0bd787a60285f525a252e77d7c264f2d6e60f7c0 (patch) | |
tree | 20fe12b60542a5d3ea43bd1ce7234242e0407183 /target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c | |
parent | baa05587d0dff779f671d96f4025bfdd99d5ac02 (diff) | |
download | master-187ad058-0bd787a60285f525a252e77d7c264f2d6e60f7c0.tar.gz master-187ad058-0bd787a60285f525a252e77d7c264f2d6e60f7c0.tar.bz2 master-187ad058-0bd787a60285f525a252e77d7c264f2d6e60f7c0.zip |
ramips: implement clock API for RT305X
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@25124 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c')
-rw-r--r-- | target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c | 93 |
1 files changed, 93 insertions, 0 deletions
diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c new file mode 100644 index 0000000000..dff3738d3d --- /dev/null +++ b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c @@ -0,0 +1,93 @@ +/* + * Ralink RT305X clock API + * + * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/err.h> +#include <linux/clk.h> + +#include <asm/mach-ralink/common.h> +#include <asm/mach-ralink/rt305x.h> +#include <asm/mach-ralink/rt305x_regs.h> +#include "common.h" + +struct clk { + unsigned long rate; +}; + +static struct clk rt305x_cpu_clk; +static struct clk rt305x_sys_clk; +static struct clk rt305x_wdt_clk; +static struct clk rt305x_uart_clk; + +void __init rt305x_clocks_init(void) +{ + u32 t; + + t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG); + t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK); + + switch (t) { + case SYSTEM_CONFIG_CPUCLK_320: + rt305x_cpu_clk.rate = 320000000; + break; + case SYSTEM_CONFIG_CPUCLK_384: + rt305x_cpu_clk.rate = 384000000; + break; + } + + rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; + rt305x_uart_clk.rate = rt305x_sys_clk.rate; + rt305x_wdt_clk.rate = rt305x_sys_clk.rate; +} + +/* + * Linux clock API + */ +struct clk *clk_get(struct device *dev, const char *id) +{ + if (!strcmp(id, "sys")) + return &rt305x_sys_clk; + + if (!strcmp(id, "cpu")) + return &rt305x_cpu_clk; + + if (!strcmp(id, "wdt")) + return &rt305x_wdt_clk; + + if (!strcmp(id, "uart")) + return &rt305x_uart_clk; + + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk->rate; +} +EXPORT_SYMBOL(clk_get_rate); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); |