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| author | Gabor Juhos <juhosg@openwrt.org> | 2012-03-11 19:05:57 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2012-03-11 19:05:57 +0000 |
| commit | ec1e076734c41c42b83039a49c4e83d8ff28f537 (patch) | |
| tree | a83f0324a52210ebb6de578b36ba93ba64197b60 /target/linux/ramips/files/arch/mips/include | |
| parent | ea8fa1a9f18312af2012425217d520d8ecb44841 (diff) | |
| download | master-187ad058-ec1e076734c41c42b83039a49c4e83d8ff28f537.tar.gz master-187ad058-ec1e076734c41c42b83039a49c4e83d8ff28f537.tar.bz2 master-187ad058-ec1e076734c41c42b83039a49c4e83d8ff28f537.zip | |
ramips: rt305x: rename SYSTEM_CONFIG_* defines to RT305X_SYSCFG_*
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30889 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips/files/arch/mips/include')
| -rw-r--r-- | target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h index 64918fe4de..1ba5535557 100644 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h @@ -61,15 +61,15 @@ #define CHIP_ID_ID_SHIFT 8 #define CHIP_ID_REV_MASK 0xff -#define SYSTEM_CONFIG_CPUCLK_SHIFT 18 -#define SYSTEM_CONFIG_CPUCLK_MASK 0x1 -#define SYSTEM_CONFIG_CPUCLK_320 0x0 -#define SYSTEM_CONFIG_CPUCLK_384 0x1 -#define SYSTEM_CONFIG_SRAM_CS0_MODE_SHIFT 2 -#define SYSTEM_CONFIG_SRAM_CS0_MODE_MASK 0x3 -#define SYSTEM_CONFIG_SRAM_CS0_MODE_NORMAL 0 -#define SYSTEM_CONFIG_SRAM_CS0_MODE_WDT 1 -#define SYSTEM_CONFIG_SRAM_CS0_MODE_BTCOEX 2 +#define RT305X_SYSCFG_CPUCLK_SHIFT 18 +#define RT305X_SYSCFG_CPUCLK_MASK 0x1 +#define RT305X_SYSCFG_CPUCLK_LOW 0x0 +#define RT305X_SYSCFG_CPUCLK_HIGH 0x1 +#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2 +#define RT305X_SYSCFG_SRAM_CS0_MODE_MASK 0x3 +#define RT305X_SYSCFG_SRAM_CS0_MODE_NORMAL 0 +#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 1 +#define RT305X_SYSCFG_SRAM_CS0_MODE_BTCOEX 2 #define RT305X_GPIO_MODE_I2C BIT(0) #define RT305X_GPIO_MODE_SPI BIT(1) |