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| author | John Crispin <blogic@openwrt.org> | 2015-11-22 11:49:13 +0000 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2015-11-22 11:49:13 +0000 |
| commit | e8db47db7b6562db7d05ee83dd421752a2d2ce57 (patch) | |
| tree | 5f1d4b6b8594649e2a41e632fc82ce58dea2a296 /target/linux/ramips/dts/mt7620n.dtsi | |
| parent | 0dc3a43640fdf43ad86a5a701acfcabc5027c488 (diff) | |
| download | master-187ad058-e8db47db7b6562db7d05ee83dd421752a2d2ce57.tar.gz master-187ad058-e8db47db7b6562db7d05ee83dd421752a2d2ce57.tar.bz2 master-187ad058-e8db47db7b6562db7d05ee83dd421752a2d2ce57.zip | |
ramips: update dtsi files to support second spi device
Signed-off-by: Michael Lee <igvtee@gmail.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@47580 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips/dts/mt7620n.dtsi')
| -rw-r--r-- | target/linux/ramips/dts/mt7620n.dtsi | 32 |
1 files changed, 30 insertions, 2 deletions
diff --git a/target/linux/ramips/dts/mt7620n.dtsi b/target/linux/ramips/dts/mt7620n.dtsi index b1586ec073..a3132b8a59 100644 --- a/target/linux/ramips/dts/mt7620n.dtsi +++ b/target/linux/ramips/dts/mt7620n.dtsi @@ -20,6 +20,11 @@ compatible = "mti,cpu-interrupt-controller"; }; + aliases { + spi0 = &spi0; + spi1 = &spi1; + }; + palmbus@10000000 { compatible = "palmbus"; reg = <0x10000000 0x200000>; @@ -154,9 +159,9 @@ status = "disabled"; }; - spi@b00 { + spi0: spi@b00 { compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi"; - reg = <0xb00 0x100>; + reg = <0xb00 0x40>; resets = <&rstctrl 18>; reset-names = "spi"; @@ -170,6 +175,22 @@ pinctrl-0 = <&spi_pins>; }; + spi1: spi@b40 { + compatible = "ralink,rt2880-spi"; + reg = <0xb40 0x60>; + + resets = <&rstctrl 18>; + reset-names = "spi"; + + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + + pinctrl-names = "default"; + pinctrl-0 = <&spi_cs1>; + }; + uartlite@c00 { compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; reg = <0xc00 0x100>; @@ -213,6 +234,13 @@ }; }; + spi_cs1: spi1 { + spi1 { + ralink,group = "spi_cs1"; + ralink,function = "spi_cs1"; + }; + }; + uartlite_pins: uartlite { uart { ralink,group = "uartlite"; |