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author | John Crispin <blogic@openwrt.org> | 2014-11-26 09:00:08 +0000 |
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committer | John Crispin <blogic@openwrt.org> | 2014-11-26 09:00:08 +0000 |
commit | 7d4dfd7dd7ce1ac02d84ad7482e3f7d168d61ec9 (patch) | |
tree | 24af078d708bfb6b3027ff4064114d439e4213e1 /target/linux/oxnas/files/drivers/clocksource | |
parent | 2088d1ea438e14be13e9d579ebf847f9cc50245d (diff) | |
download | master-187ad058-7d4dfd7dd7ce1ac02d84ad7482e3f7d168d61ec9.tar.gz master-187ad058-7d4dfd7dd7ce1ac02d84ad7482e3f7d168d61ec9.tar.bz2 master-187ad058-7d4dfd7dd7ce1ac02d84ad7482e3f7d168d61ec9.zip |
add new target 'oxnas'
This is the oxnas target previously developed at
http://gitorious.org/openwrt-oxnas
Basically, this consolidates the changes and addtionas from
http://github.org/kref/linux-oxnas
into a new OpenWrt hardware target 'oxnas' adding support for
PLX Technology NAS7820/NAS7821/NAS7825/...
formally known as
Oxford Semiconductor OXE810SE/OXE815/OX820/...
For now there are 4 supported boards:
Cloud Engines Pogoplug V3 (without PCIe)
fully supported
Cloud Engines Pogoplug Pro (with PCIe)
fully supported
MitraStar STG-212
aka ZyXEL NSA-212,
aka Medion Akoya P89625 / P89636 / P89626 / P89630,
aka Medion MD 86407 / MD 86805 / MD 86517 / MD 86587
fully supported, see http://wiki.openwrt.org/toh/medion/md86587
Shuttle KD-20
partially supported (S-ATA driver lacks support for 2nd port)
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@43388 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/oxnas/files/drivers/clocksource')
-rw-r--r-- | target/linux/oxnas/files/drivers/clocksource/oxnas_rps_timer.c | 96 |
1 files changed, 96 insertions, 0 deletions
diff --git a/target/linux/oxnas/files/drivers/clocksource/oxnas_rps_timer.c b/target/linux/oxnas/files/drivers/clocksource/oxnas_rps_timer.c new file mode 100644 index 0000000000..7c8c4cf435 --- /dev/null +++ b/target/linux/oxnas/files/drivers/clocksource/oxnas_rps_timer.c @@ -0,0 +1,96 @@ +/* + * arch/arm/mach-ox820/rps-time.c + * + * Copyright (C) 2009 Oxford Semiconductor Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/clockchips.h> +#include <linux/clk.h> +#include <linux/of_irq.h> +#include <linux/of_address.h> +#include <linux/sched_clock.h> +#include <mach/hardware.h> + +enum { + TIMER_LOAD = 0, + TIMER_CURR = 4, + TIMER_CTRL = 8, + TIMER_CLRINT = 0xC, + + TIMER_BITS = 24, + + TIMER_MAX_VAL = (1 << TIMER_BITS) - 1, + + TIMER_PERIODIC = (1 << 6), + TIMER_ENABLE = (1 << 7), + + TIMER_DIV1 = (0 << 2), + TIMER_DIV16 = (1 << 2), + TIMER_DIV256 = (2 << 2), + + TIMER1_OFFSET = 0, + TIMER2_OFFSET = 0x20, + +}; + +static u64 notrace rps_read_sched_clock(void) +{ + return ~readl_relaxed(RPSA_TIMER2_VAL); +} + +static void __init rps_clocksource_init(void __iomem *base, ulong ref_rate) +{ + int ret; + ulong clock_rate; + /* use prescale 16 */ + clock_rate = ref_rate / 16; + + iowrite32(TIMER_MAX_VAL, base + TIMER_LOAD); + iowrite32(TIMER_PERIODIC | TIMER_ENABLE | TIMER_DIV16, + base + TIMER_CTRL); + + ret = clocksource_mmio_init(base + TIMER_CURR, "rps_clocksource_timer", + clock_rate, 250, TIMER_BITS, + clocksource_mmio_readl_down); + if (ret) + panic("can't register clocksource\n"); + + sched_clock_register(rps_read_sched_clock, TIMER_BITS, clock_rate); +} + +static void __init rps_timer_init(struct device_node *np) +{ + struct clk *refclk; + unsigned long ref_rate; + void __iomem *base; + + refclk = of_clk_get(np, 0); + + if (IS_ERR(refclk) || clk_prepare_enable(refclk)) + panic("rps_timer_init: failed to get refclk\n"); + ref_rate = clk_get_rate(refclk); + + base = of_iomap(np, 0); + if (!base) + panic("rps_timer_init: failed to map io\n"); + + rps_clocksource_init(base + TIMER2_OFFSET, ref_rate); +} + +CLOCKSOURCE_OF_DECLARE(nas782x, "plxtech,nas782x-rps-timer", rps_timer_init); |