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| author | Rafał Miłecki <zajec5@gmail.com> | 2015-04-07 22:06:17 +0000 |
|---|---|---|
| committer | Rafał Miłecki <zajec5@gmail.com> | 2015-04-07 22:06:17 +0000 |
| commit | dda5e2779eeba12f21cddbd163877ab668e35400 (patch) | |
| tree | dfac0c445d4d9443a5e03a3239febe7e7b3d2d23 /target/linux/generic/patches-4.0 | |
| parent | 0d7d44e1c14da6001a358d3c1777d82d42fb12f4 (diff) | |
| download | master-187ad058-dda5e2779eeba12f21cddbd163877ab668e35400.tar.gz master-187ad058-dda5e2779eeba12f21cddbd163877ab668e35400.tar.bz2 master-187ad058-dda5e2779eeba12f21cddbd163877ab668e35400.zip | |
kernel: backport ssb patches up to changes queued for 4.1
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45306 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/generic/patches-4.0')
| -rw-r--r-- | target/linux/generic/patches-4.0/020-ssb_update.patch | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/target/linux/generic/patches-4.0/020-ssb_update.patch b/target/linux/generic/patches-4.0/020-ssb_update.patch new file mode 100644 index 0000000000..946cb3b106 --- /dev/null +++ b/target/linux/generic/patches-4.0/020-ssb_update.patch @@ -0,0 +1,29 @@ +--- a/drivers/ssb/driver_pcicore.c ++++ b/drivers/ssb/driver_pcicore.c +@@ -357,6 +357,15 @@ static void ssb_pcicore_init_hostmode(st + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, + SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA); + ++ /* ++ * Accessing PCI config without a proper delay after devices reset (not ++ * GPIO reset) was causing reboots on WRT300N v1.0. ++ * Tested delay 850 us lowered reboot chance to 50-80%, 1000 us fixed it ++ * completely. Flushing all writes was also tested but with no luck. ++ */ ++ if (pc->dev->bus->chip_id == 0x4704) ++ usleep_range(1000, 2000); ++ + /* Enable PCI bridge BAR0 prefetch and burst */ + val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2); +--- a/drivers/ssb/main.c ++++ b/drivers/ssb/main.c +@@ -1135,6 +1135,8 @@ static u32 ssb_tmslow_reject_bitmask(str + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */ + case SSB_IDLOW_SSBREV_27: /* same here */ + return SSB_TMSLOW_REJECT; /* this is a guess */ ++ case SSB_IDLOW_SSBREV: ++ break; + default: + WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev); + } |