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| author | Hauke Mehrtens <hauke@openwrt.org> | 2014-08-19 20:06:24 +0000 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@openwrt.org> | 2014-08-19 20:06:24 +0000 |
| commit | 3ba033ed1b74e693d29491e3ecb432a3461c3245 (patch) | |
| tree | ccb1a8dbfbba0b5bbd5659d2c8ea994e1018bcf3 /target/linux/generic/patches-3.10 | |
| parent | fede953fc292ccc63a470a66f2da7e44c02fb94b (diff) | |
| download | master-187ad058-3ba033ed1b74e693d29491e3ecb432a3461c3245.tar.gz master-187ad058-3ba033ed1b74e693d29491e3ecb432a3461c3245.tar.bz2 master-187ad058-3ba033ed1b74e693d29491e3ecb432a3461c3245.zip | |
kernel: update bcma to code from v3.17-rc1
This is needed for some new patches.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@42221 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/generic/patches-3.10')
| -rw-r--r-- | target/linux/generic/patches-3.10/025-bcma_backport.patch | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/target/linux/generic/patches-3.10/025-bcma_backport.patch b/target/linux/generic/patches-3.10/025-bcma_backport.patch index 2b3f4ae7e0..0d41ed03c0 100644 --- a/target/linux/generic/patches-3.10/025-bcma_backport.patch +++ b/target/linux/generic/patches-3.10/025-bcma_backport.patch @@ -996,17 +996,17 @@ { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" }, { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" }, { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" }, -+ { BCMA_CORE_PCIEG2, "PCIe Gen 2" }, -+ { BCMA_CORE_DMA, "DMA" }, -+ { BCMA_CORE_SDIO3, "SDIO3" }, -+ { BCMA_CORE_USB20, "USB 2.0" }, -+ { BCMA_CORE_USB30, "USB 3.0" }, -+ { BCMA_CORE_A9JTAG, "ARM Cortex A9 JTAG" }, -+ { BCMA_CORE_DDR23, "Denali DDR2/DDR3 memory controller" }, -+ { BCMA_CORE_ROM, "ROM" }, -+ { BCMA_CORE_NAND, "NAND flash controller" }, -+ { BCMA_CORE_QSPI, "SPI flash controller" }, -+ { BCMA_CORE_CHIPCOMMON_B, "Chipcommon B" }, ++ { BCMA_CORE_NS_PCIEG2, "PCIe Gen 2" }, ++ { BCMA_CORE_NS_DMA, "DMA" }, ++ { BCMA_CORE_NS_SDIO3, "SDIO3" }, ++ { BCMA_CORE_NS_USB20, "USB 2.0" }, ++ { BCMA_CORE_NS_USB30, "USB 3.0" }, ++ { BCMA_CORE_NS_A9JTAG, "ARM Cortex A9 JTAG" }, ++ { BCMA_CORE_NS_DDR23, "Denali DDR2/DDR3 memory controller" }, ++ { BCMA_CORE_NS_ROM, "ROM" }, ++ { BCMA_CORE_NS_NAND, "NAND flash controller" }, ++ { BCMA_CORE_NS_QSPI, "SPI flash controller" }, ++ { BCMA_CORE_NS_CHIPCOMMON_B, "Chipcommon B" }, + { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" }, { BCMA_CORE_AMEMC, "AMEMC (DDR)" }, { BCMA_CORE_ALTA, "ALTA (I2S)" }, @@ -1327,17 +1327,17 @@ /* Core-ID values. */ #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */ #define BCMA_CORE_4706_CHIPCOMMON 0x500 -+#define BCMA_CORE_PCIEG2 0x501 -+#define BCMA_CORE_DMA 0x502 -+#define BCMA_CORE_SDIO3 0x503 -+#define BCMA_CORE_USB20 0x504 -+#define BCMA_CORE_USB30 0x505 -+#define BCMA_CORE_A9JTAG 0x506 -+#define BCMA_CORE_DDR23 0x507 -+#define BCMA_CORE_ROM 0x508 -+#define BCMA_CORE_NAND 0x509 -+#define BCMA_CORE_QSPI 0x50A -+#define BCMA_CORE_CHIPCOMMON_B 0x50B ++#define BCMA_CORE_NS_PCIEG2 0x501 ++#define BCMA_CORE_NS_DMA 0x502 ++#define BCMA_CORE_NS_SDIO3 0x503 ++#define BCMA_CORE_NS_USB20 0x504 ++#define BCMA_CORE_NS_USB30 0x505 ++#define BCMA_CORE_NS_A9JTAG 0x506 ++#define BCMA_CORE_NS_DDR23 0x507 ++#define BCMA_CORE_NS_ROM 0x508 ++#define BCMA_CORE_NS_NAND 0x509 ++#define BCMA_CORE_NS_QSPI 0x50A ++#define BCMA_CORE_NS_CHIPCOMMON_B 0x50B #define BCMA_CORE_4706_SOC_RAM 0x50E +#define BCMA_CORE_ARMCA9 0x510 #define BCMA_CORE_4706_MAC_GBIT 0x52D |