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| author | Rafał Miłecki <zajec5@gmail.com> | 2015-04-12 20:00:42 +0000 |
|---|---|---|
| committer | Rafał Miłecki <zajec5@gmail.com> | 2015-04-12 20:00:42 +0000 |
| commit | 53f674d8d6f836364c65bc22bb3fede501f0281a (patch) | |
| tree | 4df99eddf9f8535bab25d9568315b1951b6bfe10 /target/linux/generic/files/drivers/net/phy/b53/b53_common.c | |
| parent | c00c6ea570be2687af253ded1b24e8de950fd375 (diff) | |
| download | master-187ad058-53f674d8d6f836364c65bc22bb3fede501f0281a.tar.gz master-187ad058-53f674d8d6f836364c65bc22bb3fede501f0281a.tar.bz2 master-187ad058-53f674d8d6f836364c65bc22bb3fede501f0281a.zip | |
b53: improve overriding CPU port state on BCM5301X
On BCM5301X there are two different cases to handle: CPU port 8 vs. any
other one. Support for CPU port 8 was already partially implemented but
it lacked setting some extra bit for 2G speed. It also will need to be
extended to implement "SMP dual core 3 GMAC setup". That's the reason
for handling it in separated code block.
This patch also adds overriding CPU port state for port other than 8. It
requires using recently defined GMII_PORT registers.
It was tested for regressions on BCM53011 revs 2 & 3. It was also
confirmed to fix switch on some internal Broadcom board.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Jonas Gorski <jogo@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45402 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/generic/files/drivers/net/phy/b53/b53_common.c')
| -rw-r--r-- | target/linux/generic/files/drivers/net/phy/b53/b53_common.c | 31 |
1 files changed, 29 insertions, 2 deletions
diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_common.c b/target/linux/generic/files/drivers/net/phy/b53/b53_common.c index d2bb51ab4a..ac7c10cadc 100644 --- a/target/linux/generic/files/drivers/net/phy/b53/b53_common.c +++ b/target/linux/generic/files/drivers/net/phy/b53/b53_common.c @@ -480,6 +480,7 @@ static void b53_switch_reset_gpio(struct b53_device *dev) static int b53_switch_reset(struct b53_device *dev) { + u8 cpu_port = dev->sw_dev.cpu_port; u8 mgmt; b53_switch_reset_gpio(dev); @@ -525,8 +526,7 @@ static int b53_switch_reset(struct b53_device *dev) return -EINVAL; } } - } else if ((is531x5(dev) || is5301x(dev)) && - dev->sw_dev.cpu_port == B53_CPU_PORT) { + } else if (is531x5(dev) && cpu_port == B53_CPU_PORT) { u8 mii_port_override; b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, @@ -534,6 +534,33 @@ static int b53_switch_reset(struct b53_device *dev) b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, mii_port_override | PORT_OVERRIDE_EN | PORT_OVERRIDE_LINK); + } else if (is5301x(dev)) { + if (cpu_port == 8) { + u8 mii_port_override; + + b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, + &mii_port_override); + mii_port_override |= PORT_OVERRIDE_LINK | + PORT_OVERRIDE_RX_FLOW | + PORT_OVERRIDE_TX_FLOW | + PORT_OVERRIDE_SPEED_2000M | + PORT_OVERRIDE_EN; + b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, + mii_port_override); + + /* TODO: Ports 5 & 7 require some extra handling */ + } else { + u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(cpu_port); + u8 gmii_po; + + b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po); + gmii_po |= GMII_PO_LINK | + GMII_PO_RX_FLOW | + GMII_PO_TX_FLOW | + GMII_PO_EN | + GMII_PO_SPEED_2000M; + b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po); + } } b53_enable_mib(dev); |