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author | Gabor Juhos <juhosg@openwrt.org> | 2012-05-18 20:10:53 +0000 |
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committer | Gabor Juhos <juhosg@openwrt.org> | 2012-05-18 20:10:53 +0000 |
commit | 020b9941036f4dd9fde62e9e3666b5e44704bb27 (patch) | |
tree | 1eb806de4cc59e2f5d288d8d3ce0cfea82e374cb /target/linux/cns3xxx/patches-3.3/105-cns3xxx_pcie_io.patch | |
parent | 67ea71e39723d1a2dbb505fa4402455c39716d2a (diff) | |
download | master-187ad058-020b9941036f4dd9fde62e9e3666b5e44704bb27.tar.gz master-187ad058-020b9941036f4dd9fde62e9e3666b5e44704bb27.tar.bz2 master-187ad058-020b9941036f4dd9fde62e9e3666b5e44704bb27.zip |
cns3xxx: add support for 3.3
Compile tested only.
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31809 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/cns3xxx/patches-3.3/105-cns3xxx_pcie_io.patch')
-rw-r--r-- | target/linux/cns3xxx/patches-3.3/105-cns3xxx_pcie_io.patch | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/target/linux/cns3xxx/patches-3.3/105-cns3xxx_pcie_io.patch b/target/linux/cns3xxx/patches-3.3/105-cns3xxx_pcie_io.patch new file mode 100644 index 0000000000..e7fe0b1e1e --- /dev/null +++ b/target/linux/cns3xxx/patches-3.3/105-cns3xxx_pcie_io.patch @@ -0,0 +1,88 @@ +--- a/arch/arm/mach-cns3xxx/core.c ++++ b/arch/arm/mach-cns3xxx/core.c +@@ -80,6 +80,16 @@ static struct map_desc cns3xxx_io_desc[] + .pfn = __phys_to_pfn(CNS3XXX_SSP_BASE), + .length = SZ_4K, + .type = MT_DEVICE, ++ }, { ++ .virtual = CNS3XXX_PCIE0_IO_BASE_VIRT, ++ .pfn = __phys_to_pfn(CNS3XXX_PCIE0_IO_BASE), ++ .length = SZ_16M, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = CNS3XXX_PCIE1_IO_BASE_VIRT, ++ .pfn = __phys_to_pfn(CNS3XXX_PCIE1_IO_BASE), ++ .length = SZ_16M, ++ .type = MT_DEVICE, + }, + }; + +@@ -155,13 +165,13 @@ void __init cns3xxx_common_init(void) + /* used by entry-macro.S */ + void __init cns3xxx_init_irq(void) + { +- gic_init(0, 29, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), +- __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT)); ++ gic_init(0, 29, (void __iomem *) CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT, ++ (void __iomem *) CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT); + } + + void cns3xxx_power_off(void) + { +- u32 __iomem *pm_base = __io(CNS3XXX_PM_BASE_VIRT); ++ u32 __iomem *pm_base = (void __iomem *) CNS3XXX_PM_BASE_VIRT; + u32 clkctrl; + + printk(KERN_INFO "powering system down...\n"); +@@ -335,7 +345,7 @@ static void __init __cns3xxx_timer_init( + + static void __init cns3xxx_timer_init(void) + { +- cns3xxx_tmr1 = __io(CNS3XXX_TIMER1_2_3_BASE_VIRT); ++ cns3xxx_tmr1 = (void __iomem *) CNS3XXX_TIMER1_2_3_BASE_VIRT; + + __cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0); + } +--- a/arch/arm/mach-cns3xxx/devices.c ++++ b/arch/arm/mach-cns3xxx/devices.c +@@ -98,7 +98,7 @@ static struct platform_device cns3xxx_sd + + void __init cns3xxx_sdhci_init(void) + { +- u32 __iomem *gpioa = __io(CNS3XXX_MISC_BASE_VIRT + 0x0014); ++ u32 __iomem *gpioa = (void __iomem *) (CNS3XXX_MISC_BASE_VIRT + 0x0014); + u32 gpioa_pins = __raw_readl(gpioa); + + /* MMC/SD pins share with GPIOA */ +--- a/arch/arm/mach-cns3xxx/include/mach/io.h ++++ b/arch/arm/mach-cns3xxx/include/mach/io.h +@@ -9,9 +9,17 @@ + #ifndef __MACH_IO_H + #define __MACH_IO_H + ++#include "cns3xxx.h" ++ + #define IO_SPACE_LIMIT 0xffffffff + +-#define __io(a) __typesafe_io(a) ++static inline void __iomem *__io(unsigned long addr) ++{ ++ return (void __iomem *)((addr - CNS3XXX_PCIE0_IO_BASE) ++ + CNS3XXX_PCIE0_IO_BASE_VIRT); ++} ++ ++#define __io(a) __io(a) + #define __mem_pci(a) (a) + + #endif +--- a/drivers/spi/spi_cns3xxx.c ++++ b/drivers/spi/spi_cns3xxx.c +@@ -273,7 +273,7 @@ done: + + static void __init cns3xxx_spi_initial(void) + { +- u32 __iomem *gpiob = __io(CNS3XXX_MISC_BASE_VIRT + 0x0018); ++ u32 __iomem *gpiob = (void __iomem *) (CNS3XXX_MISC_BASE_VIRT + 0x0018); + u32 gpiob_pins = __raw_readl(gpiob); + + /* MMC/SD pins share with GPIOA */ |