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authorAlvaro Fernández Rojas <noltari@gmail.com>2016-06-20 23:24:50 +0200
committerZoltan HERPAI <wigyori@uid0.hu>2016-06-20 23:24:50 +0200
commit2dc1e11c688a439084692e0b86d20adc0310d42c (patch)
tree75d7685ac955c38262433c6b8757cd1169b63e35 /target/linux/brcm2708/patches-4.4/0292-drm-vc4-Fix-setting-of-vertical-timings-in-the-CRTC.patch
parent14cd93c1ec0fecdd49d5bbf9ebec1a9bf02d6803 (diff)
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As usual these patches were extracted from the raspberry pi repo:
https://github.com/raspberrypi/linux/tree/rpi-4.4.y Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Diffstat (limited to 'target/linux/brcm2708/patches-4.4/0292-drm-vc4-Fix-setting-of-vertical-timings-in-the-CRTC.patch')
-rw-r--r--target/linux/brcm2708/patches-4.4/0292-drm-vc4-Fix-setting-of-vertical-timings-in-the-CRTC.patch34
1 files changed, 34 insertions, 0 deletions
diff --git a/target/linux/brcm2708/patches-4.4/0292-drm-vc4-Fix-setting-of-vertical-timings-in-the-CRTC.patch b/target/linux/brcm2708/patches-4.4/0292-drm-vc4-Fix-setting-of-vertical-timings-in-the-CRTC.patch
new file mode 100644
index 0000000000..c5a1b97d19
--- /dev/null
+++ b/target/linux/brcm2708/patches-4.4/0292-drm-vc4-Fix-setting-of-vertical-timings-in-the-CRTC.patch
@@ -0,0 +1,34 @@
+From a0d015caa8ddfd37ae8cbfc7aec1d614b5ad3b78 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Mon, 15 Feb 2016 17:31:41 -0800
+Subject: [PATCH 292/304] drm/vc4: Fix setting of vertical timings in the CRTC.
+
+It looks like when I went to add the interlaced bits, I just took the
+existing PV_VERT* block and indented it, instead of copy and pasting
+it first. Without this, changing resolution never worked.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit a7c5047d1ce178dd2b1fa577fc8909ad663d56d5)
+---
+ drivers/gpu/drm/vc4/vc4_crtc.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/drivers/gpu/drm/vc4/vc4_crtc.c
++++ b/drivers/gpu/drm/vc4/vc4_crtc.c
+@@ -217,6 +217,16 @@ static void vc4_crtc_mode_set_nofb(struc
+ PV_HORZB_HFP) |
+ VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE));
+
++ CRTC_WRITE(PV_VERTA,
++ VC4_SET_FIELD(mode->vtotal - mode->vsync_end,
++ PV_VERTA_VBP) |
++ VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
++ PV_VERTA_VSYNC));
++ CRTC_WRITE(PV_VERTB,
++ VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
++ PV_VERTB_VFP) |
++ VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));
++
+ if (interlace) {
+ CRTC_WRITE(PV_VERTA_EVEN,
+ VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1,