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| author | Hauke Mehrtens <hauke@openwrt.org> | 2015-12-02 15:23:08 +0000 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@openwrt.org> | 2015-12-02 15:23:08 +0000 |
| commit | 8fdb4d2eaa72125879fb3e05ede6913a3733f86a (patch) | |
| tree | 24384c705928c2f8a8896aa8456922a0910bb460 /target/linux/bcm53xx/patches-4.1/130-dt-bindings-add-SMP-enable-method-for-Broadcom-NSP.patch | |
| parent | 83ce86dec975da392a44c2f4287459df2b7027a4 (diff) | |
| download | master-187ad058-8fdb4d2eaa72125879fb3e05ede6913a3733f86a.tar.gz master-187ad058-8fdb4d2eaa72125879fb3e05ede6913a3733f86a.tar.bz2 master-187ad058-8fdb4d2eaa72125879fb3e05ede6913a3733f86a.zip | |
bcm53xx: update SMP patches
Broadcom submitted new SMP patches for this SoC to upstream Linux, add
them to OpenWrt.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@47687 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/bcm53xx/patches-4.1/130-dt-bindings-add-SMP-enable-method-for-Broadcom-NSP.patch')
| -rw-r--r-- | target/linux/bcm53xx/patches-4.1/130-dt-bindings-add-SMP-enable-method-for-Broadcom-NSP.patch | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/target/linux/bcm53xx/patches-4.1/130-dt-bindings-add-SMP-enable-method-for-Broadcom-NSP.patch b/target/linux/bcm53xx/patches-4.1/130-dt-bindings-add-SMP-enable-method-for-Broadcom-NSP.patch new file mode 100644 index 0000000000..ce002a29da --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/130-dt-bindings-add-SMP-enable-method-for-Broadcom-NSP.patch @@ -0,0 +1,69 @@ +From 204b9dbd7c4bd5a223fd104b9cba56c12fe04add Mon Sep 17 00:00:00 2001 +From: Kapil Hali <kapilh@broadcom.com> +Date: Wed, 19 Aug 2015 13:42:23 -0400 +Subject: [PATCH 130/134] dt-bindings: add SMP enable-method for Broadcom NSP + +Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's +Northstar Plus CPU to the 32-bit ARM CPU device tree binding +documentation file and create a new binding documentation for +Northstar Plus CPU. + +Signed-off-by: Kapil Hali <kapilh@broadcom.com> +--- + .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 39 ++++++++++++++++++++++ + Documentation/devicetree/bindings/arm/cpus.txt | 1 + + 2 files changed, 40 insertions(+) + create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt + +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt +@@ -0,0 +1,39 @@ ++Broadcom Northstar Plus SoC CPU Enable Method ++--------------------------------------------- ++This binding defines the enable method used for starting secondary ++CPUs in the following Broadcom SoCs: ++ BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 ++ ++The enable method is specified by defining the following required ++properties in the "cpus" device tree node: ++ - enable-method = "brcm,bcm-nsp-smp"; ++ - secondary-boot-reg = <...>; ++ ++The secondary-boot-reg property is a u32 value that specifies the ++physical address of the register which should hold the common ++entry point for a secondary CPU. This entry is cpu node specific ++and should be added per cpu. E.g., in case of NSP (BCM58625) which ++is a dual core CPU SoC, this entry should be added to cpu1 node. ++ ++ ++Example: ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ enable-method = "brcm,bcm-nsp-smp"; ++ ++ cpu0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a9"; ++ next-level-cache = <&L2>; ++ reg = <0>; ++ }; ++ ++ cpu1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a9"; ++ next-level-cache = <&L2>; ++ reg = <1>; ++ secondary-boot-reg = <0xffff042c>; ++ }; ++ }; +--- a/Documentation/devicetree/bindings/arm/cpus.txt ++++ b/Documentation/devicetree/bindings/arm/cpus.txt +@@ -189,6 +189,7 @@ nodes to be present and contain the prop + can be one of: + "allwinner,sun6i-a31" + "arm,psci" ++ "brcm,bcm-nsp-smp" + "brcm,brahma-b15" + "marvell,armada-375-smp" + "marvell,armada-380-smp" |