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| author | Felix Fietkau <nbd@openwrt.org> | 2015-07-19 17:58:46 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2015-07-19 17:58:46 +0000 |
| commit | 651504de1ec5fa4e661a7944746fb87659938edc (patch) | |
| tree | a6046d52b05ae64911922686327e2e92ba064dd4 /target/linux/ar71xx/patches-4.1/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch | |
| parent | ed2bc20d7f7aab0886ccf8baf4141740c249f6a8 (diff) | |
| download | master-187ad058-651504de1ec5fa4e661a7944746fb87659938edc.tar.gz master-187ad058-651504de1ec5fa4e661a7944746fb87659938edc.tar.bz2 master-187ad058-651504de1ec5fa4e661a7944746fb87659938edc.zip | |
ar71xx: refresh 4.1 patches
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@46427 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/patches-4.1/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-4.1/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target/linux/ar71xx/patches-4.1/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.1/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch index f8b1264155..2c624b3a2e 100644 --- a/target/linux/ar71xx/patches-4.1/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch +++ b/target/linux/ar71xx/patches-4.1/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch @@ -22,7 +22,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig -@@ -1205,6 +1205,10 @@ config SOC_AR934X +@@ -1229,6 +1229,10 @@ config SOC_AR934X select PCI_AR724X if PCI def_bool n @@ -33,7 +33,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. config SOC_QCA955X select HW_HAS_PCI select PCI_AR724X if PCI -@@ -1247,7 +1251,7 @@ config ATH79_DEV_USB +@@ -1271,7 +1275,7 @@ config ATH79_DEV_USB def_bool n config ATH79_DEV_WMAC @@ -394,7 +394,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. } else if (soc_is_qca955x()) { ath79_ip2_handler = ath79_default_ip2_handler; ath79_ip3_handler = ath79_default_ip3_handler; -@@ -365,6 +407,8 @@ void __init arch_init_irq(void) +@@ -364,6 +406,8 @@ void __init arch_init_irq(void) if (soc_is_ar934x()) ar934x_ip2_irq_init(); |