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| author | Gabor Juhos <juhosg@openwrt.org> | 2012-09-10 14:38:01 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2012-09-10 14:38:01 +0000 |
| commit | 888f24c4a41a4907bafc4bf108341b22201ad304 (patch) | |
| tree | da66bb7eb6bf89f8478bf887520747c84b08c1a8 /target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch | |
| parent | 9f2bbfb4236a3e11daeb722ad906ed00810d2d59 (diff) | |
| download | master-187ad058-888f24c4a41a4907bafc4bf108341b22201ad304.tar.gz master-187ad058-888f24c4a41a4907bafc4bf108341b22201ad304.tar.bz2 master-187ad058-888f24c4a41a4907bafc4bf108341b22201ad304.zip | |
ar71xx: use correct fractional dividers for {CPU,DDR}_PLL on QCA955x
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33362 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch index 289ec6d296..bb0924c430 100644 --- a/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch +++ b/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch @@ -38,7 +38,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org> + QCA955X_PLL_CPU_CONFIG_NFRAC_MASK; + + cpu_pll = nint * ath79_ref_clk.rate / ref_div; -+ cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6)); ++ cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6)); + cpu_pll /= (1 << out_div); + + pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG); @@ -52,7 +52,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org> + QCA955X_PLL_DDR_CONFIG_NFRAC_MASK; + + ddr_pll = nint * ath79_ref_clk.rate / ref_div; -+ ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10)); ++ ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10)); + ddr_pll /= (1 << out_div); + + clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG); |