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| author | John Crispin <blogic@openwrt.org> | 2014-09-15 10:19:38 +0000 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2014-09-15 10:19:38 +0000 |
| commit | ba33fec925ccd1a96921437a31a1ca49352d0595 (patch) | |
| tree | 6eb9422e5ba65e6c4d3d53848fa53555b3c11dd6 /target/linux/ar71xx/patches-3.14/601-MIPS-ath79-add-more-register-defines.patch | |
| parent | da18057e0514e7d80e81d9167b856bc20c4b12a9 (diff) | |
| download | master-187ad058-ba33fec925ccd1a96921437a31a1ca49352d0595.tar.gz master-187ad058-ba33fec925ccd1a96921437a31a1ca49352d0595.tar.bz2 master-187ad058-ba33fec925ccd1a96921437a31a1ca49352d0595.zip | |
ar71xx: add qihoo 360 c301 router support
Qihoo 360 C301 is a dual band wireless router supports 802.11n and 802.11ac.
Its chipset is AR9344 + AR9882 with two 16MB flashes.
This patch adds its initial support.
v2:
* use mtd_get_mac_ascii to fetch MAC address for ath10k.
* use ath79_register_pci to initialize AR9882.
Signed-off-by: Weijie Gao <hackpascal@gmail.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@42552 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/patches-3.14/601-MIPS-ath79-add-more-register-defines.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-3.14/601-MIPS-ath79-add-more-register-defines.patch | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/linux/ar71xx/patches-3.14/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.14/601-MIPS-ath79-add-more-register-defines.patch index 79e53b3460..2dec0209d7 100644 --- a/target/linux/ar71xx/patches-3.14/601-MIPS-ath79-add-more-register-defines.patch +++ b/target/linux/ar71xx/patches-3.14/601-MIPS-ath79-add-more-register-defines.patch @@ -207,7 +207,7 @@ #define AR934X_GPIO_REG_FUNC 0x6c #define AR71XX_GPIO_COUNT 16 -@@ -560,4 +663,148 @@ +@@ -560,4 +663,149 @@ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 @@ -279,6 +279,7 @@ +#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) + +#define AR934X_GPIO_OUT_GPIO 0 ++#define AR934X_GPIO_OUT_SPI_CS1 7 +#define AR934X_GPIO_OUT_LED_LINK0 41 +#define AR934X_GPIO_OUT_LED_LINK1 42 +#define AR934X_GPIO_OUT_LED_LINK2 43 |