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| author | Felix Fietkau <nbd@openwrt.org> | 2010-05-16 00:20:17 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2010-05-16 00:20:17 +0000 |
| commit | 55de6aeeb9321c2c31c9e0e38aa9431d9a89e13f (patch) | |
| tree | ad7ff33b39148fe64db001ba35c7573d9e1352c7 /package/uboot-lantiq | |
| parent | 8d429d0e2e4345094516081c17939b3ad9701d4f (diff) | |
| download | master-187ad058-55de6aeeb9321c2c31c9e0e38aa9431d9a89e13f.tar.gz master-187ad058-55de6aeeb9321c2c31c9e0e38aa9431d9a89e13f.tar.bz2 master-187ad058-55de6aeeb9321c2c31c9e0e38aa9431d9a89e13f.zip | |
get rid of CRLF encoding in various files
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@21462 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'package/uboot-lantiq')
3 files changed, 151 insertions, 151 deletions
diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h index cecd279b39..3a4b1350e4 100644 --- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h +++ b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h @@ -1,50 +1,50 @@ -/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */
-#define MC_DC0_VALUE 0x1B1B
-#define MC_DC1_VALUE 0x0
-#define MC_DC2_VALUE 0x0
-#define MC_DC3_VALUE 0x0
-#define MC_DC4_VALUE 0x0
-#define MC_DC5_VALUE 0x200
-#define MC_DC6_VALUE 0x605
-#define MC_DC7_VALUE 0x303
-#define MC_DC8_VALUE 0x102
-#define MC_DC9_VALUE 0x70a
-#define MC_DC10_VALUE 0x203
-#define MC_DC11_VALUE 0xc02
-#define MC_DC12_VALUE 0x1C8
-#define MC_DC13_VALUE 0x1
-#define MC_DC14_VALUE 0x0
-#define MC_DC15_VALUE 0xf3c
-#define MC_DC16_VALUE 0xC800
-#define MC_DC17_VALUE 0xd
-#define MC_DC18_VALUE 0x300
-#define MC_DC19_VALUE 0x200
-#define MC_DC20_VALUE 0xA03
-#define MC_DC21_VALUE 0x1d00
-#define MC_DC22_VALUE 0x1d1d
-#define MC_DC23_VALUE 0x0
-#define MC_DC24_VALUE 0x5e /* was 0x7f */
-#define MC_DC25_VALUE 0x0
-#define MC_DC26_VALUE 0x0
-#define MC_DC27_VALUE 0x0
-#define MC_DC28_VALUE 0x510
-#define MC_DC29_VALUE 0x2d89
-#define MC_DC30_VALUE 0x8300
-#define MC_DC31_VALUE 0x0
-#define MC_DC32_VALUE 0x0
-#define MC_DC33_VALUE 0x0
-#define MC_DC34_VALUE 0x0
-#define MC_DC35_VALUE 0x0
-#define MC_DC36_VALUE 0x0
-#define MC_DC37_VALUE 0x0
-#define MC_DC38_VALUE 0x0
-#define MC_DC39_VALUE 0x0
-#define MC_DC40_VALUE 0x0
-#define MC_DC41_VALUE 0x0
-#define MC_DC42_VALUE 0x0
-#define MC_DC43_VALUE 0x0
-#define MC_DC44_VALUE 0x0
-#define MC_DC45_VALUE 0x500
-//#define MC_DC45_VALUE 0x400
-#define MC_DC46_VALUE 0x0
+/* Settings for Denali DDR SDRAM controller */ +/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ +#define MC_DC0_VALUE 0x1B1B +#define MC_DC1_VALUE 0x0 +#define MC_DC2_VALUE 0x0 +#define MC_DC3_VALUE 0x0 +#define MC_DC4_VALUE 0x0 +#define MC_DC5_VALUE 0x200 +#define MC_DC6_VALUE 0x605 +#define MC_DC7_VALUE 0x303 +#define MC_DC8_VALUE 0x102 +#define MC_DC9_VALUE 0x70a +#define MC_DC10_VALUE 0x203 +#define MC_DC11_VALUE 0xc02 +#define MC_DC12_VALUE 0x1C8 +#define MC_DC13_VALUE 0x1 +#define MC_DC14_VALUE 0x0 +#define MC_DC15_VALUE 0xf3c +#define MC_DC16_VALUE 0xC800 +#define MC_DC17_VALUE 0xd +#define MC_DC18_VALUE 0x300 +#define MC_DC19_VALUE 0x200 +#define MC_DC20_VALUE 0xA03 +#define MC_DC21_VALUE 0x1d00 +#define MC_DC22_VALUE 0x1d1d +#define MC_DC23_VALUE 0x0 +#define MC_DC24_VALUE 0x5e /* was 0x7f */ +#define MC_DC25_VALUE 0x0 +#define MC_DC26_VALUE 0x0 +#define MC_DC27_VALUE 0x0 +#define MC_DC28_VALUE 0x510 +#define MC_DC29_VALUE 0x2d89 +#define MC_DC30_VALUE 0x8300 +#define MC_DC31_VALUE 0x0 +#define MC_DC32_VALUE 0x0 +#define MC_DC33_VALUE 0x0 +#define MC_DC34_VALUE 0x0 +#define MC_DC35_VALUE 0x0 +#define MC_DC36_VALUE 0x0 +#define MC_DC37_VALUE 0x0 +#define MC_DC38_VALUE 0x0 +#define MC_DC39_VALUE 0x0 +#define MC_DC40_VALUE 0x0 +#define MC_DC41_VALUE 0x0 +#define MC_DC42_VALUE 0x0 +#define MC_DC43_VALUE 0x0 +#define MC_DC44_VALUE 0x0 +#define MC_DC45_VALUE 0x500 +//#define MC_DC45_VALUE 0x400 +#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r111.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r111.h index 385f7e4e58..fd155973ee 100644 --- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r111.h +++ b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r111.h @@ -1,50 +1,50 @@ -/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */
-#define MC_DC0_VALUE 0x1B1B
-#define MC_DC1_VALUE 0x0
-#define MC_DC2_VALUE 0x0
-#define MC_DC3_VALUE 0x0
-#define MC_DC4_VALUE 0x0
-#define MC_DC5_VALUE 0x200
-#define MC_DC6_VALUE 0x605
-#define MC_DC7_VALUE 0x303
-#define MC_DC8_VALUE 0x102
-#define MC_DC9_VALUE 0x70a
-#define MC_DC10_VALUE 0x203
-#define MC_DC11_VALUE 0xc02
-#define MC_DC12_VALUE 0x1C8
-#define MC_DC13_VALUE 0x1
-#define MC_DC14_VALUE 0x0
-#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE 0xC800
-#define MC_DC17_VALUE 0xd
-#define MC_DC18_VALUE 0x300
-#define MC_DC19_VALUE 0x200
-#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE 0x1200
-#define MC_DC22_VALUE 0x1212
-#define MC_DC23_VALUE 0x0
-#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE 0x0
-#define MC_DC26_VALUE 0x0
-#define MC_DC27_VALUE 0x0
-#define MC_DC28_VALUE 0x510
-#define MC_DC29_VALUE 0x2d89
-#define MC_DC30_VALUE 0x8300
-#define MC_DC31_VALUE 0x0
-#define MC_DC32_VALUE 0x0
-#define MC_DC33_VALUE 0x0
-#define MC_DC34_VALUE 0x0
-#define MC_DC35_VALUE 0x0
-#define MC_DC36_VALUE 0x0
-#define MC_DC37_VALUE 0x0
-#define MC_DC38_VALUE 0x0
-#define MC_DC39_VALUE 0x0
-#define MC_DC40_VALUE 0x0
-#define MC_DC41_VALUE 0x0
-#define MC_DC42_VALUE 0x0
-#define MC_DC43_VALUE 0x0
-#define MC_DC44_VALUE 0x0
-#define MC_DC45_VALUE 0x500
-//#define MC_DC45_VALUE 0x400
-#define MC_DC46_VALUE 0x0
+/* Settings for Denali DDR SDRAM controller */ +/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */ +#define MC_DC0_VALUE 0x1B1B +#define MC_DC1_VALUE 0x0 +#define MC_DC2_VALUE 0x0 +#define MC_DC3_VALUE 0x0 +#define MC_DC4_VALUE 0x0 +#define MC_DC5_VALUE 0x200 +#define MC_DC6_VALUE 0x605 +#define MC_DC7_VALUE 0x303 +#define MC_DC8_VALUE 0x102 +#define MC_DC9_VALUE 0x70a +#define MC_DC10_VALUE 0x203 +#define MC_DC11_VALUE 0xc02 +#define MC_DC12_VALUE 0x1C8 +#define MC_DC13_VALUE 0x1 +#define MC_DC14_VALUE 0x0 +#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ +#define MC_DC16_VALUE 0xC800 +#define MC_DC17_VALUE 0xd +#define MC_DC18_VALUE 0x300 +#define MC_DC19_VALUE 0x200 +#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ +#define MC_DC21_VALUE 0x1200 +#define MC_DC22_VALUE 0x1212 +#define MC_DC23_VALUE 0x0 +#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ +#define MC_DC25_VALUE 0x0 +#define MC_DC26_VALUE 0x0 +#define MC_DC27_VALUE 0x0 +#define MC_DC28_VALUE 0x510 +#define MC_DC29_VALUE 0x2d89 +#define MC_DC30_VALUE 0x8300 +#define MC_DC31_VALUE 0x0 +#define MC_DC32_VALUE 0x0 +#define MC_DC33_VALUE 0x0 +#define MC_DC34_VALUE 0x0 +#define MC_DC35_VALUE 0x0 +#define MC_DC36_VALUE 0x0 +#define MC_DC37_VALUE 0x0 +#define MC_DC38_VALUE 0x0 +#define MC_DC39_VALUE 0x0 +#define MC_DC40_VALUE 0x0 +#define MC_DC41_VALUE 0x0 +#define MC_DC42_VALUE 0x0 +#define MC_DC43_VALUE 0x0 +#define MC_DC44_VALUE 0x0 +#define MC_DC45_VALUE 0x500 +//#define MC_DC45_VALUE 0x400 +#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h index b00177e0a5..45daa188d3 100644 --- a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h +++ b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h @@ -1,51 +1,51 @@ -/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
-
-#define MC_DC0_VALUE 0x1B1B
-#define MC_DC1_VALUE 0x0
-#define MC_DC2_VALUE 0x0
-#define MC_DC3_VALUE 0x0
-#define MC_DC4_VALUE 0x0
-#define MC_DC5_VALUE 0x200
-#define MC_DC6_VALUE 0x306
-#define MC_DC7_VALUE 0x303
-#define MC_DC8_VALUE 0x102
-#define MC_DC9_VALUE 0x80B
-#define MC_DC10_VALUE 0x203
-#define MC_DC11_VALUE 0xD02
-#define MC_DC12_VALUE 0x1C8
-#define MC_DC13_VALUE 0x1
-#define MC_DC14_VALUE 0x0
-#define MC_DC15_VALUE 0x144 /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE 0xC800
-#define MC_DC17_VALUE 0xF
-#define MC_DC18_VALUE 0x301
-#define MC_DC19_VALUE 0x200
-#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE 0x1200
-#define MC_DC22_VALUE 0x1212
-#define MC_DC23_VALUE 0x0
-#define MC_DC24_VALUE 0x66 /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE 0x0
-#define MC_DC26_VALUE 0x0
-#define MC_DC27_VALUE 0x0
-#define MC_DC28_VALUE 0x5FB
-#define MC_DC29_VALUE 0x35DF
-#define MC_DC30_VALUE 0x99E9
-#define MC_DC31_VALUE 0x0
-#define MC_DC32_VALUE 0x0
-#define MC_DC33_VALUE 0x0
-#define MC_DC34_VALUE 0x0
-#define MC_DC35_VALUE 0x0
-#define MC_DC36_VALUE 0x0
-#define MC_DC37_VALUE 0x0
-#define MC_DC38_VALUE 0x0
-#define MC_DC39_VALUE 0x0
-#define MC_DC40_VALUE 0x0
-#define MC_DC41_VALUE 0x0
-#define MC_DC42_VALUE 0x0
-#define MC_DC43_VALUE 0x0
-#define MC_DC44_VALUE 0x0
-#define MC_DC45_VALUE 0x600
-//#define MC_DC45_VALUE 0x400
-#define MC_DC46_VALUE 0x0
+/* Settings for Denali DDR SDRAM controller */ +/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */ + +#define MC_DC0_VALUE 0x1B1B +#define MC_DC1_VALUE 0x0 +#define MC_DC2_VALUE 0x0 +#define MC_DC3_VALUE 0x0 +#define MC_DC4_VALUE 0x0 +#define MC_DC5_VALUE 0x200 +#define MC_DC6_VALUE 0x306 +#define MC_DC7_VALUE 0x303 +#define MC_DC8_VALUE 0x102 +#define MC_DC9_VALUE 0x80B +#define MC_DC10_VALUE 0x203 +#define MC_DC11_VALUE 0xD02 +#define MC_DC12_VALUE 0x1C8 +#define MC_DC13_VALUE 0x1 +#define MC_DC14_VALUE 0x0 +#define MC_DC15_VALUE 0x144 /* WDQS tuning for clk_wr*/ +#define MC_DC16_VALUE 0xC800 +#define MC_DC17_VALUE 0xF +#define MC_DC18_VALUE 0x301 +#define MC_DC19_VALUE 0x200 +#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ +#define MC_DC21_VALUE 0x1200 +#define MC_DC22_VALUE 0x1212 +#define MC_DC23_VALUE 0x0 +#define MC_DC24_VALUE 0x66 /* WDQS Tuning for DQS */ +#define MC_DC25_VALUE 0x0 +#define MC_DC26_VALUE 0x0 +#define MC_DC27_VALUE 0x0 +#define MC_DC28_VALUE 0x5FB +#define MC_DC29_VALUE 0x35DF +#define MC_DC30_VALUE 0x99E9 +#define MC_DC31_VALUE 0x0 +#define MC_DC32_VALUE 0x0 +#define MC_DC33_VALUE 0x0 +#define MC_DC34_VALUE 0x0 +#define MC_DC35_VALUE 0x0 +#define MC_DC36_VALUE 0x0 +#define MC_DC37_VALUE 0x0 +#define MC_DC38_VALUE 0x0 +#define MC_DC39_VALUE 0x0 +#define MC_DC40_VALUE 0x0 +#define MC_DC41_VALUE 0x0 +#define MC_DC42_VALUE 0x0 +#define MC_DC43_VALUE 0x0 +#define MC_DC44_VALUE 0x0 +#define MC_DC45_VALUE 0x600 +//#define MC_DC45_VALUE 0x400 +#define MC_DC46_VALUE 0x0 |