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author | John Crispin <blogic@openwrt.org> | 2012-10-17 22:45:58 +0000 |
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committer | John Crispin <blogic@openwrt.org> | 2012-10-17 22:45:58 +0000 |
commit | 16ed01db05cf25221a62baf3c8eba135f933a6b1 (patch) | |
tree | 405d52924fbc92967e8681bcca5e9c17d35aab8c /package/system/ltq-dsl/src/ifxmips_atm_ppe_amazon_se.h | |
parent | 2372b1dbdb253065274b8a54846149d634bcea14 (diff) | |
download | master-187ad058-16ed01db05cf25221a62baf3c8eba135f933a6b1.tar.gz master-187ad058-16ed01db05cf25221a62baf3c8eba135f933a6b1.tar.bz2 master-187ad058-16ed01db05cf25221a62baf3c8eba135f933a6b1.zip |
[kernel] move lots of kernel related packages to the new system/ folder
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33830 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'package/system/ltq-dsl/src/ifxmips_atm_ppe_amazon_se.h')
-rw-r--r-- | package/system/ltq-dsl/src/ifxmips_atm_ppe_amazon_se.h | 94 |
1 files changed, 94 insertions, 0 deletions
diff --git a/package/system/ltq-dsl/src/ifxmips_atm_ppe_amazon_se.h b/package/system/ltq-dsl/src/ifxmips_atm_ppe_amazon_se.h new file mode 100644 index 0000000000..b9ba2c7ebd --- /dev/null +++ b/package/system/ltq-dsl/src/ifxmips_atm_ppe_amazon_se.h @@ -0,0 +1,94 @@ +#ifndef IFXMIPS_ATM_PPE_AMAZON_SE_H +#define IFXMIPS_ATM_PPE_AMAZON_SE_H + + + +/* + * FPI Configuration Bus Register and Memory Address Mapping + */ +#define IFX_PPE (KSEG1 | 0x1E180000) +#define PP32_DEBUG_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2))) +#define PPM_INT_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2))) +#define PP32_INTERNAL_RES_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2))) +#define CDM_CODE_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2))) +#define PPE_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2))) +#define CDM_DATA_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2))) +#define PPM_INT_UNIT_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2))) +#define PPM_TIMER0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2))) +#define PPM_TASK_IND_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2))) +#define PPS_BRK_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2))) +#define PPM_TIMER1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2))) +#define SB_RAM0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8200) << 2))) +#define SB_RAM1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8C00) << 2))) +#define QSB_CONF_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2))) + +/* + * DWORD-Length of Memory Blocks + */ +#define PP32_DEBUG_REG_DWLEN 0x0030 +#define PPM_INT_REG_DWLEN 0x0010 +#define PP32_INTERNAL_RES_DWLEN 0x00C0 +#define CDM_CODE_MEMORYn_DWLEN(n) ((n) == 0 ? 0x1000 : 0x0800) +#define PPE_REG_DWLEN 0x1000 +#define CDM_DATA_MEMORY_DWLEN CDM_CODE_MEMORYn_DWLEN(1) +#define PPM_INT_UNIT_DWLEN 0x0100 +#define PPM_TIMER0_DWLEN 0x0100 +#define PPM_TASK_IND_REG_DWLEN 0x0100 +#define PPS_BRK_DWLEN 0x0100 +#define PPM_TIMER1_DWLEN 0x0100 +#define SB_RAM0_DWLEN 0x0A00 +#define SB_RAM1_DWLEN 0x0A00 +#define QSB_CONF_REG_DWLEN 0x0100 + +/* + * PP32 to FPI Address Mapping + */ +#define SB_BUFFER(__sb_addr) ((volatile unsigned int *)((((__sb_addr) >= 0x2200) && ((__sb_addr) <= 0x2BFF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2200) : \ + (((__sb_addr) >= 0x2C00) && ((__sb_addr) <= 0x35FF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2C00) : \ + 0)) + +/* + * PP32 Debug Control Register + */ +#define PP32_DBG_CTRL PP32_DEBUG_REG_ADDR(0, 0x0000) + +#define DBG_CTRL_RESTART 0 +#define DBG_CTRL_STOP 1 + +#define PP32_HALT_STAT PP32_DEBUG_REG_ADDR(0, 0x0D00) +#define PP32_BREAKPOINT_REASONS PP32_DEBUG_REG_ADDR(0, 0x0A00) + +#define PP32_BRK_SRC PP32_DEBUG_REG_ADDR(0, 0x0F00) + +#define PP32_DBG_CUR_PC PP32_DEBUG_REG_ADDR(0, 0x0F80) + +#define PP32_DBG_TASK_NO PP32_DEBUG_REG_ADDR(0, 0x0F81) + +/* + * Share Buffer + */ +#define SB_MST_PRI0 PPE_REG_ADDR(0x0300) +#define SB_MST_PRI1 PPE_REG_ADDR(0x0301) + +/* + * EMA Registers + */ +#define EMA_CMDCFG PPE_REG_ADDR(0x0A00) +#define EMA_DATACFG PPE_REG_ADDR(0x0A01) +#define EMA_CMDCNT PPE_REG_ADDR(0x0A02) +#define EMA_DATACNT PPE_REG_ADDR(0x0A03) +#define EMA_ISR PPE_REG_ADDR(0x0A04) +#define EMA_IER PPE_REG_ADDR(0x0A05) +#define EMA_CFG PPE_REG_ADDR(0x0A06) +#define EMA_SUBID PPE_REG_ADDR(0x0A07) + +#define EMA_ALIGNMENT 4 + +/* + * Mailbox IGU1 Interrupt + */ +#define PPE_MAILBOX_IGU1_INT (INT_NUM_IM2_IRL0 + 13) + + + +#endif // IFXMIPS_ATM_PPE_AMAZON_SE_H |