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author | Felix Fietkau <nbd@openwrt.org> | 2011-12-05 14:20:25 +0000 |
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committer | Felix Fietkau <nbd@openwrt.org> | 2011-12-05 14:20:25 +0000 |
commit | 37f16a175ead6785797d525bd04ab1caa37f2e60 (patch) | |
tree | b3fededdf14800901ee1e33c636bb7a68ed11a4d /package/mac80211/patches/544-ath9k_fix_half_quarter_sifs.patch | |
parent | a95157c262a1c1c75151bbda240f7c107c6a9a53 (diff) | |
download | master-187ad058-37f16a175ead6785797d525bd04ab1caa37f2e60.tar.gz master-187ad058-37f16a175ead6785797d525bd04ab1caa37f2e60.tar.bz2 master-187ad058-37f16a175ead6785797d525bd04ab1caa37f2e60.zip |
ath9k: fix 5/10 mhz channel bandwidth issues
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29437 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'package/mac80211/patches/544-ath9k_fix_half_quarter_sifs.patch')
-rw-r--r-- | package/mac80211/patches/544-ath9k_fix_half_quarter_sifs.patch | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/package/mac80211/patches/544-ath9k_fix_half_quarter_sifs.patch b/package/mac80211/patches/544-ath9k_fix_half_quarter_sifs.patch new file mode 100644 index 0000000000..6bde7659f2 --- /dev/null +++ b/package/mac80211/patches/544-ath9k_fix_half_quarter_sifs.patch @@ -0,0 +1,44 @@ +--- a/drivers/net/wireless/ath/ath9k/hw.c ++++ b/drivers/net/wireless/ath/ath9k/hw.c +@@ -1007,31 +1007,35 @@ void ath9k_hw_init_global_settings(struc + if (IS_CHAN_HALF_RATE(chan)) { + eifs = 175; + +- if (!AR_SREV_9300_20_OR_LATER(ah)) ++ if (!AR_SREV_9300_20_OR_LATER(ah)) { + rx_lat = 10; +- else ++ sifstime = 8; ++ } else { + rx_lat *= 2; ++ sifstime = 32; ++ } + + tx_lat *= 2; + if (IS_CHAN_A_FAST_CLOCK(ah, chan)) + tx_lat += 11; + + slottime = 13; +- sifstime = 32; + } else if (IS_CHAN_QUARTER_RATE(chan)) { + eifs = 340; + +- if (!AR_SREV_9300_20_OR_LATER(ah)) ++ if (!AR_SREV_9300_20_OR_LATER(ah)) { + rx_lat = 20; +- else ++ sifstime = 8; ++ } else { + rx_lat = (rx_lat * 4) - 1; ++ sifstime = 64; ++ } + + tx_lat *= 4; + if (IS_CHAN_A_FAST_CLOCK(ah, chan)) + tx_lat += 22; + + slottime = 21; +- sifstime = 64; + } else { + if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { + eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; |