/-----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \-----------------------------------------------------------------------------/ yosys -- Yosys Open SYnthesis Suite =================================== This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base. Yosys is free software licensed under the ISC license (a GPL compatible license that is similar in terms to the MIT license or the 2-clause BSD license). Web Site ======== More information and documentation can be found on the Yosys web site: http://www.clifford.at/yosys/ Getting Started =============== You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make. The Qt4 library is needed for the yosys SVG viewer, that is used to display schematics, the minisat library is required for the SAT features in yosys and TCL for the scripting functionality. The extensive test suite requires Icarus Verilog. For example on Ubuntu Linux 12.04 LTS the following commands will install all prerequisites for building yosys: $ sudo apt-get install git $ sudo apt-get install g++ $ sudo apt-get install clang $ sudo apt-get install make $ sudo apt-get install bison $ sudo apt-get install flex $ sudo apt-get install libreadline-dev $ sudo apt-get install tcl8.5-dev $ sudo apt-get install minisat $ sudo apt-get install zlib1g-dev $ sudo apt-get install libqt4-dev $ sudo apt-get install mercurial $ sudo apt-get install iverilog $ sudo apt-get install graphviz To configure the build system to use a specific set of compiler and build configuration, use one of $ make config-clang-debug $ make config-gcc-debug $ make config-release For other compilers and build configurations it might be necessary to make some changes to the config section of the Makefile. $ vi Makefile To build Yosys simply type 'make' in this directory. $ make $ make test $ sudo make install If you encounter any problems during build, make sure to check the section "Workarounds for known build problems" at the end of this README file. Note that this also downloads, builds and installs ABC (using yosys-abc as executeable name). Yosys can be used with the interactive command shell, with synthesis scripts or with command line arguments. Let's perform a simple synthesis job using the interactive command shell: $ ./yosys yosys> the command "help" can be used to print a list of all available commands and "help " to print details on the specified command: yosys> help help reading the design using the verilog frontend: yosys> read_verilog tests/simple/fiedler-cooley.v writing the design to the console in yosys's internal format: yosys> write_ilang convert processes ("always" blocks) to netlist elements and perform some simple optimizations: yosys> proc; opt display design netlist using the yosys svg viewer: yosys> show the same thing using 'gv' as postscript viewer: yosys> show -format ps -viewer gv translating netlist to gate logic and perform some simple optimizations: yosys> techmap; opt write design netlist to a new verilog file: yosys> write_verilog synth.v a similar synthesis can be performed using yosys command line options only: $ ./yosys -o synth.v -p proc -p opt -p techmap -p opt tests/simple/fiedler-cooley.v or using a simple synthesis script: $ cat synth.ys read_verilog tests/simple/fiedler-cooley.v proc; opt; techmap; opt write_verilog synth.v $ ./yosys synth.ys It is also possible to only have the synthesis commands but not the read/write commands in the synthesis script: $ cat synth.ys proc; opt; techmap; opt $ ./yosys -o synth.v tests/simple/fiedler-cooley.v synth.ys The following synthesis script works reasonable for all designs: # check design hierarchy hierarchy # translate processes (always blocks) and memories (arrays) proc; memory; opt # detect and optimize FSM encodings fsm; opt # convert to gate logic techmap; opt If ABC is enabled in the Yosys build configuration and a cell library is given in the liberty file mycells.lib, the following synthesis script will synthesize for the given cell library: # the high-level stuff hierarchy; proc; memory; opt; fsm; opt # mapping to internal cell library techmap; opt # mapping flip-flops to mycells.lib dfflibmap -liberty mycells.lib # mapping logic to mycells.lib abc -liberty mycells.lib # cleanup clean If you do not have a liberty file but want to test this synthesis script, you can use the file techlibs/cmos/cmos_cells.lib from the yosys sources. Yosys is under construction. A more detailed documentation will follow. Unsupported Verilog-2005 Features ================================= The following Verilog-2005 features are not supported by yosys and there are currently no plans to add support for them: - Non-sythesizable language features as defined in IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002 - The "tri", "triand", "trior", "wand" and "wor" net types - The "config" keyword and library map files - The "disable", "primitive" and "specify" statements - Latched logic (is synthesized as logic with feedback loops) Verilog Attributes and non-standard features ============================================ - The 'full_case' attribute on case statements is supported (also the non-standard "// synopsys full_case" directive) - The 'parallel_case' attribute on case statements is supported (also the non-standard "// synopsys parallel_case" directive) - The "// synopsys translate_off" and "// synopsys translate_on" directives are also supported (but the use of `ifdef .. `endif is strongly recommended instead). - The "nomem2reg" attribute on modules or arrays pro
/*-*-c++-*-
 * $Id$
 *
 * This file is part of plptools.
 *
 *  Copyright (C) 1999  Philip Proudman <philip.proudman@btinternet.com>
 *  Copyright (C) 1999-2001 Fritz Elfert <felfert@to.com>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 */
#ifndef _LOG_H_
#define _LOG_H_

#include <iostream>

#include <syslog.h>

/**
 * A streambuffer, logging via syslog
 *
 * logbuf can be used, if you want to use syslog for
 * logging but don't want to change all your nice
 * C++-style output statements in your code.
 *
 * Here is an example showing the usage of logbuf:
 *
 * <PRE>
 *	openlog("myDaemon", LOG_CONS|LOG_PID, LOG_DAEMON);
 *	logbuf ebuf(LOG_ERR, 2);
 *	ostream lerr(&ebuf);
 *
 *	... some code ...
 *
 *	lerr << "Whoops, got an error" << endl;
 * </PRE>
 *
 * The second optional argument of the constructor can be used
 * to switch the output destination between syslog and some
 * file. If it is omitted or set to -1, logging can be switched on
 * or off. The initial state is on.
 */
class logbuf : public std::streambuf {
public:

    /**
    * Constructs a new instance.
    *
    * @param loglevel The log level for this instance.
    * 	see syslog(3) for symbolic names to use.
    * @param fd An optional file descriptor to use
    *   if switched off.
    */
    logbuf(int loglevel, int fd = -1);

    /**
    * Switches loggin on or off.
    *
    * @param newstate The desired state.
    */
    void setOn(bool newstate) { _on = newstate; }

    /**
    * Modifies the loglevel of this instance.
    * 
    * @param newlevel The new loglevel.
    */
    void setLevel(int newlevel) { _level = newlevel; }

    /**
    * Retrieve the current state.
    *
    * @returns The current state.
    */
    bool on() { return _on; }

    /**
    * Retrieves the current loglevel.
    * 
    * @returns The current loglevel.
    */
    int level() { return _level; }

    /**
    * Called by the associated
    * ostream to write a character.
    * Stores the character in a buffer
    * and calls syslog(level, buffer)
    * whenever a LF is seen.
    */
    int overflow(int c = EOF);

private:

    /**
    * Pointer to next char in buffer.
    */
    char *ptr;

    /**
    * Current length of buffer.
    */
    unsigned int len;

    /**
    * The log level to use with syslog.
    */
    int _level;

    /**
    * File descriptor to use when switched off.
    * If this is -1, don't output anything.
    */
    int _fd;

    /**
    * Log flag.
    */
    bool _on;

    /**
    * The internal buffer for holding
    * messages.
    */
    char buf[1024];
};

#endif

/*
 * Local variables:
 * c-basic-offset: 4
 * End:
 */
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