1 2 3 4 5 6 7 8 9 10 11 12 13 pre { line-height: 125%; margin: 0; } td.linenos pre { color: #000000; background-color: #f0f0f0; padding: 0 5px 0 5px; } span.linenos { color: #000000; background-color: #f0f0f0; padding: 0 5px 0 5px; } td.linenos pre.special { color: #000000; background-color: #ffffc0; padding: 0 5px 0 5px; } module dffn(input CLK, D, output reg Q, output QN); always @(negedge CLK) Q <= D; assign QN = ~Q; endmodule module dffsr(input CLK, D, CLEAR, PRESET, output reg Q, output QN); always @(posedge CLK, posedge CLEAR, posedge PRESET) if (CLEAR) Q <= 0; else if (PRESET) Q <= 1; else Q <= D; assign QN = ~Q; endmodule
module dffn(input CLK, D, output reg Q, output QN); always @(negedge CLK) Q <= D; assign QN = ~Q; endmodule module dffsr(input CLK, D, CLEAR, PRESET, output reg Q, output QN); always @(posedge CLK, posedge CLEAR, posedge PRESET) if (CLEAR) Q <= 0; else if (PRESET) Q <= 1; else Q <= D; assign QN = ~Q; endmodule
